2 * SH3 Setup code for SH7710, SH7712
4 * Copyright (C) 2006, 2007 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
28 EDMAC0, EDMAC1, EDMAC2,
29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
32 RTC_ATI, RTC_PRI, RTC_CUI,
36 /* interrupt groups */
37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
40 static struct intc_vect vectors[] __initdata = {
41 /* IRQ0->5 are handled in setup-sh3.c */
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
49 #ifdef CONFIG_CPU_SUBTYPE_SH7710
50 INTC_VECT(IPSEC, 0xbe0),
52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
53 INTC_VECT(EDMAC2, 0xc40),
54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
59 INTC_VECT(TMU2, 0x440),
60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
61 INTC_VECT(RTC_CUI, 0x4c0),
62 INTC_VECT(WDT, 0x560),
63 INTC_VECT(REF, 0x580),
66 static struct intc_group groups[] __initdata = {
67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
76 static struct intc_prio_reg prio_registers[] __initdata = {
77 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
78 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
79 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
80 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
81 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
82 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
83 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
84 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
85 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
88 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
89 NULL, prio_registers, NULL);
91 static struct resource rtc_resources[] = {
94 .end = 0xa413fec0 + 0x1e,
95 .flags = IORESOURCE_IO,
99 .flags = IORESOURCE_IRQ,
103 .flags = IORESOURCE_IRQ,
107 .flags = IORESOURCE_IRQ,
111 static struct sh_rtc_platform_info rtc_info = {
112 .capabilities = RTC_CAP_4_DIGIT_YEAR,
115 static struct platform_device rtc_device = {
118 .num_resources = ARRAY_SIZE(rtc_resources),
119 .resource = rtc_resources,
121 .platform_data = &rtc_info,
125 static struct plat_sci_port sci_platform_data[] = {
127 .mapbase = 0xa4400000,
128 .flags = UPF_BOOT_AUTOCONF,
130 .irqs = { 52, 53, 55, 54 },
132 .mapbase = 0xa4410000,
133 .flags = UPF_BOOT_AUTOCONF,
135 .irqs = { 56, 57, 59, 58 },
142 static struct platform_device sci_device = {
146 .platform_data = sci_platform_data,
150 static struct platform_device *sh7710_devices[] __initdata = {
155 static int __init sh7710_devices_setup(void)
157 return platform_add_devices(sh7710_devices,
158 ARRAY_SIZE(sh7710_devices));
160 __initcall(sh7710_devices_setup);
162 void __init plat_irq_setup(void)
164 register_intc_controller(&intc_desc);
165 plat_irq_setup_sh3();