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   1 /* chmc.c: Driver for UltraSPARC-III memory controller.
   2  *
   3  * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/types.h>
   9 #include <linux/slab.h>
  10 #include <linux/list.h>
  11 #include <linux/string.h>
  12 #include <linux/sched.h>
  13 #include <linux/smp.h>
  14 #include <linux/errno.h>
  15 #include <linux/init.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <asm/spitfire.h>
  19 #include <asm/chmctrl.h>
  20 #include <asm/cpudata.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23 #include <asm/head.h>
  24 #include <asm/io.h>
  25 #include <asm/memctrl.h>
  26
  27 #define DRV_MODULE_NAME         "chmc"
  28 #define PFX DRV_MODULE_NAME     ": "
  29 #define DRV_MODULE_VERSION      "0.2"
  30
  31 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  32 MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
  33 MODULE_LICENSE("GPL");
  34 MODULE_VERSION(DRV_MODULE_VERSION);
  35
  36 static int mc_type;
  37 #define MC_TYPE_SAFARI          1
  38 #define MC_TYPE_JBUS            2
  39
  40 static dimm_printer_t us3mc_dimm_printer;
  41
  42 #define CHMCTRL_NDGRPS  2
  43 #define CHMCTRL_NDIMMS  4
  44
  45 #define CHMC_DIMMS_PER_MC       (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
  46
  47 /* OBP memory-layout property format. */
  48 struct chmc_obp_map {
  49         unsigned char   dimm_map[144];
  50         unsigned char   pin_map[576];
  51 };
  52
  53 #define DIMM_LABEL_SZ   8
  54
  55 struct chmc_obp_mem_layout {
  56         /* One max 8-byte string label per DIMM.  Usually
  57          * this matches the label on the motherboard where
  58          * that DIMM resides.
  59          */
  60         char                    dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
  61
  62         /* If symmetric use map[0], else it is
  63          * asymmetric and map[1] should be used.
  64          */
  65         char                    symmetric;
  66
  67         struct chmc_obp_map     map[2];
  68 };
  69
  70 #define CHMCTRL_NBANKS  4
  71
  72 struct chmc_bank_info {
  73         struct chmc             *p;
  74         int                     bank_id;
  75
  76         u64                     raw_reg;
  77         int                     valid;
  78         int                     uk;
  79         int                     um;
  80         int                     lk;
  81         int                     lm;
  82         int                     interleave;
  83         unsigned long           base;
  84         unsigned long           size;
  85 };
  86
  87 struct chmc {
  88         struct list_head                list;
  89         int                             portid;
  90
  91         struct chmc_obp_mem_layout      layout_prop;
  92         int                             layout_size;
  93
  94         void __iomem                    *regs;
  95
  96         u64                             timing_control1;
  97         u64                             timing_control2;
  98         u64                             timing_control3;
  99         u64                             timing_control4;
 100         u64                             memaddr_control;
 101
 102         struct chmc_bank_info           logical_banks[CHMCTRL_NBANKS];
 103 };
 104
 105 #define JBUSMC_REGS_SIZE                8
 106
 107 #define JB_MC_REG1_DIMM2_BANK3          0x8000000000000000UL
 108 #define JB_MC_REG1_DIMM1_BANK1          0x4000000000000000UL
 109 #define JB_MC_REG1_DIMM2_BANK2          0x2000000000000000UL
 110 #define JB_MC_REG1_DIMM1_BANK0          0x1000000000000000UL
 111 #define JB_MC_REG1_XOR                  0x0000010000000000UL
 112 #define JB_MC_REG1_ADDR_GEN_2           0x000000e000000000UL
 113 #define JB_MC_REG1_ADDR_GEN_2_SHIFT     37
 114 #define JB_MC_REG1_ADDR_GEN_1           0x0000001c00000000UL
 115 #define JB_MC_REG1_ADDR_GEN_1_SHIFT     34
 116 #define JB_MC_REG1_INTERLEAVE           0x0000000001800000UL
 117 #define JB_MC_REG1_INTERLEAVE_SHIFT     23
 118 #define JB_MC_REG1_DIMM2_PTYPE          0x0000000000200000UL
 119 #define JB_MC_REG1_DIMM2_PTYPE_SHIFT    21
 120 #define JB_MC_REG1_DIMM1_PTYPE          0x0000000000100000UL
 121 #define JB_MC_REG1_DIMM1_PTYPE_SHIFT    20
 122
 123 #define PART_TYPE_X8            0
 124 #define PART_TYPE_X4            1
 125
 126 #define INTERLEAVE_NONE         0
 127 #define INTERLEAVE_SAME         1
 128 #define INTERLEAVE_INTERNAL     2
 129 #define INTERLEAVE_BOTH         3
 130
 131 #define ADDR_GEN_128MB          0
 132 #define ADDR_GEN_256MB          1
 133 #define ADDR_GEN_512MB          2
 134 #define ADDR_GEN_1GB            3
 135
 136 #define JB_NUM_DIMM_GROUPS      2
 137 #define JB_NUM_DIMMS_PER_GROUP  2
 138 #define JB_NUM_DIMMS            (JB_NUM_DIMM_GROUPS * JB_NUM_DIMMS_PER_GROUP)
 139
 140 struct jbusmc_obp_map {
 141         unsigned char   dimm_map[18];
 142         unsigned char   pin_map[144];
 143 };
 144
 145 struct jbusmc_obp_mem_layout {
 146         /* One max 8-byte string label per DIMM.  Usually
 147          * this matches the label on the motherboard where
 148          * that DIMM resides.
 149          */
 150         char            dimm_labels[JB_NUM_DIMMS][DIMM_LABEL_SZ];
 151
 152         /* If symmetric use map[0], else it is
 153          * asymmetric and map[1] should be used.
 154          */
 155         char                    symmetric;
 156
 157         struct jbusmc_obp_map   map;
 158
 159         char                    _pad;
 160 };
 161
 162 struct jbusmc_dimm_group {
 163         struct jbusmc                   *controller;
 164         int                             index;
 165         u64                             base_addr;
 166         u64                             size;
 167 };
 168
 169 struct jbusmc {
 170         void __iomem                    *regs;
 171         u64                             mc_reg_1;
 172         u32                             portid;
 173         struct jbusmc_obp_mem_layout    layout;
 174         int                             layout_len;
 175         int                             num_dimm_groups;
 176         struct jbusmc_dimm_group        dimm_groups[JB_NUM_DIMM_GROUPS];
 177         struct list_head                list;
 178 };
 179
 180 static DEFINE_SPINLOCK(mctrl_list_lock);
 181 static LIST_HEAD(mctrl_list);
 182
 183 static void mc_list_add(struct list_head *list)
 184 {
 185         spin_lock(&mctrl_list_lock);
 186         list_add(list, &mctrl_list);
 187         spin_unlock(&mctrl_list_lock);
 188 }
 189
 190 static void mc_list_del(struct list_head *list)
 191 {
 192         spin_lock(&mctrl_list_lock);
 193         list_del_init(list);
 194         spin_unlock(&mctrl_list_lock);
 195 }
 196
 197 #define SYNDROME_MIN    -1
 198 #define SYNDROME_MAX    144
 199
 200 /* Covert syndrome code into the way the bits are positioned
 201  * on the bus.
 202  */
 203 static int syndrome_to_qword_code(int syndrome_code)
 204 {
 205         if (syndrome_code < 128)
 206                 syndrome_code += 16;
 207         else if (syndrome_code < 128 + 9)
 208                 syndrome_code -= (128 - 7);
 209         else if (syndrome_code < (128 + 9 + 3))
 210                 syndrome_code -= (128 + 9 - 4);
 211         else
 212                 syndrome_code -= (128 + 9 + 3);
 213         return syndrome_code;
 214 }
 215
 216 /* All this magic has to do with how a cache line comes over the wire
 217  * on Safari and JBUS.  A 64-bit line comes over in 1 or more quadword
 218  * cycles, each of which transmit ECC/MTAG info as well as the actual
 219  * data.
 220  */
 221 #define L2_LINE_SIZE            64
 222 #define L2_LINE_ADDR_MSK        (L2_LINE_SIZE - 1)
 223 #define QW_PER_LINE             4
 224 #define QW_BYTES                (L2_LINE_SIZE / QW_PER_LINE)
 225 #define QW_BITS                 144
 226 #define SAFARI_LAST_BIT         (576 - 1)
 227 #define JBUS_LAST_BIT           (144 - 1)
 228
 229 static void get_pin_and_dimm_str(int syndrome_code, unsigned long paddr,
 230                                  int *pin_p, char **dimm_str_p, void *_prop,
 231                                  int base_dimm_offset)
 232 {
 233         int qword_code = syndrome_to_qword_code(syndrome_code);
 234         int cache_line_offset;
 235         int offset_inverse;
 236         int dimm_map_index;
 237         int map_val;
 238
 239         if (mc_type == MC_TYPE_JBUS) {
 240                 struct jbusmc_obp_mem_layout *p = _prop;
 241
 242                 /* JBUS */
 243                 cache_line_offset = qword_code;
 244                 offset_inverse = (JBUS_LAST_BIT - cache_line_offset);
 245                 dimm_map_index = offset_inverse / 8;
 246                 map_val = p->map.dimm_map[dimm_map_index];
 247                 map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1);
 248                 *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
 249                 *pin_p = p->map.pin_map[cache_line_offset];
 250         } else {
 251                 struct chmc_obp_mem_layout *p = _prop;
 252                 struct chmc_obp_map *mp;
 253                 int qword;
 254
 255                 /* Safari */
 256                 if (p->symmetric)
 257                         mp = &p->map[0];
 258                 else
 259                         mp = &p->map[1];
 260
 261                 qword = (paddr & L2_LINE_ADDR_MSK) / QW_BYTES;
 262                 cache_line_offset = ((3 - qword) * QW_BITS) + qword_code;
 263                 offset_inverse = (SAFARI_LAST_BIT - cache_line_offset);
 264                 dimm_map_index = offset_inverse >> 2;
 265                 map_val = mp->dimm_map[dimm_map_index];
 266                 map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3);
 267                 *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
 268                 *pin_p = mp->pin_map[cache_line_offset];
 269         }
 270 }
 271
 272 static struct jbusmc_dimm_group *jbusmc_find_dimm_group(unsigned long phys_addr)
 273 {
 274         struct jbusmc *p;
 275
 276         list_for_each_entry(p, &mctrl_list, list) {
 277                 int i;
 278
 279                 for (i = 0; i < p->num_dimm_groups; i++) {
 280                         struct jbusmc_dimm_group *dp = &p->dimm_groups[i];
 281
 282                         if (phys_addr < dp->base_addr ||
 283                             (dp->base_addr + dp->size) <= phys_addr)
 284                                 continue;
 285
 286                         return dp;
 287                 }
 288         }
 289         return NULL;
 290 }
 291
 292 static int jbusmc_print_dimm(int syndrome_code,
 293                              unsigned long phys_addr,
 294                              char *buf, int buflen)
 295 {
 296         struct jbusmc_obp_mem_layout *prop;
 297         struct jbusmc_dimm_group *dp;
 298         struct jbusmc *p;
 299         int first_dimm;
 300
 301         dp = jbusmc_find_dimm_group(phys_addr);
 302         if (dp == NULL ||
 303             syndrome_code < SYNDROME_MIN ||
 304             syndrome_code > SYNDROME_MAX) {
 305                 buf[0] = '?';
 306                 buf[1] = '?';
 307                 buf[2] = '?';
 308                 buf[3] = '\0';
 309                 return 0;
 310         }
 311         p = dp->controller;
 312         prop = &p->layout;
 313
 314         first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP;
 315
 316         if (syndrome_code != SYNDROME_MIN) {
 317                 char *dimm_str;
 318                 int pin;
 319
 320                 get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
 321                                      &dimm_str, prop, first_dimm);
 322                 sprintf(buf, "%s, pin %3d", dimm_str, pin);
 323         } else {
 324                 int dimm;
 325
 326                 /* Multi-bit error, we just dump out all the
 327                  * dimm labels associated with this dimm group.
 328                  */
 329                 for (dimm = 0; dimm < JB_NUM_DIMMS_PER_GROUP; dimm++) {
 330                         sprintf(buf, "%s ",
 331                                 prop->dimm_labels[first_dimm + dimm]);
 332                         buf += strlen(buf);
 333                 }
 334         }
 335
 336         return 0;
 337 }
 338
 339 static u64 __devinit jbusmc_dimm_group_size(u64 base,
 340                                             const struct linux_prom64_registers *mem_regs,
 341                                             int num_mem_regs)
 342 {
 343         u64 max = base + (8UL * 1024 * 1024 * 1024);
 344         u64 max_seen = base;
 345         int i;
 346
 347         for (i = 0; i < num_mem_regs; i++) {
 348                 const struct linux_prom64_registers *ent;
 349                 u64 this_base;
 350                 u64 this_end;
 351
 352                 ent = &mem_regs[i];
 353                 this_base = ent->phys_addr;
 354                 this_end = this_base + ent->reg_size;
 355                 if (base < this_base || base >= this_end)
 356                         continue;
 357                 if (this_end > max)
 358                         this_end = max;
 359                 if (this_end > max_seen)
 360                         max_seen = this_end;
 361         }
 362
 363         return max_seen - base;
 364 }
 365
 366 static void __devinit jbusmc_construct_one_dimm_group(struct jbusmc *p,
 367                                                       unsigned long index,
 368                                                       const struct linux_prom64_registers *mem_regs,
 369                                                       int num_mem_regs)
 370 {
 371         struct jbusmc_dimm_group *dp = &p->dimm_groups[index];
 372
 373         dp->controller = p;
 374         dp->index = index;
 375
 376         dp->base_addr  = (p->portid * (64UL * 1024 * 1024 * 1024));
 377         dp->base_addr += (index * (8UL * 1024 * 1024 * 1024));
 378         dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs);
 379 }
 380
 381 static void __devinit jbusmc_construct_dimm_groups(struct jbusmc *p,
 382                                                    const struct linux_prom64_registers *mem_regs,
 383                                                    int num_mem_regs)
 384 {
 385         if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) {
 386                 jbusmc_construct_one_dimm_group(p, 0, mem_regs, num_mem_regs);
 387                 p->num_dimm_groups++;
 388         }
 389         if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) {
 390                 jbusmc_construct_one_dimm_group(p, 1, mem_regs, num_mem_regs);
 391                 p->num_dimm_groups++;
 392         }
 393 }
 394
 395 static int __devinit jbusmc_probe(struct of_device *op,
 396                                   const struct of_device_id *match)
 397 {
 398         const struct linux_prom64_registers *mem_regs;
 399         struct device_node *mem_node;
 400         int err, len, num_mem_regs;
 401         struct jbusmc *p;
 402         const u32 *prop;
 403         const void *ml;
 404
 405         err = -ENODEV;
 406         mem_node = of_find_node_by_path("/memory");
 407         if (!mem_node) {
 408                 printk(KERN_ERR PFX "Cannot find /memory node.\n");
 409                 goto out;
 410         }
 411         mem_regs = of_get_property(mem_node, "reg", &len);
 412         if (!mem_regs) {
 413                 printk(KERN_ERR PFX "Cannot get reg property of /memory node.\n");
 414                 goto out;
 415         }
 416         num_mem_regs = len / sizeof(*mem_regs);
 417
 418         err = -ENOMEM;
 419         p = kzalloc(sizeof(*p), GFP_KERNEL);
 420         if (!p) {
 421                 printk(KERN_ERR PFX "Cannot allocate struct jbusmc.\n");
 422                 goto out;
 423         }
 424
 425         INIT_LIST_HEAD(&p->list);
 426
 427         err = -ENODEV;
 428         prop = of_get_property(op->node, "portid", &len);
 429         if (!prop || len != 4) {
 430                 printk(KERN_ERR PFX "Cannot find portid.\n");
 431                 goto out_free;
 432         }
 433
 434         p->portid = *prop;
 435
 436         prop = of_get_property(op->node, "memory-control-register-1", &len);
 437         if (!prop || len != 8) {
 438                 printk(KERN_ERR PFX "Cannot get memory control register 1.\n");
 439                 goto out_free;
 440         }
 441
 442         p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1];
 443
 444         err = -ENOMEM;
 445         p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc");
 446         if (!p->regs) {
 447                 printk(KERN_ERR PFX "Cannot map jbusmc regs.\n");
 448                 goto out_free;
 449         }
 450
 451         err = -ENODEV;
 452         ml = of_get_property(op->node, "memory-layout", &p->layout_len);
 453         if (!ml) {
 454                 printk(KERN_ERR PFX "Cannot get memory layout property.\n");
 455                 goto out_iounmap;
 456         }
 457         if (p->layout_len > sizeof(p->layout)) {
 458                 printk(KERN_ERR PFX "Unexpected memory-layout size %d\n",
 459                        p->layout_len);
 460                 goto out_iounmap;
 461         }
 462         memcpy(&p->layout, ml, p->layout_len);
 463
 464         jbusmc_construct_dimm_groups(p, mem_regs, num_mem_regs);
 465
 466         mc_list_add(&p->list);
 467
 468         printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %s\n",
 469                op->node->full_name);
 470
 471         dev_set_drvdata(&op->dev, p);
 472
 473         err = 0;
 474
 475 out:
 476         return err;
 477
 478 out_iounmap:
 479         of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
 480
 481 out_free:
 482         kfree(p);
 483         goto out;
 484 }
 485
 486 /* Does BANK decode PHYS_ADDR? */
 487 static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
 488 {
 489         unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
 490         unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
 491
 492         /* Bank must be enabled to match. */
 493         if (bp->valid == 0)
 494                 return 0;
 495
 496         /* Would BANK match upper bits? */
 497         upper_bits ^= bp->um;           /* What bits are different? */
 498         upper_bits  = ~upper_bits;      /* Invert. */
 499         upper_bits |= bp->uk;           /* What bits don't matter for matching? */
 500         upper_bits  = ~upper_bits;      /* Invert. */
 501
 502         if (upper_bits)
 503                 return 0;
 504
 505         /* Would BANK match lower bits? */
 506         lower_bits ^= bp->lm;           /* What bits are different? */
 507         lower_bits  = ~lower_bits;      /* Invert. */
 508         lower_bits |= bp->lk;           /* What bits don't matter for matching? */
 509         lower_bits  = ~lower_bits;      /* Invert. */
 510
 511         if (lower_bits)
 512                 return 0;
 513
 514         /* I always knew you'd be the one. */
 515         return 1;
 516 }
 517
 518 /* Given PHYS_ADDR, search memory controller banks for a match. */
 519 static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
 520 {
 521         struct chmc *p;
 522
 523         list_for_each_entry(p, &mctrl_list, list) {
 524                 int bank_no;
 525
 526                 for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
 527                         struct chmc_bank_info *bp;
 528
 529                         bp = &p->logical_banks[bank_no];
 530                         if (chmc_bank_match(bp, phys_addr))
 531                                 return bp;
 532                 }
 533         }
 534
 535         return NULL;
 536 }
 537
 538 /* This is the main purpose of this driver. */
 539 static int chmc_print_dimm(int syndrome_code,
 540                            unsigned long phys_addr,
 541                            char *buf, int buflen)
 542 {
 543         struct chmc_bank_info *bp;
 544         struct chmc_obp_mem_layout *prop;
 545         int bank_in_controller, first_dimm;
 546
 547         bp = chmc_find_bank(phys_addr);
 548         if (bp == NULL ||
 549             syndrome_code < SYNDROME_MIN ||
 550             syndrome_code > SYNDROME_MAX) {
 551                 buf[0] = '?';
 552                 buf[1] = '?';
 553                 buf[2] = '?';
 554                 buf[3] = '\0';
 555                 return 0;
 556         }
 557
 558         prop = &bp->p->layout_prop;
 559         bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
 560         first_dimm  = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
 561         first_dimm *= CHMCTRL_NDIMMS;
 562
 563         if (syndrome_code != SYNDROME_MIN) {
 564                 char *dimm_str;
 565                 int pin;
 566
 567                 get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
 568                                      &dimm_str, prop, first_dimm);
 569                 sprintf(buf, "%s, pin %3d", dimm_str, pin);
 570         } else {
 571                 int dimm;
 572
 573                 /* Multi-bit error, we just dump out all the
 574                  * dimm labels associated with this bank.
 575                  */
 576                 for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
 577                         sprintf(buf, "%s ",
 578                                 prop->dimm_labels[first_dimm + dimm]);
 579                         buf += strlen(buf);
 580                 }
 581         }
 582         return 0;
 583 }
 584
 585 /* Accessing the registers is slightly complicated.  If you want
 586  * to get at the memory controller which is on the same processor
 587  * the code is executing, you must use special ASI load/store else
 588  * you go through the global mapping.
 589  */
 590 static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
 591 {
 592         unsigned long ret, this_cpu;
 593
 594         preempt_disable();
 595
 596         this_cpu = real_hard_smp_processor_id();
 597
 598         if (p->portid == this_cpu) {
 599                 __asm__ __volatile__("ldxa      [%1] %2, %0"
 600                                      : "=r" (ret)
 601                                      : "r" (offset), "i" (ASI_MCU_CTRL_REG));
 602         } else {
 603                 __asm__ __volatile__("ldxa      [%1] %2, %0"
 604                                      : "=r" (ret)
 605                                      : "r" (p->regs + offset),
 606                                        "i" (ASI_PHYS_BYPASS_EC_E));
 607         }
 608
 609         preempt_enable();
 610
 611         return ret;
 612 }
 613
 614 #if 0 /* currently unused */
 615 static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
 616 {
 617         if (p->portid == smp_processor_id()) {
 618                 __asm__ __volatile__("stxa      %0, [%1] %2"
 619                                      : : "r" (val),
 620                                          "r" (offset), "i" (ASI_MCU_CTRL_REG));
 621         } else {
 622                 __asm__ __volatile__("ldxa      %0, [%1] %2"
 623                                      : : "r" (val),
 624                                          "r" (p->regs + offset),
 625                                          "i" (ASI_PHYS_BYPASS_EC_E));
 626         }
 627 }
 628 #endif
 629
 630 static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
 631 {
 632         struct chmc_bank_info *bp = &p->logical_banks[which_bank];
 633
 634         bp->p = p;
 635         bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
 636         bp->raw_reg = val;
 637         bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
 638         bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
 639         bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
 640         bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
 641         bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
 642
 643         bp->base  =  (bp->um);
 644         bp->base &= ~(bp->uk);
 645         bp->base <<= PA_UPPER_BITS_SHIFT;
 646
 647         switch(bp->lk) {
 648         case 0xf:
 649         default:
 650                 bp->interleave = 1;
 651                 break;
 652
 653         case 0xe:
 654                 bp->interleave = 2;
 655                 break;
 656
 657         case 0xc:
 658                 bp->interleave = 4;
 659                 break;
 660
 661         case 0x8:
 662                 bp->interleave = 8;
 663                 break;
 664
 665         case 0x0:
 666                 bp->interleave = 16;
 667                 break;
 668         };
 669
 670         /* UK[10] is reserved, and UK[11] is not set for the SDRAM
 671          * bank size definition.
 672          */
 673         bp->size = (((unsigned long)bp->uk &
 674                      ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
 675         bp->size /= bp->interleave;
 676 }
 677
 678 static void chmc_fetch_decode_regs(struct chmc *p)
 679 {
 680         if (p->layout_size == 0)
 681                 return;
 682
 683         chmc_interpret_one_decode_reg(p, 0,
 684                                       chmc_read_mcreg(p, CHMCTRL_DECODE1));
 685         chmc_interpret_one_decode_reg(p, 1,
 686                                       chmc_read_mcreg(p, CHMCTRL_DECODE2));
 687         chmc_interpret_one_decode_reg(p, 2,
 688                                       chmc_read_mcreg(p, CHMCTRL_DECODE3));
 689         chmc_interpret_one_decode_reg(p, 3,
 690                                       chmc_read_mcreg(p, CHMCTRL_DECODE4));
 691 }
 692
 693 static int __devinit chmc_probe(struct of_device *op,
 694                                 const struct of_device_id *match)
 695 {
 696         struct device_node *dp = op->node;
 697         unsigned long ver;
 698         const void *pval;
 699         int len, portid;
 700         struct chmc *p;
 701         int err;
 702
 703         err = -ENODEV;
 704         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 705         if ((ver >> 32UL) == __JALAPENO_ID ||
 706             (ver >> 32UL) == __SERRANO_ID)
 707                 goto out;
 708
 709         portid = of_getintprop_default(dp, "portid", -1);
 710         if (portid == -1)
 711                 goto out;
 712
 713         pval = of_get_property(dp, "memory-layout", &len);
 714         if (pval && len > sizeof(p->layout_prop)) {
 715                 printk(KERN_ERR PFX "Unexpected memory-layout property "
 716                        "size %d.\n", len);
 717                 goto out;
 718         }
 719
 720         err = -ENOMEM;
 721         p = kzalloc(sizeof(*p), GFP_KERNEL);
 722         if (!p) {
 723                 printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
 724                 goto out;
 725         }
 726
 727         p->portid = portid;
 728         p->layout_size = len;
 729         if (!pval)
 730                 p->layout_size = 0;
 731         else
 732                 memcpy(&p->layout_prop, pval, len);
 733
 734         p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
 735         if (!p->regs) {
 736                 printk(KERN_ERR PFX "Could not map registers.\n");
 737                 goto out_free;
 738         }
 739
 740         if (p->layout_size != 0UL) {
 741                 p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
 742                 p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
 743                 p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
 744                 p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
 745                 p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
 746         }
 747
 748         chmc_fetch_decode_regs(p);
 749
 750         mc_list_add(&p->list);
 751
 752         printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
 753                dp->full_name,
 754                (p->layout_size ? "ACTIVE" : "INACTIVE"));
 755
 756         dev_set_drvdata(&op->dev, p);
 757
 758         err = 0;
 759
 760 out:
 761         return err;
 762
 763 out_free:
 764         kfree(p);
 765         goto out;
 766 }
 767
 768 static int __devinit us3mc_probe(struct of_device *op,
 769                                 const struct of_device_id *match)
 770 {
 771         if (mc_type == MC_TYPE_SAFARI)
 772                 return chmc_probe(op, match);
 773         else if (mc_type == MC_TYPE_JBUS)
 774                 return jbusmc_probe(op, match);
 775         return -ENODEV;
 776 }
 777
 778 static void __devexit chmc_destroy(struct of_device *op, struct chmc *p)
 779 {
 780         list_del(&p->list);
 781         of_iounmap(&op->resource[0], p->regs, 0x48);
 782         kfree(p);
 783 }
 784
 785 static void __devexit jbusmc_destroy(struct of_device *op, struct jbusmc *p)
 786 {
 787         mc_list_del(&p->list);
 788         of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
 789         kfree(p);
 790 }
 791
 792 static int __devexit us3mc_remove(struct of_device *op)
 793 {
 794         void *p = dev_get_drvdata(&op->dev);
 795
 796         if (p) {
 797                 if (mc_type == MC_TYPE_SAFARI)
 798                         chmc_destroy(op, p);
 799                 else if (mc_type == MC_TYPE_JBUS)
 800                         jbusmc_destroy(op, p);
 801         }
 802         return 0;
 803 }
 804
 805 static const struct of_device_id us3mc_match[] = {
 806         {
 807                 .name = "memory-controller",
 808         },
 809         {},
 810 };
 811 MODULE_DEVICE_TABLE(of, us3mc_match);
 812
 813 static struct of_platform_driver us3mc_driver = {
 814         .name           = "us3mc",
 815         .match_table    = us3mc_match,
 816         .probe          = us3mc_probe,
 817         .remove         = __devexit_p(us3mc_remove),
 818 };
 819
 820 static inline bool us3mc_platform(void)
 821 {
 822         if (tlb_type == cheetah || tlb_type == cheetah_plus)
 823                 return true;
 824         return false;
 825 }
 826
 827 static int __init us3mc_init(void)
 828 {
 829         unsigned long ver;
 830         int ret;
 831
 832         if (!us3mc_platform())
 833                 return -ENODEV;
 834
 835         __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
 836         if ((ver >> 32UL) == __JALAPENO_ID ||
 837             (ver >> 32UL) == __SERRANO_ID) {
 838                 mc_type = MC_TYPE_JBUS;
 839                 us3mc_dimm_printer = jbusmc_print_dimm;
 840         } else {
 841                 mc_type = MC_TYPE_SAFARI;
 842                 us3mc_dimm_printer = chmc_print_dimm;
 843         }
 844
 845         ret = register_dimm_printer(us3mc_dimm_printer);
 846
 847         if (!ret) {
 848                 ret = of_register_driver(&us3mc_driver, &of_bus_type);
 849                 if (ret)
 850                         unregister_dimm_printer(us3mc_dimm_printer);
 851         }
 852         return ret;
 853 }
 854
 855 static void __exit us3mc_cleanup(void)
 856 {
 857         if (us3mc_platform()) {
 858                 unregister_dimm_printer(us3mc_dimm_printer);
 859                 of_unregister_driver(&us3mc_driver);
 860         }
 861 }
 862
 863 module_init(us3mc_init);
 864 module_exit(us3mc_cleanup);