git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/ip.h>
  38 #include <linux/tcp.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <net/checksum.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC64
  51 #include <asm/idprom.h>
  52 #include <asm/oplib.h>
  53 #include <asm/pbm.h>
  54 #endif
  55
  56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  57 #define TG3_VLAN_TAG_USED 1
  58 #else
  59 #define TG3_VLAN_TAG_USED 0
  60 #endif
  61
  62 #ifdef NETIF_F_TSO
  63 #define TG3_TSO_SUPPORT 1
  64 #else
  65 #define TG3_TSO_SUPPORT 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define PFX DRV_MODULE_NAME     ": "
  72 #define DRV_MODULE_VERSION      "3.60"
  73 #define DRV_MODULE_RELDATE      "June 17, 2006"
  74
  75 #define TG3_DEF_MAC_MODE        0
  76 #define TG3_DEF_RX_MODE         0
  77 #define TG3_DEF_TX_MODE         0
  78 #define TG3_DEF_MSG_ENABLE        \
  79         (NETIF_MSG_DRV          | \
  80          NETIF_MSG_PROBE        | \
  81          NETIF_MSG_LINK         | \
  82          NETIF_MSG_TIMER        | \
  83          NETIF_MSG_IFDOWN       | \
  84          NETIF_MSG_IFUP         | \
  85          NETIF_MSG_RX_ERR       | \
  86          NETIF_MSG_TX_ERR)
  87
  88 /* length of time before we decide the hardware is borked,
  89  * and dev->tx_timeout() should be called to fix the problem
  90  */
  91 #define TG3_TX_TIMEOUT                  (5 * HZ)
  92
  93 /* hardware minimum and maximum for a single frame's data payload */
  94 #define TG3_MIN_MTU                     60
  95 #define TG3_MAX_MTU(tp) \
  96         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  97
  98 /* These numbers seem to be hard coded in the NIC firmware somehow.
  99  * You can't change the ring sizes, but you can change where you place
 100  * them in the NIC onboard memory.
 101  */
 102 #define TG3_RX_RING_SIZE                512
 103 #define TG3_DEF_RX_RING_PENDING         200
 104 #define TG3_RX_JUMBO_RING_SIZE          256
 105 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                    TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define TX_BUFFS_AVAIL(TP)                                              \
 128         ((TP)->tx_pending -                                             \
 129          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
 130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 131
 132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 134
 135 /* minimum number of free TX descriptors required to wake up TX process */
 136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 137
 138 /* number of ETHTOOL_GSTATS u64's */
 139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 140
 141 #define TG3_NUM_TEST            6
 142
 143 static char version[] __devinitdata =
 144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 145
 146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 148 MODULE_LICENSE("GPL");
 149 MODULE_VERSION(DRV_MODULE_VERSION);
 150
 151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 152 module_param(tg3_debug, int, 0);
 153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 154
 155 static struct pci_device_id tg3_pci_tbl[] = {
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
 241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 242         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
 243           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 244         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
 245           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 246         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 247           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 248         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 249           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 250         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 251           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 252         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 253           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 254         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 255           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 256         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 257           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 258         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 259           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 260         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 261           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 262         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 263           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 264         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 265           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 266         { 0, }
 267 };
 268
 269 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 270
 271 static struct {
 272         const char string[ETH_GSTRING_LEN];
 273 } ethtool_stats_keys[TG3_NUM_STATS] = {
 274         { "rx_octets" },
 275         { "rx_fragments" },
 276         { "rx_ucast_packets" },
 277         { "rx_mcast_packets" },
 278         { "rx_bcast_packets" },
 279         { "rx_fcs_errors" },
 280         { "rx_align_errors" },
 281         { "rx_xon_pause_rcvd" },
 282         { "rx_xoff_pause_rcvd" },
 283         { "rx_mac_ctrl_rcvd" },
 284         { "rx_xoff_entered" },
 285         { "rx_frame_too_long_errors" },
 286         { "rx_jabbers" },
 287         { "rx_undersize_packets" },
 288         { "rx_in_length_errors" },
 289         { "rx_out_length_errors" },
 290         { "rx_64_or_less_octet_packets" },
 291         { "rx_65_to_127_octet_packets" },
 292         { "rx_128_to_255_octet_packets" },
 293         { "rx_256_to_511_octet_packets" },
 294         { "rx_512_to_1023_octet_packets" },
 295         { "rx_1024_to_1522_octet_packets" },
 296         { "rx_1523_to_2047_octet_packets" },
 297         { "rx_2048_to_4095_octet_packets" },
 298         { "rx_4096_to_8191_octet_packets" },
 299         { "rx_8192_to_9022_octet_packets" },
 300
 301         { "tx_octets" },
 302         { "tx_collisions" },
 303
 304         { "tx_xon_sent" },
 305         { "tx_xoff_sent" },
 306         { "tx_flow_control" },
 307         { "tx_mac_errors" },
 308         { "tx_single_collisions" },
 309         { "tx_mult_collisions" },
 310         { "tx_deferred" },
 311         { "tx_excessive_collisions" },
 312         { "tx_late_collisions" },
 313         { "tx_collide_2times" },
 314         { "tx_collide_3times" },
 315         { "tx_collide_4times" },
 316         { "tx_collide_5times" },
 317         { "tx_collide_6times" },
 318         { "tx_collide_7times" },
 319         { "tx_collide_8times" },
 320         { "tx_collide_9times" },
 321         { "tx_collide_10times" },
 322         { "tx_collide_11times" },
 323         { "tx_collide_12times" },
 324         { "tx_collide_13times" },
 325         { "tx_collide_14times" },
 326         { "tx_collide_15times" },
 327         { "tx_ucast_packets" },
 328         { "tx_mcast_packets" },
 329         { "tx_bcast_packets" },
 330         { "tx_carrier_sense_errors" },
 331         { "tx_discards" },
 332         { "tx_errors" },
 333
 334         { "dma_writeq_full" },
 335         { "dma_write_prioq_full" },
 336         { "rxbds_empty" },
 337         { "rx_discards" },
 338         { "rx_errors" },
 339         { "rx_threshold_hit" },
 340
 341         { "dma_readq_full" },
 342         { "dma_read_prioq_full" },
 343         { "tx_comp_queue_full" },
 344
 345         { "ring_set_send_prod_index" },
 346         { "ring_status_update" },
 347         { "nic_irqs" },
 348         { "nic_avoided_irqs" },
 349         { "nic_tx_threshold_hit" }
 350 };
 351
 352 static struct {
 353         const char string[ETH_GSTRING_LEN];
 354 } ethtool_test_keys[TG3_NUM_TEST] = {
 355         { "nvram test     (online) " },
 356         { "link test      (online) " },
 357         { "register test  (offline)" },
 358         { "memory test    (offline)" },
 359         { "loopback test  (offline)" },
 360         { "interrupt test (offline)" },
 361 };
 362
 363 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 364 {
 365         writel(val, tp->regs + off);
 366 }
 367
 368 static u32 tg3_read32(struct tg3 *tp, u32 off)
 369 {
 370         return (readl(tp->regs + off));
 371 }
 372
 373 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 374 {
 375         unsigned long flags;
 376
 377         spin_lock_irqsave(&tp->indirect_lock, flags);
 378         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 380         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 381 }
 382
 383 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 384 {
 385         writel(val, tp->regs + off);
 386         readl(tp->regs + off);
 387 }
 388
 389 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 390 {
 391         unsigned long flags;
 392         u32 val;
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 396         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398         return val;
 399 }
 400
 401 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         unsigned long flags;
 404
 405         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 406                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 407                                        TG3_64BIT_REG_LOW, val);
 408                 return;
 409         }
 410         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 411                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 412                                        TG3_64BIT_REG_LOW, val);
 413                 return;
 414         }
 415
 416         spin_lock_irqsave(&tp->indirect_lock, flags);
 417         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 418         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 419         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 420
 421         /* In indirect mode when disabling interrupts, we also need
 422          * to clear the interrupt bit in the GRC local ctrl register.
 423          */
 424         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 425             (val == 0x1)) {
 426                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 427                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 428         }
 429 }
 430
 431 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 432 {
 433         unsigned long flags;
 434         u32 val;
 435
 436         spin_lock_irqsave(&tp->indirect_lock, flags);
 437         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 438         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 439         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 440         return val;
 441 }
 442
 443 /* usec_wait specifies the wait time in usec when writing to certain registers
 444  * where it is unsafe to read back the register without some delay.
 445  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 446  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 447  */
 448 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 449 {
 450         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 451             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 452                 /* Non-posted methods */
 453                 tp->write32(tp, off, val);
 454         else {
 455                 /* Posted method */
 456                 tg3_write32(tp, off, val);
 457                 if (usec_wait)
 458                         udelay(usec_wait);
 459                 tp->read32(tp, off);
 460         }
 461         /* Wait again after the read for the posted method to guarantee that
 462          * the wait time is met.
 463          */
 464         if (usec_wait)
 465                 udelay(usec_wait);
 466 }
 467
 468 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 469 {
 470         tp->write32_mbox(tp, off, val);
 471         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 472             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 473                 tp->read32_mbox(tp, off);
 474 }
 475
 476 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 477 {
 478         void __iomem *mbox = tp->regs + off;
 479         writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 481                 writel(val, mbox);
 482         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 483                 readl(mbox);
 484 }
 485
 486 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 487 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 488 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 489 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 490 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 491
 492 #define tw32(reg,val)           tp->write32(tp, reg, val)
 493 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 494 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 495 #define tr32(reg)               tp->read32(tp, reg)
 496
 497 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 498 {
 499         unsigned long flags;
 500
 501         spin_lock_irqsave(&tp->indirect_lock, flags);
 502         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 503                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 505
 506                 /* Always leave this as zero. */
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 508         } else {
 509                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 510                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 511
 512                 /* Always leave this as zero. */
 513                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 514         }
 515         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 516 }
 517
 518 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 519 {
 520         unsigned long flags;
 521
 522         spin_lock_irqsave(&tp->indirect_lock, flags);
 523         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 524                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 525                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 526
 527                 /* Always leave this as zero. */
 528                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 529         } else {
 530                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 531                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 532
 533                 /* Always leave this as zero. */
 534                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 535         }
 536         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 537 }
 538
 539 static void tg3_disable_ints(struct tg3 *tp)
 540 {
 541         tw32(TG3PCI_MISC_HOST_CTRL,
 542              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 543         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 544 }
 545
 546 static inline void tg3_cond_int(struct tg3 *tp)
 547 {
 548         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 549             (tp->hw_status->status & SD_STATUS_UPDATED))
 550                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 551 }
 552
 553 static void tg3_enable_ints(struct tg3 *tp)
 554 {
 555         tp->irq_sync = 0;
 556         wmb();
 557
 558         tw32(TG3PCI_MISC_HOST_CTRL,
 559              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 560         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                        (tp->last_tag << 24));
 562         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 563                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 564                                (tp->last_tag << 24));
 565         tg3_cond_int(tp);
 566 }
 567
 568 static inline unsigned int tg3_has_work(struct tg3 *tp)
 569 {
 570         struct tg3_hw_status *sblk = tp->hw_status;
 571         unsigned int work_exists = 0;
 572
 573         /* check for phy events */
 574         if (!(tp->tg3_flags &
 575               (TG3_FLAG_USE_LINKCHG_REG |
 576                TG3_FLAG_POLL_SERDES))) {
 577                 if (sblk->status & SD_STATUS_LINK_CHG)
 578                         work_exists = 1;
 579         }
 580         /* check for RX/TX work to do */
 581         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 582             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 583                 work_exists = 1;
 584
 585         return work_exists;
 586 }
 587
 588 /* tg3_restart_ints
 589  *  similar to tg3_enable_ints, but it accurately determines whether there
 590  *  is new work pending and can return without flushing the PIO write
 591  *  which reenables interrupts
 592  */
 593 static void tg3_restart_ints(struct tg3 *tp)
 594 {
 595         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 596                      tp->last_tag << 24);
 597         mmiowb();
 598
 599         /* When doing tagged status, this work check is unnecessary.
 600          * The last_tag we write above tells the chip which piece of
 601          * work we've completed.
 602          */
 603         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 604             tg3_has_work(tp))
 605                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 606                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 607 }
 608
 609 static inline void tg3_netif_stop(struct tg3 *tp)
 610 {
 611         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 612         netif_poll_disable(tp->dev);
 613         netif_tx_disable(tp->dev);
 614 }
 615
 616 static inline void tg3_netif_start(struct tg3 *tp)
 617 {
 618         netif_wake_queue(tp->dev);
 619         /* NOTE: unconditional netif_wake_queue is only appropriate
 620          * so long as all callers are assured to have free tx slots
 621          * (such as after tg3_init_hw)
 622          */
 623         netif_poll_enable(tp->dev);
 624         tp->hw_status->status |= SD_STATUS_UPDATED;
 625         tg3_enable_ints(tp);
 626 }
 627
 628 static void tg3_switch_clocks(struct tg3 *tp)
 629 {
 630         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 631         u32 orig_clock_ctrl;
 632
 633         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 634                 return;
 635
 636         orig_clock_ctrl = clock_ctrl;
 637         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 638                        CLOCK_CTRL_CLKRUN_OENABLE |
 639                        0x1f);
 640         tp->pci_clock_ctrl = clock_ctrl;
 641
 642         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 643                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 644                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 645                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 646                 }
 647         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 648                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 649                             clock_ctrl |
 650                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 651                             40);
 652                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 653                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 654                             40);
 655         }
 656         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 657 }
 658
 659 #define PHY_BUSY_LOOPS  5000
 660
 661 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 662 {
 663         u32 frame_val;
 664         unsigned int loops;
 665         int ret;
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE,
 669                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 670                 udelay(80);
 671         }
 672
 673         *val = 0x0;
 674
 675         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 676                       MI_COM_PHY_ADDR_MASK);
 677         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 678                       MI_COM_REG_ADDR_MASK);
 679         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 680
 681         tw32_f(MAC_MI_COM, frame_val);
 682
 683         loops = PHY_BUSY_LOOPS;
 684         while (loops != 0) {
 685                 udelay(10);
 686                 frame_val = tr32(MAC_MI_COM);
 687
 688                 if ((frame_val & MI_COM_BUSY) == 0) {
 689                         udelay(5);
 690                         frame_val = tr32(MAC_MI_COM);
 691                         break;
 692                 }
 693                 loops -= 1;
 694         }
 695
 696         ret = -EBUSY;
 697         if (loops != 0) {
 698                 *val = frame_val & MI_COM_DATA_MASK;
 699                 ret = 0;
 700         }
 701
 702         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 703                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 704                 udelay(80);
 705         }
 706
 707         return ret;
 708 }
 709
 710 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 711 {
 712         u32 frame_val;
 713         unsigned int loops;
 714         int ret;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE,
 718                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 719                 udelay(80);
 720         }
 721
 722         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 723                       MI_COM_PHY_ADDR_MASK);
 724         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 725                       MI_COM_REG_ADDR_MASK);
 726         frame_val |= (val & MI_COM_DATA_MASK);
 727         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 728
 729         tw32_f(MAC_MI_COM, frame_val);
 730
 731         loops = PHY_BUSY_LOOPS;
 732         while (loops != 0) {
 733                 udelay(10);
 734                 frame_val = tr32(MAC_MI_COM);
 735                 if ((frame_val & MI_COM_BUSY) == 0) {
 736                         udelay(5);
 737                         frame_val = tr32(MAC_MI_COM);
 738                         break;
 739                 }
 740                 loops -= 1;
 741         }
 742
 743         ret = -EBUSY;
 744         if (loops != 0)
 745                 ret = 0;
 746
 747         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 748                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 749                 udelay(80);
 750         }
 751
 752         return ret;
 753 }
 754
 755 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 756 {
 757         u32 val;
 758
 759         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 760                 return;
 761
 762         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 763             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 764                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 765                              (val | (1 << 15) | (1 << 4)));
 766 }
 767
 768 static int tg3_bmcr_reset(struct tg3 *tp)
 769 {
 770         u32 phy_control;
 771         int limit, err;
 772
 773         /* OK, reset it, and poll the BMCR_RESET bit until it
 774          * clears or we time out.
 775          */
 776         phy_control = BMCR_RESET;
 777         err = tg3_writephy(tp, MII_BMCR, phy_control);
 778         if (err != 0)
 779                 return -EBUSY;
 780
 781         limit = 5000;
 782         while (limit--) {
 783                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 784                 if (err != 0)
 785                         return -EBUSY;
 786
 787                 if ((phy_control & BMCR_RESET) == 0) {
 788                         udelay(40);
 789                         break;
 790                 }
 791                 udelay(10);
 792         }
 793         if (limit <= 0)
 794                 return -EBUSY;
 795
 796         return 0;
 797 }
 798
 799 static int tg3_wait_macro_done(struct tg3 *tp)
 800 {
 801         int limit = 100;
 802
 803         while (limit--) {
 804                 u32 tmp32;
 805
 806                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 807                         if ((tmp32 & 0x1000) == 0)
 808                                 break;
 809                 }
 810         }
 811         if (limit <= 0)
 812                 return -EBUSY;
 813
 814         return 0;
 815 }
 816
 817 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 818 {
 819         static const u32 test_pat[4][6] = {
 820         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 821         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 822         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 823         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 824         };
 825         int chan;
 826
 827         for (chan = 0; chan < 4; chan++) {
 828                 int i;
 829
 830                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 831                              (chan * 0x2000) | 0x0200);
 832                 tg3_writephy(tp, 0x16, 0x0002);
 833
 834                 for (i = 0; i < 6; i++)
 835                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 836                                      test_pat[chan][i]);
 837
 838                 tg3_writephy(tp, 0x16, 0x0202);
 839                 if (tg3_wait_macro_done(tp)) {
 840                         *resetp = 1;
 841                         return -EBUSY;
 842                 }
 843
 844                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 845                              (chan * 0x2000) | 0x0200);
 846                 tg3_writephy(tp, 0x16, 0x0082);
 847                 if (tg3_wait_macro_done(tp)) {
 848                         *resetp = 1;
 849                         return -EBUSY;
 850                 }
 851
 852                 tg3_writephy(tp, 0x16, 0x0802);
 853                 if (tg3_wait_macro_done(tp)) {
 854                         *resetp = 1;
 855                         return -EBUSY;
 856                 }
 857
 858                 for (i = 0; i < 6; i += 2) {
 859                         u32 low, high;
 860
 861                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 862                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 863                             tg3_wait_macro_done(tp)) {
 864                                 *resetp = 1;
 865                                 return -EBUSY;
 866                         }
 867                         low &= 0x7fff;
 868                         high &= 0x000f;
 869                         if (low != test_pat[chan][i] ||
 870                             high != test_pat[chan][i+1]) {
 871                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 872                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 873                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 874
 875                                 return -EBUSY;
 876                         }
 877                 }
 878         }
 879
 880         return 0;
 881 }
 882
 883 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 884 {
 885         int chan;
 886
 887         for (chan = 0; chan < 4; chan++) {
 888                 int i;
 889
 890                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 891                              (chan * 0x2000) | 0x0200);
 892                 tg3_writephy(tp, 0x16, 0x0002);
 893                 for (i = 0; i < 6; i++)
 894                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 895                 tg3_writephy(tp, 0x16, 0x0202);
 896                 if (tg3_wait_macro_done(tp))
 897                         return -EBUSY;
 898         }
 899
 900         return 0;
 901 }
 902
 903 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 904 {
 905         u32 reg32, phy9_orig;
 906         int retries, do_phy_reset, err;
 907
 908         retries = 10;
 909         do_phy_reset = 1;
 910         do {
 911                 if (do_phy_reset) {
 912                         err = tg3_bmcr_reset(tp);
 913                         if (err)
 914                                 return err;
 915                         do_phy_reset = 0;
 916                 }
 917
 918                 /* Disable transmitter and interrupt.  */
 919                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 920                         continue;
 921
 922                 reg32 |= 0x3000;
 923                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 924
 925                 /* Set full-duplex, 1000 mbps.  */
 926                 tg3_writephy(tp, MII_BMCR,
 927                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 928
 929                 /* Set to master mode.  */
 930                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 931                         continue;
 932
 933                 tg3_writephy(tp, MII_TG3_CTRL,
 934                              (MII_TG3_CTRL_AS_MASTER |
 935                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 936
 937                 /* Enable SM_DSP_CLOCK and 6dB.  */
 938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 939
 940                 /* Block the PHY control access.  */
 941                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 942                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 943
 944                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 945                 if (!err)
 946                         break;
 947         } while (--retries);
 948
 949         err = tg3_phy_reset_chanpat(tp);
 950         if (err)
 951                 return err;
 952
 953         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 954         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 955
 956         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 957         tg3_writephy(tp, 0x16, 0x0000);
 958
 959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 960             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 961                 /* Set Extended packet length bit for jumbo frames */
 962                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 963         }
 964         else {
 965                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 966         }
 967
 968         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 969
 970         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 971                 reg32 &= ~0x3000;
 972                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 973         } else if (!err)
 974                 err = -EBUSY;
 975
 976         return err;
 977 }
 978
 979 static void tg3_link_report(struct tg3 *);
 980
 981 /* This will reset the tigon3 PHY if there is no valid
 982  * link unless the FORCE argument is non-zero.
 983  */
 984 static int tg3_phy_reset(struct tg3 *tp)
 985 {
 986         u32 phy_status;
 987         int err;
 988
 989         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 990         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 991         if (err != 0)
 992                 return -EBUSY;
 993
 994         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 995                 netif_carrier_off(tp->dev);
 996                 tg3_link_report(tp);
 997         }
 998
 999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1002                 err = tg3_phy_reset_5703_4_5(tp);
1003                 if (err)
1004                         return err;
1005                 goto out;
1006         }
1007
1008         err = tg3_bmcr_reset(tp);
1009         if (err)
1010                 return err;
1011
1012 out:
1013         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1015                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1016                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1017                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1018                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1019                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1020         }
1021         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1022                 tg3_writephy(tp, 0x1c, 0x8d68);
1023                 tg3_writephy(tp, 0x1c, 0x8d68);
1024         }
1025         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1027                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1028                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1031                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1032                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1033                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1034         }
1035         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1036                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1037                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1038                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1039                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1040         }
1041         /* Set Extended packet length bit (bit 14) on all chips that */
1042         /* support jumbo frames */
1043         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1044                 /* Cannot do read-modify-write on 5401 */
1045                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1046         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1047                 u32 phy_reg;
1048
1049                 /* Set bit 14 with read-modify-write to preserve other bits */
1050                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1051                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1052                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1053         }
1054
1055         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1056          * jumbo frames transmission.
1057          */
1058         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1059                 u32 phy_reg;
1060
1061                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1062                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1063                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1064         }
1065
1066         tg3_phy_set_wirespeed(tp);
1067         return 0;
1068 }
1069
1070 static void tg3_frob_aux_power(struct tg3 *tp)
1071 {
1072         struct tg3 *tp_peer = tp;
1073
1074         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1075                 return;
1076
1077         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1078             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1079                 struct net_device *dev_peer;
1080
1081                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1082                 /* remove_one() may have been run on the peer. */
1083                 if (!dev_peer)
1084                         tp_peer = tp;
1085                 else
1086                         tp_peer = netdev_priv(dev_peer);
1087         }
1088
1089         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1092             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1094                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1095                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1096                                     (GRC_LCLCTRL_GPIO_OE0 |
1097                                      GRC_LCLCTRL_GPIO_OE1 |
1098                                      GRC_LCLCTRL_GPIO_OE2 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1100                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1101                                     100);
1102                 } else {
1103                         u32 no_gpio2;
1104                         u32 grc_local_ctrl = 0;
1105
1106                         if (tp_peer != tp &&
1107                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1108                                 return;
1109
1110                         /* Workaround to prevent overdrawing Amps. */
1111                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1112                             ASIC_REV_5714) {
1113                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1114                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1115                                             grc_local_ctrl, 100);
1116                         }
1117
1118                         /* On 5753 and variants, GPIO2 cannot be used. */
1119                         no_gpio2 = tp->nic_sram_data_cfg &
1120                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1121
1122                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1123                                          GRC_LCLCTRL_GPIO_OE1 |
1124                                          GRC_LCLCTRL_GPIO_OE2 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1126                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1127                         if (no_gpio2) {
1128                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1129                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1130                         }
1131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132                                                     grc_local_ctrl, 100);
1133
1134                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1135
1136                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1137                                                     grc_local_ctrl, 100);
1138
1139                         if (!no_gpio2) {
1140                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1141                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1142                                             grc_local_ctrl, 100);
1143                         }
1144                 }
1145         } else {
1146                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1147                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1148                         if (tp_peer != tp &&
1149                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1150                                 return;
1151
1152                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1153                                     (GRC_LCLCTRL_GPIO_OE1 |
1154                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1155
1156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157                                     GRC_LCLCTRL_GPIO_OE1, 100);
1158
1159                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1160                                     (GRC_LCLCTRL_GPIO_OE1 |
1161                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1162                 }
1163         }
1164 }
1165
1166 static int tg3_setup_phy(struct tg3 *, int);
1167
1168 #define RESET_KIND_SHUTDOWN     0
1169 #define RESET_KIND_INIT         1
1170 #define RESET_KIND_SUSPEND      2
1171
1172 static void tg3_write_sig_post_reset(struct tg3 *, int);
1173 static int tg3_halt_cpu(struct tg3 *, u32);
1174 static int tg3_nvram_lock(struct tg3 *);
1175 static void tg3_nvram_unlock(struct tg3 *);
1176
1177 static void tg3_power_down_phy(struct tg3 *tp)
1178 {
1179         /* The PHY should not be powered down on some chips because
1180          * of bugs.
1181          */
1182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1183             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1184             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1185              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1186                 return;
1187         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1188 }
1189
1190 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1191 {
1192         u32 misc_host_ctrl;
1193         u16 power_control, power_caps;
1194         int pm = tp->pm_cap;
1195
1196         /* Make sure register accesses (indirect or otherwise)
1197          * will function correctly.
1198          */
1199         pci_write_config_dword(tp->pdev,
1200                                TG3PCI_MISC_HOST_CTRL,
1201                                tp->misc_host_ctrl);
1202
1203         pci_read_config_word(tp->pdev,
1204                              pm + PCI_PM_CTRL,
1205                              &power_control);
1206         power_control |= PCI_PM_CTRL_PME_STATUS;
1207         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1208         switch (state) {
1209         case PCI_D0:
1210                 power_control |= 0;
1211                 pci_write_config_word(tp->pdev,
1212                                       pm + PCI_PM_CTRL,
1213                                       power_control);
1214                 udelay(100);    /* Delay after power state change */
1215
1216                 /* Switch out of Vaux if it is not a LOM */
1217                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1218                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1219
1220                 return 0;
1221
1222         case PCI_D1:
1223                 power_control |= 1;
1224                 break;
1225
1226         case PCI_D2:
1227                 power_control |= 2;
1228                 break;
1229
1230         case PCI_D3hot:
1231                 power_control |= 3;
1232                 break;
1233
1234         default:
1235                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1236                        "requested.\n",
1237                        tp->dev->name, state);
1238                 return -EINVAL;
1239         };
1240
1241         power_control |= PCI_PM_CTRL_PME_ENABLE;
1242
1243         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1244         tw32(TG3PCI_MISC_HOST_CTRL,
1245              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1246
1247         if (tp->link_config.phy_is_low_power == 0) {
1248                 tp->link_config.phy_is_low_power = 1;
1249                 tp->link_config.orig_speed = tp->link_config.speed;
1250                 tp->link_config.orig_duplex = tp->link_config.duplex;
1251                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1252         }
1253
1254         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1255                 tp->link_config.speed = SPEED_10;
1256                 tp->link_config.duplex = DUPLEX_HALF;
1257                 tp->link_config.autoneg = AUTONEG_ENABLE;
1258                 tg3_setup_phy(tp, 0);
1259         }
1260
1261         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1262                 int i;
1263                 u32 val;
1264
1265                 for (i = 0; i < 200; i++) {
1266                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1267                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1268                                 break;
1269                         msleep(1);
1270                 }
1271         }
1272         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1273                                              WOL_DRV_STATE_SHUTDOWN |
1274                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1275
1276         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1277
1278         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1279                 u32 mac_mode;
1280
1281                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1282                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1283                         udelay(40);
1284
1285                         mac_mode = MAC_MODE_PORT_MODE_MII;
1286
1287                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1288                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1289                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1290                 } else {
1291                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1292                 }
1293
1294                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1295                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1296
1297                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1298                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1299                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1300
1301                 tw32_f(MAC_MODE, mac_mode);
1302                 udelay(100);
1303
1304                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1305                 udelay(10);
1306         }
1307
1308         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1309             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1310              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1311                 u32 base_val;
1312
1313                 base_val = tp->pci_clock_ctrl;
1314                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1315                              CLOCK_CTRL_TXCLK_DISABLE);
1316
1317                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1318                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1319         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1320                 /* do nothing */
1321         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1322                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1323                 u32 newbits1, newbits2;
1324
1325                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1326                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1327                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1328                                     CLOCK_CTRL_TXCLK_DISABLE |
1329                                     CLOCK_CTRL_ALTCLK);
1330                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1331                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1332                         newbits1 = CLOCK_CTRL_625_CORE;
1333                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1334                 } else {
1335                         newbits1 = CLOCK_CTRL_ALTCLK;
1336                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1337                 }
1338
1339                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1340                             40);
1341
1342                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1343                             40);
1344
1345                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1346                         u32 newbits3;
1347
1348                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1349                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1350                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1351                                             CLOCK_CTRL_TXCLK_DISABLE |
1352                                             CLOCK_CTRL_44MHZ_CORE);
1353                         } else {
1354                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1355                         }
1356
1357                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1358                                     tp->pci_clock_ctrl | newbits3, 40);
1359                 }
1360         }
1361
1362         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1363             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1364                 /* Turn off the PHY */
1365                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1366                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1367                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1368                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1369                         tg3_power_down_phy(tp);
1370                 }
1371         }
1372
1373         tg3_frob_aux_power(tp);
1374
1375         /* Workaround for unstable PLL clock */
1376         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1377             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1378                 u32 val = tr32(0x7d00);
1379
1380                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1381                 tw32(0x7d00, val);
1382                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1383                         int err;
1384
1385                         err = tg3_nvram_lock(tp);
1386                         tg3_halt_cpu(tp, RX_CPU_BASE);
1387                         if (!err)
1388                                 tg3_nvram_unlock(tp);
1389                 }
1390         }
1391
1392         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1393
1394         /* Finally, set the new power state. */
1395         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1396         udelay(100);    /* Delay after power state change */
1397
1398         return 0;
1399 }
1400
1401 static void tg3_link_report(struct tg3 *tp)
1402 {
1403         if (!netif_carrier_ok(tp->dev)) {
1404                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1405         } else {
1406                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1407                        tp->dev->name,
1408                        (tp->link_config.active_speed == SPEED_1000 ?
1409                         1000 :
1410                         (tp->link_config.active_speed == SPEED_100 ?
1411                          100 : 10)),
1412                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1413                         "full" : "half"));
1414
1415                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1416                        "%s for RX.\n",
1417                        tp->dev->name,
1418                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1419                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1420         }
1421 }
1422
1423 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1424 {
1425         u32 new_tg3_flags = 0;
1426         u32 old_rx_mode = tp->rx_mode;
1427         u32 old_tx_mode = tp->tx_mode;
1428
1429         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1430
1431                 /* Convert 1000BaseX flow control bits to 1000BaseT
1432                  * bits before resolving flow control.
1433                  */
1434                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1435                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1436                                        ADVERTISE_PAUSE_ASYM);
1437                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1438
1439                         if (local_adv & ADVERTISE_1000XPAUSE)
1440                                 local_adv |= ADVERTISE_PAUSE_CAP;
1441                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1442                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1443                         if (remote_adv & LPA_1000XPAUSE)
1444                                 remote_adv |= LPA_PAUSE_CAP;
1445                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1446                                 remote_adv |= LPA_PAUSE_ASYM;
1447                 }
1448
1449                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1450                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1451                                 if (remote_adv & LPA_PAUSE_CAP)
1452                                         new_tg3_flags |=
1453                                                 (TG3_FLAG_RX_PAUSE |
1454                                                 TG3_FLAG_TX_PAUSE);
1455                                 else if (remote_adv & LPA_PAUSE_ASYM)
1456                                         new_tg3_flags |=
1457                                                 (TG3_FLAG_RX_PAUSE);
1458                         } else {
1459                                 if (remote_adv & LPA_PAUSE_CAP)
1460                                         new_tg3_flags |=
1461                                                 (TG3_FLAG_RX_PAUSE |
1462                                                 TG3_FLAG_TX_PAUSE);
1463                         }
1464                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1465                         if ((remote_adv & LPA_PAUSE_CAP) &&
1466                         (remote_adv & LPA_PAUSE_ASYM))
1467                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1468                 }
1469
1470                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1471                 tp->tg3_flags |= new_tg3_flags;
1472         } else {
1473                 new_tg3_flags = tp->tg3_flags;
1474         }
1475
1476         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1477                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1478         else
1479                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1480
1481         if (old_rx_mode != tp->rx_mode) {
1482                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1483         }
1484
1485         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1486                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1487         else
1488                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1489
1490         if (old_tx_mode != tp->tx_mode) {
1491                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1492         }
1493 }
1494
1495 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1496 {
1497         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1498         case MII_TG3_AUX_STAT_10HALF:
1499                 *speed = SPEED_10;
1500                 *duplex = DUPLEX_HALF;
1501                 break;
1502
1503         case MII_TG3_AUX_STAT_10FULL:
1504                 *speed = SPEED_10;
1505                 *duplex = DUPLEX_FULL;
1506                 break;
1507
1508         case MII_TG3_AUX_STAT_100HALF:
1509                 *speed = SPEED_100;
1510                 *duplex = DUPLEX_HALF;
1511                 break;
1512
1513         case MII_TG3_AUX_STAT_100FULL:
1514                 *speed = SPEED_100;
1515                 *duplex = DUPLEX_FULL;
1516                 break;
1517
1518         case MII_TG3_AUX_STAT_1000HALF:
1519                 *speed = SPEED_1000;
1520                 *duplex = DUPLEX_HALF;
1521                 break;
1522
1523         case MII_TG3_AUX_STAT_1000FULL:
1524                 *speed = SPEED_1000;
1525                 *duplex = DUPLEX_FULL;
1526                 break;
1527
1528         default:
1529                 *speed = SPEED_INVALID;
1530                 *duplex = DUPLEX_INVALID;
1531                 break;
1532         };
1533 }
1534
1535 static void tg3_phy_copper_begin(struct tg3 *tp)
1536 {
1537         u32 new_adv;
1538         int i;
1539
1540         if (tp->link_config.phy_is_low_power) {
1541                 /* Entering low power mode.  Disable gigabit and
1542                  * 100baseT advertisements.
1543                  */
1544                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1545
1546                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1547                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1548                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1549                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1550
1551                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1552         } else if (tp->link_config.speed == SPEED_INVALID) {
1553                 tp->link_config.advertising =
1554                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1555                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1556                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1557                          ADVERTISED_Autoneg | ADVERTISED_MII);
1558
1559                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1560                         tp->link_config.advertising &=
1561                                 ~(ADVERTISED_1000baseT_Half |
1562                                   ADVERTISED_1000baseT_Full);
1563
1564                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1565                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1566                         new_adv |= ADVERTISE_10HALF;
1567                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1568                         new_adv |= ADVERTISE_10FULL;
1569                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1570                         new_adv |= ADVERTISE_100HALF;
1571                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1572                         new_adv |= ADVERTISE_100FULL;
1573                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1574
1575                 if (tp->link_config.advertising &
1576                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1577                         new_adv = 0;
1578                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1579                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1580                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1581                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1582                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1583                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1584                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1585                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1586                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1587                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1588                 } else {
1589                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1590                 }
1591         } else {
1592                 /* Asking for a specific link mode. */
1593                 if (tp->link_config.speed == SPEED_1000) {
1594                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1595                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1596
1597                         if (tp->link_config.duplex == DUPLEX_FULL)
1598                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1599                         else
1600                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1601                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1602                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1603                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1604                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1605                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1606                 } else {
1607                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1608
1609                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1610                         if (tp->link_config.speed == SPEED_100) {
1611                                 if (tp->link_config.duplex == DUPLEX_FULL)
1612                                         new_adv |= ADVERTISE_100FULL;
1613                                 else
1614                                         new_adv |= ADVERTISE_100HALF;
1615                         } else {
1616                                 if (tp->link_config.duplex == DUPLEX_FULL)
1617                                         new_adv |= ADVERTISE_10FULL;
1618                                 else
1619                                         new_adv |= ADVERTISE_10HALF;
1620                         }
1621                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1622                 }
1623         }
1624
1625         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1626             tp->link_config.speed != SPEED_INVALID) {
1627                 u32 bmcr, orig_bmcr;
1628
1629                 tp->link_config.active_speed = tp->link_config.speed;
1630                 tp->link_config.active_duplex = tp->link_config.duplex;
1631
1632                 bmcr = 0;
1633                 switch (tp->link_config.speed) {
1634                 default:
1635                 case SPEED_10:
1636                         break;
1637
1638                 case SPEED_100:
1639                         bmcr |= BMCR_SPEED100;
1640                         break;
1641
1642                 case SPEED_1000:
1643                         bmcr |= TG3_BMCR_SPEED1000;
1644                         break;
1645                 };
1646
1647                 if (tp->link_config.duplex == DUPLEX_FULL)
1648                         bmcr |= BMCR_FULLDPLX;
1649
1650                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1651                     (bmcr != orig_bmcr)) {
1652                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1653                         for (i = 0; i < 1500; i++) {
1654                                 u32 tmp;
1655
1656                                 udelay(10);
1657                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1658                                     tg3_readphy(tp, MII_BMSR, &tmp))
1659                                         continue;
1660                                 if (!(tmp & BMSR_LSTATUS)) {
1661                                         udelay(40);
1662                                         break;
1663                                 }
1664                         }
1665                         tg3_writephy(tp, MII_BMCR, bmcr);
1666                         udelay(40);
1667                 }
1668         } else {
1669                 tg3_writephy(tp, MII_BMCR,
1670                              BMCR_ANENABLE | BMCR_ANRESTART);
1671         }
1672 }
1673
1674 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1675 {
1676         int err;
1677
1678         /* Turn off tap power management. */
1679         /* Set Extended packet length bit */
1680         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1681
1682         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1683         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1684
1685         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1686         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1687
1688         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1689         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1690
1691         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1692         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1693
1694         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1695         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1696
1697         udelay(40);
1698
1699         return err;
1700 }
1701
1702 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1703 {
1704         u32 adv_reg, all_mask;
1705
1706         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1707                 return 0;
1708
1709         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1710                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1711         if ((adv_reg & all_mask) != all_mask)
1712                 return 0;
1713         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1714                 u32 tg3_ctrl;
1715
1716                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1717                         return 0;
1718
1719                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1720                             MII_TG3_CTRL_ADV_1000_FULL);
1721                 if ((tg3_ctrl & all_mask) != all_mask)
1722                         return 0;
1723         }
1724         return 1;
1725 }
1726
1727 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1728 {
1729         int current_link_up;
1730         u32 bmsr, dummy;
1731         u16 current_speed;
1732         u8 current_duplex;
1733         int i, err;
1734
1735         tw32(MAC_EVENT, 0);
1736
1737         tw32_f(MAC_STATUS,
1738              (MAC_STATUS_SYNC_CHANGED |
1739               MAC_STATUS_CFG_CHANGED |
1740               MAC_STATUS_MI_COMPLETION |
1741               MAC_STATUS_LNKSTATE_CHANGED));
1742         udelay(40);
1743
1744         tp->mi_mode = MAC_MI_MODE_BASE;
1745         tw32_f(MAC_MI_MODE, tp->mi_mode);
1746         udelay(80);
1747
1748         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1749
1750         /* Some third-party PHYs need to be reset on link going
1751          * down.
1752          */
1753         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1754              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1755              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1756             netif_carrier_ok(tp->dev)) {
1757                 tg3_readphy(tp, MII_BMSR, &bmsr);
1758                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1759                     !(bmsr & BMSR_LSTATUS))
1760                         force_reset = 1;
1761         }
1762         if (force_reset)
1763                 tg3_phy_reset(tp);
1764
1765         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1766                 tg3_readphy(tp, MII_BMSR, &bmsr);
1767                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1768                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1769                         bmsr = 0;
1770
1771                 if (!(bmsr & BMSR_LSTATUS)) {
1772                         err = tg3_init_5401phy_dsp(tp);
1773                         if (err)
1774                                 return err;
1775
1776                         tg3_readphy(tp, MII_BMSR, &bmsr);
1777                         for (i = 0; i < 1000; i++) {
1778                                 udelay(10);
1779                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1780                                     (bmsr & BMSR_LSTATUS)) {
1781                                         udelay(40);
1782                                         break;
1783                                 }
1784                         }
1785
1786                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1787                             !(bmsr & BMSR_LSTATUS) &&
1788                             tp->link_config.active_speed == SPEED_1000) {
1789                                 err = tg3_phy_reset(tp);
1790                                 if (!err)
1791                                         err = tg3_init_5401phy_dsp(tp);
1792                                 if (err)
1793                                         return err;
1794                         }
1795                 }
1796         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1797                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1798                 /* 5701 {A0,B0} CRC bug workaround */
1799                 tg3_writephy(tp, 0x15, 0x0a75);
1800                 tg3_writephy(tp, 0x1c, 0x8c68);
1801                 tg3_writephy(tp, 0x1c, 0x8d68);
1802                 tg3_writephy(tp, 0x1c, 0x8c68);
1803         }
1804
1805         /* Clear pending interrupts... */
1806         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1807         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1808
1809         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1810                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1811         else
1812                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1813
1814         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1815             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1816                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1817                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1818                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1819                 else
1820                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1821         }
1822
1823         current_link_up = 0;
1824         current_speed = SPEED_INVALID;
1825         current_duplex = DUPLEX_INVALID;
1826
1827         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1828                 u32 val;
1829
1830                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1831                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1832                 if (!(val & (1 << 10))) {
1833                         val |= (1 << 10);
1834                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1835                         goto relink;
1836                 }
1837         }
1838
1839         bmsr = 0;
1840         for (i = 0; i < 100; i++) {
1841                 tg3_readphy(tp, MII_BMSR, &bmsr);
1842                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1843                     (bmsr & BMSR_LSTATUS))
1844                         break;
1845                 udelay(40);
1846         }
1847
1848         if (bmsr & BMSR_LSTATUS) {
1849                 u32 aux_stat, bmcr;
1850
1851                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1852                 for (i = 0; i < 2000; i++) {
1853                         udelay(10);
1854                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1855                             aux_stat)
1856                                 break;
1857                 }
1858
1859                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1860                                              &current_speed,
1861                                              &current_duplex);
1862
1863                 bmcr = 0;
1864                 for (i = 0; i < 200; i++) {
1865                         tg3_readphy(tp, MII_BMCR, &bmcr);
1866                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1867                                 continue;
1868                         if (bmcr && bmcr != 0x7fff)
1869                                 break;
1870                         udelay(10);
1871                 }
1872
1873                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1874                         if (bmcr & BMCR_ANENABLE) {
1875                                 current_link_up = 1;
1876
1877                                 /* Force autoneg restart if we are exiting
1878                                  * low power mode.
1879                                  */
1880                                 if (!tg3_copper_is_advertising_all(tp))
1881                                         current_link_up = 0;
1882                         } else {
1883                                 current_link_up = 0;
1884                         }
1885                 } else {
1886                         if (!(bmcr & BMCR_ANENABLE) &&
1887                             tp->link_config.speed == current_speed &&
1888                             tp->link_config.duplex == current_duplex) {
1889                                 current_link_up = 1;
1890                         } else {
1891                                 current_link_up = 0;
1892                         }
1893                 }
1894
1895                 tp->link_config.active_speed = current_speed;
1896                 tp->link_config.active_duplex = current_duplex;
1897         }
1898
1899         if (current_link_up == 1 &&
1900             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1901             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1902                 u32 local_adv, remote_adv;
1903
1904                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1905                         local_adv = 0;
1906                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1907
1908                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1909                         remote_adv = 0;
1910
1911                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1912
1913                 /* If we are not advertising full pause capability,
1914                  * something is wrong.  Bring the link down and reconfigure.
1915                  */
1916                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1917                         current_link_up = 0;
1918                 } else {
1919                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1920                 }
1921         }
1922 relink:
1923         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1924                 u32 tmp;
1925
1926                 tg3_phy_copper_begin(tp);
1927
1928                 tg3_readphy(tp, MII_BMSR, &tmp);
1929                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1930                     (tmp & BMSR_LSTATUS))
1931                         current_link_up = 1;
1932         }
1933
1934         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1935         if (current_link_up == 1) {
1936                 if (tp->link_config.active_speed == SPEED_100 ||
1937                     tp->link_config.active_speed == SPEED_10)
1938                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1939                 else
1940                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1941         } else
1942                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1943
1944         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1945         if (tp->link_config.active_duplex == DUPLEX_HALF)
1946                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1947
1948         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1950                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1951                     (current_link_up == 1 &&
1952                      tp->link_config.active_speed == SPEED_10))
1953                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1954         } else {
1955                 if (current_link_up == 1)
1956                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1957         }
1958
1959         /* ??? Without this setting Netgear GA302T PHY does not
1960          * ??? send/receive packets...
1961          */
1962         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1963             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1964                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1965                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1966                 udelay(80);
1967         }
1968
1969         tw32_f(MAC_MODE, tp->mac_mode);
1970         udelay(40);
1971
1972         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1973                 /* Polled via timer. */
1974                 tw32_f(MAC_EVENT, 0);
1975         } else {
1976                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1977         }
1978         udelay(40);
1979
1980         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1981             current_link_up == 1 &&
1982             tp->link_config.active_speed == SPEED_1000 &&
1983             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1984              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1985                 udelay(120);
1986                 tw32_f(MAC_STATUS,
1987                      (MAC_STATUS_SYNC_CHANGED |
1988                       MAC_STATUS_CFG_CHANGED));
1989                 udelay(40);
1990                 tg3_write_mem(tp,
1991                               NIC_SRAM_FIRMWARE_MBOX,
1992                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1993         }
1994
1995         if (current_link_up != netif_carrier_ok(tp->dev)) {
1996                 if (current_link_up)
1997                         netif_carrier_on(tp->dev);
1998                 else
1999                         netif_carrier_off(tp->dev);
2000                 tg3_link_report(tp);
2001         }
2002
2003         return 0;
2004 }
2005
2006 struct tg3_fiber_aneginfo {
2007         int state;
2008 #define ANEG_STATE_UNKNOWN              0
2009 #define ANEG_STATE_AN_ENABLE            1
2010 #define ANEG_STATE_RESTART_INIT         2
2011 #define ANEG_STATE_RESTART              3
2012 #define ANEG_STATE_DISABLE_LINK_OK      4
2013 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2014 #define ANEG_STATE_ABILITY_DETECT       6
2015 #define ANEG_STATE_ACK_DETECT_INIT      7
2016 #define ANEG_STATE_ACK_DETECT           8
2017 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2018 #define ANEG_STATE_COMPLETE_ACK         10
2019 #define ANEG_STATE_IDLE_DETECT_INIT     11
2020 #define ANEG_STATE_IDLE_DETECT          12
2021 #define ANEG_STATE_LINK_OK              13
2022 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2023 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2024
2025         u32 flags;
2026 #define MR_AN_ENABLE            0x00000001
2027 #define MR_RESTART_AN           0x00000002
2028 #define MR_AN_COMPLETE          0x00000004
2029 #define MR_PAGE_RX              0x00000008
2030 #define MR_NP_LOADED            0x00000010
2031 #define MR_TOGGLE_TX            0x00000020
2032 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2033 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2034 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2035 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2036 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2037 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2038 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2039 #define MR_TOGGLE_RX            0x00002000
2040 #define MR_NP_RX                0x00004000
2041
2042 #define MR_LINK_OK              0x80000000
2043
2044         unsigned long link_time, cur_time;
2045
2046         u32 ability_match_cfg;
2047         int ability_match_count;
2048
2049         char ability_match, idle_match, ack_match;
2050
2051         u32 txconfig, rxconfig;
2052 #define ANEG_CFG_NP             0x00000080
2053 #define ANEG_CFG_ACK            0x00000040
2054 #define ANEG_CFG_RF2            0x00000020
2055 #define ANEG_CFG_RF1            0x00000010
2056 #define ANEG_CFG_PS2            0x00000001
2057 #define ANEG_CFG_PS1            0x00008000
2058 #define ANEG_CFG_HD             0x00004000
2059 #define ANEG_CFG_FD             0x00002000
2060 #define ANEG_CFG_INVAL          0x00001f06
2061
2062 };
2063 #define ANEG_OK         0
2064 #define ANEG_DONE       1
2065 #define ANEG_TIMER_ENAB 2
2066 #define ANEG_FAILED     -1
2067
2068 #define ANEG_STATE_SETTLE_TIME  10000
2069
2070 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2071                                    struct tg3_fiber_aneginfo *ap)
2072 {
2073         unsigned long delta;
2074         u32 rx_cfg_reg;
2075         int ret;
2076
2077         if (ap->state == ANEG_STATE_UNKNOWN) {
2078                 ap->rxconfig = 0;
2079                 ap->link_time = 0;
2080                 ap->cur_time = 0;
2081                 ap->ability_match_cfg = 0;
2082                 ap->ability_match_count = 0;
2083                 ap->ability_match = 0;
2084                 ap->idle_match = 0;
2085                 ap->ack_match = 0;
2086         }
2087         ap->cur_time++;
2088
2089         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2090                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2091
2092                 if (rx_cfg_reg != ap->ability_match_cfg) {
2093                         ap->ability_match_cfg = rx_cfg_reg;
2094                         ap->ability_match = 0;
2095                         ap->ability_match_count = 0;
2096                 } else {
2097                         if (++ap->ability_match_count > 1) {
2098                                 ap->ability_match = 1;
2099                                 ap->ability_match_cfg = rx_cfg_reg;
2100                         }
2101                 }
2102                 if (rx_cfg_reg & ANEG_CFG_ACK)
2103                         ap->ack_match = 1;
2104                 else
2105                         ap->ack_match = 0;
2106
2107                 ap->idle_match = 0;
2108         } else {
2109                 ap->idle_match = 1;
2110                 ap->ability_match_cfg = 0;
2111                 ap->ability_match_count = 0;
2112                 ap->ability_match = 0;
2113                 ap->ack_match = 0;
2114
2115                 rx_cfg_reg = 0;
2116         }
2117
2118         ap->rxconfig = rx_cfg_reg;
2119         ret = ANEG_OK;
2120
2121         switch(ap->state) {
2122         case ANEG_STATE_UNKNOWN:
2123                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2124                         ap->state = ANEG_STATE_AN_ENABLE;
2125
2126                 /* fallthru */
2127         case ANEG_STATE_AN_ENABLE:
2128                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2129                 if (ap->flags & MR_AN_ENABLE) {
2130                         ap->link_time = 0;
2131                         ap->cur_time = 0;
2132                         ap->ability_match_cfg = 0;
2133                         ap->ability_match_count = 0;
2134                         ap->ability_match = 0;
2135                         ap->idle_match = 0;
2136                         ap->ack_match = 0;
2137
2138                         ap->state = ANEG_STATE_RESTART_INIT;
2139                 } else {
2140                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2141                 }
2142                 break;
2143
2144         case ANEG_STATE_RESTART_INIT:
2145                 ap->link_time = ap->cur_time;
2146                 ap->flags &= ~(MR_NP_LOADED);
2147                 ap->txconfig = 0;
2148                 tw32(MAC_TX_AUTO_NEG, 0);
2149                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2150                 tw32_f(MAC_MODE, tp->mac_mode);
2151                 udelay(40);
2152
2153                 ret = ANEG_TIMER_ENAB;
2154                 ap->state = ANEG_STATE_RESTART;
2155
2156                 /* fallthru */
2157         case ANEG_STATE_RESTART:
2158                 delta = ap->cur_time - ap->link_time;
2159                 if (delta > ANEG_STATE_SETTLE_TIME) {
2160                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2161                 } else {
2162                         ret = ANEG_TIMER_ENAB;
2163                 }
2164                 break;
2165
2166         case ANEG_STATE_DISABLE_LINK_OK:
2167                 ret = ANEG_DONE;
2168                 break;
2169
2170         case ANEG_STATE_ABILITY_DETECT_INIT:
2171                 ap->flags &= ~(MR_TOGGLE_TX);
2172                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2173                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2174                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2175                 tw32_f(MAC_MODE, tp->mac_mode);
2176                 udelay(40);
2177
2178                 ap->state = ANEG_STATE_ABILITY_DETECT;
2179                 break;
2180
2181         case ANEG_STATE_ABILITY_DETECT:
2182                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2183                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2184                 }
2185                 break;
2186
2187         case ANEG_STATE_ACK_DETECT_INIT:
2188                 ap->txconfig |= ANEG_CFG_ACK;
2189                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2190                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2191                 tw32_f(MAC_MODE, tp->mac_mode);
2192                 udelay(40);
2193
2194                 ap->state = ANEG_STATE_ACK_DETECT;
2195
2196                 /* fallthru */
2197         case ANEG_STATE_ACK_DETECT:
2198                 if (ap->ack_match != 0) {
2199                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2200                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2201                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2202                         } else {
2203                                 ap->state = ANEG_STATE_AN_ENABLE;
2204                         }
2205                 } else if (ap->ability_match != 0 &&
2206                            ap->rxconfig == 0) {
2207                         ap->state = ANEG_STATE_AN_ENABLE;
2208                 }
2209                 break;
2210
2211         case ANEG_STATE_COMPLETE_ACK_INIT:
2212                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2213                         ret = ANEG_FAILED;
2214                         break;
2215                 }
2216                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2217                                MR_LP_ADV_HALF_DUPLEX |
2218                                MR_LP_ADV_SYM_PAUSE |
2219                                MR_LP_ADV_ASYM_PAUSE |
2220                                MR_LP_ADV_REMOTE_FAULT1 |
2221                                MR_LP_ADV_REMOTE_FAULT2 |
2222                                MR_LP_ADV_NEXT_PAGE |
2223                                MR_TOGGLE_RX |
2224                                MR_NP_RX);
2225                 if (ap->rxconfig & ANEG_CFG_FD)
2226                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2227                 if (ap->rxconfig & ANEG_CFG_HD)
2228                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2229                 if (ap->rxconfig & ANEG_CFG_PS1)
2230                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2231                 if (ap->rxconfig & ANEG_CFG_PS2)
2232                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2233                 if (ap->rxconfig & ANEG_CFG_RF1)
2234                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2235                 if (ap->rxconfig & ANEG_CFG_RF2)
2236                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2237                 if (ap->rxconfig & ANEG_CFG_NP)
2238                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2239
2240                 ap->link_time = ap->cur_time;
2241
2242                 ap->flags ^= (MR_TOGGLE_TX);
2243                 if (ap->rxconfig & 0x0008)
2244                         ap->flags |= MR_TOGGLE_RX;
2245                 if (ap->rxconfig & ANEG_CFG_NP)
2246                         ap->flags |= MR_NP_RX;
2247                 ap->flags |= MR_PAGE_RX;
2248
2249                 ap->state = ANEG_STATE_COMPLETE_ACK;
2250                 ret = ANEG_TIMER_ENAB;
2251                 break;
2252
2253         case ANEG_STATE_COMPLETE_ACK:
2254                 if (ap->ability_match != 0 &&
2255                     ap->rxconfig == 0) {
2256                         ap->state = ANEG_STATE_AN_ENABLE;
2257                         break;
2258                 }
2259                 delta = ap->cur_time - ap->link_time;
2260                 if (delta > ANEG_STATE_SETTLE_TIME) {
2261                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2262                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2263                         } else {
2264                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2265                                     !(ap->flags & MR_NP_RX)) {
2266                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2267                                 } else {
2268                                         ret = ANEG_FAILED;
2269                                 }
2270                         }
2271                 }
2272                 break;
2273
2274         case ANEG_STATE_IDLE_DETECT_INIT:
2275                 ap->link_time = ap->cur_time;
2276                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2277                 tw32_f(MAC_MODE, tp->mac_mode);
2278                 udelay(40);
2279
2280                 ap->state = ANEG_STATE_IDLE_DETECT;
2281                 ret = ANEG_TIMER_ENAB;
2282                 break;
2283
2284         case ANEG_STATE_IDLE_DETECT:
2285                 if (ap->ability_match != 0 &&
2286                     ap->rxconfig == 0) {
2287                         ap->state = ANEG_STATE_AN_ENABLE;
2288                         break;
2289                 }
2290                 delta = ap->cur_time - ap->link_time;
2291                 if (delta > ANEG_STATE_SETTLE_TIME) {
2292                         /* XXX another gem from the Broadcom driver :( */
2293                         ap->state = ANEG_STATE_LINK_OK;
2294                 }
2295                 break;
2296
2297         case ANEG_STATE_LINK_OK:
2298                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2299                 ret = ANEG_DONE;
2300                 break;
2301
2302         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2303                 /* ??? unimplemented */
2304                 break;
2305
2306         case ANEG_STATE_NEXT_PAGE_WAIT:
2307                 /* ??? unimplemented */
2308                 break;
2309
2310         default:
2311                 ret = ANEG_FAILED;
2312                 break;
2313         };
2314
2315         return ret;
2316 }
2317
2318 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2319 {
2320         int res = 0;
2321         struct tg3_fiber_aneginfo aninfo;
2322         int status = ANEG_FAILED;
2323         unsigned int tick;
2324         u32 tmp;
2325
2326         tw32_f(MAC_TX_AUTO_NEG, 0);
2327
2328         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2329         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2330         udelay(40);
2331
2332         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2333         udelay(40);
2334
2335         memset(&aninfo, 0, sizeof(aninfo));
2336         aninfo.flags |= MR_AN_ENABLE;
2337         aninfo.state = ANEG_STATE_UNKNOWN;
2338         aninfo.cur_time = 0;
2339         tick = 0;
2340         while (++tick < 195000) {
2341                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2342                 if (status == ANEG_DONE || status == ANEG_FAILED)
2343                         break;
2344
2345                 udelay(1);
2346         }
2347
2348         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2349         tw32_f(MAC_MODE, tp->mac_mode);
2350         udelay(40);
2351
2352         *flags = aninfo.flags;
2353
2354         if (status == ANEG_DONE &&
2355             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2356                              MR_LP_ADV_FULL_DUPLEX)))
2357                 res = 1;
2358
2359         return res;
2360 }
2361
2362 static void tg3_init_bcm8002(struct tg3 *tp)
2363 {
2364         u32 mac_status = tr32(MAC_STATUS);
2365         int i;
2366
2367         /* Reset when initting first time or we have a link. */
2368         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2369             !(mac_status & MAC_STATUS_PCS_SYNCED))
2370                 return;
2371
2372         /* Set PLL lock range. */
2373         tg3_writephy(tp, 0x16, 0x8007);
2374
2375         /* SW reset */
2376         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2377
2378         /* Wait for reset to complete. */
2379         /* XXX schedule_timeout() ... */
2380         for (i = 0; i < 500; i++)
2381                 udelay(10);
2382
2383         /* Config mode; select PMA/Ch 1 regs. */
2384         tg3_writephy(tp, 0x10, 0x8411);
2385
2386         /* Enable auto-lock and comdet, select txclk for tx. */
2387         tg3_writephy(tp, 0x11, 0x0a10);
2388
2389         tg3_writephy(tp, 0x18, 0x00a0);
2390         tg3_writephy(tp, 0x16, 0x41ff);
2391
2392         /* Assert and deassert POR. */
2393         tg3_writephy(tp, 0x13, 0x0400);
2394         udelay(40);
2395         tg3_writephy(tp, 0x13, 0x0000);
2396
2397         tg3_writephy(tp, 0x11, 0x0a50);
2398         udelay(40);
2399         tg3_writephy(tp, 0x11, 0x0a10);
2400
2401         /* Wait for signal to stabilize */
2402         /* XXX schedule_timeout() ... */
2403         for (i = 0; i < 15000; i++)
2404                 udelay(10);
2405
2406         /* Deselect the channel register so we can read the PHYID
2407          * later.
2408          */
2409         tg3_writephy(tp, 0x10, 0x8011);
2410 }
2411
2412 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2413 {
2414         u32 sg_dig_ctrl, sg_dig_status;
2415         u32 serdes_cfg, expected_sg_dig_ctrl;
2416         int workaround, port_a;
2417         int current_link_up;
2418
2419         serdes_cfg = 0;
2420         expected_sg_dig_ctrl = 0;
2421         workaround = 0;
2422         port_a = 1;
2423         current_link_up = 0;
2424
2425         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2426             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2427                 workaround = 1;
2428                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2429                         port_a = 0;
2430
2431                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2432                 /* preserve bits 20-23 for voltage regulator */
2433                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2434         }
2435
2436         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2437
2438         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2439                 if (sg_dig_ctrl & (1 << 31)) {
2440                         if (workaround) {
2441                                 u32 val = serdes_cfg;
2442
2443                                 if (port_a)
2444                                         val |= 0xc010000;
2445                                 else
2446                                         val |= 0x4010000;
2447                                 tw32_f(MAC_SERDES_CFG, val);
2448                         }
2449                         tw32_f(SG_DIG_CTRL, 0x01388400);
2450                 }
2451                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2452                         tg3_setup_flow_control(tp, 0, 0);
2453                         current_link_up = 1;
2454                 }
2455                 goto out;
2456         }
2457
2458         /* Want auto-negotiation.  */
2459         expected_sg_dig_ctrl = 0x81388400;
2460
2461         /* Pause capability */
2462         expected_sg_dig_ctrl |= (1 << 11);
2463
2464         /* Asymettric pause */
2465         expected_sg_dig_ctrl |= (1 << 12);
2466
2467         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2468                 if (workaround)
2469                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2470                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2471                 udelay(5);
2472                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2473
2474                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2475         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2476                                  MAC_STATUS_SIGNAL_DET)) {
2477                 int i;
2478
2479                 /* Giver time to negotiate (~200ms) */
2480                 for (i = 0; i < 40000; i++) {
2481                         sg_dig_status = tr32(SG_DIG_STATUS);
2482                         if (sg_dig_status & (0x3))
2483                                 break;
2484                         udelay(5);
2485                 }
2486                 mac_status = tr32(MAC_STATUS);
2487
2488                 if ((sg_dig_status & (1 << 1)) &&
2489                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2490                         u32 local_adv, remote_adv;
2491
2492                         local_adv = ADVERTISE_PAUSE_CAP;
2493                         remote_adv = 0;
2494                         if (sg_dig_status & (1 << 19))
2495                                 remote_adv |= LPA_PAUSE_CAP;
2496                         if (sg_dig_status & (1 << 20))
2497                                 remote_adv |= LPA_PAUSE_ASYM;
2498
2499                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2500                         current_link_up = 1;
2501                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2502                 } else if (!(sg_dig_status & (1 << 1))) {
2503                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2504                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2505                         else {
2506                                 if (workaround) {
2507                                         u32 val = serdes_cfg;
2508
2509                                         if (port_a)
2510                                                 val |= 0xc010000;
2511                                         else
2512                                                 val |= 0x4010000;
2513
2514                                         tw32_f(MAC_SERDES_CFG, val);
2515                                 }
2516
2517                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2518                                 udelay(40);
2519
2520                                 /* Link parallel detection - link is up */
2521                                 /* only if we have PCS_SYNC and not */
2522                                 /* receiving config code words */
2523                                 mac_status = tr32(MAC_STATUS);
2524                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2525                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2526                                         tg3_setup_flow_control(tp, 0, 0);
2527                                         current_link_up = 1;
2528                                 }
2529                         }
2530                 }
2531         }
2532
2533 out:
2534         return current_link_up;
2535 }
2536
2537 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2538 {
2539         int current_link_up = 0;
2540
2541         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2542                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2543                 goto out;
2544         }
2545
2546         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2547                 u32 flags;
2548                 int i;
2549
2550                 if (fiber_autoneg(tp, &flags)) {
2551                         u32 local_adv, remote_adv;
2552
2553                         local_adv = ADVERTISE_PAUSE_CAP;
2554                         remote_adv = 0;
2555                         if (flags & MR_LP_ADV_SYM_PAUSE)
2556                                 remote_adv |= LPA_PAUSE_CAP;
2557                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2558                                 remote_adv |= LPA_PAUSE_ASYM;
2559
2560                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2561
2562                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2563                         current_link_up = 1;
2564                 }
2565                 for (i = 0; i < 30; i++) {
2566                         udelay(20);
2567                         tw32_f(MAC_STATUS,
2568                                (MAC_STATUS_SYNC_CHANGED |
2569                                 MAC_STATUS_CFG_CHANGED));
2570                         udelay(40);
2571                         if ((tr32(MAC_STATUS) &
2572                              (MAC_STATUS_SYNC_CHANGED |
2573                               MAC_STATUS_CFG_CHANGED)) == 0)
2574                                 break;
2575                 }
2576
2577                 mac_status = tr32(MAC_STATUS);
2578                 if (current_link_up == 0 &&
2579                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2580                     !(mac_status & MAC_STATUS_RCVD_CFG))
2581                         current_link_up = 1;
2582         } else {
2583                 /* Forcing 1000FD link up. */
2584                 current_link_up = 1;
2585                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2586
2587                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2588                 udelay(40);
2589         }
2590
2591 out:
2592         return current_link_up;
2593 }
2594
2595 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2596 {
2597         u32 orig_pause_cfg;
2598         u16 orig_active_speed;
2599         u8 orig_active_duplex;
2600         u32 mac_status;
2601         int current_link_up;
2602         int i;
2603
2604         orig_pause_cfg =
2605                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2606                                   TG3_FLAG_TX_PAUSE));
2607         orig_active_speed = tp->link_config.active_speed;
2608         orig_active_duplex = tp->link_config.active_duplex;
2609
2610         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2611             netif_carrier_ok(tp->dev) &&
2612             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2613                 mac_status = tr32(MAC_STATUS);
2614                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2615                                MAC_STATUS_SIGNAL_DET |
2616                                MAC_STATUS_CFG_CHANGED |
2617                                MAC_STATUS_RCVD_CFG);
2618                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2619                                    MAC_STATUS_SIGNAL_DET)) {
2620                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2621                                             MAC_STATUS_CFG_CHANGED));
2622                         return 0;
2623                 }
2624         }
2625
2626         tw32_f(MAC_TX_AUTO_NEG, 0);
2627
2628         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2629         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2630         tw32_f(MAC_MODE, tp->mac_mode);
2631         udelay(40);
2632
2633         if (tp->phy_id == PHY_ID_BCM8002)
2634                 tg3_init_bcm8002(tp);
2635
2636         /* Enable link change event even when serdes polling.  */
2637         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2638         udelay(40);
2639
2640         current_link_up = 0;
2641         mac_status = tr32(MAC_STATUS);
2642
2643         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2644                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2645         else
2646                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2647
2648         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2649         tw32_f(MAC_MODE, tp->mac_mode);
2650         udelay(40);
2651
2652         tp->hw_status->status =
2653                 (SD_STATUS_UPDATED |
2654                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2655
2656         for (i = 0; i < 100; i++) {
2657                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2658                                     MAC_STATUS_CFG_CHANGED));
2659                 udelay(5);
2660                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2661                                          MAC_STATUS_CFG_CHANGED)) == 0)
2662                         break;
2663         }
2664
2665         mac_status = tr32(MAC_STATUS);
2666         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2667                 current_link_up = 0;
2668                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2669                         tw32_f(MAC_MODE, (tp->mac_mode |
2670                                           MAC_MODE_SEND_CONFIGS));
2671                         udelay(1);
2672                         tw32_f(MAC_MODE, tp->mac_mode);
2673                 }
2674         }
2675
2676         if (current_link_up == 1) {
2677                 tp->link_config.active_speed = SPEED_1000;
2678                 tp->link_config.active_duplex = DUPLEX_FULL;
2679                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2680                                     LED_CTRL_LNKLED_OVERRIDE |
2681                                     LED_CTRL_1000MBPS_ON));
2682         } else {
2683                 tp->link_config.active_speed = SPEED_INVALID;
2684                 tp->link_config.active_duplex = DUPLEX_INVALID;
2685                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2686                                     LED_CTRL_LNKLED_OVERRIDE |
2687                                     LED_CTRL_TRAFFIC_OVERRIDE));
2688         }
2689
2690         if (current_link_up != netif_carrier_ok(tp->dev)) {
2691                 if (current_link_up)
2692                         netif_carrier_on(tp->dev);
2693                 else
2694                         netif_carrier_off(tp->dev);
2695                 tg3_link_report(tp);
2696         } else {
2697                 u32 now_pause_cfg =
2698                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2699                                          TG3_FLAG_TX_PAUSE);
2700                 if (orig_pause_cfg != now_pause_cfg ||
2701                     orig_active_speed != tp->link_config.active_speed ||
2702                     orig_active_duplex != tp->link_config.active_duplex)
2703                         tg3_link_report(tp);
2704         }
2705
2706         return 0;
2707 }
2708
2709 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2710 {
2711         int current_link_up, err = 0;
2712         u32 bmsr, bmcr;
2713         u16 current_speed;
2714         u8 current_duplex;
2715
2716         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2717         tw32_f(MAC_MODE, tp->mac_mode);
2718         udelay(40);
2719
2720         tw32(MAC_EVENT, 0);
2721
2722         tw32_f(MAC_STATUS,
2723              (MAC_STATUS_SYNC_CHANGED |
2724               MAC_STATUS_CFG_CHANGED |
2725               MAC_STATUS_MI_COMPLETION |
2726               MAC_STATUS_LNKSTATE_CHANGED));
2727         udelay(40);
2728
2729         if (force_reset)
2730                 tg3_phy_reset(tp);
2731
2732         current_link_up = 0;
2733         current_speed = SPEED_INVALID;
2734         current_duplex = DUPLEX_INVALID;
2735
2736         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2737         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2738         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2739                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2740                         bmsr |= BMSR_LSTATUS;
2741                 else
2742                         bmsr &= ~BMSR_LSTATUS;
2743         }
2744
2745         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2746
2747         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2748             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2749                 /* do nothing, just check for link up at the end */
2750         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2751                 u32 adv, new_adv;
2752
2753                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2754                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2755                                   ADVERTISE_1000XPAUSE |
2756                                   ADVERTISE_1000XPSE_ASYM |
2757                                   ADVERTISE_SLCT);
2758
2759                 /* Always advertise symmetric PAUSE just like copper */
2760                 new_adv |= ADVERTISE_1000XPAUSE;
2761
2762                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2763                         new_adv |= ADVERTISE_1000XHALF;
2764                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2765                         new_adv |= ADVERTISE_1000XFULL;
2766
2767                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2768                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2769                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2770                         tg3_writephy(tp, MII_BMCR, bmcr);
2771
2772                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2773                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2774                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2775
2776                         return err;
2777                 }
2778         } else {
2779                 u32 new_bmcr;
2780
2781                 bmcr &= ~BMCR_SPEED1000;
2782                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2783
2784                 if (tp->link_config.duplex == DUPLEX_FULL)
2785                         new_bmcr |= BMCR_FULLDPLX;
2786
2787                 if (new_bmcr != bmcr) {
2788                         /* BMCR_SPEED1000 is a reserved bit that needs
2789                          * to be set on write.
2790                          */
2791                         new_bmcr |= BMCR_SPEED1000;
2792
2793                         /* Force a linkdown */
2794                         if (netif_carrier_ok(tp->dev)) {
2795                                 u32 adv;
2796
2797                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2798                                 adv &= ~(ADVERTISE_1000XFULL |
2799                                          ADVERTISE_1000XHALF |
2800                                          ADVERTISE_SLCT);
2801                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2802                                 tg3_writephy(tp, MII_BMCR, bmcr |
2803                                                            BMCR_ANRESTART |
2804                                                            BMCR_ANENABLE);
2805                                 udelay(10);
2806                                 netif_carrier_off(tp->dev);
2807                         }
2808                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2809                         bmcr = new_bmcr;
2810                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2811                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2812                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2813                             ASIC_REV_5714) {
2814                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2815                                         bmsr |= BMSR_LSTATUS;
2816                                 else
2817                                         bmsr &= ~BMSR_LSTATUS;
2818                         }
2819                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2820                 }
2821         }
2822
2823         if (bmsr & BMSR_LSTATUS) {
2824                 current_speed = SPEED_1000;
2825                 current_link_up = 1;
2826                 if (bmcr & BMCR_FULLDPLX)
2827                         current_duplex = DUPLEX_FULL;
2828                 else
2829                         current_duplex = DUPLEX_HALF;
2830
2831                 if (bmcr & BMCR_ANENABLE) {
2832                         u32 local_adv, remote_adv, common;
2833
2834                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2835                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2836                         common = local_adv & remote_adv;
2837                         if (common & (ADVERTISE_1000XHALF |
2838                                       ADVERTISE_1000XFULL)) {
2839                                 if (common & ADVERTISE_1000XFULL)
2840                                         current_duplex = DUPLEX_FULL;
2841                                 else
2842                                         current_duplex = DUPLEX_HALF;
2843
2844                                 tg3_setup_flow_control(tp, local_adv,
2845                                                        remote_adv);
2846                         }
2847                         else
2848                                 current_link_up = 0;
2849                 }
2850         }
2851
2852         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2853         if (tp->link_config.active_duplex == DUPLEX_HALF)
2854                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2855
2856         tw32_f(MAC_MODE, tp->mac_mode);
2857         udelay(40);
2858
2859         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2860
2861         tp->link_config.active_speed = current_speed;
2862         tp->link_config.active_duplex = current_duplex;
2863
2864         if (current_link_up != netif_carrier_ok(tp->dev)) {
2865                 if (current_link_up)
2866                         netif_carrier_on(tp->dev);
2867                 else {
2868                         netif_carrier_off(tp->dev);
2869                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2870                 }
2871                 tg3_link_report(tp);
2872         }
2873         return err;
2874 }
2875
2876 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2877 {
2878         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2879                 /* Give autoneg time to complete. */
2880                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2881                 return;
2882         }
2883         if (!netif_carrier_ok(tp->dev) &&
2884             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2885                 u32 bmcr;
2886
2887                 tg3_readphy(tp, MII_BMCR, &bmcr);
2888                 if (bmcr & BMCR_ANENABLE) {
2889                         u32 phy1, phy2;
2890
2891                         /* Select shadow register 0x1f */
2892                         tg3_writephy(tp, 0x1c, 0x7c00);
2893                         tg3_readphy(tp, 0x1c, &phy1);
2894
2895                         /* Select expansion interrupt status register */
2896                         tg3_writephy(tp, 0x17, 0x0f01);
2897                         tg3_readphy(tp, 0x15, &phy2);
2898                         tg3_readphy(tp, 0x15, &phy2);
2899
2900                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2901                                 /* We have signal detect and not receiving
2902                                  * config code words, link is up by parallel
2903                                  * detection.
2904                                  */
2905
2906                                 bmcr &= ~BMCR_ANENABLE;
2907                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2908                                 tg3_writephy(tp, MII_BMCR, bmcr);
2909                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2910                         }
2911                 }
2912         }
2913         else if (netif_carrier_ok(tp->dev) &&
2914                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2915                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2916                 u32 phy2;
2917
2918                 /* Select expansion interrupt status register */
2919                 tg3_writephy(tp, 0x17, 0x0f01);
2920                 tg3_readphy(tp, 0x15, &phy2);
2921                 if (phy2 & 0x20) {
2922                         u32 bmcr;
2923
2924                         /* Config code words received, turn on autoneg. */
2925                         tg3_readphy(tp, MII_BMCR, &bmcr);
2926                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2927
2928                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2929
2930                 }
2931         }
2932 }
2933
2934 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2935 {
2936         int err;
2937
2938         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2939                 err = tg3_setup_fiber_phy(tp, force_reset);
2940         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2941                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2942         } else {
2943                 err = tg3_setup_copper_phy(tp, force_reset);
2944         }
2945
2946         if (tp->link_config.active_speed == SPEED_1000 &&
2947             tp->link_config.active_duplex == DUPLEX_HALF)
2948                 tw32(MAC_TX_LENGTHS,
2949                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2950                       (6 << TX_LENGTHS_IPG_SHIFT) |
2951                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2952         else
2953                 tw32(MAC_TX_LENGTHS,
2954                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2955                       (6 << TX_LENGTHS_IPG_SHIFT) |
2956                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2957
2958         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2959                 if (netif_carrier_ok(tp->dev)) {
2960                         tw32(HOSTCC_STAT_COAL_TICKS,
2961                              tp->coal.stats_block_coalesce_usecs);
2962                 } else {
2963                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2964                 }
2965         }
2966
2967         return err;
2968 }
2969
2970 /* This is called whenever we suspect that the system chipset is re-
2971  * ordering the sequence of MMIO to the tx send mailbox. The symptom
2972  * is bogus tx completions. We try to recover by setting the
2973  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2974  * in the workqueue.
2975  */
2976 static void tg3_tx_recover(struct tg3 *tp)
2977 {
2978         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
2979                tp->write32_tx_mbox == tg3_write_indirect_mbox);
2980
2981         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
2982                "mapped I/O cycles to the network device, attempting to "
2983                "recover. Please report the problem to the driver maintainer "
2984                "and include system chipset information.\n", tp->dev->name);
2985
2986         spin_lock(&tp->lock);
2987         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
2988         spin_unlock(&tp->lock);
2989 }
2990
2991 /* Tigon3 never reports partial packet sends.  So we do not
2992  * need special logic to handle SKBs that have not had all
2993  * of their frags sent yet, like SunGEM does.
2994  */
2995 static void tg3_tx(struct tg3 *tp)
2996 {
2997         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2998         u32 sw_idx = tp->tx_cons;
2999
3000         while (sw_idx != hw_idx) {
3001                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3002                 struct sk_buff *skb = ri->skb;
3003                 int i, tx_bug = 0;
3004
3005                 if (unlikely(skb == NULL)) {
3006                         tg3_tx_recover(tp);
3007                         return;
3008                 }
3009
3010                 pci_unmap_single(tp->pdev,
3011                                  pci_unmap_addr(ri, mapping),
3012                                  skb_headlen(skb),
3013                                  PCI_DMA_TODEVICE);
3014
3015                 ri->skb = NULL;
3016
3017                 sw_idx = NEXT_TX(sw_idx);
3018
3019                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3020                         ri = &tp->tx_buffers[sw_idx];
3021                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3022                                 tx_bug = 1;
3023
3024                         pci_unmap_page(tp->pdev,
3025                                        pci_unmap_addr(ri, mapping),
3026                                        skb_shinfo(skb)->frags[i].size,
3027                                        PCI_DMA_TODEVICE);
3028
3029                         sw_idx = NEXT_TX(sw_idx);
3030                 }
3031
3032                 dev_kfree_skb(skb);
3033
3034                 if (unlikely(tx_bug)) {
3035                         tg3_tx_recover(tp);
3036                         return;
3037                 }
3038         }
3039
3040         tp->tx_cons = sw_idx;
3041
3042         if (unlikely(netif_queue_stopped(tp->dev))) {
3043                 spin_lock(&tp->tx_lock);
3044                 if (netif_queue_stopped(tp->dev) &&
3045                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
3046                         netif_wake_queue(tp->dev);
3047                 spin_unlock(&tp->tx_lock);
3048         }
3049 }
3050
3051 /* Returns size of skb allocated or < 0 on error.
3052  *
3053  * We only need to fill in the address because the other members
3054  * of the RX descriptor are invariant, see tg3_init_rings.
3055  *
3056  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3057  * posting buffers we only dirty the first cache line of the RX
3058  * descriptor (containing the address).  Whereas for the RX status
3059  * buffers the cpu only reads the last cacheline of the RX descriptor
3060  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3061  */
3062 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3063                             int src_idx, u32 dest_idx_unmasked)
3064 {
3065         struct tg3_rx_buffer_desc *desc;
3066         struct ring_info *map, *src_map;
3067         struct sk_buff *skb;
3068         dma_addr_t mapping;
3069         int skb_size, dest_idx;
3070
3071         src_map = NULL;
3072         switch (opaque_key) {
3073         case RXD_OPAQUE_RING_STD:
3074                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3075                 desc = &tp->rx_std[dest_idx];
3076                 map = &tp->rx_std_buffers[dest_idx];
3077                 if (src_idx >= 0)
3078                         src_map = &tp->rx_std_buffers[src_idx];
3079                 skb_size = tp->rx_pkt_buf_sz;
3080                 break;
3081
3082         case RXD_OPAQUE_RING_JUMBO:
3083                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3084                 desc = &tp->rx_jumbo[dest_idx];
3085                 map = &tp->rx_jumbo_buffers[dest_idx];
3086                 if (src_idx >= 0)
3087                         src_map = &tp->rx_jumbo_buffers[src_idx];
3088                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3089                 break;
3090
3091         default:
3092                 return -EINVAL;
3093         };
3094
3095         /* Do not overwrite any of the map or rp information
3096          * until we are sure we can commit to a new buffer.
3097          *
3098          * Callers depend upon this behavior and assume that
3099          * we leave everything unchanged if we fail.
3100          */
3101         skb = dev_alloc_skb(skb_size);
3102         if (skb == NULL)
3103                 return -ENOMEM;
3104
3105         skb->dev = tp->dev;
3106         skb_reserve(skb, tp->rx_offset);
3107
3108         mapping = pci_map_single(tp->pdev, skb->data,
3109                                  skb_size - tp->rx_offset,
3110                                  PCI_DMA_FROMDEVICE);
3111
3112         map->skb = skb;
3113         pci_unmap_addr_set(map, mapping, mapping);
3114
3115         if (src_map != NULL)
3116                 src_map->skb = NULL;
3117
3118         desc->addr_hi = ((u64)mapping >> 32);
3119         desc->addr_lo = ((u64)mapping & 0xffffffff);
3120
3121         return skb_size;
3122 }
3123
3124 /* We only need to move over in the address because the other
3125  * members of the RX descriptor are invariant.  See notes above
3126  * tg3_alloc_rx_skb for full details.
3127  */
3128 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3129                            int src_idx, u32 dest_idx_unmasked)
3130 {
3131         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3132         struct ring_info *src_map, *dest_map;
3133         int dest_idx;
3134
3135         switch (opaque_key) {
3136         case RXD_OPAQUE_RING_STD:
3137                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3138                 dest_desc = &tp->rx_std[dest_idx];
3139                 dest_map = &tp->rx_std_buffers[dest_idx];
3140                 src_desc = &tp->rx_std[src_idx];
3141                 src_map = &tp->rx_std_buffers[src_idx];
3142                 break;
3143
3144         case RXD_OPAQUE_RING_JUMBO:
3145                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3146                 dest_desc = &tp->rx_jumbo[dest_idx];
3147                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3148                 src_desc = &tp->rx_jumbo[src_idx];
3149                 src_map = &tp->rx_jumbo_buffers[src_idx];
3150                 break;
3151
3152         default:
3153                 return;
3154         };
3155
3156         dest_map->skb = src_map->skb;
3157         pci_unmap_addr_set(dest_map, mapping,
3158                            pci_unmap_addr(src_map, mapping));
3159         dest_desc->addr_hi = src_desc->addr_hi;
3160         dest_desc->addr_lo = src_desc->addr_lo;
3161
3162         src_map->skb = NULL;
3163 }
3164
3165 #if TG3_VLAN_TAG_USED
3166 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3167 {
3168         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3169 }
3170 #endif
3171
3172 /* The RX ring scheme is composed of multiple rings which post fresh
3173  * buffers to the chip, and one special ring the chip uses to report
3174  * status back to the host.
3175  *
3176  * The special ring reports the status of received packets to the
3177  * host.  The chip does not write into the original descriptor the
3178  * RX buffer was obtained from.  The chip simply takes the original
3179  * descriptor as provided by the host, updates the status and length
3180  * field, then writes this into the next status ring entry.
3181  *
3182  * Each ring the host uses to post buffers to the chip is described
3183  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3184  * it is first placed into the on-chip ram.  When the packet's length
3185  * is known, it walks down the TG3_BDINFO entries to select the ring.
3186  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3187  * which is within the range of the new packet's length is chosen.
3188  *
3189  * The "separate ring for rx status" scheme may sound queer, but it makes
3190  * sense from a cache coherency perspective.  If only the host writes
3191  * to the buffer post rings, and only the chip writes to the rx status
3192  * rings, then cache lines never move beyond shared-modified state.
3193  * If both the host and chip were to write into the same ring, cache line
3194  * eviction could occur since both entities want it in an exclusive state.
3195  */
3196 static int tg3_rx(struct tg3 *tp, int budget)
3197 {
3198         u32 work_mask;
3199         u32 sw_idx = tp->rx_rcb_ptr;
3200         u16 hw_idx;
3201         int received;
3202
3203         hw_idx = tp->hw_status->idx[0].rx_producer;
3204         /*
3205          * We need to order the read of hw_idx and the read of
3206          * the opaque cookie.
3207          */
3208         rmb();
3209         work_mask = 0;
3210         received = 0;
3211         while (sw_idx != hw_idx && budget > 0) {
3212                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3213                 unsigned int len;
3214                 struct sk_buff *skb;
3215                 dma_addr_t dma_addr;
3216                 u32 opaque_key, desc_idx, *post_ptr;
3217
3218                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3219                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3220                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3221                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3222                                                   mapping);
3223                         skb = tp->rx_std_buffers[desc_idx].skb;
3224                         post_ptr = &tp->rx_std_ptr;
3225                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3226                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3227                                                   mapping);
3228                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3229                         post_ptr = &tp->rx_jumbo_ptr;
3230                 }
3231                 else {
3232                         goto next_pkt_nopost;
3233                 }
3234
3235                 work_mask |= opaque_key;
3236
3237                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3238                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3239                 drop_it:
3240                         tg3_recycle_rx(tp, opaque_key,
3241                                        desc_idx, *post_ptr);
3242                 drop_it_no_recycle:
3243                         /* Other statistics kept track of by card. */
3244                         tp->net_stats.rx_dropped++;
3245                         goto next_pkt;
3246                 }
3247
3248                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3249
3250                 if (len > RX_COPY_THRESHOLD
3251                         && tp->rx_offset == 2
3252                         /* rx_offset != 2 iff this is a 5701 card running
3253                          * in PCI-X mode [see tg3_get_invariants()] */
3254                 ) {
3255                         int skb_size;
3256
3257                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3258                                                     desc_idx, *post_ptr);
3259                         if (skb_size < 0)
3260                                 goto drop_it;
3261
3262                         pci_unmap_single(tp->pdev, dma_addr,
3263                                          skb_size - tp->rx_offset,
3264                                          PCI_DMA_FROMDEVICE);
3265
3266                         skb_put(skb, len);
3267                 } else {
3268                         struct sk_buff *copy_skb;
3269
3270                         tg3_recycle_rx(tp, opaque_key,
3271                                        desc_idx, *post_ptr);
3272
3273                         copy_skb = dev_alloc_skb(len + 2);
3274                         if (copy_skb == NULL)
3275                                 goto drop_it_no_recycle;
3276
3277                         copy_skb->dev = tp->dev;
3278                         skb_reserve(copy_skb, 2);
3279                         skb_put(copy_skb, len);
3280                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3281                         memcpy(copy_skb->data, skb->data, len);
3282                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3283
3284                         /* We'll reuse the original ring buffer. */
3285                         skb = copy_skb;
3286                 }
3287
3288                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3289                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3290                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3291                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3292                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3293                 else
3294                         skb->ip_summed = CHECKSUM_NONE;
3295
3296                 skb->protocol = eth_type_trans(skb, tp->dev);
3297 #if TG3_VLAN_TAG_USED
3298                 if (tp->vlgrp != NULL &&
3299                     desc->type_flags & RXD_FLAG_VLAN) {
3300                         tg3_vlan_rx(tp, skb,
3301                                     desc->err_vlan & RXD_VLAN_MASK);
3302                 } else
3303 #endif
3304                         netif_receive_skb(skb);
3305
3306                 tp->dev->last_rx = jiffies;
3307                 received++;
3308                 budget--;
3309
3310 next_pkt:
3311                 (*post_ptr)++;
3312 next_pkt_nopost:
3313                 sw_idx++;
3314                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3315
3316                 /* Refresh hw_idx to see if there is new work */
3317                 if (sw_idx == hw_idx) {
3318                         hw_idx = tp->hw_status->idx[0].rx_producer;
3319                         rmb();
3320                 }
3321         }
3322
3323         /* ACK the status ring. */
3324         tp->rx_rcb_ptr = sw_idx;
3325         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3326
3327         /* Refill RX ring(s). */
3328         if (work_mask & RXD_OPAQUE_RING_STD) {
3329                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3330                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3331                              sw_idx);
3332         }
3333         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3334                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3335                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3336                              sw_idx);
3337         }
3338         mmiowb();
3339
3340         return received;
3341 }
3342
3343 static int tg3_poll(struct net_device *netdev, int *budget)
3344 {
3345         struct tg3 *tp = netdev_priv(netdev);
3346         struct tg3_hw_status *sblk = tp->hw_status;
3347         int done;
3348
3349         /* handle link change and other phy events */
3350         if (!(tp->tg3_flags &
3351               (TG3_FLAG_USE_LINKCHG_REG |
3352                TG3_FLAG_POLL_SERDES))) {
3353                 if (sblk->status & SD_STATUS_LINK_CHG) {
3354                         sblk->status = SD_STATUS_UPDATED |
3355                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3356                         spin_lock(&tp->lock);
3357                         tg3_setup_phy(tp, 0);
3358                         spin_unlock(&tp->lock);
3359                 }
3360         }
3361
3362         /* run TX completion thread */
3363         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3364                 tg3_tx(tp);
3365                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3366                         netif_rx_complete(netdev);
3367                         schedule_work(&tp->reset_task);
3368                         return 0;
3369                 }
3370         }
3371
3372         /* run RX thread, within the bounds set by NAPI.
3373          * All RX "locking" is done by ensuring outside
3374          * code synchronizes with dev->poll()
3375          */
3376         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3377                 int orig_budget = *budget;
3378                 int work_done;
3379
3380                 if (orig_budget > netdev->quota)
3381                         orig_budget = netdev->quota;
3382
3383                 work_done = tg3_rx(tp, orig_budget);
3384
3385                 *budget -= work_done;
3386                 netdev->quota -= work_done;
3387         }
3388
3389         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3390                 tp->last_tag = sblk->status_tag;
3391                 rmb();
3392         } else
3393                 sblk->status &= ~SD_STATUS_UPDATED;
3394
3395         /* if no more work, tell net stack and NIC we're done */
3396         done = !tg3_has_work(tp);
3397         if (done) {
3398                 netif_rx_complete(netdev);
3399                 tg3_restart_ints(tp);
3400         }
3401
3402         return (done ? 0 : 1);
3403 }
3404
3405 static void tg3_irq_quiesce(struct tg3 *tp)
3406 {
3407         BUG_ON(tp->irq_sync);
3408
3409         tp->irq_sync = 1;
3410         smp_mb();
3411
3412         synchronize_irq(tp->pdev->irq);
3413 }
3414
3415 static inline int tg3_irq_sync(struct tg3 *tp)
3416 {
3417         return tp->irq_sync;
3418 }
3419
3420 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3421  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3422  * with as well.  Most of the time, this is not necessary except when
3423  * shutting down the device.
3424  */
3425 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3426 {
3427         if (irq_sync)
3428                 tg3_irq_quiesce(tp);
3429         spin_lock_bh(&tp->lock);
3430 }
3431
3432 static inline void tg3_full_unlock(struct tg3 *tp)
3433 {
3434         spin_unlock_bh(&tp->lock);
3435 }
3436
3437 /* One-shot MSI handler - Chip automatically disables interrupt
3438  * after sending MSI so driver doesn't have to do it.
3439  */
3440 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3441 {
3442         struct net_device *dev = dev_id;
3443         struct tg3 *tp = netdev_priv(dev);
3444
3445         prefetch(tp->hw_status);
3446         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3447
3448         if (likely(!tg3_irq_sync(tp)))
3449                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3450
3451         return IRQ_HANDLED;
3452 }
3453
3454 /* MSI ISR - No need to check for interrupt sharing and no need to
3455  * flush status block and interrupt mailbox. PCI ordering rules
3456  * guarantee that MSI will arrive after the status block.
3457  */
3458 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3459 {
3460         struct net_device *dev = dev_id;
3461         struct tg3 *tp = netdev_priv(dev);
3462
3463         prefetch(tp->hw_status);
3464         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3465         /*
3466          * Writing any value to intr-mbox-0 clears PCI INTA# and
3467          * chip-internal interrupt pending events.
3468          * Writing non-zero to intr-mbox-0 additional tells the
3469          * NIC to stop sending us irqs, engaging "in-intr-handler"
3470          * event coalescing.
3471          */
3472         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3473         if (likely(!tg3_irq_sync(tp)))
3474                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3475
3476         return IRQ_RETVAL(1);
3477 }
3478
3479 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3480 {
3481         struct net_device *dev = dev_id;
3482         struct tg3 *tp = netdev_priv(dev);
3483         struct tg3_hw_status *sblk = tp->hw_status;
3484         unsigned int handled = 1;
3485
3486         /* In INTx mode, it is possible for the interrupt to arrive at
3487          * the CPU before the status block posted prior to the interrupt.
3488          * Reading the PCI State register will confirm whether the
3489          * interrupt is ours and will flush the status block.
3490          */
3491         if ((sblk->status & SD_STATUS_UPDATED) ||
3492             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3493                 /*
3494                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3495                  * chip-internal interrupt pending events.
3496                  * Writing non-zero to intr-mbox-0 additional tells the
3497                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3498                  * event coalescing.
3499                  */
3500                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3501                              0x00000001);
3502                 if (tg3_irq_sync(tp))
3503                         goto out;
3504                 sblk->status &= ~SD_STATUS_UPDATED;
3505                 if (likely(tg3_has_work(tp))) {
3506                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3507                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3508                 } else {
3509                         /* No work, shared interrupt perhaps?  re-enable
3510                          * interrupts, and flush that PCI write
3511                          */
3512                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3513                                 0x00000000);
3514                 }
3515         } else {        /* shared interrupt */
3516                 handled = 0;
3517         }
3518 out:
3519         return IRQ_RETVAL(handled);
3520 }
3521
3522 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3523 {
3524         struct net_device *dev = dev_id;
3525         struct tg3 *tp = netdev_priv(dev);
3526         struct tg3_hw_status *sblk = tp->hw_status;
3527         unsigned int handled = 1;
3528
3529         /* In INTx mode, it is possible for the interrupt to arrive at
3530          * the CPU before the status block posted prior to the interrupt.
3531          * Reading the PCI State register will confirm whether the
3532          * interrupt is ours and will flush the status block.
3533          */
3534         if ((sblk->status_tag != tp->last_tag) ||
3535             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3536                 /*
3537                  * writing any value to intr-mbox-0 clears PCI INTA# and
3538                  * chip-internal interrupt pending events.
3539                  * writing non-zero to intr-mbox-0 additional tells the
3540                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3541                  * event coalescing.
3542                  */
3543                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3544                              0x00000001);
3545                 if (tg3_irq_sync(tp))
3546                         goto out;
3547                 if (netif_rx_schedule_prep(dev)) {
3548                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3549                         /* Update last_tag to mark that this status has been
3550                          * seen. Because interrupt may be shared, we may be
3551                          * racing with tg3_poll(), so only update last_tag
3552                          * if tg3_poll() is not scheduled.
3553                          */
3554                         tp->last_tag = sblk->status_tag;
3555                         __netif_rx_schedule(dev);
3556                 }
3557         } else {        /* shared interrupt */
3558                 handled = 0;
3559         }
3560 out:
3561         return IRQ_RETVAL(handled);
3562 }
3563
3564 /* ISR for interrupt test */
3565 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3566                 struct pt_regs *regs)
3567 {
3568         struct net_device *dev = dev_id;
3569         struct tg3 *tp = netdev_priv(dev);
3570         struct tg3_hw_status *sblk = tp->hw_status;
3571
3572         if ((sblk->status & SD_STATUS_UPDATED) ||
3573             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3574                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3575                              0x00000001);
3576                 return IRQ_RETVAL(1);
3577         }
3578         return IRQ_RETVAL(0);
3579 }
3580
3581 static int tg3_init_hw(struct tg3 *, int);
3582 static int tg3_halt(struct tg3 *, int, int);
3583
3584 #ifdef CONFIG_NET_POLL_CONTROLLER
3585 static void tg3_poll_controller(struct net_device *dev)
3586 {
3587         struct tg3 *tp = netdev_priv(dev);
3588
3589         tg3_interrupt(tp->pdev->irq, dev, NULL);
3590 }
3591 #endif
3592
3593 static void tg3_reset_task(void *_data)
3594 {
3595         struct tg3 *tp = _data;
3596         unsigned int restart_timer;
3597
3598         tg3_full_lock(tp, 0);
3599         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3600
3601         if (!netif_running(tp->dev)) {
3602                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3603                 tg3_full_unlock(tp);
3604                 return;
3605         }
3606
3607         tg3_full_unlock(tp);
3608
3609         tg3_netif_stop(tp);
3610
3611         tg3_full_lock(tp, 1);
3612
3613         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3614         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3615
3616         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3617                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3618                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3619                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3620                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3621         }
3622
3623         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3624         tg3_init_hw(tp, 1);
3625
3626         tg3_netif_start(tp);
3627
3628         if (restart_timer)
3629                 mod_timer(&tp->timer, jiffies + 1);
3630
3631         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3632
3633         tg3_full_unlock(tp);
3634 }
3635
3636 static void tg3_tx_timeout(struct net_device *dev)
3637 {
3638         struct tg3 *tp = netdev_priv(dev);
3639
3640         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3641                dev->name);
3642
3643         schedule_work(&tp->reset_task);
3644 }
3645
3646 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3647 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3648 {
3649         u32 base = (u32) mapping & 0xffffffff;
3650
3651         return ((base > 0xffffdcc0) &&
3652                 (base + len + 8 < base));
3653 }
3654
3655 /* Test for DMA addresses > 40-bit */
3656 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3657                                           int len)
3658 {
3659 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3660         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3661                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3662         return 0;
3663 #else
3664         return 0;
3665 #endif
3666 }
3667
3668 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3669
3670 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3671 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3672                                        u32 last_plus_one, u32 *start,
3673                                        u32 base_flags, u32 mss)
3674 {
3675         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3676         dma_addr_t new_addr = 0;
3677         u32 entry = *start;
3678         int i, ret = 0;
3679
3680         if (!new_skb) {
3681                 ret = -1;
3682         } else {
3683                 /* New SKB is guaranteed to be linear. */
3684                 entry = *start;
3685                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3686                                           PCI_DMA_TODEVICE);
3687                 /* Make sure new skb does not cross any 4G boundaries.
3688                  * Drop the packet if it does.
3689                  */
3690                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3691                         ret = -1;
3692                         dev_kfree_skb(new_skb);
3693                         new_skb = NULL;
3694                 } else {
3695                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3696                                     base_flags, 1 | (mss << 1));
3697                         *start = NEXT_TX(entry);
3698                 }
3699         }
3700
3701         /* Now clean up the sw ring entries. */
3702         i = 0;
3703         while (entry != last_plus_one) {
3704                 int len;
3705
3706                 if (i == 0)
3707                         len = skb_headlen(skb);
3708                 else
3709                         len = skb_shinfo(skb)->frags[i-1].size;
3710                 pci_unmap_single(tp->pdev,
3711                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3712                                  len, PCI_DMA_TODEVICE);
3713                 if (i == 0) {
3714                         tp->tx_buffers[entry].skb = new_skb;
3715                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3716                 } else {
3717                         tp->tx_buffers[entry].skb = NULL;
3718                 }
3719                 entry = NEXT_TX(entry);
3720                 i++;
3721         }
3722
3723         dev_kfree_skb(skb);
3724
3725         return ret;
3726 }
3727
3728 static void tg3_set_txd(struct tg3 *tp, int entry,
3729                         dma_addr_t mapping, int len, u32 flags,
3730                         u32 mss_and_is_end)
3731 {
3732         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3733         int is_end = (mss_and_is_end & 0x1);
3734         u32 mss = (mss_and_is_end >> 1);
3735         u32 vlan_tag = 0;
3736
3737         if (is_end)
3738                 flags |= TXD_FLAG_END;
3739         if (flags & TXD_FLAG_VLAN) {
3740                 vlan_tag = flags >> 16;
3741                 flags &= 0xffff;
3742         }
3743         vlan_tag |= (mss << TXD_MSS_SHIFT);
3744
3745         txd->addr_hi = ((u64) mapping >> 32);
3746         txd->addr_lo = ((u64) mapping & 0xffffffff);
3747         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3748         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3749 }
3750
3751 /* hard_start_xmit for devices that don't have any bugs and
3752  * support TG3_FLG2_HW_TSO_2 only.
3753  */
3754 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3755 {
3756         struct tg3 *tp = netdev_priv(dev);
3757         dma_addr_t mapping;
3758         u32 len, entry, base_flags, mss;
3759
3760         len = skb_headlen(skb);
3761
3762         /* We are running in BH disabled context with netif_tx_lock
3763          * and TX reclaim runs via tp->poll inside of a software
3764          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3765          * no IRQ context deadlocks to worry about either.  Rejoice!
3766          */
3767         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3768                 if (!netif_queue_stopped(dev)) {
3769                         netif_stop_queue(dev);
3770
3771                         /* This is a hard error, log it. */
3772                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3773                                "queue awake!\n", dev->name);
3774                 }
3775                 return NETDEV_TX_BUSY;
3776         }
3777
3778         entry = tp->tx_prod;
3779         base_flags = 0;
3780 #if TG3_TSO_SUPPORT != 0
3781         mss = 0;
3782         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3783             (mss = skb_shinfo(skb)->tso_size) != 0) {
3784                 int tcp_opt_len, ip_tcp_len;
3785
3786                 if (skb_header_cloned(skb) &&
3787                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3788                         dev_kfree_skb(skb);
3789                         goto out_unlock;
3790                 }
3791
3792                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3793                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3794
3795                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3796                                TXD_FLAG_CPU_POST_DMA);
3797
3798                 skb->nh.iph->check = 0;
3799                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3800
3801                 skb->h.th->check = 0;
3802
3803                 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3804         }
3805         else if (skb->ip_summed == CHECKSUM_HW)
3806                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3807 #else
3808         mss = 0;
3809         if (skb->ip_summed == CHECKSUM_HW)
3810                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3811 #endif
3812 #if TG3_VLAN_TAG_USED
3813         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3814                 base_flags |= (TXD_FLAG_VLAN |
3815                                (vlan_tx_tag_get(skb) << 16));
3816 #endif
3817
3818         /* Queue skb data, a.k.a. the main skb fragment. */
3819         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3820
3821         tp->tx_buffers[entry].skb = skb;
3822         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3823
3824         tg3_set_txd(tp, entry, mapping, len, base_flags,
3825                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3826
3827         entry = NEXT_TX(entry);
3828
3829         /* Now loop through additional data fragments, and queue them. */
3830         if (skb_shinfo(skb)->nr_frags > 0) {
3831                 unsigned int i, last;
3832
3833                 last = skb_shinfo(skb)->nr_frags - 1;
3834                 for (i = 0; i <= last; i++) {
3835                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3836
3837                         len = frag->size;
3838                         mapping = pci_map_page(tp->pdev,
3839                                                frag->page,
3840                                                frag->page_offset,
3841                                                len, PCI_DMA_TODEVICE);
3842
3843                         tp->tx_buffers[entry].skb = NULL;
3844                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3845
3846                         tg3_set_txd(tp, entry, mapping, len,
3847                                     base_flags, (i == last) | (mss << 1));
3848
3849                         entry = NEXT_TX(entry);
3850                 }
3851         }
3852
3853         /* Packets are ready, update Tx producer idx local and on card. */
3854         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3855
3856         tp->tx_prod = entry;
3857         if (unlikely(TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))) {
3858                 spin_lock(&tp->tx_lock);
3859                 netif_stop_queue(dev);
3860                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3861                         netif_wake_queue(tp->dev);
3862                 spin_unlock(&tp->tx_lock);
3863         }
3864
3865 out_unlock:
3866         mmiowb();
3867
3868         dev->trans_start = jiffies;
3869
3870         return NETDEV_TX_OK;
3871 }
3872
3873 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3874  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3875  */
3876 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3877 {
3878         struct tg3 *tp = netdev_priv(dev);
3879         dma_addr_t mapping;
3880         u32 len, entry, base_flags, mss;
3881         int would_hit_hwbug;
3882
3883         len = skb_headlen(skb);
3884
3885         /* We are running in BH disabled context with netif_tx_lock
3886          * and TX reclaim runs via tp->poll inside of a software
3887          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3888          * no IRQ context deadlocks to worry about either.  Rejoice!
3889          */
3890         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3891                 if (!netif_queue_stopped(dev)) {
3892                         netif_stop_queue(dev);
3893
3894                         /* This is a hard error, log it. */
3895                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3896                                "queue awake!\n", dev->name);
3897                 }
3898                 return NETDEV_TX_BUSY;
3899         }
3900
3901         entry = tp->tx_prod;
3902         base_flags = 0;
3903         if (skb->ip_summed == CHECKSUM_HW)
3904                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3905 #if TG3_TSO_SUPPORT != 0
3906         mss = 0;
3907         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3908             (mss = skb_shinfo(skb)->tso_size) != 0) {
3909                 int tcp_opt_len, ip_tcp_len;
3910
3911                 if (skb_header_cloned(skb) &&
3912                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3913                         dev_kfree_skb(skb);
3914                         goto out_unlock;
3915                 }
3916
3917                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3918                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3919
3920                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3921                                TXD_FLAG_CPU_POST_DMA);
3922
3923                 skb->nh.iph->check = 0;
3924                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3925                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3926                         skb->h.th->check = 0;
3927                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3928                 }
3929                 else {
3930                         skb->h.th->check =
3931                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3932                                                    skb->nh.iph->daddr,
3933                                                    0, IPPROTO_TCP, 0);
3934                 }
3935
3936                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3937                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3938                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3939                                 int tsflags;
3940
3941                                 tsflags = ((skb->nh.iph->ihl - 5) +
3942                                            (tcp_opt_len >> 2));
3943                                 mss |= (tsflags << 11);
3944                         }
3945                 } else {
3946                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3947                                 int tsflags;
3948
3949                                 tsflags = ((skb->nh.iph->ihl - 5) +
3950                                            (tcp_opt_len >> 2));
3951                                 base_flags |= tsflags << 12;
3952                         }
3953                 }
3954         }
3955 #else
3956         mss = 0;
3957 #endif
3958 #if TG3_VLAN_TAG_USED
3959         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3960                 base_flags |= (TXD_FLAG_VLAN |
3961                                (vlan_tx_tag_get(skb) << 16));
3962 #endif
3963
3964         /* Queue skb data, a.k.a. the main skb fragment. */
3965         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3966
3967         tp->tx_buffers[entry].skb = skb;
3968         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3969
3970         would_hit_hwbug = 0;
3971
3972         if (tg3_4g_overflow_test(mapping, len))
3973                 would_hit_hwbug = 1;
3974
3975         tg3_set_txd(tp, entry, mapping, len, base_flags,
3976                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3977
3978         entry = NEXT_TX(entry);
3979
3980         /* Now loop through additional data fragments, and queue them. */
3981         if (skb_shinfo(skb)->nr_frags > 0) {
3982                 unsigned int i, last;
3983
3984                 last = skb_shinfo(skb)->nr_frags - 1;
3985                 for (i = 0; i <= last; i++) {
3986                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3987
3988                         len = frag->size;
3989                         mapping = pci_map_page(tp->pdev,
3990                                                frag->page,
3991                                                frag->page_offset,
3992                                                len, PCI_DMA_TODEVICE);
3993
3994                         tp->tx_buffers[entry].skb = NULL;
3995                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3996
3997                         if (tg3_4g_overflow_test(mapping, len))
3998                                 would_hit_hwbug = 1;
3999
4000                         if (tg3_40bit_overflow_test(tp, mapping, len))
4001                                 would_hit_hwbug = 1;
4002
4003                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4004                                 tg3_set_txd(tp, entry, mapping, len,
4005                                             base_flags, (i == last)|(mss << 1));
4006                         else
4007                                 tg3_set_txd(tp, entry, mapping, len,
4008                                             base_flags, (i == last));
4009
4010                         entry = NEXT_TX(entry);
4011                 }
4012         }
4013
4014         if (would_hit_hwbug) {
4015                 u32 last_plus_one = entry;
4016                 u32 start;
4017
4018                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4019                 start &= (TG3_TX_RING_SIZE - 1);
4020
4021                 /* If the workaround fails due to memory/mapping
4022                  * failure, silently drop this packet.
4023                  */
4024                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4025                                                 &start, base_flags, mss))
4026                         goto out_unlock;
4027
4028                 entry = start;
4029         }
4030
4031         /* Packets are ready, update Tx producer idx local and on card. */
4032         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4033
4034         tp->tx_prod = entry;
4035         if (unlikely(TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))) {
4036                 spin_lock(&tp->tx_lock);
4037                 netif_stop_queue(dev);
4038                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
4039                         netif_wake_queue(tp->dev);
4040                 spin_unlock(&tp->tx_lock);
4041         }
4042
4043 out_unlock:
4044         mmiowb();
4045
4046         dev->trans_start = jiffies;
4047
4048         return NETDEV_TX_OK;
4049 }
4050
4051 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4052                                int new_mtu)
4053 {
4054         dev->mtu = new_mtu;
4055
4056         if (new_mtu > ETH_DATA_LEN) {
4057                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4058                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4059                         ethtool_op_set_tso(dev, 0);
4060                 }
4061                 else
4062                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4063         } else {
4064                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4065                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4066                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4067         }
4068 }
4069
4070 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4071 {
4072         struct tg3 *tp = netdev_priv(dev);
4073
4074         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4075                 return -EINVAL;
4076
4077         if (!netif_running(dev)) {
4078                 /* We'll just catch it later when the
4079                  * device is up'd.
4080                  */
4081                 tg3_set_mtu(dev, tp, new_mtu);
4082                 return 0;
4083         }
4084
4085         tg3_netif_stop(tp);
4086
4087         tg3_full_lock(tp, 1);
4088
4089         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4090
4091         tg3_set_mtu(dev, tp, new_mtu);
4092
4093         tg3_init_hw(tp, 0);
4094
4095         tg3_netif_start(tp);
4096
4097         tg3_full_unlock(tp);
4098
4099         return 0;
4100 }
4101
4102 /* Free up pending packets in all rx/tx rings.
4103  *
4104  * The chip has been shut down and the driver detached from
4105  * the networking, so no interrupts or new tx packets will
4106  * end up in the driver.  tp->{tx,}lock is not held and we are not
4107  * in an interrupt context and thus may sleep.
4108  */
4109 static void tg3_free_rings(struct tg3 *tp)
4110 {
4111         struct ring_info *rxp;
4112         int i;
4113
4114         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4115                 rxp = &tp->rx_std_buffers[i];
4116
4117                 if (rxp->skb == NULL)
4118                         continue;
4119                 pci_unmap_single(tp->pdev,
4120                                  pci_unmap_addr(rxp, mapping),
4121                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4122                                  PCI_DMA_FROMDEVICE);
4123                 dev_kfree_skb_any(rxp->skb);
4124                 rxp->skb = NULL;
4125         }
4126
4127         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4128                 rxp = &tp->rx_jumbo_buffers[i];
4129
4130                 if (rxp->skb == NULL)
4131                         continue;
4132                 pci_unmap_single(tp->pdev,
4133                                  pci_unmap_addr(rxp, mapping),
4134                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4135                                  PCI_DMA_FROMDEVICE);
4136                 dev_kfree_skb_any(rxp->skb);
4137                 rxp->skb = NULL;
4138         }
4139
4140         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4141                 struct tx_ring_info *txp;
4142                 struct sk_buff *skb;
4143                 int j;
4144
4145                 txp = &tp->tx_buffers[i];
4146                 skb = txp->skb;
4147
4148                 if (skb == NULL) {
4149                         i++;
4150                         continue;
4151                 }
4152
4153                 pci_unmap_single(tp->pdev,
4154                                  pci_unmap_addr(txp, mapping),
4155                                  skb_headlen(skb),
4156                                  PCI_DMA_TODEVICE);
4157                 txp->skb = NULL;
4158
4159                 i++;
4160
4161                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4162                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4163                         pci_unmap_page(tp->pdev,
4164                                        pci_unmap_addr(txp, mapping),
4165                                        skb_shinfo(skb)->frags[j].size,
4166                                        PCI_DMA_TODEVICE);
4167                         i++;
4168                 }
4169
4170                 dev_kfree_skb_any(skb);
4171         }
4172 }
4173
4174 /* Initialize tx/rx rings for packet processing.
4175  *
4176  * The chip has been shut down and the driver detached from
4177  * the networking, so no interrupts or new tx packets will
4178  * end up in the driver.  tp->{tx,}lock are held and thus
4179  * we may not sleep.
4180  */
4181 static void tg3_init_rings(struct tg3 *tp)
4182 {
4183         u32 i;
4184
4185         /* Free up all the SKBs. */
4186         tg3_free_rings(tp);
4187
4188         /* Zero out all descriptors. */
4189         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4190         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4191         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4192         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4193
4194         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4195         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4196             (tp->dev->mtu > ETH_DATA_LEN))
4197                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4198
4199         /* Initialize invariants of the rings, we only set this
4200          * stuff once.  This works because the card does not
4201          * write into the rx buffer posting rings.
4202          */
4203         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4204                 struct tg3_rx_buffer_desc *rxd;
4205
4206                 rxd = &tp->rx_std[i];
4207                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4208                         << RXD_LEN_SHIFT;
4209                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4210                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4211                                (i << RXD_OPAQUE_INDEX_SHIFT));
4212         }
4213
4214         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4215                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4216                         struct tg3_rx_buffer_desc *rxd;
4217
4218                         rxd = &tp->rx_jumbo[i];
4219                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4220                                 << RXD_LEN_SHIFT;
4221                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4222                                 RXD_FLAG_JUMBO;
4223                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4224                                (i << RXD_OPAQUE_INDEX_SHIFT));
4225                 }
4226         }
4227
4228         /* Now allocate fresh SKBs for each rx ring. */
4229         for (i = 0; i < tp->rx_pending; i++) {
4230                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
4231                                      -1, i) < 0)
4232                         break;
4233         }
4234
4235         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4236                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4237                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4238                                              -1, i) < 0)
4239                                 break;
4240                 }
4241         }
4242 }
4243
4244 /*
4245  * Must not be invoked with interrupt sources disabled and
4246  * the hardware shutdown down.
4247  */
4248 static void tg3_free_consistent(struct tg3 *tp)
4249 {
4250         kfree(tp->rx_std_buffers);
4251         tp->rx_std_buffers = NULL;
4252         if (tp->rx_std) {
4253                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4254                                     tp->rx_std, tp->rx_std_mapping);
4255                 tp->rx_std = NULL;
4256         }
4257         if (tp->rx_jumbo) {
4258                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4259                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4260                 tp->rx_jumbo = NULL;
4261         }
4262         if (tp->rx_rcb) {
4263                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4264                                     tp->rx_rcb, tp->rx_rcb_mapping);
4265                 tp->rx_rcb = NULL;
4266         }
4267         if (tp->tx_ring) {
4268                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4269                         tp->tx_ring, tp->tx_desc_mapping);
4270                 tp->tx_ring = NULL;
4271         }
4272         if (tp->hw_status) {
4273                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4274                                     tp->hw_status, tp->status_mapping);
4275                 tp->hw_status = NULL;
4276         }
4277         if (tp->hw_stats) {
4278                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4279                                     tp->hw_stats, tp->stats_mapping);
4280                 tp->hw_stats = NULL;
4281         }
4282 }
4283
4284 /*
4285  * Must not be invoked with interrupt sources disabled and
4286  * the hardware shutdown down.  Can sleep.
4287  */
4288 static int tg3_alloc_consistent(struct tg3 *tp)
4289 {
4290         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4291                                       (TG3_RX_RING_SIZE +
4292                                        TG3_RX_JUMBO_RING_SIZE)) +
4293                                      (sizeof(struct tx_ring_info) *
4294                                       TG3_TX_RING_SIZE),
4295                                      GFP_KERNEL);
4296         if (!tp->rx_std_buffers)
4297                 return -ENOMEM;
4298
4299         memset(tp->rx_std_buffers, 0,
4300                (sizeof(struct ring_info) *
4301                 (TG3_RX_RING_SIZE +
4302                  TG3_RX_JUMBO_RING_SIZE)) +
4303                (sizeof(struct tx_ring_info) *
4304                 TG3_TX_RING_SIZE));
4305
4306         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4307         tp->tx_buffers = (struct tx_ring_info *)
4308                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4309
4310         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4311                                           &tp->rx_std_mapping);
4312         if (!tp->rx_std)
4313                 goto err_out;
4314
4315         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4316                                             &tp->rx_jumbo_mapping);
4317
4318         if (!tp->rx_jumbo)
4319                 goto err_out;
4320
4321         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4322                                           &tp->rx_rcb_mapping);
4323         if (!tp->rx_rcb)
4324                 goto err_out;
4325
4326         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4327                                            &tp->tx_desc_mapping);
4328         if (!tp->tx_ring)
4329                 goto err_out;
4330
4331         tp->hw_status = pci_alloc_consistent(tp->pdev,
4332                                              TG3_HW_STATUS_SIZE,
4333                                              &tp->status_mapping);
4334         if (!tp->hw_status)
4335                 goto err_out;
4336
4337         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4338                                             sizeof(struct tg3_hw_stats),
4339                                             &tp->stats_mapping);
4340         if (!tp->hw_stats)
4341                 goto err_out;
4342
4343         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4344         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4345
4346         return 0;
4347
4348 err_out:
4349         tg3_free_consistent(tp);
4350         return -ENOMEM;
4351 }
4352
4353 #define MAX_WAIT_CNT 1000
4354
4355 /* To stop a block, clear the enable bit and poll till it
4356  * clears.  tp->lock is held.
4357  */
4358 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4359 {
4360         unsigned int i;
4361         u32 val;
4362
4363         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4364                 switch (ofs) {
4365                 case RCVLSC_MODE:
4366                 case DMAC_MODE:
4367                 case MBFREE_MODE:
4368                 case BUFMGR_MODE:
4369                 case MEMARB_MODE:
4370                         /* We can't enable/disable these bits of the
4371                          * 5705/5750, just say success.
4372                          */
4373                         return 0;
4374
4375                 default:
4376                         break;
4377                 };
4378         }
4379
4380         val = tr32(ofs);
4381         val &= ~enable_bit;
4382         tw32_f(ofs, val);
4383
4384         for (i = 0; i < MAX_WAIT_CNT; i++) {
4385                 udelay(100);
4386                 val = tr32(ofs);
4387                 if ((val & enable_bit) == 0)
4388                         break;
4389         }
4390
4391         if (i == MAX_WAIT_CNT && !silent) {
4392                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4393                        "ofs=%lx enable_bit=%x\n",
4394                        ofs, enable_bit);
4395                 return -ENODEV;
4396         }
4397
4398         return 0;
4399 }
4400
4401 /* tp->lock is held. */
4402 static int tg3_abort_hw(struct tg3 *tp, int silent)
4403 {
4404         int i, err;
4405
4406         tg3_disable_ints(tp);
4407
4408         tp->rx_mode &= ~RX_MODE_ENABLE;
4409         tw32_f(MAC_RX_MODE, tp->rx_mode);
4410         udelay(10);
4411
4412         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4413         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4414         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4415         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4416         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4417         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4418
4419         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4420         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4421         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4422         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4423         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4424         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4425         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4426
4427         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4428         tw32_f(MAC_MODE, tp->mac_mode);
4429         udelay(40);
4430
4431         tp->tx_mode &= ~TX_MODE_ENABLE;
4432         tw32_f(MAC_TX_MODE, tp->tx_mode);
4433
4434         for (i = 0; i < MAX_WAIT_CNT; i++) {
4435                 udelay(100);
4436                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4437                         break;
4438         }
4439         if (i >= MAX_WAIT_CNT) {
4440                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4441                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4442                        tp->dev->name, tr32(MAC_TX_MODE));
4443                 err |= -ENODEV;
4444         }
4445
4446         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4447         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4448         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4449
4450         tw32(FTQ_RESET, 0xffffffff);
4451         tw32(FTQ_RESET, 0x00000000);
4452
4453         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4454         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4455
4456         if (tp->hw_status)
4457                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4458         if (tp->hw_stats)
4459                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4460
4461         return err;
4462 }
4463
4464 /* tp->lock is held. */
4465 static int tg3_nvram_lock(struct tg3 *tp)
4466 {
4467         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4468                 int i;
4469
4470                 if (tp->nvram_lock_cnt == 0) {
4471                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4472                         for (i = 0; i < 8000; i++) {
4473                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4474                                         break;
4475                                 udelay(20);
4476                         }
4477                         if (i == 8000) {
4478                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4479                                 return -ENODEV;
4480                         }
4481                 }
4482                 tp->nvram_lock_cnt++;
4483         }
4484         return 0;
4485 }
4486
4487 /* tp->lock is held. */
4488 static void tg3_nvram_unlock(struct tg3 *tp)
4489 {
4490         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4491                 if (tp->nvram_lock_cnt > 0)
4492                         tp->nvram_lock_cnt--;
4493                 if (tp->nvram_lock_cnt == 0)
4494                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4495         }
4496 }
4497
4498 /* tp->lock is held. */
4499 static void tg3_enable_nvram_access(struct tg3 *tp)
4500 {
4501         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4502             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4503                 u32 nvaccess = tr32(NVRAM_ACCESS);
4504
4505                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4506         }
4507 }
4508
4509 /* tp->lock is held. */
4510 static void tg3_disable_nvram_access(struct tg3 *tp)
4511 {
4512         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4513             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4514                 u32 nvaccess = tr32(NVRAM_ACCESS);
4515
4516                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4517         }
4518 }
4519
4520 /* tp->lock is held. */
4521 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4522 {
4523         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4524                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4525
4526         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4527                 switch (kind) {
4528                 case RESET_KIND_INIT:
4529                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4530                                       DRV_STATE_START);
4531                         break;
4532
4533                 case RESET_KIND_SHUTDOWN:
4534                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4535                                       DRV_STATE_UNLOAD);
4536                         break;
4537
4538                 case RESET_KIND_SUSPEND:
4539                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4540                                       DRV_STATE_SUSPEND);
4541                         break;
4542
4543                 default:
4544                         break;
4545                 };
4546         }
4547 }
4548
4549 /* tp->lock is held. */
4550 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4551 {
4552         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4553                 switch (kind) {
4554                 case RESET_KIND_INIT:
4555                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4556                                       DRV_STATE_START_DONE);
4557                         break;
4558
4559                 case RESET_KIND_SHUTDOWN:
4560                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4561                                       DRV_STATE_UNLOAD_DONE);
4562                         break;
4563
4564                 default:
4565                         break;
4566                 };
4567         }
4568 }
4569
4570 /* tp->lock is held. */
4571 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4572 {
4573         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4574                 switch (kind) {
4575                 case RESET_KIND_INIT:
4576                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4577                                       DRV_STATE_START);
4578                         break;
4579
4580                 case RESET_KIND_SHUTDOWN:
4581                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4582                                       DRV_STATE_UNLOAD);
4583                         break;
4584
4585                 case RESET_KIND_SUSPEND:
4586                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4587                                       DRV_STATE_SUSPEND);
4588                         break;
4589
4590                 default:
4591                         break;
4592                 };
4593         }
4594 }
4595
4596 static void tg3_stop_fw(struct tg3 *);
4597
4598 /* tp->lock is held. */
4599 static int tg3_chip_reset(struct tg3 *tp)
4600 {
4601         u32 val;
4602         void (*write_op)(struct tg3 *, u32, u32);
4603         int i;
4604
4605         tg3_nvram_lock(tp);
4606
4607         /* No matching tg3_nvram_unlock() after this because
4608          * chip reset below will undo the nvram lock.
4609          */
4610         tp->nvram_lock_cnt = 0;
4611
4612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4613             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4614             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4615                 tw32(GRC_FASTBOOT_PC, 0);
4616
4617         /*
4618          * We must avoid the readl() that normally takes place.
4619          * It locks machines, causes machine checks, and other
4620          * fun things.  So, temporarily disable the 5701
4621          * hardware workaround, while we do the reset.
4622          */
4623         write_op = tp->write32;
4624         if (write_op == tg3_write_flush_reg32)
4625                 tp->write32 = tg3_write32;
4626
4627         /* do the reset */
4628         val = GRC_MISC_CFG_CORECLK_RESET;
4629
4630         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4631                 if (tr32(0x7e2c) == 0x60) {
4632                         tw32(0x7e2c, 0x20);
4633                 }
4634                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4635                         tw32(GRC_MISC_CFG, (1 << 29));
4636                         val |= (1 << 29);
4637                 }
4638         }
4639
4640         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4641                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4642         tw32(GRC_MISC_CFG, val);
4643
4644         /* restore 5701 hardware bug workaround write method */
4645         tp->write32 = write_op;
4646
4647         /* Unfortunately, we have to delay before the PCI read back.
4648          * Some 575X chips even will not respond to a PCI cfg access
4649          * when the reset command is given to the chip.
4650          *
4651          * How do these hardware designers expect things to work
4652          * properly if the PCI write is posted for a long period
4653          * of time?  It is always necessary to have some method by
4654          * which a register read back can occur to push the write
4655          * out which does the reset.
4656          *
4657          * For most tg3 variants the trick below was working.
4658          * Ho hum...
4659          */
4660         udelay(120);
4661
4662         /* Flush PCI posted writes.  The normal MMIO registers
4663          * are inaccessible at this time so this is the only
4664          * way to make this reliably (actually, this is no longer
4665          * the case, see above).  I tried to use indirect
4666          * register read/write but this upset some 5701 variants.
4667          */
4668         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4669
4670         udelay(120);
4671
4672         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4673                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4674                         int i;
4675                         u32 cfg_val;
4676
4677                         /* Wait for link training to complete.  */
4678                         for (i = 0; i < 5000; i++)
4679                                 udelay(100);
4680
4681                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4682                         pci_write_config_dword(tp->pdev, 0xc4,
4683                                                cfg_val | (1 << 15));
4684                 }
4685                 /* Set PCIE max payload size and clear error status.  */
4686                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4687         }
4688
4689         /* Re-enable indirect register accesses. */
4690         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4691                                tp->misc_host_ctrl);
4692
4693         /* Set MAX PCI retry to zero. */
4694         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4695         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4696             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4697                 val |= PCISTATE_RETRY_SAME_DMA;
4698         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4699
4700         pci_restore_state(tp->pdev);
4701
4702         /* Make sure PCI-X relaxed ordering bit is clear. */
4703         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4704         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4705         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4706
4707         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4708                 u32 val;
4709
4710                 /* Chip reset on 5780 will reset MSI enable bit,
4711                  * so need to restore it.
4712                  */
4713                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4714                         u16 ctrl;
4715
4716                         pci_read_config_word(tp->pdev,
4717                                              tp->msi_cap + PCI_MSI_FLAGS,
4718                                              &ctrl);
4719                         pci_write_config_word(tp->pdev,
4720                                               tp->msi_cap + PCI_MSI_FLAGS,
4721                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4722                         val = tr32(MSGINT_MODE);
4723                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4724                 }
4725
4726                 val = tr32(MEMARB_MODE);
4727                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4728
4729         } else
4730                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4731
4732         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4733                 tg3_stop_fw(tp);
4734                 tw32(0x5000, 0x400);
4735         }
4736
4737         tw32(GRC_MODE, tp->grc_mode);
4738
4739         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4740                 u32 val = tr32(0xc4);
4741
4742                 tw32(0xc4, val | (1 << 15));
4743         }
4744
4745         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4746             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4747                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4748                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4749                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4750                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4751         }
4752
4753         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4754                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4755                 tw32_f(MAC_MODE, tp->mac_mode);
4756         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4757                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4758                 tw32_f(MAC_MODE, tp->mac_mode);
4759         } else
4760                 tw32_f(MAC_MODE, 0);
4761         udelay(40);
4762
4763         /* Wait for firmware initialization to complete. */
4764         for (i = 0; i < 100000; i++) {
4765                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4766                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4767                         break;
4768                 udelay(10);
4769         }
4770
4771         /* Chip might not be fitted with firmare.  Some Sun onboard
4772          * parts are configured like that.  So don't signal the timeout
4773          * of the above loop as an error, but do report the lack of
4774          * running firmware once.
4775          */
4776         if (i >= 100000 &&
4777             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4778                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4779
4780                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4781                        tp->dev->name);
4782         }
4783
4784         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4785             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4786                 u32 val = tr32(0x7c00);
4787
4788                 tw32(0x7c00, val | (1 << 25));
4789         }
4790
4791         /* Reprobe ASF enable state.  */
4792         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4793         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4794         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4795         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4796                 u32 nic_cfg;
4797
4798                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4799                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4800                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4801                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4802                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4803                 }
4804         }
4805
4806         return 0;
4807 }
4808
4809 /* tp->lock is held. */
4810 static void tg3_stop_fw(struct tg3 *tp)
4811 {
4812         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4813                 u32 val;
4814                 int i;
4815
4816                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4817                 val = tr32(GRC_RX_CPU_EVENT);
4818                 val |= (1 << 14);
4819                 tw32(GRC_RX_CPU_EVENT, val);
4820
4821                 /* Wait for RX cpu to ACK the event.  */
4822                 for (i = 0; i < 100; i++) {
4823                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4824                                 break;
4825                         udelay(1);
4826                 }
4827         }
4828 }
4829
4830 /* tp->lock is held. */
4831 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4832 {
4833         int err;
4834
4835         tg3_stop_fw(tp);
4836
4837         tg3_write_sig_pre_reset(tp, kind);
4838
4839         tg3_abort_hw(tp, silent);
4840         err = tg3_chip_reset(tp);
4841
4842         tg3_write_sig_legacy(tp, kind);
4843         tg3_write_sig_post_reset(tp, kind);
4844
4845         if (err)
4846                 return err;
4847
4848         return 0;
4849 }
4850
4851 #define TG3_FW_RELEASE_MAJOR    0x0
4852 #define TG3_FW_RELASE_MINOR     0x0
4853 #define TG3_FW_RELEASE_FIX      0x0
4854 #define TG3_FW_START_ADDR       0x08000000
4855 #define TG3_FW_TEXT_ADDR        0x08000000
4856 #define TG3_FW_TEXT_LEN         0x9c0
4857 #define TG3_FW_RODATA_ADDR      0x080009c0
4858 #define TG3_FW_RODATA_LEN       0x60
4859 #define TG3_FW_DATA_ADDR        0x08000a40
4860 #define TG3_FW_DATA_LEN         0x20
4861 #define TG3_FW_SBSS_ADDR        0x08000a60
4862 #define TG3_FW_SBSS_LEN         0xc
4863 #define TG3_FW_BSS_ADDR         0x08000a70
4864 #define TG3_FW_BSS_LEN          0x10
4865
4866 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4867         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4868         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4869         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4870         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4871         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4872         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4873         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4874         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4875         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4876         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4877         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4878         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4879         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4880         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4881         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4882         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4883         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4884         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4885         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4886         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4887         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4888         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4889         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4890         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4891         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4892         0, 0, 0, 0, 0, 0,
4893         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4894         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4895         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4896         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4897         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4898         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4899         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4900         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4901         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4902         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4903         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4904         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4905         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4906         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4907         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4908         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4909         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4910         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4911         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4912         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4913         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4914         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4915         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4916         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4917         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4918         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4919         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4920         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4921         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4922         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4923         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4924         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4925         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4926         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4927         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4928         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4929         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4930         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4931         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4932         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4933         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4934         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4935         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4936         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4937         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4938         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4939         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4940         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4941         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4942         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4943         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4944         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4945         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4946         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4947         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4948         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4949         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4950         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4951         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4952         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4953         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4954         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4955         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4956         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4957         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4958 };
4959
4960 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4961         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4962         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4963         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4964         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4965         0x00000000
4966 };
4967
4968 #if 0 /* All zeros, don't eat up space with it. */
4969 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4970         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4971         0x00000000, 0x00000000, 0x00000000, 0x00000000
4972 };
4973 #endif
4974
4975 #define RX_CPU_SCRATCH_BASE     0x30000
4976 #define RX_CPU_SCRATCH_SIZE     0x04000
4977 #define TX_CPU_SCRATCH_BASE     0x34000
4978 #define TX_CPU_SCRATCH_SIZE     0x04000
4979
4980 /* tp->lock is held. */
4981 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4982 {
4983         int i;
4984
4985         BUG_ON(offset == TX_CPU_BASE &&
4986             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
4987
4988         if (offset == RX_CPU_BASE) {
4989                 for (i = 0; i < 10000; i++) {
4990                         tw32(offset + CPU_STATE, 0xffffffff);
4991                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4992                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4993                                 break;
4994                 }
4995
4996                 tw32(offset + CPU_STATE, 0xffffffff);
4997                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4998                 udelay(10);
4999         } else {
5000                 for (i = 0; i < 10000; i++) {
5001                         tw32(offset + CPU_STATE, 0xffffffff);
5002                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5003                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5004                                 break;
5005                 }
5006         }
5007
5008         if (i >= 10000) {
5009                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5010                        "and %s CPU\n",
5011                        tp->dev->name,
5012                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5013                 return -ENODEV;
5014         }
5015
5016         /* Clear firmware's nvram arbitration. */
5017         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5018                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5019         return 0;
5020 }
5021
5022 struct fw_info {
5023         unsigned int text_base;
5024         unsigned int text_len;
5025         u32 *text_data;
5026         unsigned int rodata_base;
5027         unsigned int rodata_len;
5028         u32 *rodata_data;
5029         unsigned int data_base;
5030         unsigned int data_len;
5031         u32 *data_data;
5032 };
5033
5034 /* tp->lock is held. */
5035 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5036                                  int cpu_scratch_size, struct fw_info *info)
5037 {
5038         int err, lock_err, i;
5039         void (*write_op)(struct tg3 *, u32, u32);
5040
5041         if (cpu_base == TX_CPU_BASE &&
5042             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5043                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5044                        "TX cpu firmware on %s which is 5705.\n",
5045                        tp->dev->name);
5046                 return -EINVAL;
5047         }
5048
5049         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5050                 write_op = tg3_write_mem;
5051         else
5052                 write_op = tg3_write_indirect_reg32;
5053
5054         /* It is possible that bootcode is still loading at this point.
5055          * Get the nvram lock first before halting the cpu.
5056          */
5057         lock_err = tg3_nvram_lock(tp);
5058         err = tg3_halt_cpu(tp, cpu_base);
5059         if (!lock_err)
5060                 tg3_nvram_unlock(tp);
5061         if (err)
5062                 goto out;
5063
5064         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5065                 write_op(tp, cpu_scratch_base + i, 0);
5066         tw32(cpu_base + CPU_STATE, 0xffffffff);
5067         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5068         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5069                 write_op(tp, (cpu_scratch_base +
5070                               (info->text_base & 0xffff) +
5071                               (i * sizeof(u32))),
5072                          (info->text_data ?
5073                           info->text_data[i] : 0));
5074         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5075                 write_op(tp, (cpu_scratch_base +
5076                               (info->rodata_base & 0xffff) +
5077                               (i * sizeof(u32))),
5078                          (info->rodata_data ?
5079                           info->rodata_data[i] : 0));
5080         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5081                 write_op(tp, (cpu_scratch_base +
5082                               (info->data_base & 0xffff) +
5083                               (i * sizeof(u32))),
5084                          (info->data_data ?
5085                           info->data_data[i] : 0));
5086
5087         err = 0;
5088
5089 out:
5090         return err;
5091 }
5092
5093 /* tp->lock is held. */
5094 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5095 {
5096         struct fw_info info;
5097         int err, i;
5098
5099         info.text_base = TG3_FW_TEXT_ADDR;
5100         info.text_len = TG3_FW_TEXT_LEN;
5101         info.text_data = &tg3FwText[0];
5102         info.rodata_base = TG3_FW_RODATA_ADDR;
5103         info.rodata_len = TG3_FW_RODATA_LEN;
5104         info.rodata_data = &tg3FwRodata[0];
5105         info.data_base = TG3_FW_DATA_ADDR;
5106         info.data_len = TG3_FW_DATA_LEN;
5107         info.data_data = NULL;
5108
5109         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5110                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5111                                     &info);
5112         if (err)
5113                 return err;
5114
5115         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5116                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5117                                     &info);
5118         if (err)
5119                 return err;
5120
5121         /* Now startup only the RX cpu. */
5122         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5123         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5124
5125         for (i = 0; i < 5; i++) {
5126                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5127                         break;
5128                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5129                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5130                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5131                 udelay(1000);
5132         }
5133         if (i >= 5) {
5134                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5135                        "to set RX CPU PC, is %08x should be %08x\n",
5136                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5137                        TG3_FW_TEXT_ADDR);
5138                 return -ENODEV;
5139         }
5140         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5141         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5142
5143         return 0;
5144 }
5145
5146 #if TG3_TSO_SUPPORT != 0
5147
5148 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5149 #define TG3_TSO_FW_RELASE_MINOR         0x6
5150 #define TG3_TSO_FW_RELEASE_FIX          0x0
5151 #define TG3_TSO_FW_START_ADDR           0x08000000
5152 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5153 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5154 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5155 #define TG3_TSO_FW_RODATA_LEN           0x60
5156 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5157 #define TG3_TSO_FW_DATA_LEN             0x30
5158 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5159 #define TG3_TSO_FW_SBSS_LEN             0x2c
5160 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5161 #define TG3_TSO_FW_BSS_LEN              0x894
5162
5163 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5164         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5165         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5166         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5167         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5168         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5169         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5170         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5171         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5172         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5173         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5174         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5175         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5176         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5177         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5178         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5179         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5180         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5181         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5182         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5183         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5184         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5185         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5186         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5187         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5188         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5189         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5190         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5191         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5192         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5193         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5194         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5195         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5196         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5197         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5198         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5199         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5200         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5201         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5202         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5203         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5204         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5205         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5206         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5207         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5208         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5209         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5210         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5211         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5212         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5213         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5214         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5215         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5216         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5217         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5218         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5219         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5220         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5221         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5222         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5223         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5224         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5225         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5226         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5227         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5228         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5229         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5230         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5231         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5232         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5233         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5234         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5235         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5236         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5237         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5238         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5239         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5240         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5241         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5242         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5243         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5244         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5245         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5246         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5247         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5248         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5249         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5250         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5251         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5252         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5253         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5254         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5255         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5256         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5257         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5258         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5259         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5260         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5261         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5262         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5263         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5264         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5265         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5266         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5267         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5268         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5269         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5270         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5271         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5272         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5273         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5274         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5275         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5276         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5277         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5278         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5279         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5280         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5281         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5282         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5283         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5284         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5285         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5286         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5287         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5288         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5289         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5290         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5291         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5292         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5293         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5294         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5295         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5296         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5297         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5298         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5299         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5300         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5301         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5302         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5303         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5304         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5305         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5306         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5307         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5308         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5309         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5310         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5311         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5312         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5313         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5314         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5315         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5316         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5317         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5318         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5319         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5320         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5321         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5322         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5323         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5324         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5325         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5326         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5327         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5328         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5329         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5330         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5331         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5332         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5333         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5334         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5335         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5336         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5337         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5338         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5339         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5340         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5341         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5342         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5343         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5344         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5345         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5346         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5347         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5348         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5349         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5350         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5351         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5352         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5353         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5354         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5355         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5356         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5357         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5358         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5359         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5360         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5361         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5362         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5363         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5364         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5365         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5366         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5367         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5368         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5369         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5370         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5371         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5372         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5373         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5374         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5375         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5376         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5377         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5378         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5379         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5380         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5381         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5382         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5383         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5384         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5385         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5386         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5387         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5388         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5389         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5390         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5391         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5392         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5393         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5394         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5395         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5396         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5397         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5398         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5399         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5400         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5401         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5402         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5403         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5404         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5405         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5406         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5407         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5408         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5409         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5410         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5411         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5412         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5413         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5414         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5415         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5416         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5417         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5418         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5419         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5420         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5421         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5422         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5423         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5424         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5425         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5426         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5427         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5428         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5429         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5430         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5431         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5432         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5433         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5434         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5435         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5436         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5437         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5438         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5439         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5440         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5441         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5442         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5443         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5444         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5445         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5446         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5447         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5448 };
5449
5450 static u32 tg3TsoFwRodata[] = {
5451         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5452         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5453         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5454         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5455         0x00000000,
5456 };
5457
5458 static u32 tg3TsoFwData[] = {
5459         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5460         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5461         0x00000000,
5462 };
5463
5464 /* 5705 needs a special version of the TSO firmware.  */
5465 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5466 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5467 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5468 #define TG3_TSO5_FW_START_ADDR          0x00010000
5469 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5470 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5471 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5472 #define TG3_TSO5_FW_RODATA_LEN          0x50
5473 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5474 #define TG3_TSO5_FW_DATA_LEN            0x20
5475 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5476 #define TG3_TSO5_FW_SBSS_LEN            0x28
5477 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5478 #define TG3_TSO5_FW_BSS_LEN             0x88
5479
5480 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5481         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5482         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5483         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5484         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5485         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5486         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5487         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5488         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5489         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5490         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5491         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5492         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5493         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5494         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5495         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5496         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5497         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5498         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5499         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5500         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5501         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5502         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5503         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5504         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5505         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5506         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5507         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5508         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5509         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5510         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5511         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5512         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5513         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5514         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5515         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5516         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5517         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5518         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5519         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5520         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5521         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5522         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5523         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5524         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5525         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5526         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5527         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5528         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5529         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5530         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5531         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5532         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5533         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5534         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5535         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5536         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5537         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5538         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5539         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5540         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5541         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5542         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5543         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5544         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5545         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5546         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5547         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5548         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5549         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5550         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5551         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5552         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5553         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5554         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5555         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5556         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5557         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5558         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5559         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5560         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5561         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5562         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5563         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5564         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5565         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5566         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5567         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5568         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5569         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5570         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5571         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5572         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5573         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5574         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5575         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5576         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5577         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5578         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5579         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5580         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5581         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5582         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5583         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5584         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5585         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5586         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5587         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5588         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5589         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5590         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5591         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5592         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5593         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5594         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5595         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5596         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5597         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5598         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5599         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5600         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5601         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5602         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5603         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5604         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5605         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5606         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5607         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5608         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5609         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5610         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5611         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5612         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5613         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5614         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5615         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5616         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5617         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5618         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5619         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5620         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5621         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5622         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5623         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5624         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5625         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5626         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5627         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5628         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5629         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5630         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5631         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5632         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5633         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5634         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5635         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5636         0x00000000, 0x00000000, 0x00000000,
5637 };
5638
5639 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5640         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5641         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5642         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5643         0x00000000, 0x00000000, 0x00000000,
5644 };
5645
5646 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5647         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5648         0x00000000, 0x00000000, 0x00000000,
5649 };
5650
5651 /* tp->lock is held. */
5652 static int tg3_load_tso_firmware(struct tg3 *tp)
5653 {
5654         struct fw_info info;
5655         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5656         int err, i;
5657
5658         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5659                 return 0;
5660
5661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5662                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5663                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5664                 info.text_data = &tg3Tso5FwText[0];
5665                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5666                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5667                 info.rodata_data = &tg3Tso5FwRodata[0];
5668                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5669                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5670                 info.data_data = &tg3Tso5FwData[0];
5671                 cpu_base = RX_CPU_BASE;
5672                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5673                 cpu_scratch_size = (info.text_len +
5674                                     info.rodata_len +
5675                                     info.data_len +
5676                                     TG3_TSO5_FW_SBSS_LEN +
5677                                     TG3_TSO5_FW_BSS_LEN);
5678         } else {
5679                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5680                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5681                 info.text_data = &tg3TsoFwText[0];
5682                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5683                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5684                 info.rodata_data = &tg3TsoFwRodata[0];
5685                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5686                 info.data_len = TG3_TSO_FW_DATA_LEN;
5687                 info.data_data = &tg3TsoFwData[0];
5688                 cpu_base = TX_CPU_BASE;
5689                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5690                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5691         }
5692
5693         err = tg3_load_firmware_cpu(tp, cpu_base,
5694                                     cpu_scratch_base, cpu_scratch_size,
5695                                     &info);
5696         if (err)
5697                 return err;
5698
5699         /* Now startup the cpu. */
5700         tw32(cpu_base + CPU_STATE, 0xffffffff);
5701         tw32_f(cpu_base + CPU_PC,    info.text_base);
5702
5703         for (i = 0; i < 5; i++) {
5704                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5705                         break;
5706                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5707                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5708                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5709                 udelay(1000);
5710         }
5711         if (i >= 5) {
5712                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5713                        "to set CPU PC, is %08x should be %08x\n",
5714                        tp->dev->name, tr32(cpu_base + CPU_PC),
5715                        info.text_base);
5716                 return -ENODEV;
5717         }
5718         tw32(cpu_base + CPU_STATE, 0xffffffff);
5719         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5720         return 0;
5721 }
5722
5723 #endif /* TG3_TSO_SUPPORT != 0 */
5724
5725 /* tp->lock is held. */
5726 static void __tg3_set_mac_addr(struct tg3 *tp)
5727 {
5728         u32 addr_high, addr_low;
5729         int i;
5730
5731         addr_high = ((tp->dev->dev_addr[0] << 8) |
5732                      tp->dev->dev_addr[1]);
5733         addr_low = ((tp->dev->dev_addr[2] << 24) |
5734                     (tp->dev->dev_addr[3] << 16) |
5735                     (tp->dev->dev_addr[4] <<  8) |
5736                     (tp->dev->dev_addr[5] <<  0));
5737         for (i = 0; i < 4; i++) {
5738                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5739                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5740         }
5741
5742         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5743             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5744                 for (i = 0; i < 12; i++) {
5745                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5746                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5747                 }
5748         }
5749
5750         addr_high = (tp->dev->dev_addr[0] +
5751                      tp->dev->dev_addr[1] +
5752                      tp->dev->dev_addr[2] +
5753                      tp->dev->dev_addr[3] +
5754                      tp->dev->dev_addr[4] +
5755                      tp->dev->dev_addr[5]) &
5756                 TX_BACKOFF_SEED_MASK;
5757         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5758 }
5759
5760 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5761 {
5762         struct tg3 *tp = netdev_priv(dev);
5763         struct sockaddr *addr = p;
5764
5765         if (!is_valid_ether_addr(addr->sa_data))
5766                 return -EINVAL;
5767
5768         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5769
5770         if (!netif_running(dev))
5771                 return 0;
5772
5773         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5774                 /* Reset chip so that ASF can re-init any MAC addresses it
5775                  * needs.
5776                  */
5777                 tg3_netif_stop(tp);
5778                 tg3_full_lock(tp, 1);
5779
5780                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5781                 tg3_init_hw(tp, 0);
5782
5783                 tg3_netif_start(tp);
5784                 tg3_full_unlock(tp);
5785         } else {
5786                 spin_lock_bh(&tp->lock);
5787                 __tg3_set_mac_addr(tp);
5788                 spin_unlock_bh(&tp->lock);
5789         }
5790
5791         return 0;
5792 }
5793
5794 /* tp->lock is held. */
5795 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5796                            dma_addr_t mapping, u32 maxlen_flags,
5797                            u32 nic_addr)
5798 {
5799         tg3_write_mem(tp,
5800                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5801                       ((u64) mapping >> 32));
5802         tg3_write_mem(tp,
5803                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5804                       ((u64) mapping & 0xffffffff));
5805         tg3_write_mem(tp,
5806                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5807                        maxlen_flags);
5808
5809         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5810                 tg3_write_mem(tp,
5811                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5812                               nic_addr);
5813 }
5814
5815 static void __tg3_set_rx_mode(struct net_device *);
5816 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5817 {
5818         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5819         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5820         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5821         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5822         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5823                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5824                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5825         }
5826         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5827         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5828         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5829                 u32 val = ec->stats_block_coalesce_usecs;
5830
5831                 if (!netif_carrier_ok(tp->dev))
5832                         val = 0;
5833
5834                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5835         }
5836 }
5837
5838 /* tp->lock is held. */
5839 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5840 {
5841         u32 val, rdmac_mode;
5842         int i, err, limit;
5843
5844         tg3_disable_ints(tp);
5845
5846         tg3_stop_fw(tp);
5847
5848         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5849
5850         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5851                 tg3_abort_hw(tp, 1);
5852         }
5853
5854         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5855                 tg3_phy_reset(tp);
5856
5857         err = tg3_chip_reset(tp);
5858         if (err)
5859                 return err;
5860
5861         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5862
5863         /* This works around an issue with Athlon chipsets on
5864          * B3 tigon3 silicon.  This bit has no effect on any
5865          * other revision.  But do not set this on PCI Express
5866          * chips.
5867          */
5868         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5869                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5870         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5871
5872         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5873             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5874                 val = tr32(TG3PCI_PCISTATE);
5875                 val |= PCISTATE_RETRY_SAME_DMA;
5876                 tw32(TG3PCI_PCISTATE, val);
5877         }
5878
5879         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5880                 /* Enable some hw fixes.  */
5881                 val = tr32(TG3PCI_MSI_DATA);
5882                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5883                 tw32(TG3PCI_MSI_DATA, val);
5884         }
5885
5886         /* Descriptor ring init may make accesses to the
5887          * NIC SRAM area to setup the TX descriptors, so we
5888          * can only do this after the hardware has been
5889          * successfully reset.
5890          */
5891         tg3_init_rings(tp);
5892
5893         /* This value is determined during the probe time DMA
5894          * engine test, tg3_test_dma.
5895          */
5896         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5897
5898         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5899                           GRC_MODE_4X_NIC_SEND_RINGS |
5900                           GRC_MODE_NO_TX_PHDR_CSUM |
5901                           GRC_MODE_NO_RX_PHDR_CSUM);
5902         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5903
5904         /* Pseudo-header checksum is done by hardware logic and not
5905          * the offload processers, so make the chip do the pseudo-
5906          * header checksums on receive.  For transmit it is more
5907          * convenient to do the pseudo-header checksum in software
5908          * as Linux does that on transmit for us in all cases.
5909          */
5910         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5911
5912         tw32(GRC_MODE,
5913              tp->grc_mode |
5914              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5915
5916         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5917         val = tr32(GRC_MISC_CFG);
5918         val &= ~0xff;
5919         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5920         tw32(GRC_MISC_CFG, val);
5921
5922         /* Initialize MBUF/DESC pool. */
5923         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5924                 /* Do nothing.  */
5925         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5926                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5927                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5928                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5929                 else
5930                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5931                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5932                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5933         }
5934 #if TG3_TSO_SUPPORT != 0
5935         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5936                 int fw_len;
5937
5938                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5939                           TG3_TSO5_FW_RODATA_LEN +
5940                           TG3_TSO5_FW_DATA_LEN +
5941                           TG3_TSO5_FW_SBSS_LEN +
5942                           TG3_TSO5_FW_BSS_LEN);
5943                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5944                 tw32(BUFMGR_MB_POOL_ADDR,
5945                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5946                 tw32(BUFMGR_MB_POOL_SIZE,
5947                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5948         }
5949 #endif
5950
5951         if (tp->dev->mtu <= ETH_DATA_LEN) {
5952                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5953                      tp->bufmgr_config.mbuf_read_dma_low_water);
5954                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5955                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5956                 tw32(BUFMGR_MB_HIGH_WATER,
5957                      tp->bufmgr_config.mbuf_high_water);
5958         } else {
5959                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5960                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5961                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5962                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5963                 tw32(BUFMGR_MB_HIGH_WATER,
5964                      tp->bufmgr_config.mbuf_high_water_jumbo);
5965         }
5966         tw32(BUFMGR_DMA_LOW_WATER,
5967              tp->bufmgr_config.dma_low_water);
5968         tw32(BUFMGR_DMA_HIGH_WATER,
5969              tp->bufmgr_config.dma_high_water);
5970
5971         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5972         for (i = 0; i < 2000; i++) {
5973                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5974                         break;
5975                 udelay(10);
5976         }
5977         if (i >= 2000) {
5978                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5979                        tp->dev->name);
5980                 return -ENODEV;
5981         }
5982
5983         /* Setup replenish threshold. */
5984         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5985
5986         /* Initialize TG3_BDINFO's at:
5987          *  RCVDBDI_STD_BD:     standard eth size rx ring
5988          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5989          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5990          *
5991          * like so:
5992          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5993          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5994          *                              ring attribute flags
5995          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5996          *
5997          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5998          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5999          *
6000          * The size of each ring is fixed in the firmware, but the location is
6001          * configurable.
6002          */
6003         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6004              ((u64) tp->rx_std_mapping >> 32));
6005         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6006              ((u64) tp->rx_std_mapping & 0xffffffff));
6007         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6008              NIC_SRAM_RX_BUFFER_DESC);
6009
6010         /* Don't even try to program the JUMBO/MINI buffer descriptor
6011          * configs on 5705.
6012          */
6013         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6014                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6015                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6016         } else {
6017                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6018                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6019
6020                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6021                      BDINFO_FLAGS_DISABLED);
6022
6023                 /* Setup replenish threshold. */
6024                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6025
6026                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6027                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6028                              ((u64) tp->rx_jumbo_mapping >> 32));
6029                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6030                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6031                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6032                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6033                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6034                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6035                 } else {
6036                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6037                              BDINFO_FLAGS_DISABLED);
6038                 }
6039
6040         }
6041
6042         /* There is only one send ring on 5705/5750, no need to explicitly
6043          * disable the others.
6044          */
6045         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6046                 /* Clear out send RCB ring in SRAM. */
6047                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6048                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6049                                       BDINFO_FLAGS_DISABLED);
6050         }
6051
6052         tp->tx_prod = 0;
6053         tp->tx_cons = 0;
6054         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6055         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6056
6057         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6058                        tp->tx_desc_mapping,
6059                        (TG3_TX_RING_SIZE <<
6060                         BDINFO_FLAGS_MAXLEN_SHIFT),
6061                        NIC_SRAM_TX_BUFFER_DESC);
6062
6063         /* There is only one receive return ring on 5705/5750, no need
6064          * to explicitly disable the others.
6065          */
6066         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6067                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6068                      i += TG3_BDINFO_SIZE) {
6069                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6070                                       BDINFO_FLAGS_DISABLED);
6071                 }
6072         }
6073
6074         tp->rx_rcb_ptr = 0;
6075         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6076
6077         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6078                        tp->rx_rcb_mapping,
6079                        (TG3_RX_RCB_RING_SIZE(tp) <<
6080                         BDINFO_FLAGS_MAXLEN_SHIFT),
6081                        0);
6082
6083         tp->rx_std_ptr = tp->rx_pending;
6084         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6085                      tp->rx_std_ptr);
6086
6087         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6088                                                 tp->rx_jumbo_pending : 0;
6089         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6090                      tp->rx_jumbo_ptr);
6091
6092         /* Initialize MAC address and backoff seed. */
6093         __tg3_set_mac_addr(tp);
6094
6095         /* MTU + ethernet header + FCS + optional VLAN tag */
6096         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6097
6098         /* The slot time is changed by tg3_setup_phy if we
6099          * run at gigabit with half duplex.
6100          */
6101         tw32(MAC_TX_LENGTHS,
6102              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6103              (6 << TX_LENGTHS_IPG_SHIFT) |
6104              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6105
6106         /* Receive rules. */
6107         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6108         tw32(RCVLPC_CONFIG, 0x0181);
6109
6110         /* Calculate RDMAC_MODE setting early, we need it to determine
6111          * the RCVLPC_STATE_ENABLE mask.
6112          */
6113         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6114                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6115                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6116                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6117                       RDMAC_MODE_LNGREAD_ENAB);
6118         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6119                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6120
6121         /* If statement applies to 5705 and 5750 PCI devices only */
6122         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6123              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6124             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6125                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6126                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6127                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6128                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6129                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6130                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6131                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6132                 }
6133         }
6134
6135         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6136                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6137
6138 #if TG3_TSO_SUPPORT != 0
6139         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6140                 rdmac_mode |= (1 << 27);
6141 #endif
6142
6143         /* Receive/send statistics. */
6144         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6145             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6146                 val = tr32(RCVLPC_STATS_ENABLE);
6147                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6148                 tw32(RCVLPC_STATS_ENABLE, val);
6149         } else {
6150                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6151         }
6152         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6153         tw32(SNDDATAI_STATSENAB, 0xffffff);
6154         tw32(SNDDATAI_STATSCTRL,
6155              (SNDDATAI_SCTRL_ENABLE |
6156               SNDDATAI_SCTRL_FASTUPD));
6157
6158         /* Setup host coalescing engine. */
6159         tw32(HOSTCC_MODE, 0);
6160         for (i = 0; i < 2000; i++) {
6161                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6162                         break;
6163                 udelay(10);
6164         }
6165
6166         __tg3_set_coalesce(tp, &tp->coal);
6167
6168         /* set status block DMA address */
6169         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6170              ((u64) tp->status_mapping >> 32));
6171         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6172              ((u64) tp->status_mapping & 0xffffffff));
6173
6174         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6175                 /* Status/statistics block address.  See tg3_timer,
6176                  * the tg3_periodic_fetch_stats call there, and
6177                  * tg3_get_stats to see how this works for 5705/5750 chips.
6178                  */
6179                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6180                      ((u64) tp->stats_mapping >> 32));
6181                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6182                      ((u64) tp->stats_mapping & 0xffffffff));
6183                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6184                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6185         }
6186
6187         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6188
6189         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6190         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6191         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6192                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6193
6194         /* Clear statistics/status block in chip, and status block in ram. */
6195         for (i = NIC_SRAM_STATS_BLK;
6196              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6197              i += sizeof(u32)) {
6198                 tg3_write_mem(tp, i, 0);
6199                 udelay(40);
6200         }
6201         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6202
6203         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6204                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6205                 /* reset to prevent losing 1st rx packet intermittently */
6206                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6207                 udelay(10);
6208         }
6209
6210         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6211                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6212         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6213         udelay(40);
6214
6215         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6216          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6217          * register to preserve the GPIO settings for LOMs. The GPIOs,
6218          * whether used as inputs or outputs, are set by boot code after
6219          * reset.
6220          */
6221         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6222                 u32 gpio_mask;
6223
6224                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6225                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6226
6227                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6228                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6229                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6230
6231                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6232                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6233
6234                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6235
6236                 /* GPIO1 must be driven high for eeprom write protect */
6237                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6238                                        GRC_LCLCTRL_GPIO_OUTPUT1);
6239         }
6240         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6241         udelay(100);
6242
6243         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6244         tp->last_tag = 0;
6245
6246         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6247                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6248                 udelay(40);
6249         }
6250
6251         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6252                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6253                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6254                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6255                WDMAC_MODE_LNGREAD_ENAB);
6256
6257         /* If statement applies to 5705 and 5750 PCI devices only */
6258         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6259              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6260             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6261                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6262                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6263                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6264                         /* nothing */
6265                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6266                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6267                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6268                         val |= WDMAC_MODE_RX_ACCEL;
6269                 }
6270         }
6271
6272         /* Enable host coalescing bug fix */
6273         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6274             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6275                 val |= (1 << 29);
6276
6277         tw32_f(WDMAC_MODE, val);
6278         udelay(40);
6279
6280         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6281                 val = tr32(TG3PCI_X_CAPS);
6282                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6283                         val &= ~PCIX_CAPS_BURST_MASK;
6284                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6285                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6286                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6287                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6288                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6289                                 val |= (tp->split_mode_max_reqs <<
6290                                         PCIX_CAPS_SPLIT_SHIFT);
6291                 }
6292                 tw32(TG3PCI_X_CAPS, val);
6293         }
6294
6295         tw32_f(RDMAC_MODE, rdmac_mode);
6296         udelay(40);
6297
6298         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6299         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6300                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6301         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6302         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6303         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6304         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6305         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6306 #if TG3_TSO_SUPPORT != 0
6307         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6308                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6309 #endif
6310         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6311         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6312
6313         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6314                 err = tg3_load_5701_a0_firmware_fix(tp);
6315                 if (err)
6316                         return err;
6317         }
6318
6319 #if TG3_TSO_SUPPORT != 0
6320         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6321                 err = tg3_load_tso_firmware(tp);
6322                 if (err)
6323                         return err;
6324         }
6325 #endif
6326
6327         tp->tx_mode = TX_MODE_ENABLE;
6328         tw32_f(MAC_TX_MODE, tp->tx_mode);
6329         udelay(100);
6330
6331         tp->rx_mode = RX_MODE_ENABLE;
6332         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6333                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6334
6335         tw32_f(MAC_RX_MODE, tp->rx_mode);
6336         udelay(10);
6337
6338         if (tp->link_config.phy_is_low_power) {
6339                 tp->link_config.phy_is_low_power = 0;
6340                 tp->link_config.speed = tp->link_config.orig_speed;
6341                 tp->link_config.duplex = tp->link_config.orig_duplex;
6342                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6343         }
6344
6345         tp->mi_mode = MAC_MI_MODE_BASE;
6346         tw32_f(MAC_MI_MODE, tp->mi_mode);
6347         udelay(80);
6348
6349         tw32(MAC_LED_CTRL, tp->led_ctrl);
6350
6351         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6352         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6353                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6354                 udelay(10);
6355         }
6356         tw32_f(MAC_RX_MODE, tp->rx_mode);
6357         udelay(10);
6358
6359         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6360                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6361                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6362                         /* Set drive transmission level to 1.2V  */
6363                         /* only if the signal pre-emphasis bit is not set  */
6364                         val = tr32(MAC_SERDES_CFG);
6365                         val &= 0xfffff000;
6366                         val |= 0x880;
6367                         tw32(MAC_SERDES_CFG, val);
6368                 }
6369                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6370                         tw32(MAC_SERDES_CFG, 0x616000);
6371         }
6372
6373         /* Prevent chip from dropping frames when flow control
6374          * is enabled.
6375          */
6376         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6377
6378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6379             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6380                 /* Use hardware link auto-negotiation */
6381                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6382         }
6383
6384         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6385             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6386                 u32 tmp;
6387
6388                 tmp = tr32(SERDES_RX_CTRL);
6389                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6390                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6391                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6392                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6393         }
6394
6395         err = tg3_setup_phy(tp, reset_phy);
6396         if (err)
6397                 return err;
6398
6399         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6400                 u32 tmp;
6401
6402                 /* Clear CRC stats. */
6403                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6404                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6405                         tg3_readphy(tp, 0x14, &tmp);
6406                 }
6407         }
6408
6409         __tg3_set_rx_mode(tp->dev);
6410
6411         /* Initialize receive rules. */
6412         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6413         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6414         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6415         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6416
6417         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6418             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6419                 limit = 8;
6420         else
6421                 limit = 16;
6422         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6423                 limit -= 4;
6424         switch (limit) {
6425         case 16:
6426                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6427         case 15:
6428                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6429         case 14:
6430                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6431         case 13:
6432                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6433         case 12:
6434                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6435         case 11:
6436                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6437         case 10:
6438                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6439         case 9:
6440                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6441         case 8:
6442                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6443         case 7:
6444                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6445         case 6:
6446                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6447         case 5:
6448                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6449         case 4:
6450                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6451         case 3:
6452                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6453         case 2:
6454         case 1:
6455
6456         default:
6457                 break;
6458         };
6459
6460         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6461
6462         return 0;
6463 }
6464
6465 /* Called at device open time to get the chip ready for
6466  * packet processing.  Invoked with tp->lock held.
6467  */
6468 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6469 {
6470         int err;
6471
6472         /* Force the chip into D0. */
6473         err = tg3_set_power_state(tp, PCI_D0);
6474         if (err)
6475                 goto out;
6476
6477         tg3_switch_clocks(tp);
6478
6479         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6480
6481         err = tg3_reset_hw(tp, reset_phy);
6482
6483 out:
6484         return err;
6485 }
6486
6487 #define TG3_STAT_ADD32(PSTAT, REG) \
6488 do {    u32 __val = tr32(REG); \
6489         (PSTAT)->low += __val; \
6490         if ((PSTAT)->low < __val) \
6491                 (PSTAT)->high += 1; \
6492 } while (0)
6493
6494 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6495 {
6496         struct tg3_hw_stats *sp = tp->hw_stats;
6497
6498         if (!netif_carrier_ok(tp->dev))
6499                 return;
6500
6501         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6502         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6503         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6504         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6505         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6506         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6507         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6508         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6509         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6510         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6511         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6512         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6513         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6514
6515         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6516         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6517         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6518         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6519         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6520         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6521         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6522         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6523         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6524         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6525         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6526         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6527         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6528         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6529
6530         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6531         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6532         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6533 }
6534
6535 static void tg3_timer(unsigned long __opaque)
6536 {
6537         struct tg3 *tp = (struct tg3 *) __opaque;
6538
6539         if (tp->irq_sync)
6540                 goto restart_timer;
6541
6542         spin_lock(&tp->lock);
6543
6544         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6545                 /* All of this garbage is because when using non-tagged
6546                  * IRQ status the mailbox/status_block protocol the chip
6547                  * uses with the cpu is race prone.
6548                  */
6549                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6550                         tw32(GRC_LOCAL_CTRL,
6551                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6552                 } else {
6553                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6554                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6555                 }
6556
6557                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6558                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6559                         spin_unlock(&tp->lock);
6560                         schedule_work(&tp->reset_task);
6561                         return;
6562                 }
6563         }
6564
6565         /* This part only runs once per second. */
6566         if (!--tp->timer_counter) {
6567                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6568                         tg3_periodic_fetch_stats(tp);
6569
6570                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6571                         u32 mac_stat;
6572                         int phy_event;
6573
6574                         mac_stat = tr32(MAC_STATUS);
6575
6576                         phy_event = 0;
6577                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6578                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6579                                         phy_event = 1;
6580                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6581                                 phy_event = 1;
6582
6583                         if (phy_event)
6584                                 tg3_setup_phy(tp, 0);
6585                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6586                         u32 mac_stat = tr32(MAC_STATUS);
6587                         int need_setup = 0;
6588
6589                         if (netif_carrier_ok(tp->dev) &&
6590                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6591                                 need_setup = 1;
6592                         }
6593                         if (! netif_carrier_ok(tp->dev) &&
6594                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6595                                          MAC_STATUS_SIGNAL_DET))) {
6596                                 need_setup = 1;
6597                         }
6598                         if (need_setup) {
6599                                 tw32_f(MAC_MODE,
6600                                      (tp->mac_mode &
6601                                       ~MAC_MODE_PORT_MODE_MASK));
6602                                 udelay(40);
6603                                 tw32_f(MAC_MODE, tp->mac_mode);
6604                                 udelay(40);
6605                                 tg3_setup_phy(tp, 0);
6606                         }
6607                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6608                         tg3_serdes_parallel_detect(tp);
6609
6610                 tp->timer_counter = tp->timer_multiplier;
6611         }
6612
6613         /* Heartbeat is only sent once every 2 seconds.  */
6614         if (!--tp->asf_counter) {
6615                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6616                         u32 val;
6617
6618                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6619                                       FWCMD_NICDRV_ALIVE2);
6620                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6621                         /* 5 seconds timeout */
6622                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6623                         val = tr32(GRC_RX_CPU_EVENT);
6624                         val |= (1 << 14);
6625                         tw32(GRC_RX_CPU_EVENT, val);
6626                 }
6627                 tp->asf_counter = tp->asf_multiplier;
6628         }
6629
6630         spin_unlock(&tp->lock);
6631
6632 restart_timer:
6633         tp->timer.expires = jiffies + tp->timer_offset;
6634         add_timer(&tp->timer);
6635 }
6636
6637 static int tg3_request_irq(struct tg3 *tp)
6638 {
6639         irqreturn_t (*fn)(int, void *, struct pt_regs *);
6640         unsigned long flags;
6641         struct net_device *dev = tp->dev;
6642
6643         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6644                 fn = tg3_msi;
6645                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6646                         fn = tg3_msi_1shot;
6647                 flags = SA_SAMPLE_RANDOM;
6648         } else {
6649                 fn = tg3_interrupt;
6650                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6651                         fn = tg3_interrupt_tagged;
6652                 flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
6653         }
6654         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6655 }
6656
6657 static int tg3_test_interrupt(struct tg3 *tp)
6658 {
6659         struct net_device *dev = tp->dev;
6660         int err, i;
6661         u32 int_mbox = 0;
6662
6663         if (!netif_running(dev))
6664                 return -ENODEV;
6665
6666         tg3_disable_ints(tp);
6667
6668         free_irq(tp->pdev->irq, dev);
6669
6670         err = request_irq(tp->pdev->irq, tg3_test_isr,
6671                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6672         if (err)
6673                 return err;
6674
6675         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6676         tg3_enable_ints(tp);
6677
6678         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6679                HOSTCC_MODE_NOW);
6680
6681         for (i = 0; i < 5; i++) {
6682                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6683                                         TG3_64BIT_REG_LOW);
6684                 if (int_mbox != 0)
6685                         break;
6686                 msleep(10);
6687         }
6688
6689         tg3_disable_ints(tp);
6690
6691         free_irq(tp->pdev->irq, dev);
6692
6693         err = tg3_request_irq(tp);
6694
6695         if (err)
6696                 return err;
6697
6698         if (int_mbox != 0)
6699                 return 0;
6700
6701         return -EIO;
6702 }
6703
6704 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6705  * successfully restored
6706  */
6707 static int tg3_test_msi(struct tg3 *tp)
6708 {
6709         struct net_device *dev = tp->dev;
6710         int err;
6711         u16 pci_cmd;
6712
6713         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6714                 return 0;
6715
6716         /* Turn off SERR reporting in case MSI terminates with Master
6717          * Abort.
6718          */
6719         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6720         pci_write_config_word(tp->pdev, PCI_COMMAND,
6721                               pci_cmd & ~PCI_COMMAND_SERR);
6722
6723         err = tg3_test_interrupt(tp);
6724
6725         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6726
6727         if (!err)
6728                 return 0;
6729
6730         /* other failures */
6731         if (err != -EIO)
6732                 return err;
6733
6734         /* MSI test failed, go back to INTx mode */
6735         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6736                "switching to INTx mode. Please report this failure to "
6737                "the PCI maintainer and include system chipset information.\n",
6738                        tp->dev->name);
6739
6740         free_irq(tp->pdev->irq, dev);
6741         pci_disable_msi(tp->pdev);
6742
6743         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6744
6745         err = tg3_request_irq(tp);
6746         if (err)
6747                 return err;
6748
6749         /* Need to reset the chip because the MSI cycle may have terminated
6750          * with Master Abort.
6751          */
6752         tg3_full_lock(tp, 1);
6753
6754         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6755         err = tg3_init_hw(tp, 1);
6756
6757         tg3_full_unlock(tp);
6758
6759         if (err)
6760                 free_irq(tp->pdev->irq, dev);
6761
6762         return err;
6763 }
6764
6765 static int tg3_open(struct net_device *dev)
6766 {
6767         struct tg3 *tp = netdev_priv(dev);
6768         int err;
6769
6770         tg3_full_lock(tp, 0);
6771
6772         err = tg3_set_power_state(tp, PCI_D0);
6773         if (err)
6774                 return err;
6775
6776         tg3_disable_ints(tp);
6777         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6778
6779         tg3_full_unlock(tp);
6780
6781         /* The placement of this call is tied
6782          * to the setup and use of Host TX descriptors.
6783          */
6784         err = tg3_alloc_consistent(tp);
6785         if (err)
6786                 return err;
6787
6788         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6789             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6790             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6791             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
6792               (tp->pdev_peer == tp->pdev))) {
6793                 /* All MSI supporting chips should support tagged
6794                  * status.  Assert that this is the case.
6795                  */
6796                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6797                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6798                                "Not using MSI.\n", tp->dev->name);
6799                 } else if (pci_enable_msi(tp->pdev) == 0) {
6800                         u32 msi_mode;
6801
6802                         msi_mode = tr32(MSGINT_MODE);
6803                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6804                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6805                 }
6806         }
6807         err = tg3_request_irq(tp);
6808
6809         if (err) {
6810                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6811                         pci_disable_msi(tp->pdev);
6812                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6813                 }
6814                 tg3_free_consistent(tp);
6815                 return err;
6816         }
6817
6818         tg3_full_lock(tp, 0);
6819
6820         err = tg3_init_hw(tp, 1);
6821         if (err) {
6822                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6823                 tg3_free_rings(tp);
6824         } else {
6825                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6826                         tp->timer_offset = HZ;
6827                 else
6828                         tp->timer_offset = HZ / 10;
6829
6830                 BUG_ON(tp->timer_offset > HZ);
6831                 tp->timer_counter = tp->timer_multiplier =
6832                         (HZ / tp->timer_offset);
6833                 tp->asf_counter = tp->asf_multiplier =
6834                         ((HZ / tp->timer_offset) * 2);
6835
6836                 init_timer(&tp->timer);
6837                 tp->timer.expires = jiffies + tp->timer_offset;
6838                 tp->timer.data = (unsigned long) tp;
6839                 tp->timer.function = tg3_timer;
6840         }
6841
6842         tg3_full_unlock(tp);
6843
6844         if (err) {
6845                 free_irq(tp->pdev->irq, dev);
6846                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6847                         pci_disable_msi(tp->pdev);
6848                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6849                 }
6850                 tg3_free_consistent(tp);
6851                 return err;
6852         }
6853
6854         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6855                 err = tg3_test_msi(tp);
6856
6857                 if (err) {
6858                         tg3_full_lock(tp, 0);
6859
6860                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6861                                 pci_disable_msi(tp->pdev);
6862                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6863                         }
6864                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6865                         tg3_free_rings(tp);
6866                         tg3_free_consistent(tp);
6867
6868                         tg3_full_unlock(tp);
6869
6870                         return err;
6871                 }
6872
6873                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6874                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
6875                                 u32 val = tr32(0x7c04);
6876
6877                                 tw32(0x7c04, val | (1 << 29));
6878                         }
6879                 }
6880         }
6881
6882         tg3_full_lock(tp, 0);
6883
6884         add_timer(&tp->timer);
6885         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6886         tg3_enable_ints(tp);
6887
6888         tg3_full_unlock(tp);
6889
6890         netif_start_queue(dev);
6891
6892         return 0;
6893 }
6894
6895 #if 0
6896 /*static*/ void tg3_dump_state(struct tg3 *tp)
6897 {
6898         u32 val32, val32_2, val32_3, val32_4, val32_5;
6899         u16 val16;
6900         int i;
6901
6902         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6903         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6904         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6905                val16, val32);
6906
6907         /* MAC block */
6908         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6909                tr32(MAC_MODE), tr32(MAC_STATUS));
6910         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6911                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6912         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6913                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6914         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6915                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6916
6917         /* Send data initiator control block */
6918         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6919                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6920         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6921                tr32(SNDDATAI_STATSCTRL));
6922
6923         /* Send data completion control block */
6924         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6925
6926         /* Send BD ring selector block */
6927         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6928                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6929
6930         /* Send BD initiator control block */
6931         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6932                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6933
6934         /* Send BD completion control block */
6935         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6936
6937         /* Receive list placement control block */
6938         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6939                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6940         printk("       RCVLPC_STATSCTRL[%08x]\n",
6941                tr32(RCVLPC_STATSCTRL));
6942
6943         /* Receive data and receive BD initiator control block */
6944         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6945                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6946
6947         /* Receive data completion control block */
6948         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6949                tr32(RCVDCC_MODE));
6950
6951         /* Receive BD initiator control block */
6952         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6953                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6954
6955         /* Receive BD completion control block */
6956         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6957                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6958
6959         /* Receive list selector control block */
6960         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6961                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6962
6963         /* Mbuf cluster free block */
6964         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6965                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6966
6967         /* Host coalescing control block */
6968         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6969                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6970         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6971                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6972                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6973         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6974                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6975                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6976         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6977                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6978         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6979                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6980
6981         /* Memory arbiter control block */
6982         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6983                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6984
6985         /* Buffer manager control block */
6986         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6987                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6988         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6989                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6990         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6991                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6992                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6993                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6994
6995         /* Read DMA control block */
6996         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6997                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6998
6999         /* Write DMA control block */
7000         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7001                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7002
7003         /* DMA completion block */
7004         printk("DEBUG: DMAC_MODE[%08x]\n",
7005                tr32(DMAC_MODE));
7006
7007         /* GRC block */
7008         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7009                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7010         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7011                tr32(GRC_LOCAL_CTRL));
7012
7013         /* TG3_BDINFOs */
7014         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7015                tr32(RCVDBDI_JUMBO_BD + 0x0),
7016                tr32(RCVDBDI_JUMBO_BD + 0x4),
7017                tr32(RCVDBDI_JUMBO_BD + 0x8),
7018                tr32(RCVDBDI_JUMBO_BD + 0xc));
7019         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7020                tr32(RCVDBDI_STD_BD + 0x0),
7021                tr32(RCVDBDI_STD_BD + 0x4),
7022                tr32(RCVDBDI_STD_BD + 0x8),
7023                tr32(RCVDBDI_STD_BD + 0xc));
7024         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7025                tr32(RCVDBDI_MINI_BD + 0x0),
7026                tr32(RCVDBDI_MINI_BD + 0x4),
7027                tr32(RCVDBDI_MINI_BD + 0x8),
7028                tr32(RCVDBDI_MINI_BD + 0xc));
7029
7030         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7031         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7032         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7033         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7034         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7035                val32, val32_2, val32_3, val32_4);
7036
7037         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7038         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7039         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7040         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7041         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7042                val32, val32_2, val32_3, val32_4);
7043
7044         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7045         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7046         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7047         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7048         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7049         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7050                val32, val32_2, val32_3, val32_4, val32_5);
7051
7052         /* SW status block */
7053         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7054                tp->hw_status->status,
7055                tp->hw_status->status_tag,
7056                tp->hw_status->rx_jumbo_consumer,
7057                tp->hw_status->rx_consumer,
7058                tp->hw_status->rx_mini_consumer,
7059                tp->hw_status->idx[0].rx_producer,
7060                tp->hw_status->idx[0].tx_consumer);
7061
7062         /* SW statistics block */
7063         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7064                ((u32 *)tp->hw_stats)[0],
7065                ((u32 *)tp->hw_stats)[1],
7066                ((u32 *)tp->hw_stats)[2],
7067                ((u32 *)tp->hw_stats)[3]);
7068
7069         /* Mailboxes */
7070         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7071                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7072                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7073                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7074                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7075
7076         /* NIC side send descriptors. */
7077         for (i = 0; i < 6; i++) {
7078                 unsigned long txd;
7079
7080                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7081                         + (i * sizeof(struct tg3_tx_buffer_desc));
7082                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7083                        i,
7084                        readl(txd + 0x0), readl(txd + 0x4),
7085                        readl(txd + 0x8), readl(txd + 0xc));
7086         }
7087
7088         /* NIC side RX descriptors. */
7089         for (i = 0; i < 6; i++) {
7090                 unsigned long rxd;
7091
7092                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7093                         + (i * sizeof(struct tg3_rx_buffer_desc));
7094                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7095                        i,
7096                        readl(rxd + 0x0), readl(rxd + 0x4),
7097                        readl(rxd + 0x8), readl(rxd + 0xc));
7098                 rxd += (4 * sizeof(u32));
7099                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7100                        i,
7101                        readl(rxd + 0x0), readl(rxd + 0x4),
7102                        readl(rxd + 0x8), readl(rxd + 0xc));
7103         }
7104
7105         for (i = 0; i < 6; i++) {
7106                 unsigned long rxd;
7107
7108                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7109                         + (i * sizeof(struct tg3_rx_buffer_desc));
7110                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7111                        i,
7112                        readl(rxd + 0x0), readl(rxd + 0x4),
7113                        readl(rxd + 0x8), readl(rxd + 0xc));
7114                 rxd += (4 * sizeof(u32));
7115                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7116                        i,
7117                        readl(rxd + 0x0), readl(rxd + 0x4),
7118                        readl(rxd + 0x8), readl(rxd + 0xc));
7119         }
7120 }
7121 #endif
7122
7123 static struct net_device_stats *tg3_get_stats(struct net_device *);
7124 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7125
7126 static int tg3_close(struct net_device *dev)
7127 {
7128         struct tg3 *tp = netdev_priv(dev);
7129
7130         /* Calling flush_scheduled_work() may deadlock because
7131          * linkwatch_event() may be on the workqueue and it will try to get
7132          * the rtnl_lock which we are holding.
7133          */
7134         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7135                 msleep(1);
7136
7137         netif_stop_queue(dev);
7138
7139         del_timer_sync(&tp->timer);
7140
7141         tg3_full_lock(tp, 1);
7142 #if 0
7143         tg3_dump_state(tp);
7144 #endif
7145
7146         tg3_disable_ints(tp);
7147
7148         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7149         tg3_free_rings(tp);
7150         tp->tg3_flags &=
7151                 ~(TG3_FLAG_INIT_COMPLETE |
7152                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7153
7154         tg3_full_unlock(tp);
7155
7156         free_irq(tp->pdev->irq, dev);
7157         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7158                 pci_disable_msi(tp->pdev);
7159                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7160         }
7161
7162         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7163                sizeof(tp->net_stats_prev));
7164         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7165                sizeof(tp->estats_prev));
7166
7167         tg3_free_consistent(tp);
7168
7169         tg3_set_power_state(tp, PCI_D3hot);
7170
7171         netif_carrier_off(tp->dev);
7172
7173         return 0;
7174 }
7175
7176 static inline unsigned long get_stat64(tg3_stat64_t *val)
7177 {
7178         unsigned long ret;
7179
7180 #if (BITS_PER_LONG == 32)
7181         ret = val->low;
7182 #else
7183         ret = ((u64)val->high << 32) | ((u64)val->low);
7184 #endif
7185         return ret;
7186 }
7187
7188 static unsigned long calc_crc_errors(struct tg3 *tp)
7189 {
7190         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7191
7192         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7193             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7194              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7195                 u32 val;
7196
7197                 spin_lock_bh(&tp->lock);
7198                 if (!tg3_readphy(tp, 0x1e, &val)) {
7199                         tg3_writephy(tp, 0x1e, val | 0x8000);
7200                         tg3_readphy(tp, 0x14, &val);
7201                 } else
7202                         val = 0;
7203                 spin_unlock_bh(&tp->lock);
7204
7205                 tp->phy_crc_errors += val;
7206
7207                 return tp->phy_crc_errors;
7208         }
7209
7210         return get_stat64(&hw_stats->rx_fcs_errors);
7211 }
7212
7213 #define ESTAT_ADD(member) \
7214         estats->member =        old_estats->member + \
7215                                 get_stat64(&hw_stats->member)
7216
7217 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7218 {
7219         struct tg3_ethtool_stats *estats = &tp->estats;
7220         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7221         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7222
7223         if (!hw_stats)
7224                 return old_estats;
7225
7226         ESTAT_ADD(rx_octets);
7227         ESTAT_ADD(rx_fragments);
7228         ESTAT_ADD(rx_ucast_packets);
7229         ESTAT_ADD(rx_mcast_packets);
7230         ESTAT_ADD(rx_bcast_packets);
7231         ESTAT_ADD(rx_fcs_errors);
7232         ESTAT_ADD(rx_align_errors);
7233         ESTAT_ADD(rx_xon_pause_rcvd);
7234         ESTAT_ADD(rx_xoff_pause_rcvd);
7235         ESTAT_ADD(rx_mac_ctrl_rcvd);
7236         ESTAT_ADD(rx_xoff_entered);
7237         ESTAT_ADD(rx_frame_too_long_errors);
7238         ESTAT_ADD(rx_jabbers);
7239         ESTAT_ADD(rx_undersize_packets);
7240         ESTAT_ADD(rx_in_length_errors);
7241         ESTAT_ADD(rx_out_length_errors);
7242         ESTAT_ADD(rx_64_or_less_octet_packets);
7243         ESTAT_ADD(rx_65_to_127_octet_packets);
7244         ESTAT_ADD(rx_128_to_255_octet_packets);
7245         ESTAT_ADD(rx_256_to_511_octet_packets);
7246         ESTAT_ADD(rx_512_to_1023_octet_packets);
7247         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7248         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7249         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7250         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7251         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7252
7253         ESTAT_ADD(tx_octets);
7254         ESTAT_ADD(tx_collisions);
7255         ESTAT_ADD(tx_xon_sent);
7256         ESTAT_ADD(tx_xoff_sent);
7257         ESTAT_ADD(tx_flow_control);
7258         ESTAT_ADD(tx_mac_errors);
7259         ESTAT_ADD(tx_single_collisions);
7260         ESTAT_ADD(tx_mult_collisions);
7261         ESTAT_ADD(tx_deferred);
7262         ESTAT_ADD(tx_excessive_collisions);
7263         ESTAT_ADD(tx_late_collisions);
7264         ESTAT_ADD(tx_collide_2times);
7265         ESTAT_ADD(tx_collide_3times);
7266         ESTAT_ADD(tx_collide_4times);
7267         ESTAT_ADD(tx_collide_5times);
7268         ESTAT_ADD(tx_collide_6times);
7269         ESTAT_ADD(tx_collide_7times);
7270         ESTAT_ADD(tx_collide_8times);
7271         ESTAT_ADD(tx_collide_9times);
7272         ESTAT_ADD(tx_collide_10times);
7273         ESTAT_ADD(tx_collide_11times);
7274         ESTAT_ADD(tx_collide_12times);
7275         ESTAT_ADD(tx_collide_13times);
7276         ESTAT_ADD(tx_collide_14times);
7277         ESTAT_ADD(tx_collide_15times);
7278         ESTAT_ADD(tx_ucast_packets);
7279         ESTAT_ADD(tx_mcast_packets);
7280         ESTAT_ADD(tx_bcast_packets);
7281         ESTAT_ADD(tx_carrier_sense_errors);
7282         ESTAT_ADD(tx_discards);
7283         ESTAT_ADD(tx_errors);
7284
7285         ESTAT_ADD(dma_writeq_full);
7286         ESTAT_ADD(dma_write_prioq_full);
7287         ESTAT_ADD(rxbds_empty);
7288         ESTAT_ADD(rx_discards);
7289         ESTAT_ADD(rx_errors);
7290         ESTAT_ADD(rx_threshold_hit);
7291
7292         ESTAT_ADD(dma_readq_full);
7293         ESTAT_ADD(dma_read_prioq_full);
7294         ESTAT_ADD(tx_comp_queue_full);
7295
7296         ESTAT_ADD(ring_set_send_prod_index);
7297         ESTAT_ADD(ring_status_update);
7298         ESTAT_ADD(nic_irqs);
7299         ESTAT_ADD(nic_avoided_irqs);
7300         ESTAT_ADD(nic_tx_threshold_hit);
7301
7302         return estats;
7303 }
7304
7305 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7306 {
7307         struct tg3 *tp = netdev_priv(dev);
7308         struct net_device_stats *stats = &tp->net_stats;
7309         struct net_device_stats *old_stats = &tp->net_stats_prev;
7310         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7311
7312         if (!hw_stats)
7313                 return old_stats;
7314
7315         stats->rx_packets = old_stats->rx_packets +
7316                 get_stat64(&hw_stats->rx_ucast_packets) +
7317                 get_stat64(&hw_stats->rx_mcast_packets) +
7318                 get_stat64(&hw_stats->rx_bcast_packets);
7319
7320         stats->tx_packets = old_stats->tx_packets +
7321                 get_stat64(&hw_stats->tx_ucast_packets) +
7322                 get_stat64(&hw_stats->tx_mcast_packets) +
7323                 get_stat64(&hw_stats->tx_bcast_packets);
7324
7325         stats->rx_bytes = old_stats->rx_bytes +
7326                 get_stat64(&hw_stats->rx_octets);
7327         stats->tx_bytes = old_stats->tx_bytes +
7328                 get_stat64(&hw_stats->tx_octets);
7329
7330         stats->rx_errors = old_stats->rx_errors +
7331                 get_stat64(&hw_stats->rx_errors);
7332         stats->tx_errors = old_stats->tx_errors +
7333                 get_stat64(&hw_stats->tx_errors) +
7334                 get_stat64(&hw_stats->tx_mac_errors) +
7335                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7336                 get_stat64(&hw_stats->tx_discards);
7337
7338         stats->multicast = old_stats->multicast +
7339                 get_stat64(&hw_stats->rx_mcast_packets);
7340         stats->collisions = old_stats->collisions +
7341                 get_stat64(&hw_stats->tx_collisions);
7342
7343         stats->rx_length_errors = old_stats->rx_length_errors +
7344                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7345                 get_stat64(&hw_stats->rx_undersize_packets);
7346
7347         stats->rx_over_errors = old_stats->rx_over_errors +
7348                 get_stat64(&hw_stats->rxbds_empty);
7349         stats->rx_frame_errors = old_stats->rx_frame_errors +
7350                 get_stat64(&hw_stats->rx_align_errors);
7351         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7352                 get_stat64(&hw_stats->tx_discards);
7353         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7354                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7355
7356         stats->rx_crc_errors = old_stats->rx_crc_errors +
7357                 calc_crc_errors(tp);
7358
7359         stats->rx_missed_errors = old_stats->rx_missed_errors +
7360                 get_stat64(&hw_stats->rx_discards);
7361
7362         return stats;
7363 }
7364
7365 static inline u32 calc_crc(unsigned char *buf, int len)
7366 {
7367         u32 reg;
7368         u32 tmp;
7369         int j, k;
7370
7371         reg = 0xffffffff;
7372
7373         for (j = 0; j < len; j++) {
7374                 reg ^= buf[j];
7375
7376                 for (k = 0; k < 8; k++) {
7377                         tmp = reg & 0x01;
7378
7379                         reg >>= 1;
7380
7381                         if (tmp) {
7382                                 reg ^= 0xedb88320;
7383                         }
7384                 }
7385         }
7386
7387         return ~reg;
7388 }
7389
7390 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7391 {
7392         /* accept or reject all multicast frames */
7393         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7394         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7395         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7396         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7397 }
7398
7399 static void __tg3_set_rx_mode(struct net_device *dev)
7400 {
7401         struct tg3 *tp = netdev_priv(dev);
7402         u32 rx_mode;
7403
7404         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7405                                   RX_MODE_KEEP_VLAN_TAG);
7406
7407         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7408          * flag clear.
7409          */
7410 #if TG3_VLAN_TAG_USED
7411         if (!tp->vlgrp &&
7412             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7413                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7414 #else
7415         /* By definition, VLAN is disabled always in this
7416          * case.
7417          */
7418         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7419                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7420 #endif
7421
7422         if (dev->flags & IFF_PROMISC) {
7423                 /* Promiscuous mode. */
7424                 rx_mode |= RX_MODE_PROMISC;
7425         } else if (dev->flags & IFF_ALLMULTI) {
7426                 /* Accept all multicast. */
7427                 tg3_set_multi (tp, 1);
7428         } else if (dev->mc_count < 1) {
7429                 /* Reject all multicast. */
7430                 tg3_set_multi (tp, 0);
7431         } else {
7432                 /* Accept one or more multicast(s). */
7433                 struct dev_mc_list *mclist;
7434                 unsigned int i;
7435                 u32 mc_filter[4] = { 0, };
7436                 u32 regidx;
7437                 u32 bit;
7438                 u32 crc;
7439
7440                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7441                      i++, mclist = mclist->next) {
7442
7443                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7444                         bit = ~crc & 0x7f;
7445                         regidx = (bit & 0x60) >> 5;
7446                         bit &= 0x1f;
7447                         mc_filter[regidx] |= (1 << bit);
7448                 }
7449
7450                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7451                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7452                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7453                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7454         }
7455
7456         if (rx_mode != tp->rx_mode) {
7457                 tp->rx_mode = rx_mode;
7458                 tw32_f(MAC_RX_MODE, rx_mode);
7459                 udelay(10);
7460         }
7461 }
7462
7463 static void tg3_set_rx_mode(struct net_device *dev)
7464 {
7465         struct tg3 *tp = netdev_priv(dev);
7466
7467         if (!netif_running(dev))
7468                 return;
7469
7470         tg3_full_lock(tp, 0);
7471         __tg3_set_rx_mode(dev);
7472         tg3_full_unlock(tp);
7473 }
7474
7475 #define TG3_REGDUMP_LEN         (32 * 1024)
7476
7477 static int tg3_get_regs_len(struct net_device *dev)
7478 {
7479         return TG3_REGDUMP_LEN;
7480 }
7481
7482 static void tg3_get_regs(struct net_device *dev,
7483                 struct ethtool_regs *regs, void *_p)
7484 {
7485         u32 *p = _p;
7486         struct tg3 *tp = netdev_priv(dev);
7487         u8 *orig_p = _p;
7488         int i;
7489
7490         regs->version = 0;
7491
7492         memset(p, 0, TG3_REGDUMP_LEN);
7493
7494         if (tp->link_config.phy_is_low_power)
7495                 return;
7496
7497         tg3_full_lock(tp, 0);
7498
7499 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7500 #define GET_REG32_LOOP(base,len)                \
7501 do {    p = (u32 *)(orig_p + (base));           \
7502         for (i = 0; i < len; i += 4)            \
7503                 __GET_REG32((base) + i);        \
7504 } while (0)
7505 #define GET_REG32_1(reg)                        \
7506 do {    p = (u32 *)(orig_p + (reg));            \
7507         __GET_REG32((reg));                     \
7508 } while (0)
7509
7510         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7511         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7512         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7513         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7514         GET_REG32_1(SNDDATAC_MODE);
7515         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7516         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7517         GET_REG32_1(SNDBDC_MODE);
7518         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7519         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7520         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7521         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7522         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7523         GET_REG32_1(RCVDCC_MODE);
7524         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7525         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7526         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7527         GET_REG32_1(MBFREE_MODE);
7528         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7529         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7530         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7531         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7532         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7533         GET_REG32_1(RX_CPU_MODE);
7534         GET_REG32_1(RX_CPU_STATE);
7535         GET_REG32_1(RX_CPU_PGMCTR);
7536         GET_REG32_1(RX_CPU_HWBKPT);
7537         GET_REG32_1(TX_CPU_MODE);
7538         GET_REG32_1(TX_CPU_STATE);
7539         GET_REG32_1(TX_CPU_PGMCTR);
7540         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7541         GET_REG32_LOOP(FTQ_RESET, 0x120);
7542         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7543         GET_REG32_1(DMAC_MODE);
7544         GET_REG32_LOOP(GRC_MODE, 0x4c);
7545         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7546                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7547
7548 #undef __GET_REG32
7549 #undef GET_REG32_LOOP
7550 #undef GET_REG32_1
7551
7552         tg3_full_unlock(tp);
7553 }
7554
7555 static int tg3_get_eeprom_len(struct net_device *dev)
7556 {
7557         struct tg3 *tp = netdev_priv(dev);
7558
7559         return tp->nvram_size;
7560 }
7561
7562 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7563 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7564
7565 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7566 {
7567         struct tg3 *tp = netdev_priv(dev);
7568         int ret;
7569         u8  *pd;
7570         u32 i, offset, len, val, b_offset, b_count;
7571
7572         if (tp->link_config.phy_is_low_power)
7573                 return -EAGAIN;
7574
7575         offset = eeprom->offset;
7576         len = eeprom->len;
7577         eeprom->len = 0;
7578
7579         eeprom->magic = TG3_EEPROM_MAGIC;
7580
7581         if (offset & 3) {
7582                 /* adjustments to start on required 4 byte boundary */
7583                 b_offset = offset & 3;
7584                 b_count = 4 - b_offset;
7585                 if (b_count > len) {
7586                         /* i.e. offset=1 len=2 */
7587                         b_count = len;
7588                 }
7589                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7590                 if (ret)
7591                         return ret;
7592                 val = cpu_to_le32(val);
7593                 memcpy(data, ((char*)&val) + b_offset, b_count);
7594                 len -= b_count;
7595                 offset += b_count;
7596                 eeprom->len += b_count;
7597         }
7598
7599         /* read bytes upto the last 4 byte boundary */
7600         pd = &data[eeprom->len];
7601         for (i = 0; i < (len - (len & 3)); i += 4) {
7602                 ret = tg3_nvram_read(tp, offset + i, &val);
7603                 if (ret) {
7604                         eeprom->len += i;
7605                         return ret;
7606                 }
7607                 val = cpu_to_le32(val);
7608                 memcpy(pd + i, &val, 4);
7609         }
7610         eeprom->len += i;
7611
7612         if (len & 3) {
7613                 /* read last bytes not ending on 4 byte boundary */
7614                 pd = &data[eeprom->len];
7615                 b_count = len & 3;
7616                 b_offset = offset + len - b_count;
7617                 ret = tg3_nvram_read(tp, b_offset, &val);
7618                 if (ret)
7619                         return ret;
7620                 val = cpu_to_le32(val);
7621                 memcpy(pd, ((char*)&val), b_count);
7622                 eeprom->len += b_count;
7623         }
7624         return 0;
7625 }
7626
7627 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7628
7629 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7630 {
7631         struct tg3 *tp = netdev_priv(dev);
7632         int ret;
7633         u32 offset, len, b_offset, odd_len, start, end;
7634         u8 *buf;
7635
7636         if (tp->link_config.phy_is_low_power)
7637                 return -EAGAIN;
7638
7639         if (eeprom->magic != TG3_EEPROM_MAGIC)
7640                 return -EINVAL;
7641
7642         offset = eeprom->offset;
7643         len = eeprom->len;
7644
7645         if ((b_offset = (offset & 3))) {
7646                 /* adjustments to start on required 4 byte boundary */
7647                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7648                 if (ret)
7649                         return ret;
7650                 start = cpu_to_le32(start);
7651                 len += b_offset;
7652                 offset &= ~3;
7653                 if (len < 4)
7654                         len = 4;
7655         }
7656
7657         odd_len = 0;
7658         if (len & 3) {
7659                 /* adjustments to end on required 4 byte boundary */
7660                 odd_len = 1;
7661                 len = (len + 3) & ~3;
7662                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7663                 if (ret)
7664                         return ret;
7665                 end = cpu_to_le32(end);
7666         }
7667
7668         buf = data;
7669         if (b_offset || odd_len) {
7670                 buf = kmalloc(len, GFP_KERNEL);
7671                 if (buf == 0)
7672                         return -ENOMEM;
7673                 if (b_offset)
7674                         memcpy(buf, &start, 4);
7675                 if (odd_len)
7676                         memcpy(buf+len-4, &end, 4);
7677                 memcpy(buf + b_offset, data, eeprom->len);
7678         }
7679
7680         ret = tg3_nvram_write_block(tp, offset, len, buf);
7681
7682         if (buf != data)
7683                 kfree(buf);
7684
7685         return ret;
7686 }
7687
7688 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7689 {
7690         struct tg3 *tp = netdev_priv(dev);
7691
7692         cmd->supported = (SUPPORTED_Autoneg);
7693
7694         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7695                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7696                                    SUPPORTED_1000baseT_Full);
7697
7698         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7699                 cmd->supported |= (SUPPORTED_100baseT_Half |
7700                                   SUPPORTED_100baseT_Full |
7701                                   SUPPORTED_10baseT_Half |
7702                                   SUPPORTED_10baseT_Full |
7703                                   SUPPORTED_MII);
7704                 cmd->port = PORT_TP;
7705         } else {
7706                 cmd->supported |= SUPPORTED_FIBRE;
7707                 cmd->port = PORT_FIBRE;
7708         }
7709
7710         cmd->advertising = tp->link_config.advertising;
7711         if (netif_running(dev)) {
7712                 cmd->speed = tp->link_config.active_speed;
7713                 cmd->duplex = tp->link_config.active_duplex;
7714         }
7715         cmd->phy_address = PHY_ADDR;
7716         cmd->transceiver = 0;
7717         cmd->autoneg = tp->link_config.autoneg;
7718         cmd->maxtxpkt = 0;
7719         cmd->maxrxpkt = 0;
7720         return 0;
7721 }
7722
7723 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7724 {
7725         struct tg3 *tp = netdev_priv(dev);
7726
7727         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7728                 /* These are the only valid advertisement bits allowed.  */
7729                 if (cmd->autoneg == AUTONEG_ENABLE &&
7730                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7731                                           ADVERTISED_1000baseT_Full |
7732                                           ADVERTISED_Autoneg |
7733                                           ADVERTISED_FIBRE)))
7734                         return -EINVAL;
7735                 /* Fiber can only do SPEED_1000.  */
7736                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7737                          (cmd->speed != SPEED_1000))
7738                         return -EINVAL;
7739         /* Copper cannot force SPEED_1000.  */
7740         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7741                    (cmd->speed == SPEED_1000))
7742                 return -EINVAL;
7743         else if ((cmd->speed == SPEED_1000) &&
7744                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7745                 return -EINVAL;
7746
7747         tg3_full_lock(tp, 0);
7748
7749         tp->link_config.autoneg = cmd->autoneg;
7750         if (cmd->autoneg == AUTONEG_ENABLE) {
7751                 tp->link_config.advertising = cmd->advertising;
7752                 tp->link_config.speed = SPEED_INVALID;
7753                 tp->link_config.duplex = DUPLEX_INVALID;
7754         } else {
7755                 tp->link_config.advertising = 0;
7756                 tp->link_config.speed = cmd->speed;
7757                 tp->link_config.duplex = cmd->duplex;
7758         }
7759
7760         if (netif_running(dev))
7761                 tg3_setup_phy(tp, 1);
7762
7763         tg3_full_unlock(tp);
7764
7765         return 0;
7766 }
7767
7768 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7769 {
7770         struct tg3 *tp = netdev_priv(dev);
7771
7772         strcpy(info->driver, DRV_MODULE_NAME);
7773         strcpy(info->version, DRV_MODULE_VERSION);
7774         strcpy(info->fw_version, tp->fw_ver);
7775         strcpy(info->bus_info, pci_name(tp->pdev));
7776 }
7777
7778 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7779 {
7780         struct tg3 *tp = netdev_priv(dev);
7781
7782         wol->supported = WAKE_MAGIC;
7783         wol->wolopts = 0;
7784         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7785                 wol->wolopts = WAKE_MAGIC;
7786         memset(&wol->sopass, 0, sizeof(wol->sopass));
7787 }
7788
7789 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7790 {
7791         struct tg3 *tp = netdev_priv(dev);
7792
7793         if (wol->wolopts & ~WAKE_MAGIC)
7794                 return -EINVAL;
7795         if ((wol->wolopts & WAKE_MAGIC) &&
7796             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7797             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7798                 return -EINVAL;
7799
7800         spin_lock_bh(&tp->lock);
7801         if (wol->wolopts & WAKE_MAGIC)
7802                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7803         else
7804                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7805         spin_unlock_bh(&tp->lock);
7806
7807         return 0;
7808 }
7809
7810 static u32 tg3_get_msglevel(struct net_device *dev)
7811 {
7812         struct tg3 *tp = netdev_priv(dev);
7813         return tp->msg_enable;
7814 }
7815
7816 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7817 {
7818         struct tg3 *tp = netdev_priv(dev);
7819         tp->msg_enable = value;
7820 }
7821
7822 #if TG3_TSO_SUPPORT != 0
7823 static int tg3_set_tso(struct net_device *dev, u32 value)
7824 {
7825         struct tg3 *tp = netdev_priv(dev);
7826
7827         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7828                 if (value)
7829                         return -EINVAL;
7830                 return 0;
7831         }
7832         return ethtool_op_set_tso(dev, value);
7833 }
7834 #endif
7835
7836 static int tg3_nway_reset(struct net_device *dev)
7837 {
7838         struct tg3 *tp = netdev_priv(dev);
7839         u32 bmcr;
7840         int r;
7841
7842         if (!netif_running(dev))
7843                 return -EAGAIN;
7844
7845         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7846                 return -EINVAL;
7847
7848         spin_lock_bh(&tp->lock);
7849         r = -EINVAL;
7850         tg3_readphy(tp, MII_BMCR, &bmcr);
7851         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7852             ((bmcr & BMCR_ANENABLE) ||
7853              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7854                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7855                                            BMCR_ANENABLE);
7856                 r = 0;
7857         }
7858         spin_unlock_bh(&tp->lock);
7859
7860         return r;
7861 }
7862
7863 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7864 {
7865         struct tg3 *tp = netdev_priv(dev);
7866
7867         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7868         ering->rx_mini_max_pending = 0;
7869         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7870                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7871         else
7872                 ering->rx_jumbo_max_pending = 0;
7873
7874         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7875
7876         ering->rx_pending = tp->rx_pending;
7877         ering->rx_mini_pending = 0;
7878         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7879                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7880         else
7881                 ering->rx_jumbo_pending = 0;
7882
7883         ering->tx_pending = tp->tx_pending;
7884 }
7885
7886 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7887 {
7888         struct tg3 *tp = netdev_priv(dev);
7889         int irq_sync = 0;
7890
7891         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7892             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7893             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7894                 return -EINVAL;
7895
7896         if (netif_running(dev)) {
7897                 tg3_netif_stop(tp);
7898                 irq_sync = 1;
7899         }
7900
7901         tg3_full_lock(tp, irq_sync);
7902
7903         tp->rx_pending = ering->rx_pending;
7904
7905         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7906             tp->rx_pending > 63)
7907                 tp->rx_pending = 63;
7908         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7909         tp->tx_pending = ering->tx_pending;
7910
7911         if (netif_running(dev)) {
7912                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7913                 tg3_init_hw(tp, 1);
7914                 tg3_netif_start(tp);
7915         }
7916
7917         tg3_full_unlock(tp);
7918
7919         return 0;
7920 }
7921
7922 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7923 {
7924         struct tg3 *tp = netdev_priv(dev);
7925
7926         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7927         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7928         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7929 }
7930
7931 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7932 {
7933         struct tg3 *tp = netdev_priv(dev);
7934         int irq_sync = 0;
7935
7936         if (netif_running(dev)) {
7937                 tg3_netif_stop(tp);
7938                 irq_sync = 1;
7939         }
7940
7941         tg3_full_lock(tp, irq_sync);
7942
7943         if (epause->autoneg)
7944                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7945         else
7946                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7947         if (epause->rx_pause)
7948                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7949         else
7950                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7951         if (epause->tx_pause)
7952                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7953         else
7954                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7955
7956         if (netif_running(dev)) {
7957                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7958                 tg3_init_hw(tp, 1);
7959                 tg3_netif_start(tp);
7960         }
7961
7962         tg3_full_unlock(tp);
7963
7964         return 0;
7965 }
7966
7967 static u32 tg3_get_rx_csum(struct net_device *dev)
7968 {
7969         struct tg3 *tp = netdev_priv(dev);
7970         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7971 }
7972
7973 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7974 {
7975         struct tg3 *tp = netdev_priv(dev);
7976
7977         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7978                 if (data != 0)
7979                         return -EINVAL;
7980                 return 0;
7981         }
7982
7983         spin_lock_bh(&tp->lock);
7984         if (data)
7985                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7986         else
7987                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7988         spin_unlock_bh(&tp->lock);
7989
7990         return 0;
7991 }
7992
7993 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7994 {
7995         struct tg3 *tp = netdev_priv(dev);
7996
7997         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7998                 if (data != 0)
7999                         return -EINVAL;
8000                 return 0;
8001         }
8002
8003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8005                 ethtool_op_set_tx_hw_csum(dev, data);
8006         else
8007                 ethtool_op_set_tx_csum(dev, data);
8008
8009         return 0;
8010 }
8011
8012 static int tg3_get_stats_count (struct net_device *dev)
8013 {
8014         return TG3_NUM_STATS;
8015 }
8016
8017 static int tg3_get_test_count (struct net_device *dev)
8018 {
8019         return TG3_NUM_TEST;
8020 }
8021
8022 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8023 {
8024         switch (stringset) {
8025         case ETH_SS_STATS:
8026                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8027                 break;
8028         case ETH_SS_TEST:
8029                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8030                 break;
8031         default:
8032                 WARN_ON(1);     /* we need a WARN() */
8033                 break;
8034         }
8035 }
8036
8037 static int tg3_phys_id(struct net_device *dev, u32 data)
8038 {
8039         struct tg3 *tp = netdev_priv(dev);
8040         int i;
8041
8042         if (!netif_running(tp->dev))
8043                 return -EAGAIN;
8044
8045         if (data == 0)
8046                 data = 2;
8047
8048         for (i = 0; i < (data * 2); i++) {
8049                 if ((i % 2) == 0)
8050                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8051                                            LED_CTRL_1000MBPS_ON |
8052                                            LED_CTRL_100MBPS_ON |
8053                                            LED_CTRL_10MBPS_ON |
8054                                            LED_CTRL_TRAFFIC_OVERRIDE |
8055                                            LED_CTRL_TRAFFIC_BLINK |
8056                                            LED_CTRL_TRAFFIC_LED);
8057
8058                 else
8059                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8060                                            LED_CTRL_TRAFFIC_OVERRIDE);
8061
8062                 if (msleep_interruptible(500))
8063                         break;
8064         }
8065         tw32(MAC_LED_CTRL, tp->led_ctrl);
8066         return 0;
8067 }
8068
8069 static void tg3_get_ethtool_stats (struct net_device *dev,
8070                                    struct ethtool_stats *estats, u64 *tmp_stats)
8071 {
8072         struct tg3 *tp = netdev_priv(dev);
8073         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8074 }
8075
8076 #define NVRAM_TEST_SIZE 0x100
8077 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8078
8079 static int tg3_test_nvram(struct tg3 *tp)
8080 {
8081         u32 *buf, csum, magic;
8082         int i, j, err = 0, size;
8083
8084         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8085                 return -EIO;
8086
8087         if (magic == TG3_EEPROM_MAGIC)
8088                 size = NVRAM_TEST_SIZE;
8089         else if ((magic & 0xff000000) == 0xa5000000) {
8090                 if ((magic & 0xe00000) == 0x200000)
8091                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8092                 else
8093                         return 0;
8094         } else
8095                 return -EIO;
8096
8097         buf = kmalloc(size, GFP_KERNEL);
8098         if (buf == NULL)
8099                 return -ENOMEM;
8100
8101         err = -EIO;
8102         for (i = 0, j = 0; i < size; i += 4, j++) {
8103                 u32 val;
8104
8105                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8106                         break;
8107                 buf[j] = cpu_to_le32(val);
8108         }
8109         if (i < size)
8110                 goto out;
8111
8112         /* Selfboot format */
8113         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
8114                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8115
8116                 for (i = 0; i < size; i++)
8117                         csum8 += buf8[i];
8118
8119                 if (csum8 == 0) {
8120                         err = 0;
8121                         goto out;
8122                 }
8123
8124                 err = -EIO;
8125                 goto out;
8126         }
8127
8128         /* Bootstrap checksum at offset 0x10 */
8129         csum = calc_crc((unsigned char *) buf, 0x10);
8130         if(csum != cpu_to_le32(buf[0x10/4]))
8131                 goto out;
8132
8133         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8134         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8135         if (csum != cpu_to_le32(buf[0xfc/4]))
8136                  goto out;
8137
8138         err = 0;
8139
8140 out:
8141         kfree(buf);
8142         return err;
8143 }
8144
8145 #define TG3_SERDES_TIMEOUT_SEC  2
8146 #define TG3_COPPER_TIMEOUT_SEC  6
8147
8148 static int tg3_test_link(struct tg3 *tp)
8149 {
8150         int i, max;
8151
8152         if (!netif_running(tp->dev))
8153                 return -ENODEV;
8154
8155         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8156                 max = TG3_SERDES_TIMEOUT_SEC;
8157         else
8158                 max = TG3_COPPER_TIMEOUT_SEC;
8159
8160         for (i = 0; i < max; i++) {
8161                 if (netif_carrier_ok(tp->dev))
8162                         return 0;
8163
8164                 if (msleep_interruptible(1000))
8165                         break;
8166         }
8167
8168         return -EIO;
8169 }
8170
8171 /* Only test the commonly used registers */
8172 static int tg3_test_registers(struct tg3 *tp)
8173 {
8174         int i, is_5705;
8175         u32 offset, read_mask, write_mask, val, save_val, read_val;
8176         static struct {
8177                 u16 offset;
8178                 u16 flags;
8179 #define TG3_FL_5705     0x1
8180 #define TG3_FL_NOT_5705 0x2
8181 #define TG3_FL_NOT_5788 0x4
8182                 u32 read_mask;
8183                 u32 write_mask;
8184         } reg_tbl[] = {
8185                 /* MAC Control Registers */
8186                 { MAC_MODE, TG3_FL_NOT_5705,
8187                         0x00000000, 0x00ef6f8c },
8188                 { MAC_MODE, TG3_FL_5705,
8189                         0x00000000, 0x01ef6b8c },
8190                 { MAC_STATUS, TG3_FL_NOT_5705,
8191                         0x03800107, 0x00000000 },
8192                 { MAC_STATUS, TG3_FL_5705,
8193                         0x03800100, 0x00000000 },
8194                 { MAC_ADDR_0_HIGH, 0x0000,
8195                         0x00000000, 0x0000ffff },
8196                 { MAC_ADDR_0_LOW, 0x0000,
8197                         0x00000000, 0xffffffff },
8198                 { MAC_RX_MTU_SIZE, 0x0000,
8199                         0x00000000, 0x0000ffff },
8200                 { MAC_TX_MODE, 0x0000,
8201                         0x00000000, 0x00000070 },
8202                 { MAC_TX_LENGTHS, 0x0000,
8203                         0x00000000, 0x00003fff },
8204                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8205                         0x00000000, 0x000007fc },
8206                 { MAC_RX_MODE, TG3_FL_5705,
8207                         0x00000000, 0x000007dc },
8208                 { MAC_HASH_REG_0, 0x0000,
8209                         0x00000000, 0xffffffff },
8210                 { MAC_HASH_REG_1, 0x0000,
8211                         0x00000000, 0xffffffff },
8212                 { MAC_HASH_REG_2, 0x0000,
8213                         0x00000000, 0xffffffff },
8214                 { MAC_HASH_REG_3, 0x0000,
8215                         0x00000000, 0xffffffff },
8216
8217                 /* Receive Data and Receive BD Initiator Control Registers. */
8218                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8219                         0x00000000, 0xffffffff },
8220                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8221                         0x00000000, 0xffffffff },
8222                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8223                         0x00000000, 0x00000003 },
8224                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8225                         0x00000000, 0xffffffff },
8226                 { RCVDBDI_STD_BD+0, 0x0000,
8227                         0x00000000, 0xffffffff },
8228                 { RCVDBDI_STD_BD+4, 0x0000,
8229                         0x00000000, 0xffffffff },
8230                 { RCVDBDI_STD_BD+8, 0x0000,
8231                         0x00000000, 0xffff0002 },
8232                 { RCVDBDI_STD_BD+0xc, 0x0000,
8233                         0x00000000, 0xffffffff },
8234
8235                 /* Receive BD Initiator Control Registers. */
8236                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8237                         0x00000000, 0xffffffff },
8238                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8239                         0x00000000, 0x000003ff },
8240                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8241                         0x00000000, 0xffffffff },
8242
8243                 /* Host Coalescing Control Registers. */
8244                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8245                         0x00000000, 0x00000004 },
8246                 { HOSTCC_MODE, TG3_FL_5705,
8247                         0x00000000, 0x000000f6 },
8248                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8249                         0x00000000, 0xffffffff },
8250                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8251                         0x00000000, 0x000003ff },
8252                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8253                         0x00000000, 0xffffffff },
8254                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8255                         0x00000000, 0x000003ff },
8256                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8257                         0x00000000, 0xffffffff },
8258                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8259                         0x00000000, 0x000000ff },
8260                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8261                         0x00000000, 0xffffffff },
8262                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8263                         0x00000000, 0x000000ff },
8264                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8265                         0x00000000, 0xffffffff },
8266                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8267                         0x00000000, 0xffffffff },
8268                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8269                         0x00000000, 0xffffffff },
8270                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8271                         0x00000000, 0x000000ff },
8272                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8273                         0x00000000, 0xffffffff },
8274                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8275                         0x00000000, 0x000000ff },
8276                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8277                         0x00000000, 0xffffffff },
8278                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8279                         0x00000000, 0xffffffff },
8280                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8281                         0x00000000, 0xffffffff },
8282                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8283                         0x00000000, 0xffffffff },
8284                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8285                         0x00000000, 0xffffffff },
8286                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8287                         0xffffffff, 0x00000000 },
8288                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8289                         0xffffffff, 0x00000000 },
8290
8291                 /* Buffer Manager Control Registers. */
8292                 { BUFMGR_MB_POOL_ADDR, 0x0000,
8293                         0x00000000, 0x007fff80 },
8294                 { BUFMGR_MB_POOL_SIZE, 0x0000,
8295                         0x00000000, 0x007fffff },
8296                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8297                         0x00000000, 0x0000003f },
8298                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8299                         0x00000000, 0x000001ff },
8300                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8301                         0x00000000, 0x000001ff },
8302                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8303                         0xffffffff, 0x00000000 },
8304                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8305                         0xffffffff, 0x00000000 },
8306
8307                 /* Mailbox Registers */
8308                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8309                         0x00000000, 0x000001ff },
8310                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8311                         0x00000000, 0x000001ff },
8312                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8313                         0x00000000, 0x000007ff },
8314                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8315                         0x00000000, 0x000001ff },
8316
8317                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8318         };
8319
8320         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8321                 is_5705 = 1;
8322         else
8323                 is_5705 = 0;
8324
8325         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8326                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8327                         continue;
8328
8329                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8330                         continue;
8331
8332                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8333                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8334                         continue;
8335
8336                 offset = (u32) reg_tbl[i].offset;
8337                 read_mask = reg_tbl[i].read_mask;
8338                 write_mask = reg_tbl[i].write_mask;
8339
8340                 /* Save the original register content */
8341                 save_val = tr32(offset);
8342
8343                 /* Determine the read-only value. */
8344                 read_val = save_val & read_mask;
8345
8346                 /* Write zero to the register, then make sure the read-only bits
8347                  * are not changed and the read/write bits are all zeros.
8348                  */
8349                 tw32(offset, 0);
8350
8351                 val = tr32(offset);
8352
8353                 /* Test the read-only and read/write bits. */
8354                 if (((val & read_mask) != read_val) || (val & write_mask))
8355                         goto out;
8356
8357                 /* Write ones to all the bits defined by RdMask and WrMask, then
8358                  * make sure the read-only bits are not changed and the
8359                  * read/write bits are all ones.
8360                  */
8361                 tw32(offset, read_mask | write_mask);
8362
8363                 val = tr32(offset);
8364
8365                 /* Test the read-only bits. */
8366                 if ((val & read_mask) != read_val)
8367                         goto out;
8368
8369                 /* Test the read/write bits. */
8370                 if ((val & write_mask) != write_mask)
8371                         goto out;
8372
8373                 tw32(offset, save_val);
8374         }
8375
8376         return 0;
8377
8378 out:
8379         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8380         tw32(offset, save_val);
8381         return -EIO;
8382 }
8383
8384 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8385 {
8386         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8387         int i;
8388         u32 j;
8389
8390         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8391                 for (j = 0; j < len; j += 4) {
8392                         u32 val;
8393
8394                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8395                         tg3_read_mem(tp, offset + j, &val);
8396                         if (val != test_pattern[i])
8397                                 return -EIO;
8398                 }
8399         }
8400         return 0;
8401 }
8402
8403 static int tg3_test_memory(struct tg3 *tp)
8404 {
8405         static struct mem_entry {
8406                 u32 offset;
8407                 u32 len;
8408         } mem_tbl_570x[] = {
8409                 { 0x00000000, 0x00b50},
8410                 { 0x00002000, 0x1c000},
8411                 { 0xffffffff, 0x00000}
8412         }, mem_tbl_5705[] = {
8413                 { 0x00000100, 0x0000c},
8414                 { 0x00000200, 0x00008},
8415                 { 0x00004000, 0x00800},
8416                 { 0x00006000, 0x01000},
8417                 { 0x00008000, 0x02000},
8418                 { 0x00010000, 0x0e000},
8419                 { 0xffffffff, 0x00000}
8420         }, mem_tbl_5755[] = {
8421                 { 0x00000200, 0x00008},
8422                 { 0x00004000, 0x00800},
8423                 { 0x00006000, 0x00800},
8424                 { 0x00008000, 0x02000},
8425                 { 0x00010000, 0x0c000},
8426                 { 0xffffffff, 0x00000}
8427         };
8428         struct mem_entry *mem_tbl;
8429         int err = 0;
8430         int i;
8431
8432         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8433                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8434                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8435                         mem_tbl = mem_tbl_5755;
8436                 else
8437                         mem_tbl = mem_tbl_5705;
8438         } else
8439                 mem_tbl = mem_tbl_570x;
8440
8441         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8442                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8443                     mem_tbl[i].len)) != 0)
8444                         break;
8445         }
8446
8447         return err;
8448 }
8449
8450 #define TG3_MAC_LOOPBACK        0
8451 #define TG3_PHY_LOOPBACK        1
8452
8453 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8454 {
8455         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8456         u32 desc_idx;
8457         struct sk_buff *skb, *rx_skb;
8458         u8 *tx_data;
8459         dma_addr_t map;
8460         int num_pkts, tx_len, rx_len, i, err;
8461         struct tg3_rx_buffer_desc *desc;
8462
8463         if (loopback_mode == TG3_MAC_LOOPBACK) {
8464                 /* HW errata - mac loopback fails in some cases on 5780.
8465                  * Normal traffic and PHY loopback are not affected by
8466                  * errata.
8467                  */
8468                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8469                         return 0;
8470
8471                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8472                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8473                            MAC_MODE_PORT_MODE_GMII;
8474                 tw32(MAC_MODE, mac_mode);
8475         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8476                 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8477                                            BMCR_SPEED1000);
8478                 udelay(40);
8479                 /* reset to prevent losing 1st rx packet intermittently */
8480                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8481                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8482                         udelay(10);
8483                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8484                 }
8485                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8486                            MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8487                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8488                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8489                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8490                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8491                 }
8492                 tw32(MAC_MODE, mac_mode);
8493         }
8494         else
8495                 return -EINVAL;
8496
8497         err = -EIO;
8498
8499         tx_len = 1514;
8500         skb = dev_alloc_skb(tx_len);
8501         if (!skb)
8502                 return -ENOMEM;
8503
8504         tx_data = skb_put(skb, tx_len);
8505         memcpy(tx_data, tp->dev->dev_addr, 6);
8506         memset(tx_data + 6, 0x0, 8);
8507
8508         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8509
8510         for (i = 14; i < tx_len; i++)
8511                 tx_data[i] = (u8) (i & 0xff);
8512
8513         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8514
8515         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8516              HOSTCC_MODE_NOW);
8517
8518         udelay(10);
8519
8520         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8521
8522         num_pkts = 0;
8523
8524         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8525
8526         tp->tx_prod++;
8527         num_pkts++;
8528
8529         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8530                      tp->tx_prod);
8531         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8532
8533         udelay(10);
8534
8535         for (i = 0; i < 10; i++) {
8536                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8537                        HOSTCC_MODE_NOW);
8538
8539                 udelay(10);
8540
8541                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8542                 rx_idx = tp->hw_status->idx[0].rx_producer;
8543                 if ((tx_idx == tp->tx_prod) &&
8544                     (rx_idx == (rx_start_idx + num_pkts)))
8545                         break;
8546         }
8547
8548         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8549         dev_kfree_skb(skb);
8550
8551         if (tx_idx != tp->tx_prod)
8552                 goto out;
8553
8554         if (rx_idx != rx_start_idx + num_pkts)
8555                 goto out;
8556
8557         desc = &tp->rx_rcb[rx_start_idx];
8558         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8559         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8560         if (opaque_key != RXD_OPAQUE_RING_STD)
8561                 goto out;
8562
8563         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8564             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8565                 goto out;
8566
8567         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8568         if (rx_len != tx_len)
8569                 goto out;
8570
8571         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8572
8573         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8574         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8575
8576         for (i = 14; i < tx_len; i++) {
8577                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8578                         goto out;
8579         }
8580         err = 0;
8581
8582         /* tg3_free_rings will unmap and free the rx_skb */
8583 out:
8584         return err;
8585 }
8586
8587 #define TG3_MAC_LOOPBACK_FAILED         1
8588 #define TG3_PHY_LOOPBACK_FAILED         2
8589 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8590                                          TG3_PHY_LOOPBACK_FAILED)
8591
8592 static int tg3_test_loopback(struct tg3 *tp)
8593 {
8594         int err = 0;
8595
8596         if (!netif_running(tp->dev))
8597                 return TG3_LOOPBACK_FAILED;
8598
8599         tg3_reset_hw(tp, 1);
8600
8601         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8602                 err |= TG3_MAC_LOOPBACK_FAILED;
8603         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8604                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8605                         err |= TG3_PHY_LOOPBACK_FAILED;
8606         }
8607
8608         return err;
8609 }
8610
8611 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8612                           u64 *data)
8613 {
8614         struct tg3 *tp = netdev_priv(dev);
8615
8616         if (tp->link_config.phy_is_low_power)
8617                 tg3_set_power_state(tp, PCI_D0);
8618
8619         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8620
8621         if (tg3_test_nvram(tp) != 0) {
8622                 etest->flags |= ETH_TEST_FL_FAILED;
8623                 data[0] = 1;
8624         }
8625         if (tg3_test_link(tp) != 0) {
8626                 etest->flags |= ETH_TEST_FL_FAILED;
8627                 data[1] = 1;
8628         }
8629         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8630                 int err, irq_sync = 0;
8631
8632                 if (netif_running(dev)) {
8633                         tg3_netif_stop(tp);
8634                         irq_sync = 1;
8635                 }
8636
8637                 tg3_full_lock(tp, irq_sync);
8638
8639                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8640                 err = tg3_nvram_lock(tp);
8641                 tg3_halt_cpu(tp, RX_CPU_BASE);
8642                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8643                         tg3_halt_cpu(tp, TX_CPU_BASE);
8644                 if (!err)
8645                         tg3_nvram_unlock(tp);
8646
8647                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8648                         tg3_phy_reset(tp);
8649
8650                 if (tg3_test_registers(tp) != 0) {
8651                         etest->flags |= ETH_TEST_FL_FAILED;
8652                         data[2] = 1;
8653                 }
8654                 if (tg3_test_memory(tp) != 0) {
8655                         etest->flags |= ETH_TEST_FL_FAILED;
8656                         data[3] = 1;
8657                 }
8658                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8659                         etest->flags |= ETH_TEST_FL_FAILED;
8660
8661                 tg3_full_unlock(tp);
8662
8663                 if (tg3_test_interrupt(tp) != 0) {
8664                         etest->flags |= ETH_TEST_FL_FAILED;
8665                         data[5] = 1;
8666                 }
8667
8668                 tg3_full_lock(tp, 0);
8669
8670                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8671                 if (netif_running(dev)) {
8672                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8673                         tg3_init_hw(tp, 1);
8674                         tg3_netif_start(tp);
8675                 }
8676
8677                 tg3_full_unlock(tp);
8678         }
8679         if (tp->link_config.phy_is_low_power)
8680                 tg3_set_power_state(tp, PCI_D3hot);
8681
8682 }
8683
8684 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8685 {
8686         struct mii_ioctl_data *data = if_mii(ifr);
8687         struct tg3 *tp = netdev_priv(dev);
8688         int err;
8689
8690         switch(cmd) {
8691         case SIOCGMIIPHY:
8692                 data->phy_id = PHY_ADDR;
8693
8694                 /* fallthru */
8695         case SIOCGMIIREG: {
8696                 u32 mii_regval;
8697
8698                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8699                         break;                  /* We have no PHY */
8700
8701                 if (tp->link_config.phy_is_low_power)
8702                         return -EAGAIN;
8703
8704                 spin_lock_bh(&tp->lock);
8705                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8706                 spin_unlock_bh(&tp->lock);
8707
8708                 data->val_out = mii_regval;
8709
8710                 return err;
8711         }
8712
8713         case SIOCSMIIREG:
8714                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8715                         break;                  /* We have no PHY */
8716
8717                 if (!capable(CAP_NET_ADMIN))
8718                         return -EPERM;
8719
8720                 if (tp->link_config.phy_is_low_power)
8721                         return -EAGAIN;
8722
8723                 spin_lock_bh(&tp->lock);
8724                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8725                 spin_unlock_bh(&tp->lock);
8726
8727                 return err;
8728
8729         default:
8730                 /* do nothing */
8731                 break;
8732         }
8733         return -EOPNOTSUPP;
8734 }
8735
8736 #if TG3_VLAN_TAG_USED
8737 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8738 {
8739         struct tg3 *tp = netdev_priv(dev);
8740
8741         tg3_full_lock(tp, 0);
8742
8743         tp->vlgrp = grp;
8744
8745         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8746         __tg3_set_rx_mode(dev);
8747
8748         tg3_full_unlock(tp);
8749 }
8750
8751 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8752 {
8753         struct tg3 *tp = netdev_priv(dev);
8754
8755         tg3_full_lock(tp, 0);
8756         if (tp->vlgrp)
8757                 tp->vlgrp->vlan_devices[vid] = NULL;
8758         tg3_full_unlock(tp);
8759 }
8760 #endif
8761
8762 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8763 {
8764         struct tg3 *tp = netdev_priv(dev);
8765
8766         memcpy(ec, &tp->coal, sizeof(*ec));
8767         return 0;
8768 }
8769
8770 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8771 {
8772         struct tg3 *tp = netdev_priv(dev);
8773         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8774         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8775
8776         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8777                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8778                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8779                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8780                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8781         }
8782
8783         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8784             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8785             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8786             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8787             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8788             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8789             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8790             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8791             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8792             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8793                 return -EINVAL;
8794
8795         /* No rx interrupts will be generated if both are zero */
8796         if ((ec->rx_coalesce_usecs == 0) &&
8797             (ec->rx_max_coalesced_frames == 0))
8798                 return -EINVAL;
8799
8800         /* No tx interrupts will be generated if both are zero */
8801         if ((ec->tx_coalesce_usecs == 0) &&
8802             (ec->tx_max_coalesced_frames == 0))
8803                 return -EINVAL;
8804
8805         /* Only copy relevant parameters, ignore all others. */
8806         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8807         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8808         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8809         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8810         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8811         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8812         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8813         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8814         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8815
8816         if (netif_running(dev)) {
8817                 tg3_full_lock(tp, 0);
8818                 __tg3_set_coalesce(tp, &tp->coal);
8819                 tg3_full_unlock(tp);
8820         }
8821         return 0;
8822 }
8823
8824 static struct ethtool_ops tg3_ethtool_ops = {
8825         .get_settings           = tg3_get_settings,
8826         .set_settings           = tg3_set_settings,
8827         .get_drvinfo            = tg3_get_drvinfo,
8828         .get_regs_len           = tg3_get_regs_len,
8829         .get_regs               = tg3_get_regs,
8830         .get_wol                = tg3_get_wol,
8831         .set_wol                = tg3_set_wol,
8832         .get_msglevel           = tg3_get_msglevel,
8833         .set_msglevel           = tg3_set_msglevel,
8834         .nway_reset             = tg3_nway_reset,
8835         .get_link               = ethtool_op_get_link,
8836         .get_eeprom_len         = tg3_get_eeprom_len,
8837         .get_eeprom             = tg3_get_eeprom,
8838         .set_eeprom             = tg3_set_eeprom,
8839         .get_ringparam          = tg3_get_ringparam,
8840         .set_ringparam          = tg3_set_ringparam,
8841         .get_pauseparam         = tg3_get_pauseparam,
8842         .set_pauseparam         = tg3_set_pauseparam,
8843         .get_rx_csum            = tg3_get_rx_csum,
8844         .set_rx_csum            = tg3_set_rx_csum,
8845         .get_tx_csum            = ethtool_op_get_tx_csum,
8846         .set_tx_csum            = tg3_set_tx_csum,
8847         .get_sg                 = ethtool_op_get_sg,
8848         .set_sg                 = ethtool_op_set_sg,
8849 #if TG3_TSO_SUPPORT != 0
8850         .get_tso                = ethtool_op_get_tso,
8851         .set_tso                = tg3_set_tso,
8852 #endif
8853         .self_test_count        = tg3_get_test_count,
8854         .self_test              = tg3_self_test,
8855         .get_strings            = tg3_get_strings,
8856         .phys_id                = tg3_phys_id,
8857         .get_stats_count        = tg3_get_stats_count,
8858         .get_ethtool_stats      = tg3_get_ethtool_stats,
8859         .get_coalesce           = tg3_get_coalesce,
8860         .set_coalesce           = tg3_set_coalesce,
8861         .get_perm_addr          = ethtool_op_get_perm_addr,
8862 };
8863
8864 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8865 {
8866         u32 cursize, val, magic;
8867
8868         tp->nvram_size = EEPROM_CHIP_SIZE;
8869
8870         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8871                 return;
8872
8873         if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
8874                 return;
8875
8876         /*
8877          * Size the chip by reading offsets at increasing powers of two.
8878          * When we encounter our validation signature, we know the addressing
8879          * has wrapped around, and thus have our chip size.
8880          */
8881         cursize = 0x10;
8882
8883         while (cursize < tp->nvram_size) {
8884                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8885                         return;
8886
8887                 if (val == magic)
8888                         break;
8889
8890                 cursize <<= 1;
8891         }
8892
8893         tp->nvram_size = cursize;
8894 }
8895
8896 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8897 {
8898         u32 val;
8899
8900         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
8901                 return;
8902
8903         /* Selfboot format */
8904         if (val != TG3_EEPROM_MAGIC) {
8905                 tg3_get_eeprom_size(tp);
8906                 return;
8907         }
8908
8909         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8910                 if (val != 0) {
8911                         tp->nvram_size = (val >> 16) * 1024;
8912                         return;
8913                 }
8914         }
8915         tp->nvram_size = 0x20000;
8916 }
8917
8918 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8919 {
8920         u32 nvcfg1;
8921
8922         nvcfg1 = tr32(NVRAM_CFG1);
8923         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8924                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8925         }
8926         else {
8927                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8928                 tw32(NVRAM_CFG1, nvcfg1);
8929         }
8930
8931         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8932             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8933                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8934                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8935                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8936                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8937                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8938                                 break;
8939                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8940                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8941                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8942                                 break;
8943                         case FLASH_VENDOR_ATMEL_EEPROM:
8944                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8945                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8946                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8947                                 break;
8948                         case FLASH_VENDOR_ST:
8949                                 tp->nvram_jedecnum = JEDEC_ST;
8950                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8951                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8952                                 break;
8953                         case FLASH_VENDOR_SAIFUN:
8954                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8955                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8956                                 break;
8957                         case FLASH_VENDOR_SST_SMALL:
8958                         case FLASH_VENDOR_SST_LARGE:
8959                                 tp->nvram_jedecnum = JEDEC_SST;
8960                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8961                                 break;
8962                 }
8963         }
8964         else {
8965                 tp->nvram_jedecnum = JEDEC_ATMEL;
8966                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8967                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8968         }
8969 }
8970
8971 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8972 {
8973         u32 nvcfg1;
8974
8975         nvcfg1 = tr32(NVRAM_CFG1);
8976
8977         /* NVRAM protection for TPM */
8978         if (nvcfg1 & (1 << 27))
8979                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8980
8981         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8982                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8983                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8984                         tp->nvram_jedecnum = JEDEC_ATMEL;
8985                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8986                         break;
8987                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8988                         tp->nvram_jedecnum = JEDEC_ATMEL;
8989                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8990                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8991                         break;
8992                 case FLASH_5752VENDOR_ST_M45PE10:
8993                 case FLASH_5752VENDOR_ST_M45PE20:
8994                 case FLASH_5752VENDOR_ST_M45PE40:
8995                         tp->nvram_jedecnum = JEDEC_ST;
8996                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8997                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8998                         break;
8999         }
9000
9001         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9002                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9003                         case FLASH_5752PAGE_SIZE_256:
9004                                 tp->nvram_pagesize = 256;
9005                                 break;
9006                         case FLASH_5752PAGE_SIZE_512:
9007                                 tp->nvram_pagesize = 512;
9008                                 break;
9009                         case FLASH_5752PAGE_SIZE_1K:
9010                                 tp->nvram_pagesize = 1024;
9011                                 break;
9012                         case FLASH_5752PAGE_SIZE_2K:
9013                                 tp->nvram_pagesize = 2048;
9014                                 break;
9015                         case FLASH_5752PAGE_SIZE_4K:
9016                                 tp->nvram_pagesize = 4096;
9017                                 break;
9018                         case FLASH_5752PAGE_SIZE_264:
9019                                 tp->nvram_pagesize = 264;
9020                                 break;
9021                 }
9022         }
9023         else {
9024                 /* For eeprom, set pagesize to maximum eeprom size */
9025                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9026
9027                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9028                 tw32(NVRAM_CFG1, nvcfg1);
9029         }
9030 }
9031
9032 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9033 {
9034         u32 nvcfg1;
9035
9036         nvcfg1 = tr32(NVRAM_CFG1);
9037
9038         /* NVRAM protection for TPM */
9039         if (nvcfg1 & (1 << 27))
9040                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9041
9042         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9043                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9044                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9045                         tp->nvram_jedecnum = JEDEC_ATMEL;
9046                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9047                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9048
9049                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9050                         tw32(NVRAM_CFG1, nvcfg1);
9051                         break;
9052                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9053                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9054                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9055                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9056                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9057                         tp->nvram_jedecnum = JEDEC_ATMEL;
9058                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9059                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9060                         tp->nvram_pagesize = 264;
9061                         break;
9062                 case FLASH_5752VENDOR_ST_M45PE10:
9063                 case FLASH_5752VENDOR_ST_M45PE20:
9064                 case FLASH_5752VENDOR_ST_M45PE40:
9065                         tp->nvram_jedecnum = JEDEC_ST;
9066                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9067                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9068                         tp->nvram_pagesize = 256;
9069                         break;
9070         }
9071 }
9072
9073 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9074 {
9075         u32 nvcfg1;
9076
9077         nvcfg1 = tr32(NVRAM_CFG1);
9078
9079         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9080                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9081                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9082                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9083                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9084                         tp->nvram_jedecnum = JEDEC_ATMEL;
9085                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9086                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9087
9088                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9089                         tw32(NVRAM_CFG1, nvcfg1);
9090                         break;
9091                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9092                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9093                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9094                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9095                         tp->nvram_jedecnum = JEDEC_ATMEL;
9096                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9097                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9098                         tp->nvram_pagesize = 264;
9099                         break;
9100                 case FLASH_5752VENDOR_ST_M45PE10:
9101                 case FLASH_5752VENDOR_ST_M45PE20:
9102                 case FLASH_5752VENDOR_ST_M45PE40:
9103                         tp->nvram_jedecnum = JEDEC_ST;
9104                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9105                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9106                         tp->nvram_pagesize = 256;
9107                         break;
9108         }
9109 }
9110
9111 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9112 static void __devinit tg3_nvram_init(struct tg3 *tp)
9113 {
9114         int j;
9115
9116         tw32_f(GRC_EEPROM_ADDR,
9117              (EEPROM_ADDR_FSM_RESET |
9118               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9119                EEPROM_ADDR_CLKPERD_SHIFT)));
9120
9121         /* XXX schedule_timeout() ... */
9122         for (j = 0; j < 100; j++)
9123                 udelay(10);
9124
9125         /* Enable seeprom accesses. */
9126         tw32_f(GRC_LOCAL_CTRL,
9127              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9128         udelay(100);
9129
9130         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9131             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9132                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9133
9134                 if (tg3_nvram_lock(tp)) {
9135                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9136                                "tg3_nvram_init failed.\n", tp->dev->name);
9137                         return;
9138                 }
9139                 tg3_enable_nvram_access(tp);
9140
9141                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9142                         tg3_get_5752_nvram_info(tp);
9143                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9144                         tg3_get_5755_nvram_info(tp);
9145                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9146                         tg3_get_5787_nvram_info(tp);
9147                 else
9148                         tg3_get_nvram_info(tp);
9149
9150                 tg3_get_nvram_size(tp);
9151
9152                 tg3_disable_nvram_access(tp);
9153                 tg3_nvram_unlock(tp);
9154
9155         } else {
9156                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9157
9158                 tg3_get_eeprom_size(tp);
9159         }
9160 }
9161
9162 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9163                                         u32 offset, u32 *val)
9164 {
9165         u32 tmp;
9166         int i;
9167
9168         if (offset > EEPROM_ADDR_ADDR_MASK ||
9169             (offset % 4) != 0)
9170                 return -EINVAL;
9171
9172         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9173                                         EEPROM_ADDR_DEVID_MASK |
9174                                         EEPROM_ADDR_READ);
9175         tw32(GRC_EEPROM_ADDR,
9176              tmp |
9177              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9178              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9179               EEPROM_ADDR_ADDR_MASK) |
9180              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9181
9182         for (i = 0; i < 10000; i++) {
9183                 tmp = tr32(GRC_EEPROM_ADDR);
9184
9185                 if (tmp & EEPROM_ADDR_COMPLETE)
9186                         break;
9187                 udelay(100);
9188         }
9189         if (!(tmp & EEPROM_ADDR_COMPLETE))
9190                 return -EBUSY;
9191
9192         *val = tr32(GRC_EEPROM_DATA);
9193         return 0;
9194 }
9195
9196 #define NVRAM_CMD_TIMEOUT 10000
9197
9198 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9199 {
9200         int i;
9201
9202         tw32(NVRAM_CMD, nvram_cmd);
9203         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9204                 udelay(10);
9205                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9206                         udelay(10);
9207                         break;
9208                 }
9209         }
9210         if (i == NVRAM_CMD_TIMEOUT) {
9211                 return -EBUSY;
9212         }
9213         return 0;
9214 }
9215
9216 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9217 {
9218         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9219             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9220             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9221             (tp->nvram_jedecnum == JEDEC_ATMEL))
9222
9223                 addr = ((addr / tp->nvram_pagesize) <<
9224                         ATMEL_AT45DB0X1B_PAGE_POS) +
9225                        (addr % tp->nvram_pagesize);
9226
9227         return addr;
9228 }
9229
9230 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9231 {
9232         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9233             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9234             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9235             (tp->nvram_jedecnum == JEDEC_ATMEL))
9236
9237                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9238                         tp->nvram_pagesize) +
9239                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9240
9241         return addr;
9242 }
9243
9244 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9245 {
9246         int ret;
9247
9248         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9249                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9250
9251         offset = tg3_nvram_phys_addr(tp, offset);
9252
9253         if (offset > NVRAM_ADDR_MSK)
9254                 return -EINVAL;
9255
9256         ret = tg3_nvram_lock(tp);
9257         if (ret)
9258                 return ret;
9259
9260         tg3_enable_nvram_access(tp);
9261
9262         tw32(NVRAM_ADDR, offset);
9263         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9264                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9265
9266         if (ret == 0)
9267                 *val = swab32(tr32(NVRAM_RDDATA));
9268
9269         tg3_disable_nvram_access(tp);
9270
9271         tg3_nvram_unlock(tp);
9272
9273         return ret;
9274 }
9275
9276 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9277 {
9278         int err;
9279         u32 tmp;
9280
9281         err = tg3_nvram_read(tp, offset, &tmp);
9282         *val = swab32(tmp);
9283         return err;
9284 }
9285
9286 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9287                                     u32 offset, u32 len, u8 *buf)
9288 {
9289         int i, j, rc = 0;
9290         u32 val;
9291
9292         for (i = 0; i < len; i += 4) {
9293                 u32 addr, data;
9294
9295                 addr = offset + i;
9296
9297                 memcpy(&data, buf + i, 4);
9298
9299                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9300
9301                 val = tr32(GRC_EEPROM_ADDR);
9302                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9303
9304                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9305                         EEPROM_ADDR_READ);
9306                 tw32(GRC_EEPROM_ADDR, val |
9307                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9308                         (addr & EEPROM_ADDR_ADDR_MASK) |
9309                         EEPROM_ADDR_START |
9310                         EEPROM_ADDR_WRITE);
9311
9312                 for (j = 0; j < 10000; j++) {
9313                         val = tr32(GRC_EEPROM_ADDR);
9314
9315                         if (val & EEPROM_ADDR_COMPLETE)
9316                                 break;
9317                         udelay(100);
9318                 }
9319                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9320                         rc = -EBUSY;
9321                         break;
9322                 }
9323         }
9324
9325         return rc;
9326 }
9327
9328 /* offset and length are dword aligned */
9329 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9330                 u8 *buf)
9331 {
9332         int ret = 0;
9333         u32 pagesize = tp->nvram_pagesize;
9334         u32 pagemask = pagesize - 1;
9335         u32 nvram_cmd;
9336         u8 *tmp;
9337
9338         tmp = kmalloc(pagesize, GFP_KERNEL);
9339         if (tmp == NULL)
9340                 return -ENOMEM;
9341
9342         while (len) {
9343                 int j;
9344                 u32 phy_addr, page_off, size;
9345
9346                 phy_addr = offset & ~pagemask;
9347
9348                 for (j = 0; j < pagesize; j += 4) {
9349                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9350                                                 (u32 *) (tmp + j))))
9351                                 break;
9352                 }
9353                 if (ret)
9354                         break;
9355
9356                 page_off = offset & pagemask;
9357                 size = pagesize;
9358                 if (len < size)
9359                         size = len;
9360
9361                 len -= size;
9362
9363                 memcpy(tmp + page_off, buf, size);
9364
9365                 offset = offset + (pagesize - page_off);
9366
9367                 tg3_enable_nvram_access(tp);
9368
9369                 /*
9370                  * Before we can erase the flash page, we need
9371                  * to issue a special "write enable" command.
9372                  */
9373                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9374
9375                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9376                         break;
9377
9378                 /* Erase the target page */
9379                 tw32(NVRAM_ADDR, phy_addr);
9380
9381                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9382                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9383
9384                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9385                         break;
9386
9387                 /* Issue another write enable to start the write. */
9388                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9389
9390                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9391                         break;
9392
9393                 for (j = 0; j < pagesize; j += 4) {
9394                         u32 data;
9395
9396                         data = *((u32 *) (tmp + j));
9397                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9398
9399                         tw32(NVRAM_ADDR, phy_addr + j);
9400
9401                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9402                                 NVRAM_CMD_WR;
9403
9404                         if (j == 0)
9405                                 nvram_cmd |= NVRAM_CMD_FIRST;
9406                         else if (j == (pagesize - 4))
9407                                 nvram_cmd |= NVRAM_CMD_LAST;
9408
9409                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9410                                 break;
9411                 }
9412                 if (ret)
9413                         break;
9414         }
9415
9416         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9417         tg3_nvram_exec_cmd(tp, nvram_cmd);
9418
9419         kfree(tmp);
9420
9421         return ret;
9422 }
9423
9424 /* offset and length are dword aligned */
9425 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9426                 u8 *buf)
9427 {
9428         int i, ret = 0;
9429
9430         for (i = 0; i < len; i += 4, offset += 4) {
9431                 u32 data, page_off, phy_addr, nvram_cmd;
9432
9433                 memcpy(&data, buf + i, 4);
9434                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9435
9436                 page_off = offset % tp->nvram_pagesize;
9437
9438                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9439
9440                 tw32(NVRAM_ADDR, phy_addr);
9441
9442                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9443
9444                 if ((page_off == 0) || (i == 0))
9445                         nvram_cmd |= NVRAM_CMD_FIRST;
9446                 if (page_off == (tp->nvram_pagesize - 4))
9447                         nvram_cmd |= NVRAM_CMD_LAST;
9448
9449                 if (i == (len - 4))
9450                         nvram_cmd |= NVRAM_CMD_LAST;
9451
9452                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9453                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9454                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9455                     (tp->nvram_jedecnum == JEDEC_ST) &&
9456                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9457
9458                         if ((ret = tg3_nvram_exec_cmd(tp,
9459                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9460                                 NVRAM_CMD_DONE)))
9461
9462                                 break;
9463                 }
9464                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9465                         /* We always do complete word writes to eeprom. */
9466                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9467                 }
9468
9469                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9470                         break;
9471         }
9472         return ret;
9473 }
9474
9475 /* offset and length are dword aligned */
9476 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9477 {
9478         int ret;
9479
9480         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9481                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9482                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9483                 udelay(40);
9484         }
9485
9486         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9487                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9488         }
9489         else {
9490                 u32 grc_mode;
9491
9492                 ret = tg3_nvram_lock(tp);
9493                 if (ret)
9494                         return ret;
9495
9496                 tg3_enable_nvram_access(tp);
9497                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9498                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9499                         tw32(NVRAM_WRITE1, 0x406);
9500
9501                 grc_mode = tr32(GRC_MODE);
9502                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9503
9504                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9505                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9506
9507                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9508                                 buf);
9509                 }
9510                 else {
9511                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9512                                 buf);
9513                 }
9514
9515                 grc_mode = tr32(GRC_MODE);
9516                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9517
9518                 tg3_disable_nvram_access(tp);
9519                 tg3_nvram_unlock(tp);
9520         }
9521
9522         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9523                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9524                 udelay(40);
9525         }
9526
9527         return ret;
9528 }
9529
9530 struct subsys_tbl_ent {
9531         u16 subsys_vendor, subsys_devid;
9532         u32 phy_id;
9533 };
9534
9535 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9536         /* Broadcom boards. */
9537         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9538         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9539         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9540         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9541         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9542         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9543         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9544         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9545         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9546         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9547         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9548
9549         /* 3com boards. */
9550         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9551         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9552         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9553         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9554         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9555
9556         /* DELL boards. */
9557         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9558         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9559         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9560         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9561
9562         /* Compaq boards. */
9563         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9564         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9565         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9566         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9567         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9568
9569         /* IBM boards. */
9570         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9571 };
9572
9573 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9574 {
9575         int i;
9576
9577         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9578                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9579                      tp->pdev->subsystem_vendor) &&
9580                     (subsys_id_to_phy_id[i].subsys_devid ==
9581                      tp->pdev->subsystem_device))
9582                         return &subsys_id_to_phy_id[i];
9583         }
9584         return NULL;
9585 }
9586
9587 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9588 {
9589         u32 val;
9590         u16 pmcsr;
9591
9592         /* On some early chips the SRAM cannot be accessed in D3hot state,
9593          * so need make sure we're in D0.
9594          */
9595         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9596         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9597         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9598         msleep(1);
9599
9600         /* Make sure register accesses (indirect or otherwise)
9601          * will function correctly.
9602          */
9603         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9604                                tp->misc_host_ctrl);
9605
9606         /* The memory arbiter has to be enabled in order for SRAM accesses
9607          * to succeed.  Normally on powerup the tg3 chip firmware will make
9608          * sure it is enabled, but other entities such as system netboot
9609          * code might disable it.
9610          */
9611         val = tr32(MEMARB_MODE);
9612         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9613
9614         tp->phy_id = PHY_ID_INVALID;
9615         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9616
9617         /* Assume an onboard device by default.  */
9618         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9619
9620         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9621         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9622                 u32 nic_cfg, led_cfg;
9623                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9624                 int eeprom_phy_serdes = 0;
9625
9626                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9627                 tp->nic_sram_data_cfg = nic_cfg;
9628
9629                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9630                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9631                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9632                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9633                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9634                     (ver > 0) && (ver < 0x100))
9635                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9636
9637                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9638                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9639                         eeprom_phy_serdes = 1;
9640
9641                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9642                 if (nic_phy_id != 0) {
9643                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9644                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9645
9646                         eeprom_phy_id  = (id1 >> 16) << 10;
9647                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
9648                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
9649                 } else
9650                         eeprom_phy_id = 0;
9651
9652                 tp->phy_id = eeprom_phy_id;
9653                 if (eeprom_phy_serdes) {
9654                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9655                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9656                         else
9657                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9658                 }
9659
9660                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9661                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9662                                     SHASTA_EXT_LED_MODE_MASK);
9663                 else
9664                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9665
9666                 switch (led_cfg) {
9667                 default:
9668                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9669                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9670                         break;
9671
9672                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9673                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9674                         break;
9675
9676                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9677                         tp->led_ctrl = LED_CTRL_MODE_MAC;
9678
9679                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9680                          * read on some older 5700/5701 bootcode.
9681                          */
9682                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9683                             ASIC_REV_5700 ||
9684                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
9685                             ASIC_REV_5701)
9686                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9687
9688                         break;
9689
9690                 case SHASTA_EXT_LED_SHARED:
9691                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
9692                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9693                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9694                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9695                                                  LED_CTRL_MODE_PHY_2);
9696                         break;
9697
9698                 case SHASTA_EXT_LED_MAC:
9699                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9700                         break;
9701
9702                 case SHASTA_EXT_LED_COMBO:
9703                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
9704                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9705                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9706                                                  LED_CTRL_MODE_PHY_2);
9707                         break;
9708
9709                 };
9710
9711                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9712                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9713                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9714                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9715
9716                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9717                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9718                 else
9719                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9720
9721                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9722                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9723                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9724                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9725                 }
9726                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9727                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9728
9729                 if (cfg2 & (1 << 17))
9730                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9731
9732                 /* serdes signal pre-emphasis in register 0x590 set by */
9733                 /* bootcode if bit 18 is set */
9734                 if (cfg2 & (1 << 18))
9735                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9736         }
9737 }
9738
9739 static int __devinit tg3_phy_probe(struct tg3 *tp)
9740 {
9741         u32 hw_phy_id_1, hw_phy_id_2;
9742         u32 hw_phy_id, hw_phy_id_masked;
9743         int err;
9744
9745         /* Reading the PHY ID register can conflict with ASF
9746          * firwmare access to the PHY hardware.
9747          */
9748         err = 0;
9749         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9750                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9751         } else {
9752                 /* Now read the physical PHY_ID from the chip and verify
9753                  * that it is sane.  If it doesn't look good, we fall back
9754                  * to either the hard-coded table based PHY_ID and failing
9755                  * that the value found in the eeprom area.
9756                  */
9757                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9758                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9759
9760                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
9761                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9762                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
9763
9764                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9765         }
9766
9767         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9768                 tp->phy_id = hw_phy_id;
9769                 if (hw_phy_id_masked == PHY_ID_BCM8002)
9770                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9771                 else
9772                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9773         } else {
9774                 if (tp->phy_id != PHY_ID_INVALID) {
9775                         /* Do nothing, phy ID already set up in
9776                          * tg3_get_eeprom_hw_cfg().
9777                          */
9778                 } else {
9779                         struct subsys_tbl_ent *p;
9780
9781                         /* No eeprom signature?  Try the hardcoded
9782                          * subsys device table.
9783                          */
9784                         p = lookup_by_subsys(tp);
9785                         if (!p)
9786                                 return -ENODEV;
9787
9788                         tp->phy_id = p->phy_id;
9789                         if (!tp->phy_id ||
9790                             tp->phy_id == PHY_ID_BCM8002)
9791                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9792                 }
9793         }
9794
9795         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9796             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9797                 u32 bmsr, adv_reg, tg3_ctrl;
9798
9799                 tg3_readphy(tp, MII_BMSR, &bmsr);
9800                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9801                     (bmsr & BMSR_LSTATUS))
9802                         goto skip_phy_reset;
9803
9804                 err = tg3_phy_reset(tp);
9805                 if (err)
9806                         return err;
9807
9808                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9809                            ADVERTISE_100HALF | ADVERTISE_100FULL |
9810                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9811                 tg3_ctrl = 0;
9812                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9813                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9814                                     MII_TG3_CTRL_ADV_1000_FULL);
9815                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9816                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9817                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9818                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
9819                 }
9820
9821                 if (!tg3_copper_is_advertising_all(tp)) {
9822                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9823
9824                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9825                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9826
9827                         tg3_writephy(tp, MII_BMCR,
9828                                      BMCR_ANENABLE | BMCR_ANRESTART);
9829                 }
9830                 tg3_phy_set_wirespeed(tp);
9831
9832                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9833                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9834                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9835         }
9836
9837 skip_phy_reset:
9838         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9839                 err = tg3_init_5401phy_dsp(tp);
9840                 if (err)
9841                         return err;
9842         }
9843
9844         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9845                 err = tg3_init_5401phy_dsp(tp);
9846         }
9847
9848         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9849                 tp->link_config.advertising =
9850                         (ADVERTISED_1000baseT_Half |
9851                          ADVERTISED_1000baseT_Full |
9852                          ADVERTISED_Autoneg |
9853                          ADVERTISED_FIBRE);
9854         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9855                 tp->link_config.advertising &=
9856                         ~(ADVERTISED_1000baseT_Half |
9857                           ADVERTISED_1000baseT_Full);
9858
9859         return err;
9860 }
9861
9862 static void __devinit tg3_read_partno(struct tg3 *tp)
9863 {
9864         unsigned char vpd_data[256];
9865         int i;
9866         u32 magic;
9867
9868         if (tg3_nvram_read_swab(tp, 0x0, &magic))
9869                 goto out_not_found;
9870
9871         if (magic == TG3_EEPROM_MAGIC) {
9872                 for (i = 0; i < 256; i += 4) {
9873                         u32 tmp;
9874
9875                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9876                                 goto out_not_found;
9877
9878                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
9879                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
9880                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9881                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9882                 }
9883         } else {
9884                 int vpd_cap;
9885
9886                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
9887                 for (i = 0; i < 256; i += 4) {
9888                         u32 tmp, j = 0;
9889                         u16 tmp16;
9890
9891                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
9892                                               i);
9893                         while (j++ < 100) {
9894                                 pci_read_config_word(tp->pdev, vpd_cap +
9895                                                      PCI_VPD_ADDR, &tmp16);
9896                                 if (tmp16 & 0x8000)
9897                                         break;
9898                                 msleep(1);
9899                         }
9900                         if (!(tmp16 & 0x8000))
9901                                 goto out_not_found;
9902
9903                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9904                                               &tmp);
9905                         tmp = cpu_to_le32(tmp);
9906                         memcpy(&vpd_data[i], &tmp, 4);
9907                 }
9908         }
9909
9910         /* Now parse and find the part number. */
9911         for (i = 0; i < 256; ) {
9912                 unsigned char val = vpd_data[i];
9913                 int block_end;
9914
9915                 if (val == 0x82 || val == 0x91) {
9916                         i = (i + 3 +
9917                              (vpd_data[i + 1] +
9918                               (vpd_data[i + 2] << 8)));
9919                         continue;
9920                 }
9921
9922                 if (val != 0x90)
9923                         goto out_not_found;
9924
9925                 block_end = (i + 3 +
9926                              (vpd_data[i + 1] +
9927                               (vpd_data[i + 2] << 8)));
9928                 i += 3;
9929                 while (i < block_end) {
9930                         if (vpd_data[i + 0] == 'P' &&
9931                             vpd_data[i + 1] == 'N') {
9932                                 int partno_len = vpd_data[i + 2];
9933
9934                                 if (partno_len > 24)
9935                                         goto out_not_found;
9936
9937                                 memcpy(tp->board_part_number,
9938                                        &vpd_data[i + 3],
9939                                        partno_len);
9940
9941                                 /* Success. */
9942                                 return;
9943                         }
9944                 }
9945
9946                 /* Part number not found. */
9947                 goto out_not_found;
9948         }
9949
9950 out_not_found:
9951         strcpy(tp->board_part_number, "none");
9952 }
9953
9954 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9955 {
9956         u32 val, offset, start;
9957
9958         if (tg3_nvram_read_swab(tp, 0, &val))
9959                 return;
9960
9961         if (val != TG3_EEPROM_MAGIC)
9962                 return;
9963
9964         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
9965             tg3_nvram_read_swab(tp, 0x4, &start))
9966                 return;
9967
9968         offset = tg3_nvram_logical_addr(tp, offset);
9969         if (tg3_nvram_read_swab(tp, offset, &val))
9970                 return;
9971
9972         if ((val & 0xfc000000) == 0x0c000000) {
9973                 u32 ver_offset, addr;
9974                 int i;
9975
9976                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
9977                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
9978                         return;
9979
9980                 if (val != 0)
9981                         return;
9982
9983                 addr = offset + ver_offset - start;
9984                 for (i = 0; i < 16; i += 4) {
9985                         if (tg3_nvram_read(tp, addr + i, &val))
9986                                 return;
9987
9988                         val = cpu_to_le32(val);
9989                         memcpy(tp->fw_ver + i, &val, 4);
9990                 }
9991         }
9992 }
9993
9994 static int __devinit tg3_get_invariants(struct tg3 *tp)
9995 {
9996         static struct pci_device_id write_reorder_chipsets[] = {
9997                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9998                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9999                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10000                              PCI_DEVICE_ID_VIA_8385_0) },
10001                 { },
10002         };
10003         u32 misc_ctrl_reg;
10004         u32 cacheline_sz_reg;
10005         u32 pci_state_reg, grc_misc_cfg;
10006         u32 val;
10007         u16 pci_cmd;
10008         int err;
10009
10010         /* Force memory write invalidate off.  If we leave it on,
10011          * then on 5700_BX chips we have to enable a workaround.
10012          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10013          * to match the cacheline size.  The Broadcom driver have this
10014          * workaround but turns MWI off all the times so never uses
10015          * it.  This seems to suggest that the workaround is insufficient.
10016          */
10017         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10018         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10019         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10020
10021         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10022          * has the register indirect write enable bit set before
10023          * we try to access any of the MMIO registers.  It is also
10024          * critical that the PCI-X hw workaround situation is decided
10025          * before that as well.
10026          */
10027         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10028                               &misc_ctrl_reg);
10029
10030         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10031                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10032
10033         /* Wrong chip ID in 5752 A0. This code can be removed later
10034          * as A0 is not in production.
10035          */
10036         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10037                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10038
10039         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10040          * we need to disable memory and use config. cycles
10041          * only to access all registers. The 5702/03 chips
10042          * can mistakenly decode the special cycles from the
10043          * ICH chipsets as memory write cycles, causing corruption
10044          * of register and memory space. Only certain ICH bridges
10045          * will drive special cycles with non-zero data during the
10046          * address phase which can fall within the 5703's address
10047          * range. This is not an ICH bug as the PCI spec allows
10048          * non-zero address during special cycles. However, only
10049          * these ICH bridges are known to drive non-zero addresses
10050          * during special cycles.
10051          *
10052          * Since special cycles do not cross PCI bridges, we only
10053          * enable this workaround if the 5703 is on the secondary
10054          * bus of these ICH bridges.
10055          */
10056         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10057             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10058                 static struct tg3_dev_id {
10059                         u32     vendor;
10060                         u32     device;
10061                         u32     rev;
10062                 } ich_chipsets[] = {
10063                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10064                           PCI_ANY_ID },
10065                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10066                           PCI_ANY_ID },
10067                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10068                           0xa },
10069                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10070                           PCI_ANY_ID },
10071                         { },
10072                 };
10073                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10074                 struct pci_dev *bridge = NULL;
10075
10076                 while (pci_id->vendor != 0) {
10077                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10078                                                 bridge);
10079                         if (!bridge) {
10080                                 pci_id++;
10081                                 continue;
10082                         }
10083                         if (pci_id->rev != PCI_ANY_ID) {
10084                                 u8 rev;
10085
10086                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10087                                                      &rev);
10088                                 if (rev > pci_id->rev)
10089                                         continue;
10090                         }
10091                         if (bridge->subordinate &&
10092                             (bridge->subordinate->number ==
10093                              tp->pdev->bus->number)) {
10094
10095                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10096                                 pci_dev_put(bridge);
10097                                 break;
10098                         }
10099                 }
10100         }
10101
10102         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10103          * DMA addresses > 40-bit. This bridge may have other additional
10104          * 57xx devices behind it in some 4-port NIC designs for example.
10105          * Any tg3 device found behind the bridge will also need the 40-bit
10106          * DMA workaround.
10107          */
10108         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10109             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10110                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10111                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10112                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10113         }
10114         else {
10115                 struct pci_dev *bridge = NULL;
10116
10117                 do {
10118                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10119                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10120                                                 bridge);
10121                         if (bridge && bridge->subordinate &&
10122                             (bridge->subordinate->number <=
10123                              tp->pdev->bus->number) &&
10124                             (bridge->subordinate->subordinate >=
10125                              tp->pdev->bus->number)) {
10126                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10127                                 pci_dev_put(bridge);
10128                                 break;
10129                         }
10130                 } while (bridge);
10131         }
10132
10133         /* Initialize misc host control in PCI block. */
10134         tp->misc_host_ctrl |= (misc_ctrl_reg &
10135                                MISC_HOST_CTRL_CHIPREV);
10136         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10137                                tp->misc_host_ctrl);
10138
10139         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10140                               &cacheline_sz_reg);
10141
10142         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10143         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10144         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10145         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10146
10147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10148             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10149             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10150             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10151             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10152                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10153
10154         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10155             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10156                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10157
10158         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10159                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10160                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10161                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10162                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10163                 } else
10164                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
10165         }
10166
10167         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10168             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10169             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10170             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10171             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
10172                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10173
10174         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10175                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10176
10177         /* If we have an AMD 762 or VIA K8T800 chipset, write
10178          * reordering to the mailbox registers done by the host
10179          * controller can cause major troubles.  We read back from
10180          * every mailbox register write to force the writes to be
10181          * posted to the chip in order.
10182          */
10183         if (pci_dev_present(write_reorder_chipsets) &&
10184             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10185                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10186
10187         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10188             tp->pci_lat_timer < 64) {
10189                 tp->pci_lat_timer = 64;
10190
10191                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10192                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10193                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10194                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10195
10196                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10197                                        cacheline_sz_reg);
10198         }
10199
10200         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10201                               &pci_state_reg);
10202
10203         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10204                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10205
10206                 /* If this is a 5700 BX chipset, and we are in PCI-X
10207                  * mode, enable register write workaround.
10208                  *
10209                  * The workaround is to use indirect register accesses
10210                  * for all chip writes not to mailbox registers.
10211                  */
10212                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10213                         u32 pm_reg;
10214                         u16 pci_cmd;
10215
10216                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10217
10218                         /* The chip can have it's power management PCI config
10219                          * space registers clobbered due to this bug.
10220                          * So explicitly force the chip into D0 here.
10221                          */
10222                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10223                                               &pm_reg);
10224                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10225                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10226                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10227                                                pm_reg);
10228
10229                         /* Also, force SERR#/PERR# in PCI command. */
10230                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10231                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10232                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10233                 }
10234         }
10235
10236         /* 5700 BX chips need to have their TX producer index mailboxes
10237          * written twice to workaround a bug.
10238          */
10239         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10240                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10241
10242         /* Back to back register writes can cause problems on this chip,
10243          * the workaround is to read back all reg writes except those to
10244          * mailbox regs.  See tg3_write_indirect_reg32().
10245          *
10246          * PCI Express 5750_A0 rev chips need this workaround too.
10247          */
10248         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10249             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10250              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10251                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10252
10253         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10254                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10255         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10256                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10257
10258         /* Chip-specific fixup from Broadcom driver */
10259         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10260             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10261                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10262                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10263         }
10264
10265         /* Default fast path register access methods */
10266         tp->read32 = tg3_read32;
10267         tp->write32 = tg3_write32;
10268         tp->read32_mbox = tg3_read32;
10269         tp->write32_mbox = tg3_write32;
10270         tp->write32_tx_mbox = tg3_write32;
10271         tp->write32_rx_mbox = tg3_write32;
10272
10273         /* Various workaround register access methods */
10274         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10275                 tp->write32 = tg3_write_indirect_reg32;
10276         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10277                 tp->write32 = tg3_write_flush_reg32;
10278
10279         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10280             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10281                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10282                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10283                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10284         }
10285
10286         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10287                 tp->read32 = tg3_read_indirect_reg32;
10288                 tp->write32 = tg3_write_indirect_reg32;
10289                 tp->read32_mbox = tg3_read_indirect_mbox;
10290                 tp->write32_mbox = tg3_write_indirect_mbox;
10291                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10292                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10293
10294                 iounmap(tp->regs);
10295                 tp->regs = NULL;
10296
10297                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10298                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10299                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10300         }
10301
10302         if (tp->write32 == tg3_write_indirect_reg32 ||
10303             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10304              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10305               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10306                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10307
10308         /* Get eeprom hw config before calling tg3_set_power_state().
10309          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10310          * determined before calling tg3_set_power_state() so that
10311          * we know whether or not to switch out of Vaux power.
10312          * When the flag is set, it means that GPIO1 is used for eeprom
10313          * write protect and also implies that it is a LOM where GPIOs
10314          * are not used to switch power.
10315          */
10316         tg3_get_eeprom_hw_cfg(tp);
10317
10318         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10319          * GPIO1 driven high will bring 5700's external PHY out of reset.
10320          * It is also used as eeprom write protect on LOMs.
10321          */
10322         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10323         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10324             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10325                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10326                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10327         /* Unused GPIO3 must be driven as output on 5752 because there
10328          * are no pull-up resistors on unused GPIO pins.
10329          */
10330         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10331                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10332
10333         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10334                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10335
10336         /* Force the chip into D0. */
10337         err = tg3_set_power_state(tp, PCI_D0);
10338         if (err) {
10339                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10340                        pci_name(tp->pdev));
10341                 return err;
10342         }
10343
10344         /* 5700 B0 chips do not support checksumming correctly due
10345          * to hardware bugs.
10346          */
10347         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10348                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10349
10350         /* Derive initial jumbo mode from MTU assigned in
10351          * ether_setup() via the alloc_etherdev() call
10352          */
10353         if (tp->dev->mtu > ETH_DATA_LEN &&
10354             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10355                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10356
10357         /* Determine WakeOnLan speed to use. */
10358         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10359             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10360             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10361             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10362                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10363         } else {
10364                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10365         }
10366
10367         /* A few boards don't want Ethernet@WireSpeed phy feature */
10368         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10369             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10370              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10371              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10372             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10373                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10374
10375         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10376             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10377                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10378         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10379                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10380
10381         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10382                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10383                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10384                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10385                 else
10386                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10387         }
10388
10389         tp->coalesce_mode = 0;
10390         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10391             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10392                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10393
10394         /* Initialize MAC MI mode, polling disabled. */
10395         tw32_f(MAC_MI_MODE, tp->mi_mode);
10396         udelay(80);
10397
10398         /* Initialize data/descriptor byte/word swapping. */
10399         val = tr32(GRC_MODE);
10400         val &= GRC_MODE_HOST_STACKUP;
10401         tw32(GRC_MODE, val | tp->grc_mode);
10402
10403         tg3_switch_clocks(tp);
10404
10405         /* Clear this out for sanity. */
10406         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10407
10408         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10409                               &pci_state_reg);
10410         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10411             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10412                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10413
10414                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10415                     chiprevid == CHIPREV_ID_5701_B0 ||
10416                     chiprevid == CHIPREV_ID_5701_B2 ||
10417                     chiprevid == CHIPREV_ID_5701_B5) {
10418                         void __iomem *sram_base;
10419
10420                         /* Write some dummy words into the SRAM status block
10421                          * area, see if it reads back correctly.  If the return
10422                          * value is bad, force enable the PCIX workaround.
10423                          */
10424                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10425
10426                         writel(0x00000000, sram_base);
10427                         writel(0x00000000, sram_base + 4);
10428                         writel(0xffffffff, sram_base + 4);
10429                         if (readl(sram_base) != 0x00000000)
10430                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10431                 }
10432         }
10433
10434         udelay(50);
10435         tg3_nvram_init(tp);
10436
10437         grc_misc_cfg = tr32(GRC_MISC_CFG);
10438         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10439
10440         /* Broadcom's driver says that CIOBE multisplit has a bug */
10441 #if 0
10442         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10443             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10444                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10445                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10446         }
10447 #endif
10448         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10449             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10450              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10451                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10452
10453         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10454             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10455                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10456         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10457                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10458                                       HOSTCC_MODE_CLRTICK_TXBD);
10459
10460                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10461                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10462                                        tp->misc_host_ctrl);
10463         }
10464
10465         /* these are limited to 10/100 only */
10466         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10467              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10468             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10469              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10470              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10471               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10472               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10473             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10474              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10475               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10476                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10477
10478         err = tg3_phy_probe(tp);
10479         if (err) {
10480                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10481                        pci_name(tp->pdev), err);
10482                 /* ... but do not return immediately ... */
10483         }
10484
10485         tg3_read_partno(tp);
10486         tg3_read_fw_ver(tp);
10487
10488         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10489                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10490         } else {
10491                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10492                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10493                 else
10494                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10495         }
10496
10497         /* 5700 {AX,BX} chips have a broken status block link
10498          * change bit implementation, so we must use the
10499          * status register in those cases.
10500          */
10501         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10502                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10503         else
10504                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10505
10506         /* The led_ctrl is set during tg3_phy_probe, here we might
10507          * have to force the link status polling mechanism based
10508          * upon subsystem IDs.
10509          */
10510         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10511             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10512                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10513                                   TG3_FLAG_USE_LINKCHG_REG);
10514         }
10515
10516         /* For all SERDES we poll the MAC status register. */
10517         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10518                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10519         else
10520                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10521
10522         /* All chips before 5787 can get confused if TX buffers
10523          * straddle the 4GB address boundary in some cases.
10524          */
10525         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10526             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10527                 tp->dev->hard_start_xmit = tg3_start_xmit;
10528         else
10529                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10530
10531         tp->rx_offset = 2;
10532         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10533             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10534                 tp->rx_offset = 0;
10535
10536         /* By default, disable wake-on-lan.  User can change this
10537          * using ETHTOOL_SWOL.
10538          */
10539         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10540
10541         return err;
10542 }
10543
10544 #ifdef CONFIG_SPARC64
10545 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10546 {
10547         struct net_device *dev = tp->dev;
10548         struct pci_dev *pdev = tp->pdev;
10549         struct pcidev_cookie *pcp = pdev->sysdata;
10550
10551         if (pcp != NULL) {
10552                 int node = pcp->prom_node;
10553
10554                 if (prom_getproplen(node, "local-mac-address") == 6) {
10555                         prom_getproperty(node, "local-mac-address",
10556                                          dev->dev_addr, 6);
10557                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10558                         return 0;
10559                 }
10560         }
10561         return -ENODEV;
10562 }
10563
10564 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10565 {
10566         struct net_device *dev = tp->dev;
10567
10568         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10569         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10570         return 0;
10571 }
10572 #endif
10573
10574 static int __devinit tg3_get_device_address(struct tg3 *tp)
10575 {
10576         struct net_device *dev = tp->dev;
10577         u32 hi, lo, mac_offset;
10578         int addr_ok = 0;
10579
10580 #ifdef CONFIG_SPARC64
10581         if (!tg3_get_macaddr_sparc(tp))
10582                 return 0;
10583 #endif
10584
10585         mac_offset = 0x7c;
10586         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10587             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10588                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10589                         mac_offset = 0xcc;
10590                 if (tg3_nvram_lock(tp))
10591                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10592                 else
10593                         tg3_nvram_unlock(tp);
10594         }
10595
10596         /* First try to get it from MAC address mailbox. */
10597         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10598         if ((hi >> 16) == 0x484b) {
10599                 dev->dev_addr[0] = (hi >>  8) & 0xff;
10600                 dev->dev_addr[1] = (hi >>  0) & 0xff;
10601
10602                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10603                 dev->dev_addr[2] = (lo >> 24) & 0xff;
10604                 dev->dev_addr[3] = (lo >> 16) & 0xff;
10605                 dev->dev_addr[4] = (lo >>  8) & 0xff;
10606                 dev->dev_addr[5] = (lo >>  0) & 0xff;
10607
10608                 /* Some old bootcode may report a 0 MAC address in SRAM */
10609                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10610         }
10611         if (!addr_ok) {
10612                 /* Next, try NVRAM. */
10613                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10614                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10615                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
10616                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
10617                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
10618                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
10619                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
10620                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
10621                 }
10622                 /* Finally just fetch it out of the MAC control regs. */
10623                 else {
10624                         hi = tr32(MAC_ADDR_0_HIGH);
10625                         lo = tr32(MAC_ADDR_0_LOW);
10626
10627                         dev->dev_addr[5] = lo & 0xff;
10628                         dev->dev_addr[4] = (lo >> 8) & 0xff;
10629                         dev->dev_addr[3] = (lo >> 16) & 0xff;
10630                         dev->dev_addr[2] = (lo >> 24) & 0xff;
10631                         dev->dev_addr[1] = hi & 0xff;
10632                         dev->dev_addr[0] = (hi >> 8) & 0xff;
10633                 }
10634         }
10635
10636         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
10637 #ifdef CONFIG_SPARC64
10638                 if (!tg3_get_default_macaddr_sparc(tp))
10639                         return 0;
10640 #endif
10641                 return -EINVAL;
10642         }
10643         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
10644         return 0;
10645 }
10646
10647 #define BOUNDARY_SINGLE_CACHELINE       1
10648 #define BOUNDARY_MULTI_CACHELINE        2
10649
10650 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10651 {
10652         int cacheline_size;
10653         u8 byte;
10654         int goal;
10655
10656         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10657         if (byte == 0)
10658                 cacheline_size = 1024;
10659         else
10660                 cacheline_size = (int) byte * 4;
10661
10662         /* On 5703 and later chips, the boundary bits have no
10663          * effect.
10664          */
10665         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10666             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10667             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10668                 goto out;
10669
10670 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10671         goal = BOUNDARY_MULTI_CACHELINE;
10672 #else
10673 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10674         goal = BOUNDARY_SINGLE_CACHELINE;
10675 #else
10676         goal = 0;
10677 #endif
10678 #endif
10679
10680         if (!goal)
10681                 goto out;
10682
10683         /* PCI controllers on most RISC systems tend to disconnect
10684          * when a device tries to burst across a cache-line boundary.
10685          * Therefore, letting tg3 do so just wastes PCI bandwidth.
10686          *
10687          * Unfortunately, for PCI-E there are only limited
10688          * write-side controls for this, and thus for reads
10689          * we will still get the disconnects.  We'll also waste
10690          * these PCI cycles for both read and write for chips
10691          * other than 5700 and 5701 which do not implement the
10692          * boundary bits.
10693          */
10694         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10695             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10696                 switch (cacheline_size) {
10697                 case 16:
10698                 case 32:
10699                 case 64:
10700                 case 128:
10701                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10702                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10703                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10704                         } else {
10705                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10706                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10707                         }
10708                         break;
10709
10710                 case 256:
10711                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10712                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10713                         break;
10714
10715                 default:
10716                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10717                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10718                         break;
10719                 };
10720         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10721                 switch (cacheline_size) {
10722                 case 16:
10723                 case 32:
10724                 case 64:
10725                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10726                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10727                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10728                                 break;
10729                         }
10730                         /* fallthrough */
10731                 case 128:
10732                 default:
10733                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10734                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10735                         break;
10736                 };
10737         } else {
10738                 switch (cacheline_size) {
10739                 case 16:
10740                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10741                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10742                                         DMA_RWCTRL_WRITE_BNDRY_16);
10743                                 break;
10744                         }
10745                         /* fallthrough */
10746                 case 32:
10747                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10748                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10749                                         DMA_RWCTRL_WRITE_BNDRY_32);
10750                                 break;
10751                         }
10752                         /* fallthrough */
10753                 case 64:
10754                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10755                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10756                                         DMA_RWCTRL_WRITE_BNDRY_64);
10757                                 break;
10758                         }
10759                         /* fallthrough */
10760                 case 128:
10761                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10762                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10763                                         DMA_RWCTRL_WRITE_BNDRY_128);
10764                                 break;
10765                         }
10766                         /* fallthrough */
10767                 case 256:
10768                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
10769                                 DMA_RWCTRL_WRITE_BNDRY_256);
10770                         break;
10771                 case 512:
10772                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
10773                                 DMA_RWCTRL_WRITE_BNDRY_512);
10774                         break;
10775                 case 1024:
10776                 default:
10777                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10778                                 DMA_RWCTRL_WRITE_BNDRY_1024);
10779                         break;
10780                 };
10781         }
10782
10783 out:
10784         return val;
10785 }
10786
10787 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10788 {
10789         struct tg3_internal_buffer_desc test_desc;
10790         u32 sram_dma_descs;
10791         int i, ret;
10792
10793         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10794
10795         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10796         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10797         tw32(RDMAC_STATUS, 0);
10798         tw32(WDMAC_STATUS, 0);
10799
10800         tw32(BUFMGR_MODE, 0);
10801         tw32(FTQ_RESET, 0);
10802
10803         test_desc.addr_hi = ((u64) buf_dma) >> 32;
10804         test_desc.addr_lo = buf_dma & 0xffffffff;
10805         test_desc.nic_mbuf = 0x00002100;
10806         test_desc.len = size;
10807
10808         /*
10809          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10810          * the *second* time the tg3 driver was getting loaded after an
10811          * initial scan.
10812          *
10813          * Broadcom tells me:
10814          *   ...the DMA engine is connected to the GRC block and a DMA
10815          *   reset may affect the GRC block in some unpredictable way...
10816          *   The behavior of resets to individual blocks has not been tested.
10817          *
10818          * Broadcom noted the GRC reset will also reset all sub-components.
10819          */
10820         if (to_device) {
10821                 test_desc.cqid_sqid = (13 << 8) | 2;
10822
10823                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10824                 udelay(40);
10825         } else {
10826                 test_desc.cqid_sqid = (16 << 8) | 7;
10827
10828                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10829                 udelay(40);
10830         }
10831         test_desc.flags = 0x00000005;
10832
10833         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10834                 u32 val;
10835
10836                 val = *(((u32 *)&test_desc) + i);
10837                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10838                                        sram_dma_descs + (i * sizeof(u32)));
10839                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10840         }
10841         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10842
10843         if (to_device) {
10844                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10845         } else {
10846                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10847         }
10848
10849         ret = -ENODEV;
10850         for (i = 0; i < 40; i++) {
10851                 u32 val;
10852
10853                 if (to_device)
10854                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10855                 else
10856                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10857                 if ((val & 0xffff) == sram_dma_descs) {
10858                         ret = 0;
10859                         break;
10860                 }
10861
10862                 udelay(100);
10863         }
10864
10865         return ret;
10866 }
10867
10868 #define TEST_BUFFER_SIZE        0x2000
10869
10870 static int __devinit tg3_test_dma(struct tg3 *tp)
10871 {
10872         dma_addr_t buf_dma;
10873         u32 *buf, saved_dma_rwctrl;
10874         int ret;
10875
10876         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10877         if (!buf) {
10878                 ret = -ENOMEM;
10879                 goto out_nofree;
10880         }
10881
10882         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10883                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10884
10885         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10886
10887         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10888                 /* DMA read watermark not used on PCIE */
10889                 tp->dma_rwctrl |= 0x00180000;
10890         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10891                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10892                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10893                         tp->dma_rwctrl |= 0x003f0000;
10894                 else
10895                         tp->dma_rwctrl |= 0x003f000f;
10896         } else {
10897                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10898                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10899                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10900
10901                         /* If the 5704 is behind the EPB bridge, we can
10902                          * do the less restrictive ONE_DMA workaround for
10903                          * better performance.
10904                          */
10905                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
10906                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10907                                 tp->dma_rwctrl |= 0x8000;
10908                         else if (ccval == 0x6 || ccval == 0x7)
10909                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10910
10911                         /* Set bit 23 to enable PCIX hw bug fix */
10912                         tp->dma_rwctrl |= 0x009f0000;
10913                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10914                         /* 5780 always in PCIX mode */
10915                         tp->dma_rwctrl |= 0x00144000;
10916                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10917                         /* 5714 always in PCIX mode */
10918                         tp->dma_rwctrl |= 0x00148000;
10919                 } else {
10920                         tp->dma_rwctrl |= 0x001b000f;
10921                 }
10922         }
10923
10924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10925             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10926                 tp->dma_rwctrl &= 0xfffffff0;
10927
10928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10930                 /* Remove this if it causes problems for some boards. */
10931                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10932
10933                 /* On 5700/5701 chips, we need to set this bit.
10934                  * Otherwise the chip will issue cacheline transactions
10935                  * to streamable DMA memory with not all the byte
10936                  * enables turned on.  This is an error on several
10937                  * RISC PCI controllers, in particular sparc64.
10938                  *
10939                  * On 5703/5704 chips, this bit has been reassigned
10940                  * a different meaning.  In particular, it is used
10941                  * on those chips to enable a PCI-X workaround.
10942                  */
10943                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10944         }
10945
10946         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10947
10948 #if 0
10949         /* Unneeded, already done by tg3_get_invariants.  */
10950         tg3_switch_clocks(tp);
10951 #endif
10952
10953         ret = 0;
10954         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10955             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10956                 goto out;
10957
10958         /* It is best to perform DMA test with maximum write burst size
10959          * to expose the 5700/5701 write DMA bug.
10960          */
10961         saved_dma_rwctrl = tp->dma_rwctrl;
10962         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10963         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10964
10965         while (1) {
10966                 u32 *p = buf, i;
10967
10968                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10969                         p[i] = i;
10970
10971                 /* Send the buffer to the chip. */
10972                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10973                 if (ret) {
10974                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10975                         break;
10976                 }
10977
10978 #if 0
10979                 /* validate data reached card RAM correctly. */
10980                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10981                         u32 val;
10982                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
10983                         if (le32_to_cpu(val) != p[i]) {
10984                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
10985                                 /* ret = -ENODEV here? */
10986                         }
10987                         p[i] = 0;
10988                 }
10989 #endif
10990                 /* Now read it back. */
10991                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10992                 if (ret) {
10993                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10994
10995                         break;
10996                 }
10997
10998                 /* Verify it. */
10999                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11000                         if (p[i] == i)
11001                                 continue;
11002
11003                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11004                             DMA_RWCTRL_WRITE_BNDRY_16) {
11005                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11006                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11007                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11008                                 break;
11009                         } else {
11010                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11011                                 ret = -ENODEV;
11012                                 goto out;
11013                         }
11014                 }
11015
11016                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11017                         /* Success. */
11018                         ret = 0;
11019                         break;
11020                 }
11021         }
11022         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11023             DMA_RWCTRL_WRITE_BNDRY_16) {
11024                 static struct pci_device_id dma_wait_state_chipsets[] = {
11025                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11026                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11027                         { },
11028                 };
11029
11030                 /* DMA test passed without adjusting DMA boundary,
11031                  * now look for chipsets that are known to expose the
11032                  * DMA bug without failing the test.
11033                  */
11034                 if (pci_dev_present(dma_wait_state_chipsets)) {
11035                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11036                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11037                 }
11038                 else
11039                         /* Safe to use the calculated DMA boundary. */
11040                         tp->dma_rwctrl = saved_dma_rwctrl;
11041
11042                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11043         }
11044
11045 out:
11046         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11047 out_nofree:
11048         return ret;
11049 }
11050
11051 static void __devinit tg3_init_link_config(struct tg3 *tp)
11052 {
11053         tp->link_config.advertising =
11054                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11055                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11056                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11057                  ADVERTISED_Autoneg | ADVERTISED_MII);
11058         tp->link_config.speed = SPEED_INVALID;
11059         tp->link_config.duplex = DUPLEX_INVALID;
11060         tp->link_config.autoneg = AUTONEG_ENABLE;
11061         tp->link_config.active_speed = SPEED_INVALID;
11062         tp->link_config.active_duplex = DUPLEX_INVALID;
11063         tp->link_config.phy_is_low_power = 0;
11064         tp->link_config.orig_speed = SPEED_INVALID;
11065         tp->link_config.orig_duplex = DUPLEX_INVALID;
11066         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11067 }
11068
11069 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11070 {
11071         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11072                 tp->bufmgr_config.mbuf_read_dma_low_water =
11073                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11074                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11075                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11076                 tp->bufmgr_config.mbuf_high_water =
11077                         DEFAULT_MB_HIGH_WATER_5705;
11078
11079                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11080                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11081                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11082                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11083                 tp->bufmgr_config.mbuf_high_water_jumbo =
11084                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11085         } else {
11086                 tp->bufmgr_config.mbuf_read_dma_low_water =
11087                         DEFAULT_MB_RDMA_LOW_WATER;
11088                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11089                         DEFAULT_MB_MACRX_LOW_WATER;
11090                 tp->bufmgr_config.mbuf_high_water =
11091                         DEFAULT_MB_HIGH_WATER;
11092
11093                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11094                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11095                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11096                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11097                 tp->bufmgr_config.mbuf_high_water_jumbo =
11098                         DEFAULT_MB_HIGH_WATER_JUMBO;
11099         }
11100
11101         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11102         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11103 }
11104
11105 static char * __devinit tg3_phy_string(struct tg3 *tp)
11106 {
11107         switch (tp->phy_id & PHY_ID_MASK) {
11108         case PHY_ID_BCM5400:    return "5400";
11109         case PHY_ID_BCM5401:    return "5401";
11110         case PHY_ID_BCM5411:    return "5411";
11111         case PHY_ID_BCM5701:    return "5701";
11112         case PHY_ID_BCM5703:    return "5703";
11113         case PHY_ID_BCM5704:    return "5704";
11114         case PHY_ID_BCM5705:    return "5705";
11115         case PHY_ID_BCM5750:    return "5750";
11116         case PHY_ID_BCM5752:    return "5752";
11117         case PHY_ID_BCM5714:    return "5714";
11118         case PHY_ID_BCM5780:    return "5780";
11119         case PHY_ID_BCM5755:    return "5755";
11120         case PHY_ID_BCM5787:    return "5787";
11121         case PHY_ID_BCM8002:    return "8002/serdes";
11122         case 0:                 return "serdes";
11123         default:                return "unknown";
11124         };
11125 }
11126
11127 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11128 {
11129         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11130                 strcpy(str, "PCI Express");
11131                 return str;
11132         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11133                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11134
11135                 strcpy(str, "PCIX:");
11136
11137                 if ((clock_ctrl == 7) ||
11138                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11139                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11140                         strcat(str, "133MHz");
11141                 else if (clock_ctrl == 0)
11142                         strcat(str, "33MHz");
11143                 else if (clock_ctrl == 2)
11144                         strcat(str, "50MHz");
11145                 else if (clock_ctrl == 4)
11146                         strcat(str, "66MHz");
11147                 else if (clock_ctrl == 6)
11148                         strcat(str, "100MHz");
11149         } else {
11150                 strcpy(str, "PCI:");
11151                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11152                         strcat(str, "66MHz");
11153                 else
11154                         strcat(str, "33MHz");
11155         }
11156         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11157                 strcat(str, ":32-bit");
11158         else
11159                 strcat(str, ":64-bit");
11160         return str;
11161 }
11162
11163 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11164 {
11165         struct pci_dev *peer;
11166         unsigned int func, devnr = tp->pdev->devfn & ~7;
11167
11168         for (func = 0; func < 8; func++) {
11169                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11170                 if (peer && peer != tp->pdev)
11171                         break;
11172                 pci_dev_put(peer);
11173         }
11174         /* 5704 can be configured in single-port mode, set peer to
11175          * tp->pdev in that case.
11176          */
11177         if (!peer) {
11178                 peer = tp->pdev;
11179                 return peer;
11180         }
11181
11182         /*
11183          * We don't need to keep the refcount elevated; there's no way
11184          * to remove one half of this device without removing the other
11185          */
11186         pci_dev_put(peer);
11187
11188         return peer;
11189 }
11190
11191 static void __devinit tg3_init_coal(struct tg3 *tp)
11192 {
11193         struct ethtool_coalesce *ec = &tp->coal;
11194
11195         memset(ec, 0, sizeof(*ec));
11196         ec->cmd = ETHTOOL_GCOALESCE;
11197         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11198         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11199         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11200         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11201         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11202         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11203         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11204         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11205         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11206
11207         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11208                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11209                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11210                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11211                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11212                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11213         }
11214
11215         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11216                 ec->rx_coalesce_usecs_irq = 0;
11217                 ec->tx_coalesce_usecs_irq = 0;
11218                 ec->stats_block_coalesce_usecs = 0;
11219         }
11220 }
11221
11222 static int __devinit tg3_init_one(struct pci_dev *pdev,
11223                                   const struct pci_device_id *ent)
11224 {
11225         static int tg3_version_printed = 0;
11226         unsigned long tg3reg_base, tg3reg_len;
11227         struct net_device *dev;
11228         struct tg3 *tp;
11229         int i, err, pm_cap;
11230         char str[40];
11231         u64 dma_mask, persist_dma_mask;
11232
11233         if (tg3_version_printed++ == 0)
11234                 printk(KERN_INFO "%s", version);
11235
11236         err = pci_enable_device(pdev);
11237         if (err) {
11238                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11239                        "aborting.\n");
11240                 return err;
11241         }
11242
11243         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11244                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11245                        "base address, aborting.\n");
11246                 err = -ENODEV;
11247                 goto err_out_disable_pdev;
11248         }
11249
11250         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11251         if (err) {
11252                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11253                        "aborting.\n");
11254                 goto err_out_disable_pdev;
11255         }
11256
11257         pci_set_master(pdev);
11258
11259         /* Find power-management capability. */
11260         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11261         if (pm_cap == 0) {
11262                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11263                        "aborting.\n");
11264                 err = -EIO;
11265                 goto err_out_free_res;
11266         }
11267
11268         tg3reg_base = pci_resource_start(pdev, 0);
11269         tg3reg_len = pci_resource_len(pdev, 0);
11270
11271         dev = alloc_etherdev(sizeof(*tp));
11272         if (!dev) {
11273                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11274                 err = -ENOMEM;
11275                 goto err_out_free_res;
11276         }
11277
11278         SET_MODULE_OWNER(dev);
11279         SET_NETDEV_DEV(dev, &pdev->dev);
11280
11281 #if TG3_VLAN_TAG_USED
11282         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11283         dev->vlan_rx_register = tg3_vlan_rx_register;
11284         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11285 #endif
11286
11287         tp = netdev_priv(dev);
11288         tp->pdev = pdev;
11289         tp->dev = dev;
11290         tp->pm_cap = pm_cap;
11291         tp->mac_mode = TG3_DEF_MAC_MODE;
11292         tp->rx_mode = TG3_DEF_RX_MODE;
11293         tp->tx_mode = TG3_DEF_TX_MODE;
11294         tp->mi_mode = MAC_MI_MODE_BASE;
11295         if (tg3_debug > 0)
11296                 tp->msg_enable = tg3_debug;
11297         else
11298                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11299
11300         /* The word/byte swap controls here control register access byte
11301          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11302          * setting below.
11303          */
11304         tp->misc_host_ctrl =
11305                 MISC_HOST_CTRL_MASK_PCI_INT |
11306                 MISC_HOST_CTRL_WORD_SWAP |
11307                 MISC_HOST_CTRL_INDIR_ACCESS |
11308                 MISC_HOST_CTRL_PCISTATE_RW;
11309
11310         /* The NONFRM (non-frame) byte/word swap controls take effect
11311          * on descriptor entries, anything which isn't packet data.
11312          *
11313          * The StrongARM chips on the board (one for tx, one for rx)
11314          * are running in big-endian mode.
11315          */
11316         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11317                         GRC_MODE_WSWAP_NONFRM_DATA);
11318 #ifdef __BIG_ENDIAN
11319         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11320 #endif
11321         spin_lock_init(&tp->lock);
11322         spin_lock_init(&tp->tx_lock);
11323         spin_lock_init(&tp->indirect_lock);
11324         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11325
11326         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11327         if (tp->regs == 0UL) {
11328                 printk(KERN_ERR PFX "Cannot map device registers, "
11329                        "aborting.\n");
11330                 err = -ENOMEM;
11331                 goto err_out_free_dev;
11332         }
11333
11334         tg3_init_link_config(tp);
11335
11336         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11337         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11338         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11339
11340         dev->open = tg3_open;
11341         dev->stop = tg3_close;
11342         dev->get_stats = tg3_get_stats;
11343         dev->set_multicast_list = tg3_set_rx_mode;
11344         dev->set_mac_address = tg3_set_mac_addr;
11345         dev->do_ioctl = tg3_ioctl;
11346         dev->tx_timeout = tg3_tx_timeout;
11347         dev->poll = tg3_poll;
11348         dev->ethtool_ops = &tg3_ethtool_ops;
11349         dev->weight = 64;
11350         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11351         dev->change_mtu = tg3_change_mtu;
11352         dev->irq = pdev->irq;
11353 #ifdef CONFIG_NET_POLL_CONTROLLER
11354         dev->poll_controller = tg3_poll_controller;
11355 #endif
11356
11357         err = tg3_get_invariants(tp);
11358         if (err) {
11359                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11360                        "aborting.\n");
11361                 goto err_out_iounmap;
11362         }
11363
11364         /* The EPB bridge inside 5714, 5715, and 5780 and any
11365          * device behind the EPB cannot support DMA addresses > 40-bit.
11366          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11367          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11368          * do DMA address check in tg3_start_xmit().
11369          */
11370         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11371                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11372         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11373                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11374 #ifdef CONFIG_HIGHMEM
11375                 dma_mask = DMA_64BIT_MASK;
11376 #endif
11377         } else
11378                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11379
11380         /* Configure DMA attributes. */
11381         if (dma_mask > DMA_32BIT_MASK) {
11382                 err = pci_set_dma_mask(pdev, dma_mask);
11383                 if (!err) {
11384                         dev->features |= NETIF_F_HIGHDMA;
11385                         err = pci_set_consistent_dma_mask(pdev,
11386                                                           persist_dma_mask);
11387                         if (err < 0) {
11388                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11389                                        "DMA for consistent allocations\n");
11390                                 goto err_out_iounmap;
11391                         }
11392                 }
11393         }
11394         if (err || dma_mask == DMA_32BIT_MASK) {
11395                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11396                 if (err) {
11397                         printk(KERN_ERR PFX "No usable DMA configuration, "
11398                                "aborting.\n");
11399                         goto err_out_iounmap;
11400                 }
11401         }
11402
11403         tg3_init_bufmgr_config(tp);
11404
11405 #if TG3_TSO_SUPPORT != 0
11406         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11407                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11408         }
11409         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11410             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11411             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11412             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11413                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11414         } else {
11415                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11416         }
11417
11418         /* TSO is on by default on chips that support hardware TSO.
11419          * Firmware TSO on older chips gives lower performance, so it
11420          * is off by default, but can be enabled using ethtool.
11421          */
11422         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
11423                 dev->features |= NETIF_F_TSO;
11424
11425 #endif
11426
11427         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11428             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11429             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11430                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11431                 tp->rx_pending = 63;
11432         }
11433
11434         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11435             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11436                 tp->pdev_peer = tg3_find_peer(tp);
11437
11438         err = tg3_get_device_address(tp);
11439         if (err) {
11440                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11441                        "aborting.\n");
11442                 goto err_out_iounmap;
11443         }
11444
11445         /*
11446          * Reset chip in case UNDI or EFI driver did not shutdown
11447          * DMA self test will enable WDMAC and we'll see (spurious)
11448          * pending DMA on the PCI bus at that point.
11449          */
11450         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11451             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11452                 pci_save_state(tp->pdev);
11453                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11454                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11455         }
11456
11457         err = tg3_test_dma(tp);
11458         if (err) {
11459                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11460                 goto err_out_iounmap;
11461         }
11462
11463         /* Tigon3 can do ipv4 only... and some chips have buggy
11464          * checksumming.
11465          */
11466         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11467                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11468                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11469                         dev->features |= NETIF_F_HW_CSUM;
11470                 else
11471                         dev->features |= NETIF_F_IP_CSUM;
11472                 dev->features |= NETIF_F_SG;
11473                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11474         } else
11475                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11476
11477         /* flow control autonegotiation is default behavior */
11478         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11479
11480         tg3_init_coal(tp);
11481
11482         /* Now that we have fully setup the chip, save away a snapshot
11483          * of the PCI config space.  We need to restore this after
11484          * GRC_MISC_CFG core clock resets and some resume events.
11485          */
11486         pci_save_state(tp->pdev);
11487
11488         err = register_netdev(dev);
11489         if (err) {
11490                 printk(KERN_ERR PFX "Cannot register net device, "
11491                        "aborting.\n");
11492                 goto err_out_iounmap;
11493         }
11494
11495         pci_set_drvdata(pdev, dev);
11496
11497         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11498                dev->name,
11499                tp->board_part_number,
11500                tp->pci_chip_rev_id,
11501                tg3_phy_string(tp),
11502                tg3_bus_string(tp, str),
11503                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11504
11505         for (i = 0; i < 6; i++)
11506                 printk("%2.2x%c", dev->dev_addr[i],
11507                        i == 5 ? '\n' : ':');
11508
11509         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11510                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11511                "TSOcap[%d] \n",
11512                dev->name,
11513                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11514                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11515                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11516                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11517                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11518                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11519                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11520         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11521                dev->name, tp->dma_rwctrl,
11522                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11523                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11524
11525         netif_carrier_off(tp->dev);
11526
11527         return 0;
11528
11529 err_out_iounmap:
11530         if (tp->regs) {
11531                 iounmap(tp->regs);
11532                 tp->regs = NULL;
11533         }
11534
11535 err_out_free_dev:
11536         free_netdev(dev);
11537
11538 err_out_free_res:
11539         pci_release_regions(pdev);
11540
11541 err_out_disable_pdev:
11542         pci_disable_device(pdev);
11543         pci_set_drvdata(pdev, NULL);
11544         return err;
11545 }
11546
11547 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11548 {
11549         struct net_device *dev = pci_get_drvdata(pdev);
11550
11551         if (dev) {
11552                 struct tg3 *tp = netdev_priv(dev);
11553
11554                 flush_scheduled_work();
11555                 unregister_netdev(dev);
11556                 if (tp->regs) {
11557                         iounmap(tp->regs);
11558                         tp->regs = NULL;
11559                 }
11560                 free_netdev(dev);
11561                 pci_release_regions(pdev);
11562                 pci_disable_device(pdev);
11563                 pci_set_drvdata(pdev, NULL);
11564         }
11565 }
11566
11567 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11568 {
11569         struct net_device *dev = pci_get_drvdata(pdev);
11570         struct tg3 *tp = netdev_priv(dev);
11571         int err;
11572
11573         if (!netif_running(dev))
11574                 return 0;
11575
11576         flush_scheduled_work();
11577         tg3_netif_stop(tp);
11578
11579         del_timer_sync(&tp->timer);
11580
11581         tg3_full_lock(tp, 1);
11582         tg3_disable_ints(tp);
11583         tg3_full_unlock(tp);
11584
11585         netif_device_detach(dev);
11586
11587         tg3_full_lock(tp, 0);
11588         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11589         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11590         tg3_full_unlock(tp);
11591
11592         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11593         if (err) {
11594                 tg3_full_lock(tp, 0);
11595
11596                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11597                 tg3_init_hw(tp, 1);
11598
11599                 tp->timer.expires = jiffies + tp->timer_offset;
11600                 add_timer(&tp->timer);
11601
11602                 netif_device_attach(dev);
11603                 tg3_netif_start(tp);
11604
11605                 tg3_full_unlock(tp);
11606         }
11607
11608         return err;
11609 }
11610
11611 static int tg3_resume(struct pci_dev *pdev)
11612 {
11613         struct net_device *dev = pci_get_drvdata(pdev);
11614         struct tg3 *tp = netdev_priv(dev);
11615         int err;
11616
11617         if (!netif_running(dev))
11618                 return 0;
11619
11620         pci_restore_state(tp->pdev);
11621
11622         err = tg3_set_power_state(tp, PCI_D0);
11623         if (err)
11624                 return err;
11625
11626         netif_device_attach(dev);
11627
11628         tg3_full_lock(tp, 0);
11629
11630         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11631         tg3_init_hw(tp, 1);
11632
11633         tp->timer.expires = jiffies + tp->timer_offset;
11634         add_timer(&tp->timer);
11635
11636         tg3_netif_start(tp);
11637
11638         tg3_full_unlock(tp);
11639
11640         return 0;
11641 }
11642
11643 static struct pci_driver tg3_driver = {
11644         .name           = DRV_MODULE_NAME,
11645         .id_table       = tg3_pci_tbl,
11646         .probe          = tg3_init_one,
11647         .remove         = __devexit_p(tg3_remove_one),
11648         .suspend        = tg3_suspend,
11649         .resume         = tg3_resume
11650 };
11651
11652 static int __init tg3_init(void)
11653 {
11654         return pci_module_init(&tg3_driver);
11655 }
11656
11657 static void __exit tg3_cleanup(void)
11658 {
11659         pci_unregister_driver(&tg3_driver);
11660 }
11661
11662 module_init(tg3_init);
11663 module_exit(tg3_cleanup);