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   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  *
   6  * Author: Jon Mason <jdmason@us.ibm.com>
   7  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   8
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44
  45 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  46 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  47         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  48
  49 /* we need these for register space address calculation */
  50 #define START_ADDRESS           0xfe000000
  51 #define CHASSIS_BASE            0
  52 #define ONE_BASED_CHASSIS_NUM   1
  53
  54 /* register offsets inside the host bridge space */
  55 #define PHB_CSR_OFFSET          0x0110
  56 #define PHB_PLSSR_OFFSET        0x0120
  57 #define PHB_CONFIG_RW_OFFSET    0x0160
  58 #define PHB_IOBASE_BAR_LOW      0x0170
  59 #define PHB_IOBASE_BAR_HIGH     0x0180
  60 #define PHB_MEM_1_LOW           0x0190
  61 #define PHB_MEM_1_HIGH          0x01A0
  62 #define PHB_IO_ADDR_SIZE        0x01B0
  63 #define PHB_MEM_1_SIZE          0x01C0
  64 #define PHB_MEM_ST_OFFSET       0x01D0
  65 #define PHB_AER_OFFSET          0x0200
  66 #define PHB_CONFIG_0_HIGH       0x0220
  67 #define PHB_CONFIG_0_LOW        0x0230
  68 #define PHB_CONFIG_0_END        0x0240
  69 #define PHB_MEM_2_LOW           0x02B0
  70 #define PHB_MEM_2_HIGH          0x02C0
  71 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  72 #define PHB_MEM_2_SIZE_LOW      0x02E0
  73 #define PHB_DOSHOLE_OFFSET      0x08E0
  74
  75 /* PHB_CONFIG_RW */
  76 #define PHB_TCE_ENABLE          0x20000000
  77 #define PHB_SLOT_DISABLE        0x1C000000
  78 #define PHB_DAC_DISABLE         0x01000000
  79 #define PHB_MEM2_ENABLE         0x00400000
  80 #define PHB_MCSR_ENABLE         0x00100000
  81 /* TAR (Table Address Register) */
  82 #define TAR_SW_BITS             0x0000ffffffff800fUL
  83 #define TAR_VALID               0x0000000000000008UL
  84 /* CSR (Channel/DMA Status Register) */
  85 #define CSR_AGENT_MASK          0xffe0ffff
  86
  87 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  88 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
  89 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) /* max dev->bus->number */
  90 #define PHBS_PER_CALGARY        4
  91
  92 /* register offsets in Calgary's internal register space */
  93 static const unsigned long tar_offsets[] = {
  94         0x0580 /* TAR0 */,
  95         0x0588 /* TAR1 */,
  96         0x0590 /* TAR2 */,
  97         0x0598 /* TAR3 */
  98 };
  99
 100 static const unsigned long split_queue_offsets[] = {
 101         0x4870 /* SPLIT QUEUE 0 */,
 102         0x5870 /* SPLIT QUEUE 1 */,
 103         0x6870 /* SPLIT QUEUE 2 */,
 104         0x7870 /* SPLIT QUEUE 3 */
 105 };
 106
 107 static const unsigned long phb_offsets[] = {
 108         0x8000 /* PHB0 */,
 109         0x9000 /* PHB1 */,
 110         0xA000 /* PHB2 */,
 111         0xB000 /* PHB3 */
 112 };
 113
 114 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 115 static int translate_empty_slots __read_mostly = 0;
 116 static int calgary_detected __read_mostly = 0;
 117
 118 struct calgary_bus_info {
 119         void *tce_space;
 120         unsigned char translation_disabled;
 121         signed char phbid;
 122 };
 123
 124 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 125
 126 static void tce_cache_blast(struct iommu_table *tbl);
 127
 128 /* enable this to stress test the chip's TCE cache */
 129 #ifdef CONFIG_IOMMU_DEBUG
 130 int debugging __read_mostly = 1;
 131
 132 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 133         int expected, unsigned long start, unsigned long end)
 134 {
 135         unsigned long idx = start;
 136
 137         BUG_ON(start >= end);
 138
 139         while (idx < end) {
 140                 if (!!test_bit(idx, bitmap) != expected)
 141                         return idx;
 142                 ++idx;
 143         }
 144
 145         /* all bits have the expected value */
 146         return ~0UL;
 147 }
 148 #else /* debugging is disabled */
 149 int debugging __read_mostly = 0;
 150
 151 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 152         int expected, unsigned long start, unsigned long end)
 153 {
 154         return ~0UL;
 155 }
 156 #endif /* CONFIG_IOMMU_DEBUG */
 157
 158 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 159 {
 160         unsigned int npages;
 161
 162         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 163         npages >>= PAGE_SHIFT;
 164
 165         return npages;
 166 }
 167
 168 static inline int translate_phb(struct pci_dev* dev)
 169 {
 170         int disabled = bus_info[dev->bus->number].translation_disabled;
 171         return !disabled;
 172 }
 173
 174 static void iommu_range_reserve(struct iommu_table *tbl,
 175         unsigned long start_addr, unsigned int npages)
 176 {
 177         unsigned long index;
 178         unsigned long end;
 179         unsigned long badbit;
 180
 181         index = start_addr >> PAGE_SHIFT;
 182
 183         /* bail out if we're asked to reserve a region we don't cover */
 184         if (index >= tbl->it_size)
 185                 return;
 186
 187         end = index + npages;
 188         if (end > tbl->it_size) /* don't go off the table */
 189                 end = tbl->it_size;
 190
 191         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 192         if (badbit != ~0UL) {
 193                 if (printk_ratelimit())
 194                         printk(KERN_ERR "Calgary: entry already allocated at "
 195                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 196                                badbit, tbl, start_addr, npages);
 197         }
 198
 199         set_bit_string(tbl->it_map, index, npages);
 200 }
 201
 202 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 203         unsigned int npages)
 204 {
 205         unsigned long offset;
 206
 207         BUG_ON(npages == 0);
 208
 209         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 210                                        tbl->it_size, npages);
 211         if (offset == ~0UL) {
 212                 tce_cache_blast(tbl);
 213                 offset = find_next_zero_string(tbl->it_map, 0,
 214                                                tbl->it_size, npages);
 215                 if (offset == ~0UL) {
 216                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 217                         if (panic_on_overflow)
 218                                 panic("Calgary: fix the allocator.\n");
 219                         else
 220                                 return bad_dma_address;
 221                 }
 222         }
 223
 224         set_bit_string(tbl->it_map, offset, npages);
 225         tbl->it_hint = offset + npages;
 226         BUG_ON(tbl->it_hint > tbl->it_size);
 227
 228         return offset;
 229 }
 230
 231 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 232         unsigned int npages, int direction)
 233 {
 234         unsigned long entry, flags;
 235         dma_addr_t ret = bad_dma_address;
 236
 237         spin_lock_irqsave(&tbl->it_lock, flags);
 238
 239         entry = iommu_range_alloc(tbl, npages);
 240
 241         if (unlikely(entry == bad_dma_address))
 242                 goto error;
 243
 244         /* set the return dma address */
 245         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 246
 247         /* put the TCEs in the HW table */
 248         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 249                   direction);
 250
 251         spin_unlock_irqrestore(&tbl->it_lock, flags);
 252
 253         return ret;
 254
 255 error:
 256         spin_unlock_irqrestore(&tbl->it_lock, flags);
 257         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 258                "iommu %p\n", npages, tbl);
 259         return bad_dma_address;
 260 }
 261
 262 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 263         unsigned int npages)
 264 {
 265         unsigned long entry;
 266         unsigned long badbit;
 267
 268         entry = dma_addr >> PAGE_SHIFT;
 269
 270         BUG_ON(entry + npages > tbl->it_size);
 271
 272         tce_free(tbl, entry, npages);
 273
 274         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 275         if (badbit != ~0UL) {
 276                 if (printk_ratelimit())
 277                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 278                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 279                                badbit, tbl, dma_addr, entry, npages);
 280         }
 281
 282         __clear_bit_string(tbl->it_map, entry, npages);
 283 }
 284
 285 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 286         unsigned int npages)
 287 {
 288         unsigned long flags;
 289
 290         spin_lock_irqsave(&tbl->it_lock, flags);
 291
 292         __iommu_free(tbl, dma_addr, npages);
 293
 294         spin_unlock_irqrestore(&tbl->it_lock, flags);
 295 }
 296
 297 static void __calgary_unmap_sg(struct iommu_table *tbl,
 298         struct scatterlist *sglist, int nelems, int direction)
 299 {
 300         while (nelems--) {
 301                 unsigned int npages;
 302                 dma_addr_t dma = sglist->dma_address;
 303                 unsigned int dmalen = sglist->dma_length;
 304
 305                 if (dmalen == 0)
 306                         break;
 307
 308                 npages = num_dma_pages(dma, dmalen);
 309                 __iommu_free(tbl, dma, npages);
 310                 sglist++;
 311         }
 312 }
 313
 314 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 315                       int nelems, int direction)
 316 {
 317         unsigned long flags;
 318         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 319
 320         if (!translate_phb(to_pci_dev(dev)))
 321                 return;
 322
 323         spin_lock_irqsave(&tbl->it_lock, flags);
 324
 325         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 326
 327         spin_unlock_irqrestore(&tbl->it_lock, flags);
 328 }
 329
 330 static int calgary_nontranslate_map_sg(struct device* dev,
 331         struct scatterlist *sg, int nelems, int direction)
 332 {
 333         int i;
 334
 335         for (i = 0; i < nelems; i++ ) {
 336                 struct scatterlist *s = &sg[i];
 337                 BUG_ON(!s->page);
 338                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 339                 s->dma_length = s->length;
 340         }
 341         return nelems;
 342 }
 343
 344 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 345         int nelems, int direction)
 346 {
 347         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 348         unsigned long flags;
 349         unsigned long vaddr;
 350         unsigned int npages;
 351         unsigned long entry;
 352         int i;
 353
 354         if (!translate_phb(to_pci_dev(dev)))
 355                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 356
 357         spin_lock_irqsave(&tbl->it_lock, flags);
 358
 359         for (i = 0; i < nelems; i++ ) {
 360                 struct scatterlist *s = &sg[i];
 361                 BUG_ON(!s->page);
 362
 363                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 364                 npages = num_dma_pages(vaddr, s->length);
 365
 366                 entry = iommu_range_alloc(tbl, npages);
 367                 if (entry == bad_dma_address) {
 368                         /* makes sure unmap knows to stop */
 369                         s->dma_length = 0;
 370                         goto error;
 371                 }
 372
 373                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 374
 375                 /* insert into HW table */
 376                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 377                           direction);
 378
 379                 s->dma_length = s->length;
 380         }
 381
 382         spin_unlock_irqrestore(&tbl->it_lock, flags);
 383
 384         return nelems;
 385 error:
 386         __calgary_unmap_sg(tbl, sg, nelems, direction);
 387         for (i = 0; i < nelems; i++) {
 388                 sg[i].dma_address = bad_dma_address;
 389                 sg[i].dma_length = 0;
 390         }
 391         spin_unlock_irqrestore(&tbl->it_lock, flags);
 392         return 0;
 393 }
 394
 395 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 396         size_t size, int direction)
 397 {
 398         dma_addr_t dma_handle = bad_dma_address;
 399         unsigned long uaddr;
 400         unsigned int npages;
 401         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 402
 403         uaddr = (unsigned long)vaddr;
 404         npages = num_dma_pages(uaddr, size);
 405
 406         if (translate_phb(to_pci_dev(dev)))
 407                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 408         else
 409                 dma_handle = virt_to_bus(vaddr);
 410
 411         return dma_handle;
 412 }
 413
 414 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 415         size_t size, int direction)
 416 {
 417         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 418         unsigned int npages;
 419
 420         if (!translate_phb(to_pci_dev(dev)))
 421                 return;
 422
 423         npages = num_dma_pages(dma_handle, size);
 424         iommu_free(tbl, dma_handle, npages);
 425 }
 426
 427 void* calgary_alloc_coherent(struct device *dev, size_t size,
 428         dma_addr_t *dma_handle, gfp_t flag)
 429 {
 430         void *ret = NULL;
 431         dma_addr_t mapping;
 432         unsigned int npages, order;
 433         struct iommu_table *tbl;
 434
 435         tbl = to_pci_dev(dev)->bus->self->sysdata;
 436
 437         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 438         npages = size >> PAGE_SHIFT;
 439         order = get_order(size);
 440
 441         /* alloc enough pages (and possibly more) */
 442         ret = (void *)__get_free_pages(flag, order);
 443         if (!ret)
 444                 goto error;
 445         memset(ret, 0, size);
 446
 447         if (translate_phb(to_pci_dev(dev))) {
 448                 /* set up tces to cover the allocated range */
 449                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 450                 if (mapping == bad_dma_address)
 451                         goto free;
 452
 453                 *dma_handle = mapping;
 454         } else /* non translated slot */
 455                 *dma_handle = virt_to_bus(ret);
 456
 457         return ret;
 458
 459 free:
 460         free_pages((unsigned long)ret, get_order(size));
 461         ret = NULL;
 462 error:
 463         return ret;
 464 }
 465
 466 static struct dma_mapping_ops calgary_dma_ops = {
 467         .alloc_coherent = calgary_alloc_coherent,
 468         .map_single = calgary_map_single,
 469         .unmap_single = calgary_unmap_single,
 470         .map_sg = calgary_map_sg,
 471         .unmap_sg = calgary_unmap_sg,
 472 };
 473
 474 static inline int busno_to_phbid(unsigned char num)
 475 {
 476         return bus_info[num].phbid;
 477 }
 478
 479 static inline unsigned long split_queue_offset(unsigned char num)
 480 {
 481         size_t idx = busno_to_phbid(num);
 482
 483         return split_queue_offsets[idx];
 484 }
 485
 486 static inline unsigned long tar_offset(unsigned char num)
 487 {
 488         size_t idx = busno_to_phbid(num);
 489
 490         return tar_offsets[idx];
 491 }
 492
 493 static inline unsigned long phb_offset(unsigned char num)
 494 {
 495         size_t idx = busno_to_phbid(num);
 496
 497         return phb_offsets[idx];
 498 }
 499
 500 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 501 {
 502         unsigned long target = ((unsigned long)bar) | offset;
 503         return (void __iomem*)target;
 504 }
 505
 506 static void tce_cache_blast(struct iommu_table *tbl)
 507 {
 508         u64 val;
 509         u32 aer;
 510         int i = 0;
 511         void __iomem *bbar = tbl->bbar;
 512         void __iomem *target;
 513
 514         /* disable arbitration on the bus */
 515         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 516         aer = readl(target);
 517         writel(0, target);
 518
 519         /* read plssr to ensure it got there */
 520         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 521         val = readl(target);
 522
 523         /* poll split queues until all DMA activity is done */
 524         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 525         do {
 526                 val = readq(target);
 527                 i++;
 528         } while ((val & 0xff) != 0xff && i < 100);
 529         if (i == 100)
 530                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 531                        "continuing anyway\n");
 532
 533         /* invalidate TCE cache */
 534         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 535         writeq(tbl->tar_val, target);
 536
 537         /* enable arbitration */
 538         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 539         writel(aer, target);
 540         (void)readl(target); /* flush */
 541 }
 542
 543 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 544         u64 limit)
 545 {
 546         unsigned int numpages;
 547
 548         limit = limit | 0xfffff;
 549         limit++;
 550
 551         numpages = ((limit - start) >> PAGE_SHIFT);
 552         iommu_range_reserve(dev->sysdata, start, numpages);
 553 }
 554
 555 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 556 {
 557         void __iomem *target;
 558         u64 low, high, sizelow;
 559         u64 start, limit;
 560         struct iommu_table *tbl = dev->sysdata;
 561         unsigned char busnum = dev->bus->number;
 562         void __iomem *bbar = tbl->bbar;
 563
 564         /* peripheral MEM_1 region */
 565         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 566         low = be32_to_cpu(readl(target));
 567         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 568         high = be32_to_cpu(readl(target));
 569         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 570         sizelow = be32_to_cpu(readl(target));
 571
 572         start = (high << 32) | low;
 573         limit = sizelow;
 574
 575         calgary_reserve_mem_region(dev, start, limit);
 576 }
 577
 578 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 579 {
 580         void __iomem *target;
 581         u32 val32;
 582         u64 low, high, sizelow, sizehigh;
 583         u64 start, limit;
 584         struct iommu_table *tbl = dev->sysdata;
 585         unsigned char busnum = dev->bus->number;
 586         void __iomem *bbar = tbl->bbar;
 587
 588         /* is it enabled? */
 589         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 590         val32 = be32_to_cpu(readl(target));
 591         if (!(val32 & PHB_MEM2_ENABLE))
 592                 return;
 593
 594         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 595         low = be32_to_cpu(readl(target));
 596         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 597         high = be32_to_cpu(readl(target));
 598         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 599         sizelow = be32_to_cpu(readl(target));
 600         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 601         sizehigh = be32_to_cpu(readl(target));
 602
 603         start = (high << 32) | low;
 604         limit = (sizehigh << 32) | sizelow;
 605
 606         calgary_reserve_mem_region(dev, start, limit);
 607 }
 608
 609 /*
 610  * some regions of the IO address space do not get translated, so we
 611  * must not give devices IO addresses in those regions. The regions
 612  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 613  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 614  * later.
 615  */
 616 static void __init calgary_reserve_regions(struct pci_dev *dev)
 617 {
 618         unsigned int npages;
 619         void __iomem *bbar;
 620         unsigned char busnum;
 621         u64 start;
 622         struct iommu_table *tbl = dev->sysdata;
 623
 624         bbar = tbl->bbar;
 625         busnum = dev->bus->number;
 626
 627         /* reserve bad_dma_address in case it's a legal address */
 628         iommu_range_reserve(tbl, bad_dma_address, 1);
 629
 630         /* avoid the BIOS/VGA first 640KB-1MB region */
 631         start = (640 * 1024);
 632         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 633         iommu_range_reserve(tbl, start, npages);
 634
 635         /* reserve the two PCI peripheral memory regions in IO space */
 636         calgary_reserve_peripheral_mem_1(dev);
 637         calgary_reserve_peripheral_mem_2(dev);
 638 }
 639
 640 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 641 {
 642         u64 val64;
 643         u64 table_phys;
 644         void __iomem *target;
 645         int ret;
 646         struct iommu_table *tbl;
 647
 648         /* build TCE tables for each PHB */
 649         ret = build_tce_table(dev, bbar);
 650         if (ret)
 651                 return ret;
 652
 653         tbl = dev->sysdata;
 654         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 655         tce_free(tbl, 0, tbl->it_size);
 656
 657         calgary_reserve_regions(dev);
 658
 659         /* set TARs for each PHB */
 660         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 661         val64 = be64_to_cpu(readq(target));
 662
 663         /* zero out all TAR bits under sw control */
 664         val64 &= ~TAR_SW_BITS;
 665
 666         tbl = dev->sysdata;
 667         table_phys = (u64)__pa(tbl->it_base);
 668         val64 |= table_phys;
 669
 670         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 671         val64 |= (u64) specified_table_size;
 672
 673         tbl->tar_val = cpu_to_be64(val64);
 674         writeq(tbl->tar_val, target);
 675         readq(target); /* flush */
 676
 677         return 0;
 678 }
 679
 680 static void __init calgary_free_bus(struct pci_dev *dev)
 681 {
 682         u64 val64;
 683         struct iommu_table *tbl = dev->sysdata;
 684         void __iomem *target;
 685         unsigned int bitmapsz;
 686
 687         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 688         val64 = be64_to_cpu(readq(target));
 689         val64 &= ~TAR_SW_BITS;
 690         writeq(cpu_to_be64(val64), target);
 691         readq(target); /* flush */
 692
 693         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 694         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 695         tbl->it_map = NULL;
 696
 697         kfree(tbl);
 698         dev->sysdata = NULL;
 699
 700         /* Can't free bootmem allocated memory after system is up :-( */
 701         bus_info[dev->bus->number].tce_space = NULL;
 702 }
 703
 704 static void calgary_watchdog(unsigned long data)
 705 {
 706         struct pci_dev *dev = (struct pci_dev *)data;
 707         struct iommu_table *tbl = dev->sysdata;
 708         void __iomem *bbar = tbl->bbar;
 709         u32 val32;
 710         void __iomem *target;
 711
 712         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 713         val32 = be32_to_cpu(readl(target));
 714
 715         /* If no error, the agent ID in the CSR is not valid */
 716         if (val32 & CSR_AGENT_MASK) {
 717                 printk(KERN_EMERG "calgary_watchdog: DMA error on bus %d, "
 718                                   "CSR = %#x\n", dev->bus->number, val32);
 719                 writel(0, target);
 720
 721                 /* Disable bus that caused the error */
 722                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 723                                            PHB_CONFIG_RW_OFFSET);
 724                 val32 = be32_to_cpu(readl(target));
 725                 val32 |= PHB_SLOT_DISABLE;
 726                 writel(cpu_to_be32(val32), target);
 727                 readl(target); /* flush */
 728         } else {
 729                 /* Reset the timer */
 730                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 731         }
 732 }
 733
 734 static void __init calgary_enable_translation(struct pci_dev *dev)
 735 {
 736         u32 val32;
 737         unsigned char busnum;
 738         void __iomem *target;
 739         void __iomem *bbar;
 740         struct iommu_table *tbl;
 741
 742         busnum = dev->bus->number;
 743         tbl = dev->sysdata;
 744         bbar = tbl->bbar;
 745
 746         /* enable TCE in PHB Config Register */
 747         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 748         val32 = be32_to_cpu(readl(target));
 749         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 750
 751         printk(KERN_INFO "Calgary: enabling translation on PHB %d\n", busnum);
 752         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 753                "bus.\n");
 754
 755         writel(cpu_to_be32(val32), target);
 756         readl(target); /* flush */
 757
 758         init_timer(&tbl->watchdog_timer);
 759         tbl->watchdog_timer.function = &calgary_watchdog;
 760         tbl->watchdog_timer.data = (unsigned long)dev;
 761         mod_timer(&tbl->watchdog_timer, jiffies);
 762 }
 763
 764 static void __init calgary_disable_translation(struct pci_dev *dev)
 765 {
 766         u32 val32;
 767         unsigned char busnum;
 768         void __iomem *target;
 769         void __iomem *bbar;
 770         struct iommu_table *tbl;
 771
 772         busnum = dev->bus->number;
 773         tbl = dev->sysdata;
 774         bbar = tbl->bbar;
 775
 776         /* disable TCE in PHB Config Register */
 777         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 778         val32 = be32_to_cpu(readl(target));
 779         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 780
 781         printk(KERN_INFO "Calgary: disabling translation on PHB %d!\n", busnum);
 782         writel(cpu_to_be32(val32), target);
 783         readl(target); /* flush */
 784
 785         del_timer_sync(&tbl->watchdog_timer);
 786 }
 787
 788 static inline unsigned int __init locate_register_space(struct pci_dev *dev)
 789 {
 790         int rionodeid;
 791         u32 address;
 792
 793         rionodeid = (dev->bus->number % 15 > 4) ? 3 : 2;
 794         /*
 795          * register space address calculation as follows:
 796          * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase)
 797          * ChassisBase is always zero for x366/x260/x460
 798          * RioNodeId is 2 for first Calgary, 3 for second Calgary
 799          */
 800         address = START_ADDRESS -
 801                 (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 15)) +
 802                 (0x100000) * (rionodeid - CHASSIS_BASE);
 803         return address;
 804 }
 805
 806 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
 807 {
 808         pci_dev_get(dev);
 809         dev->sysdata = NULL;
 810         dev->bus->self = dev;
 811 }
 812
 813 static int __init calgary_init_one(struct pci_dev *dev)
 814 {
 815         u32 address;
 816         void __iomem *bbar;
 817         int ret;
 818
 819         address = locate_register_space(dev);
 820         /* map entire 1MB of Calgary config space */
 821         bbar = ioremap_nocache(address, 1024 * 1024);
 822         if (!bbar) {
 823                 ret = -ENODATA;
 824                 goto done;
 825         }
 826
 827         ret = calgary_setup_tar(dev, bbar);
 828         if (ret)
 829                 goto iounmap;
 830
 831         pci_dev_get(dev);
 832         dev->bus->self = dev;
 833         calgary_enable_translation(dev);
 834
 835         return 0;
 836
 837 iounmap:
 838         iounmap(bbar);
 839 done:
 840         return ret;
 841 }
 842
 843 static int __init calgary_init(void)
 844 {
 845         int i, ret = -ENODEV;
 846         struct pci_dev *dev = NULL;
 847
 848         for (i = 0; i < MAX_PHB_BUS_NUM; i++) {
 849                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 850                                      PCI_DEVICE_ID_IBM_CALGARY,
 851                                      dev);
 852                 if (!dev)
 853                         break;
 854                 if (!translate_phb(dev)) {
 855                         calgary_init_one_nontraslated(dev);
 856                         continue;
 857                 }
 858                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 859                         continue;
 860
 861                 ret = calgary_init_one(dev);
 862                 if (ret)
 863                         goto error;
 864         }
 865
 866         return ret;
 867
 868 error:
 869         for (i--; i >= 0; i--) {
 870                 dev = pci_find_device_reverse(PCI_VENDOR_ID_IBM,
 871                                               PCI_DEVICE_ID_IBM_CALGARY,
 872                                               dev);
 873                 if (!dev)
 874                         break;
 875                 if (!translate_phb(dev)) {
 876                         pci_dev_put(dev);
 877                         continue;
 878                 }
 879                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 880                         continue;
 881
 882                 calgary_disable_translation(dev);
 883                 calgary_free_bus(dev);
 884                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
 885         }
 886
 887         return ret;
 888 }
 889
 890 static inline int __init determine_tce_table_size(u64 ram)
 891 {
 892         int ret;
 893
 894         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
 895                 return specified_table_size;
 896
 897         /*
 898          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
 899          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
 900          * larger table size has twice as many entries, so shift the
 901          * max ram address by 13 to divide by 8K and then look at the
 902          * order of the result to choose between 0-7.
 903          */
 904         ret = get_order(ram >> 13);
 905         if (ret > TCE_TABLE_SIZE_8M)
 906                 ret = TCE_TABLE_SIZE_8M;
 907
 908         return ret;
 909 }
 910
 911 void __init detect_calgary(void)
 912 {
 913         u32 val;
 914         int bus;
 915         void *tbl;
 916         int calgary_found = 0;
 917         int phb = -1;
 918
 919         /*
 920          * if the user specified iommu=off or iommu=soft or we found
 921          * another HW IOMMU already, bail out.
 922          */
 923         if (swiotlb || no_iommu || iommu_detected)
 924                 return;
 925
 926         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
 927
 928         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
 929                 int dev;
 930                 struct calgary_bus_info *info = &bus_info[bus];
 931                 info->phbid = -1;
 932
 933                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
 934                         continue;
 935
 936                 /*
 937                  * There are 4 PHBs per Calgary chip.  Set phb to which phb (0-3)
 938                  * it is connected to releative to the clagary chip.
 939                  */
 940                 phb = (phb + 1) % PHBS_PER_CALGARY;
 941
 942                 if (info->translation_disabled)
 943                         continue;
 944
 945                 /*
 946                  * Scan the slots of the PCI bus to see if there is a device present.
 947                  * The parent bus will be the zero-ith device, so start at 1.
 948                  */
 949                 for (dev = 1; dev < 8; dev++) {
 950                         val = read_pci_config(bus, dev, 0, 0);
 951                         if (val != 0xffffffff || translate_empty_slots) {
 952                                 tbl = alloc_tce_table();
 953                                 if (!tbl)
 954                                         goto cleanup;
 955                                 info->tce_space = tbl;
 956                                 info->phbid = phb;
 957                                 calgary_found = 1;
 958                                 break;
 959                         }
 960                 }
 961         }
 962
 963         if (calgary_found) {
 964                 iommu_detected = 1;
 965                 calgary_detected = 1;
 966                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
 967                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
 968                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
 969                        debugging ? "enabled" : "disabled");
 970         }
 971         return;
 972
 973 cleanup:
 974         for (--bus; bus >= 0; --bus) {
 975                 struct calgary_bus_info *info = &bus_info[bus];
 976
 977                 if (info->tce_space)
 978                         free_tce_table(info->tce_space);
 979         }
 980 }
 981
 982 int __init calgary_iommu_init(void)
 983 {
 984         int ret;
 985
 986         if (no_iommu || swiotlb)
 987                 return -ENODEV;
 988
 989         if (!calgary_detected)
 990                 return -ENODEV;
 991
 992         /* ok, we're trying to use Calgary - let's roll */
 993         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
 994
 995         ret = calgary_init();
 996         if (ret) {
 997                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
 998                        "falling back to no_iommu\n", ret);
 999                 if (end_pfn > MAX_DMA32_PFN)
1000                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1001                                         "32bit PCI may malfunction.\n");
1002                 return ret;
1003         }
1004
1005         force_iommu = 1;
1006         dma_ops = &calgary_dma_ops;
1007
1008         return 0;
1009 }
1010
1011 static int __init calgary_parse_options(char *p)
1012 {
1013         unsigned int bridge;
1014         size_t len;
1015         char* endp;
1016
1017         while (*p) {
1018                 if (!strncmp(p, "64k", 3))
1019                         specified_table_size = TCE_TABLE_SIZE_64K;
1020                 else if (!strncmp(p, "128k", 4))
1021                         specified_table_size = TCE_TABLE_SIZE_128K;
1022                 else if (!strncmp(p, "256k", 4))
1023                         specified_table_size = TCE_TABLE_SIZE_256K;
1024                 else if (!strncmp(p, "512k", 4))
1025                         specified_table_size = TCE_TABLE_SIZE_512K;
1026                 else if (!strncmp(p, "1M", 2))
1027                         specified_table_size = TCE_TABLE_SIZE_1M;
1028                 else if (!strncmp(p, "2M", 2))
1029                         specified_table_size = TCE_TABLE_SIZE_2M;
1030                 else if (!strncmp(p, "4M", 2))
1031                         specified_table_size = TCE_TABLE_SIZE_4M;
1032                 else if (!strncmp(p, "8M", 2))
1033                         specified_table_size = TCE_TABLE_SIZE_8M;
1034
1035                 len = strlen("translate_empty_slots");
1036                 if (!strncmp(p, "translate_empty_slots", len))
1037                         translate_empty_slots = 1;
1038
1039                 len = strlen("disable");
1040                 if (!strncmp(p, "disable", len)) {
1041                         p += len;
1042                         if (*p == '=')
1043                                 ++p;
1044                         if (*p == '\0')
1045                                 break;
1046                         bridge = simple_strtol(p, &endp, 0);
1047                         if (p == endp)
1048                                 break;
1049
1050                         if (bridge < MAX_PHB_BUS_NUM) {
1051                                 printk(KERN_INFO "Calgary: disabling "
1052                                        "translation for PHB 0x%x\n", bridge);
1053                                 bus_info[bridge].translation_disabled = 1;
1054                         }
1055                 }
1056
1057                 p = strpbrk(p, ",");
1058                 if (!p)
1059                         break;
1060
1061                 p++; /* skip ',' */
1062         }
1063         return 1;
1064 }
1065 __setup("calgary=", calgary_parse_options);