git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/cpu/cpufreq/speedstep-lib.c

   1 /*
   2  * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Library for common functions for Intel SpeedStep v.1 and v.2 support
   7  *
   8  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/slab.h>
  17
  18 #include <asm/msr.h>
  19 #include "speedstep-lib.h"
  20
  21 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
  22
  23 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  24 static int relaxed_check = 0;
  25 #else
  26 #define relaxed_check 0
  27 #endif
  28
  29 /*********************************************************************
  30  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  31  *********************************************************************/
  32
  33 static unsigned int pentium3_get_frequency (unsigned int processor)
  34 {
  35         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  36         struct {
  37                 unsigned int ratio;     /* Frequency Multiplier (x10) */
  38                 u8 bitmap;              /* power on configuration bits
  39                                         [27, 25:22] (in MSR 0x2a) */
  40         } msr_decode_mult [] = {
  41                 { 30, 0x01 },
  42                 { 35, 0x05 },
  43                 { 40, 0x02 },
  44                 { 45, 0x06 },
  45                 { 50, 0x00 },
  46                 { 55, 0x04 },
  47                 { 60, 0x0b },
  48                 { 65, 0x0f },
  49                 { 70, 0x09 },
  50                 { 75, 0x0d },
  51                 { 80, 0x0a },
  52                 { 85, 0x26 },
  53                 { 90, 0x20 },
  54                 { 100, 0x2b },
  55                 { 0, 0xff }     /* error or unknown value */
  56         };
  57
  58         /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  59         struct {
  60                 unsigned int value;     /* Front Side Bus speed in MHz */
  61                 u8 bitmap;              /* power on configuration bits [18: 19]
  62                                         (in MSR 0x2a) */
  63         } msr_decode_fsb [] = {
  64                 {  66, 0x0 },
  65                 { 100, 0x2 },
  66                 { 133, 0x1 },
  67                 {   0, 0xff}
  68         };
  69
  70         u32 msr_lo, msr_tmp;
  71         int i = 0, j = 0;
  72
  73         /* read MSR 0x2a - we only need the low 32 bits */
  74         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  75         dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  76         msr_tmp = msr_lo;
  77
  78         /* decode the FSB */
  79         msr_tmp &= 0x00c0000;
  80         msr_tmp >>= 18;
  81         while (msr_tmp != msr_decode_fsb[i].bitmap) {
  82                 if (msr_decode_fsb[i].bitmap == 0xff)
  83                         return 0;
  84                 i++;
  85         }
  86
  87         /* decode the multiplier */
  88         if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
  89                 dprintk("workaround for early PIIIs\n");
  90                 msr_lo &= 0x03c00000;
  91         } else
  92                 msr_lo &= 0x0bc00000;
  93         msr_lo >>= 22;
  94         while (msr_lo != msr_decode_mult[j].bitmap) {
  95                 if (msr_decode_mult[j].bitmap == 0xff)
  96                         return 0;
  97                 j++;
  98         }
  99
 100         dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
 101
 102         return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
 103 }
 104
 105
 106 static unsigned int pentiumM_get_frequency(void)
 107 {
 108         u32 msr_lo, msr_tmp;
 109
 110         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 111         dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 112
 113         /* see table B-2 of 24547212.pdf */
 114         if (msr_lo & 0x00040000) {
 115                 printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
 116                 return 0;
 117         }
 118
 119         msr_tmp = (msr_lo >> 22) & 0x1f;
 120         dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));
 121
 122         return (msr_tmp * 100 * 1000);
 123 }
 124
 125 static unsigned int pentium_core_get_frequency(void)
 126 {
 127         u32 fsb = 0;
 128         u32 msr_lo, msr_tmp;
 129
 130         rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
 131         /* see table B-2 of 25366920.pdf */
 132         switch (msr_lo & 0x07) {
 133         case 5:
 134                 fsb = 100000;
 135                 break;
 136         case 1:
 137                 fsb = 133333;
 138                 break;
 139         case 3:
 140                 fsb = 166667;
 141                 break;
 142         default:
 143                 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
 144         }
 145
 146         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 147         dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 148
 149         msr_tmp = (msr_lo >> 22) & 0x1f;
 150         dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb));
 151
 152         return (msr_tmp * fsb);
 153 }
 154
 155
 156 static unsigned int pentium4_get_frequency(void)
 157 {
 158         struct cpuinfo_x86 *c = &boot_cpu_data;
 159         u32 msr_lo, msr_hi, mult;
 160         unsigned int fsb = 0;
 161
 162         rdmsr(0x2c, msr_lo, msr_hi);
 163
 164         dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
 165
 166         /* decode the FSB: see IA-32 Intel (C) Architecture Software
 167          * Developer's Manual, Volume 3: System Prgramming Guide,
 168          * revision #12 in Table B-1: MSRs in the Pentium 4 and
 169          * Intel Xeon Processors, on page B-4 and B-5.
 170          */
 171         if (c->x86_model < 2)
 172                 fsb = 100 * 1000;
 173         else {
 174                 u8 fsb_code = (msr_lo >> 16) & 0x7;
 175                 switch (fsb_code) {
 176                 case 0:
 177                         fsb = 100 * 1000;
 178                         break;
 179                 case 1:
 180                         fsb = 13333 * 10;
 181                         break;
 182                 case 2:
 183                         fsb = 200 * 1000;
 184                         break;
 185                 }
 186         }
 187
 188         if (!fsb)
 189                 printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
 190
 191         /* Multiplier. */
 192         if (c->x86_model < 2)
 193                 mult = msr_lo >> 27;
 194         else
 195                 mult = msr_lo >> 24;
 196
 197         dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
 198
 199         return (fsb * mult);
 200 }
 201
 202
 203 unsigned int speedstep_get_processor_frequency(unsigned int processor)
 204 {
 205         switch (processor) {
 206         case SPEEDSTEP_PROCESSOR_PCORE:
 207                 return pentium_core_get_frequency();
 208         case SPEEDSTEP_PROCESSOR_PM:
 209                 return pentiumM_get_frequency();
 210         case SPEEDSTEP_PROCESSOR_P4D:
 211         case SPEEDSTEP_PROCESSOR_P4M:
 212                 return pentium4_get_frequency();
 213         case SPEEDSTEP_PROCESSOR_PIII_T:
 214         case SPEEDSTEP_PROCESSOR_PIII_C:
 215         case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
 216                 return pentium3_get_frequency(processor);
 217         default:
 218                 return 0;
 219         };
 220         return 0;
 221 }
 222 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
 223
 224
 225 /*********************************************************************
 226  *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 227  *********************************************************************/
 228
 229 unsigned int speedstep_detect_processor (void)
 230 {
 231         struct cpuinfo_x86 *c = cpu_data;
 232         u32 ebx, msr_lo, msr_hi;
 233
 234         dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
 235
 236         if ((c->x86_vendor != X86_VENDOR_INTEL) ||
 237             ((c->x86 != 6) && (c->x86 != 0xF)))
 238                 return 0;
 239
 240         if (c->x86 == 0xF) {
 241                 /* Intel Mobile Pentium 4-M
 242                  * or Intel Mobile Pentium 4 with 533 MHz FSB */
 243                 if (c->x86_model != 2)
 244                         return 0;
 245
 246                 ebx = cpuid_ebx(0x00000001);
 247                 ebx &= 0x000000FF;
 248
 249                 dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
 250
 251                 switch (c->x86_mask) {
 252                 case 4:
 253                         /*
 254                          * B-stepping [M-P4-M]
 255                          * sample has ebx = 0x0f, production has 0x0e.
 256                          */
 257                         if ((ebx == 0x0e) || (ebx == 0x0f))
 258                                 return SPEEDSTEP_PROCESSOR_P4M;
 259                         break;
 260                 case 7:
 261                         /*
 262                          * C-stepping [M-P4-M]
 263                          * needs to have ebx=0x0e, else it's a celeron:
 264                          * cf. 25130917.pdf / page 7, footnote 5 even
 265                          * though 25072120.pdf / page 7 doesn't say
 266                          * samples are only of B-stepping...
 267                          */
 268                         if (ebx == 0x0e)
 269                                 return SPEEDSTEP_PROCESSOR_P4M;
 270                         break;
 271                 case 9:
 272                         /*
 273                          * D-stepping [M-P4-M or M-P4/533]
 274                          *
 275                          * this is totally strange: CPUID 0x0F29 is
 276                          * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
 277                          * The latter need to be sorted out as they don't
 278                          * support speedstep.
 279                          * Celerons with CPUID 0x0F29 may have either
 280                          * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
 281                          * specific.
 282                          * M-P4-Ms may have either ebx=0xe or 0xf [see above]
 283                          * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
 284                          * also, M-P4M HTs have ebx=0x8, too
 285                          * For now, they are distinguished by the model_id string
 286                          */
 287                         if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
 288                                 return SPEEDSTEP_PROCESSOR_P4M;
 289                         break;
 290                 default:
 291                         break;
 292                 }
 293                 return 0;
 294         }
 295
 296         switch (c->x86_model) {
 297         case 0x0B: /* Intel PIII [Tualatin] */
 298                 /* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
 299                 ebx = cpuid_ebx(0x00000001);
 300                 dprintk("ebx is %x\n", ebx);
 301
 302                 ebx &= 0x000000FF;
 303
 304                 if (ebx != 0x06)
 305                         return 0;
 306
 307                 /* So far all PIII-M processors support SpeedStep. See
 308                  * Intel's 24540640.pdf of June 2003
 309                  */
 310                 return SPEEDSTEP_PROCESSOR_PIII_T;
 311
 312         case 0x08: /* Intel PIII [Coppermine] */
 313
 314                 /* all mobile PIII Coppermines have FSB 100 MHz
 315                  * ==> sort out a few desktop PIIIs. */
 316                 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
 317                 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
 318                 msr_lo &= 0x00c0000;
 319                 if (msr_lo != 0x0080000)
 320                         return 0;
 321
 322                 /*
 323                  * If the processor is a mobile version,
 324                  * platform ID has bit 50 set
 325                  * it has SpeedStep technology if either
 326                  * bit 56 or 57 is set
 327                  */
 328                 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
 329                 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
 330                 if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
 331                         if (c->x86_mask == 0x01) {
 332                                 dprintk("early PIII version\n");
 333                                 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
 334                         } else
 335                                 return SPEEDSTEP_PROCESSOR_PIII_C;
 336                 }
 337
 338         default:
 339                 return 0;
 340         }
 341 }
 342 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
 343
 344
 345 /*********************************************************************
 346  *                     DETECT SPEEDSTEP SPEEDS                       *
 347  *********************************************************************/
 348
 349 unsigned int speedstep_get_freqs(unsigned int processor,
 350                                   unsigned int *low_speed,
 351                                   unsigned int *high_speed,
 352                                   unsigned int *transition_latency,
 353                                   void (*set_state) (unsigned int state))
 354 {
 355         unsigned int prev_speed;
 356         unsigned int ret = 0;
 357         unsigned long flags;
 358         struct timeval tv1, tv2;
 359
 360         if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
 361                 return -EINVAL;
 362
 363         dprintk("trying to determine both speeds\n");
 364
 365         /* get current speed */
 366         prev_speed = speedstep_get_processor_frequency(processor);
 367         if (!prev_speed)
 368                 return -EIO;
 369
 370         dprintk("previous speed is %u\n", prev_speed);
 371
 372         local_irq_save(flags);
 373
 374         /* switch to low state */
 375         set_state(SPEEDSTEP_LOW);
 376         *low_speed = speedstep_get_processor_frequency(processor);
 377         if (!*low_speed) {
 378                 ret = -EIO;
 379                 goto out;
 380         }
 381
 382         dprintk("low speed is %u\n", *low_speed);
 383
 384         /* start latency measurement */
 385         if (transition_latency)
 386                 do_gettimeofday(&tv1);
 387
 388         /* switch to high state */
 389         set_state(SPEEDSTEP_HIGH);
 390
 391         /* end latency measurement */
 392         if (transition_latency)
 393                 do_gettimeofday(&tv2);
 394
 395         *high_speed = speedstep_get_processor_frequency(processor);
 396         if (!*high_speed) {
 397                 ret = -EIO;
 398                 goto out;
 399         }
 400
 401         dprintk("high speed is %u\n", *high_speed);
 402
 403         if (*low_speed == *high_speed) {
 404                 ret = -ENODEV;
 405                 goto out;
 406         }
 407
 408         /* switch to previous state, if necessary */
 409         if (*high_speed != prev_speed)
 410                 set_state(SPEEDSTEP_LOW);
 411
 412         if (transition_latency) {
 413                 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
 414                         tv2.tv_usec - tv1.tv_usec;
 415                 dprintk("transition latency is %u uSec\n", *transition_latency);
 416
 417                 /* convert uSec to nSec and add 20% for safety reasons */
 418                 *transition_latency *= 1200;
 419
 420                 /* check if the latency measurement is too high or too low
 421                  * and set it to a safe value (500uSec) in that case
 422                  */
 423                 if (*transition_latency > 10000000 || *transition_latency < 50000) {
 424                         printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
 425                                         "range (%u nSec), falling back to a safe one of %u nSec.\n",
 426                                         *transition_latency, 500000);
 427                         *transition_latency = 500000;
 428                 }
 429         }
 430
 431 out:
 432         local_irq_restore(flags);
 433         return (ret);
 434 }
 435 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
 436
 437 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
 438 module_param(relaxed_check, int, 0444);
 439 MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
 440 #endif
 441
 442 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
 443 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
 444 MODULE_LICENSE ("GPL");