Merge HEAD from ../linux-2.6
[linux-2.6] / arch / ppc / platforms / hdpu.c
1
2 /*
3  * arch/ppc/platforms/hdpu_setup.c
4  *
5  * Board setup routines for the Sky Computers HDPU Compute Blade.
6  *
7  * Written by Brian Waite <waite@skycomputers.com>
8  *
9  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
10  *                         Rabeeh Khoury - rabeeh@galileo.co.il
11  *
12  * This program is free software; you can redistribute  it and/or modify it
13  * under  the terms of  the GNU General  Public License as published by the
14  * Free Software Foundation;  either version 2 of the  License, or (at your
15  * option) any later version.
16  */
17
18 #include <linux/config.h>
19
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/irq.h>
23 #include <linux/ide.h>
24 #include <linux/seq_file.h>
25 #include <linux/platform_device.h>
26
27 #include <linux/initrd.h>
28 #include <linux/root_dev.h>
29 #include <linux/smp.h>
30
31 #include <asm/time.h>
32 #include <asm/machdep.h>
33 #include <asm/todc.h>
34 #include <asm/mv64x60.h>
35 #include <asm/ppcboot.h>
36 #include <platforms/hdpu.h>
37 #include <linux/mv643xx.h>
38 #include <linux/hdpu_features.h>
39 #include <linux/device.h>
40 #include <linux/mtd/physmap.h>
41
42 #define BOARD_VENDOR    "Sky Computers"
43 #define BOARD_MACHINE   "HDPU-CB-A"
44
45 bd_t ppcboot_bd;
46 int ppcboot_bd_valid = 0;
47
48 static mv64x60_handle_t bh;
49
50 extern char cmd_line[];
51
52 unsigned long hdpu_find_end_of_memory(void);
53 void hdpu_mpsc_progress(char *s, unsigned short hex);
54 void hdpu_heartbeat(void);
55
56 static void parse_bootinfo(unsigned long r3,
57                            unsigned long r4, unsigned long r5,
58                            unsigned long r6, unsigned long r7);
59 static void hdpu_set_l1pe(void);
60 static void hdpu_cpustate_set(unsigned char new_state);
61 #ifdef CONFIG_SMP
62 static DEFINE_SPINLOCK(timebase_lock);
63 static unsigned int timebase_upper = 0, timebase_lower = 0;
64 extern int smp_tb_synchronized;
65
66 void __devinit hdpu_tben_give(void);
67 void __devinit hdpu_tben_take(void);
68 #endif
69
70 static int __init
71 hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
72 {
73         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
74
75         if (hose->index == 0) {
76                 static char pci_irq_table[][4] = {
77                         {HDPU_PCI_0_IRQ, 0, 0, 0},
78                         {HDPU_PCI_0_IRQ, 0, 0, 0},
79                 };
80
81                 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
82                 return PCI_IRQ_TABLE_LOOKUP;
83         } else {
84                 static char pci_irq_table[][4] = {
85                         {HDPU_PCI_1_IRQ, 0, 0, 0},
86                 };
87
88                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
89                 return PCI_IRQ_TABLE_LOOKUP;
90         }
91 }
92
93 static void __init hdpu_intr_setup(void)
94 {
95         mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
96                       (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
97                        (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
98                        (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
99                        (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
100                        (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
101
102         /* XXXX Erranum FEr PCI-#8 */
103         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
104         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
105
106         /*
107          * Dismiss and then enable interrupt on GPP interrupt cause
108          * for CPU #0
109          */
110         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
111         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
112
113         /*
114          * Dismiss and then enable interrupt on CPU #0 high cause reg
115          * BIT25 summarizes GPP interrupts 8-15
116          */
117         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
118 }
119
120 static void __init hdpu_setup_peripherals(void)
121 {
122         unsigned int val;
123
124         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
125                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
126         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
127
128         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
129                                  HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
130         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
131
132         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
133                                  HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
134         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
135
136         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
137                                  HDPU_INTERNAL_SRAM_BASE,
138                                  HDPU_INTERNAL_SRAM_SIZE, 0);
139         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
140
141         bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
142         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
143
144         mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
145         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
146         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
147                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
148
149         /* Enable pipelining */
150         mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
151         /* Enable Snoop Pipelineing */
152         mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
153
154         /*
155          * Change DRAM read buffer assignment.
156          * Assign read buffer 0 dedicated only for CPU,
157          * and the rest read buffer 1.
158          */
159         val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
160         val = val & 0x03ffffff;
161         val = val | 0xf8000000;
162         mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
163
164         /*
165          * Configure internal SRAM -
166          * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
167          * Parity enabled.
168          * Parity error propagation
169          * Arbitration not parked for CPU only
170          * Other bits are reserved.
171          */
172 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
173         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
174 #else
175         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
176 #endif
177
178         hdpu_intr_setup();
179 }
180
181 static void __init hdpu_setup_bridge(void)
182 {
183         struct mv64x60_setup_info si;
184         int i;
185
186         memset(&si, 0, sizeof(si));
187
188         si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
189         si.pci_0.enable_bus = 1;
190         si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
191         si.pci_0.pci_io.pci_base_hi = 0;
192         si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
193         si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
194         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
195         si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
196         si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
197         si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
198         si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
199         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
200         si.pci_0.pci_cmd_bits = 0;
201         si.pci_0.latency_timer = 0x80;
202
203         si.pci_1.enable_bus = 1;
204         si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
205         si.pci_1.pci_io.pci_base_hi = 0;
206         si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
207         si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
208         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
209         si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
210         si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
211         si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
212         si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
213         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
214         si.pci_1.pci_cmd_bits = 0;
215         si.pci_1.latency_timer = 0x80;
216
217         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
218 #if defined(CONFIG_NOT_COHERENT_CACHE)
219                 si.cpu_prot_options[i] = 0;
220                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
221                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
222                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
223
224                 si.pci_1.acc_cntl_options[i] =
225                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
226                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
227                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
228                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
229
230                 si.pci_0.acc_cntl_options[i] =
231                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
232                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
233                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
234                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
235
236 #else
237                 si.cpu_prot_options[i] = 0;
238                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
239                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
240                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
241
242                 si.pci_0.acc_cntl_options[i] =
243                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
244                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
245                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
246                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
247
248                 si.pci_1.acc_cntl_options[i] =
249                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
250                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
251                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
252                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
253 #endif
254         }
255
256         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
257
258         /* Lookup PCI host bridges */
259         mv64x60_init(&bh, &si);
260         pci_dram_offset = 0;    /* System mem at same addr on PCI & cpu bus */
261         ppc_md.pci_swizzle = common_swizzle;
262         ppc_md.pci_map_irq = hdpu_map_irq;
263
264         mv64x60_set_bus(&bh, 0, 0);
265         bh.hose_a->first_busno = 0;
266         bh.hose_a->last_busno = 0xff;
267         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
268
269         bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
270         mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
271         bh.hose_b->last_busno = 0xff;
272         bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
273                 bh.hose_b->first_busno);
274
275         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
276
277         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
278         /*
279          * Enabling of PCI internal-vs-external arbitration
280          * is a platform- and errata-dependent decision.
281          */
282         return;
283 }
284
285 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
286 static void __init hdpu_early_serial_map(void)
287 {
288 #ifdef  CONFIG_KGDB
289         static char first_time = 1;
290
291 #if defined(CONFIG_KGDB_TTYS0)
292 #define KGDB_PORT 0
293 #elif defined(CONFIG_KGDB_TTYS1)
294 #define KGDB_PORT 1
295 #else
296 #error "Invalid kgdb_tty port"
297 #endif
298
299         if (first_time) {
300                 gt_early_mpsc_init(KGDB_PORT,
301                                    B9600 | CS8 | CREAD | HUPCL | CLOCAL);
302                 first_time = 0;
303         }
304
305         return;
306 #endif
307 }
308 #endif
309
310 static void hdpu_init2(void)
311 {
312         return;
313 }
314
315 #if defined(CONFIG_MV643XX_ETH)
316 static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
317 {
318
319         struct mv643xx_eth_platform_data *eth_pd;
320         eth_pd = pd->dev.platform_data;
321
322         eth_pd->force_phy_addr = 1;
323         eth_pd->phy_addr = pd->id;
324         eth_pd->speed = SPEED_100;
325         eth_pd->duplex = DUPLEX_FULL;
326         eth_pd->tx_queue_size = 400;
327         eth_pd->rx_queue_size = 800;
328 }
329 #endif
330
331 static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
332 {
333
334         struct mpsc_pdata *pdata;
335
336         pdata = (struct mpsc_pdata *)pd->dev.platform_data;
337
338         pdata->max_idle = 40;
339         if (ppcboot_bd_valid)
340                 pdata->default_baud = ppcboot_bd.bi_baudrate;
341         else
342                 pdata->default_baud = HDPU_DEFAULT_BAUD;
343         pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
344         pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
345 }
346
347 #if defined(CONFIG_HDPU_FEATURES)
348 static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
349 {
350         struct platform_device *pds[1];
351         pds[0] = pd;
352         mv64x60_pd_fixup(&bh, pds, 1);
353 }
354 #endif
355
356 static int __init hdpu_platform_notify(struct device *dev)
357 {
358         static struct {
359                 char *bus_id;
360                 void ((*rtn) (struct platform_device * pdev));
361         } dev_map[] = {
362                 {
363                 MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
364 #if defined(CONFIG_MV643XX_ETH)
365                 {
366                 MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
367 #endif
368 #if defined(CONFIG_HDPU_FEATURES)
369                 {
370                 HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
371 #endif
372         };
373         struct platform_device *pdev;
374         int i;
375
376         if (dev && dev->bus_id)
377                 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
378                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
379                                      BUS_ID_SIZE)) {
380
381                                 pdev = container_of(dev,
382                                                     struct platform_device,
383                                                     dev);
384                                 dev_map[i].rtn(pdev);
385                         }
386
387         return 0;
388 }
389
390 static void __init hdpu_setup_arch(void)
391 {
392         if (ppc_md.progress)
393                 ppc_md.progress("hdpu_setup_arch: enter", 0);
394 #ifdef CONFIG_BLK_DEV_INITRD
395         if (initrd_start)
396                 ROOT_DEV = Root_RAM0;
397         else
398 #endif
399 #ifdef  CONFIG_ROOT_NFS
400                 ROOT_DEV = Root_NFS;
401 #else
402                 ROOT_DEV = Root_SDA2;
403 #endif
404
405         ppc_md.heartbeat = hdpu_heartbeat;
406
407         ppc_md.heartbeat_reset = HZ;
408         ppc_md.heartbeat_count = 1;
409
410         if (ppc_md.progress)
411                 ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
412
413         /* Enable L1 Parity Bits */
414         hdpu_set_l1pe();
415
416         /* Enable L2 and L3 caches (if 745x) */
417         _set_L2CR(0x80080000);
418
419         if (ppc_md.progress)
420                 ppc_md.progress("hdpu_setup_arch: enter", 0);
421
422         hdpu_setup_bridge();
423
424         hdpu_setup_peripherals();
425
426 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
427         hdpu_early_serial_map();
428 #endif
429
430         printk("SKY HDPU Compute Blade \n");
431
432         if (ppc_md.progress)
433                 ppc_md.progress("hdpu_setup_arch: exit", 0);
434
435         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
436         return;
437 }
438 static void __init hdpu_init_irq(void)
439 {
440         mv64360_init_irq();
441 }
442
443 static void __init hdpu_set_l1pe()
444 {
445         unsigned long ictrl;
446         asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
447         ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
448         asm volatile ("mtspr 1011, %0"::"r" (ictrl));
449 }
450
451 /*
452  * Set BAT 1 to map 0xf1000000 to end of physical memory space.
453  */
454 static __inline__ void hdpu_set_bat(void)
455 {
456         mb();
457         mtspr(SPRN_DBAT1U, 0xf10001fe);
458         mtspr(SPRN_DBAT1L, 0xf100002a);
459         mb();
460
461         return;
462 }
463
464 unsigned long __init hdpu_find_end_of_memory(void)
465 {
466         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
467                                     MV64x60_TYPE_MV64360);
468 }
469
470 static void hdpu_reset_board(void)
471 {
472         volatile int infinite = 1;
473
474         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
475
476         local_irq_disable();
477
478         /* Clear all the LEDs */
479         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
480                                                    (1 << 5) | (1 << 6)));
481
482         /* disable and invalidate the L2 cache */
483         _set_L2CR(0);
484         _set_L2CR(0x200000);
485
486         /* flush and disable L1 I/D cache */
487         __asm__ __volatile__
488             ("\n"
489              "mfspr   3,1008\n"
490              "ori       5,5,0xcc00\n"
491              "ori       4,3,0xc00\n"
492              "andc      5,3,5\n"
493              "sync\n"
494              "mtspr     1008,4\n"
495              "isync\n" "sync\n" "mtspr  1008,5\n" "isync\n" "sync\n");
496
497         /* Hit the reset bit */
498         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
499
500         while (infinite)
501                 infinite = infinite;
502
503         return;
504 }
505
506 static void hdpu_restart(char *cmd)
507 {
508         volatile ulong i = 10000000;
509
510         hdpu_reset_board();
511
512         while (i-- > 0) ;
513         panic("restart failed\n");
514 }
515
516 static void hdpu_halt(void)
517 {
518         local_irq_disable();
519
520         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
521
522         /* Clear all the LEDs */
523         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
524                                                    (1 << 6)));
525         while (1) ;
526         /* NOTREACHED */
527 }
528
529 static void hdpu_power_off(void)
530 {
531         hdpu_halt();
532         /* NOTREACHED */
533 }
534
535 static int hdpu_show_cpuinfo(struct seq_file *m)
536 {
537         uint pvid;
538
539         pvid = mfspr(SPRN_PVR);
540         seq_printf(m, "vendor\t\t: Sky Computers\n");
541         seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
542         seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
543                    pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
544
545         return 0;
546 }
547
548 static void __init hdpu_calibrate_decr(void)
549 {
550         ulong freq;
551
552         if (ppcboot_bd_valid)
553                 freq = ppcboot_bd.bi_busfreq / 4;
554         else
555                 freq = 133000000;
556
557         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
558                freq / 1000000, freq % 1000000);
559
560         tb_ticks_per_jiffy = freq / HZ;
561         tb_to_us = mulhwu_scale_factor(freq, 1000000);
562
563         return;
564 }
565
566 static void parse_bootinfo(unsigned long r3,
567                            unsigned long r4, unsigned long r5,
568                            unsigned long r6, unsigned long r7)
569 {
570         bd_t *bd = NULL;
571         char *cmdline_start = NULL;
572         int cmdline_len = 0;
573
574         if (r3) {
575                 if ((r3 & 0xf0000000) == 0)
576                         r3 += KERNELBASE;
577                 if ((r3 & 0xf0000000) == KERNELBASE) {
578                         bd = (void *)r3;
579
580                         memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
581                         ppcboot_bd_valid = 1;
582                 }
583         }
584 #ifdef CONFIG_BLK_DEV_INITRD
585         if (r4 && r5 && r5 > r4) {
586                 if ((r4 & 0xf0000000) == 0)
587                         r4 += KERNELBASE;
588                 if ((r5 & 0xf0000000) == 0)
589                         r5 += KERNELBASE;
590                 if ((r4 & 0xf0000000) == KERNELBASE) {
591                         initrd_start = r4;
592                         initrd_end = r5;
593                         initrd_below_start_ok = 1;
594                 }
595         }
596 #endif                          /* CONFIG_BLK_DEV_INITRD */
597
598         if (r6 && r7 && r7 > r6) {
599                 if ((r6 & 0xf0000000) == 0)
600                         r6 += KERNELBASE;
601                 if ((r7 & 0xf0000000) == 0)
602                         r7 += KERNELBASE;
603                 if ((r6 & 0xf0000000) == KERNELBASE) {
604                         cmdline_start = (void *)r6;
605                         cmdline_len = (r7 - r6);
606                         strncpy(cmd_line, cmdline_start, cmdline_len);
607                 }
608         }
609 }
610
611 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
612 static void
613 hdpu_ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
614 {
615         request_region(from, extent, name);
616         return;
617 }
618
619 static void hdpu_ide_release_region(ide_ioreg_t from, unsigned int extent)
620 {
621         release_region(from, extent);
622         return;
623 }
624
625 static void __init
626 hdpu_ide_pci_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
627                              ide_ioreg_t ctrl_port, int *irq)
628 {
629         struct pci_dev *dev;
630
631         pci_for_each_dev(dev) {
632                 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
633                     ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
634                         hw->irq = dev->irq;
635
636                         if (irq != NULL) {
637                                 *irq = dev->irq;
638                         }
639                 }
640         }
641
642         return;
643 }
644 #endif
645
646 void hdpu_heartbeat(void)
647 {
648         if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
649                 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
650         else
651                 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
652
653         ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
654
655 }
656
657 static void __init hdpu_map_io(void)
658 {
659         io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
660 }
661
662 #ifdef CONFIG_SMP
663 char hdpu_smp0[] = "SMP Cpu #0";
664 char hdpu_smp1[] = "SMP Cpu #1";
665
666 static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id,
667                                              struct pt_regs *regs)
668 {
669         volatile unsigned int doorbell;
670
671         doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
672
673         /* Ack the doorbell interrupts */
674         mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
675
676         if (doorbell & 1) {
677                 smp_message_recv(0, regs);
678         }
679         if (doorbell & 2) {
680                 smp_message_recv(1, regs);
681         }
682         if (doorbell & 4) {
683                 smp_message_recv(2, regs);
684         }
685         if (doorbell & 8) {
686                 smp_message_recv(3, regs);
687         }
688         return IRQ_HANDLED;
689 }
690
691 static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id,
692                                              struct pt_regs *regs)
693 {
694         volatile unsigned int doorbell;
695
696         doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
697
698         /* Ack the doorbell interrupts */
699         mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
700
701         if (doorbell & 1) {
702                 smp_message_recv(0, regs);
703         }
704         if (doorbell & 2) {
705                 smp_message_recv(1, regs);
706         }
707         if (doorbell & 4) {
708                 smp_message_recv(2, regs);
709         }
710         if (doorbell & 8) {
711                 smp_message_recv(3, regs);
712         }
713         return IRQ_HANDLED;
714 }
715
716 static void smp_hdpu_CPU_two(void)
717 {
718         __asm__ __volatile__
719             ("\n"
720              "lis     3,0x0000\n"
721              "ori     3,3,0x00c0\n"
722              "mtspr   26, 3\n" "li      4,0\n" "mtspr   27,4\n" "rfi");
723
724 }
725
726 static int smp_hdpu_probe(void)
727 {
728         int *cpu_count_reg;
729         int num_cpus = 0;
730
731         cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
732         if (cpu_count_reg) {
733                 num_cpus = (*cpu_count_reg >> 20) & 0x3;
734                 iounmap(cpu_count_reg);
735         }
736
737         /* Validate the bits in the CPLD. If we could not map the reg, return 2.
738          * If the register reported 0 or 3, return 2.
739          * Older CPLD revisions set these bits to all ones (val = 3).
740          */
741         if ((num_cpus < 1) || (num_cpus > 2)) {
742                 printk
743                     ("Unable to determine the number of processors %d . deafulting to 2.\n",
744                      num_cpus);
745                 num_cpus = 2;
746         }
747         return num_cpus;
748 }
749
750 static void
751 smp_hdpu_message_pass(int target, int msg)
752 {
753         if (msg > 0x3) {
754                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
755                        smp_processor_id(), msg);
756                 return;
757         }
758         switch (target) {
759         case MSG_ALL:
760                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
761                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
762                 break;
763         case MSG_ALL_BUT_SELF:
764                 if (smp_processor_id())
765                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
766                 else
767                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
768                 break;
769         default:
770                 if (target == 0)
771                         mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
772                 else
773                         mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
774                 break;
775         }
776 }
777
778 static void smp_hdpu_kick_cpu(int nr)
779 {
780         volatile unsigned int *bootaddr;
781
782         if (ppc_md.progress)
783                 ppc_md.progress("smp_hdpu_kick_cpu", 0);
784
785         hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
786
787        /* Disable BootCS. Must also reduce the windows size to zero. */
788         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
789         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
790
791         bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
792         if (!bootaddr) {
793                 if (ppc_md.progress)
794                         ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
795                 return;
796         }
797
798         memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
799
800         /* map SRAM to 0xfff00000 */
801         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
802
803         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
804                                  0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
805         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
806
807         /* Enable CPU1 arbitration */
808         mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
809
810         /*
811          * Wait 100mSecond until other CPU has reached __secondary_start.
812          * When it reaches, it is permittable to rever the SRAM mapping etc...
813          */
814         mdelay(100);
815         *(unsigned long *)KERNELBASE = nr;
816         asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
817
818         iounmap(bootaddr);
819
820         /* Set up window for internal sram (256KByte insize) */
821         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
822         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
823                                  HDPU_INTERNAL_SRAM_BASE,
824                                  HDPU_INTERNAL_SRAM_SIZE, 0);
825         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
826         /*
827          * Set up windows for embedded FLASH (using boot CS window).
828          */
829
830         bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
831         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
832                                  HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
833         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
834 }
835
836 static void smp_hdpu_setup_cpu(int cpu_nr)
837 {
838         if (cpu_nr == 0) {
839                 if (ppc_md.progress)
840                         ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
841                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
842                 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
843                 request_irq(60, hdpu_smp_cpu0_int_handler,
844                             SA_INTERRUPT, hdpu_smp0, 0);
845         }
846
847         if (cpu_nr == 1) {
848                 if (ppc_md.progress)
849                         ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
850
851                 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
852                                   CPUSTATE_KERNEL_CPU1_OK);
853
854                 /* Enable L1 Parity Bits */
855                 hdpu_set_l1pe();
856
857                 /* Enable L2 cache */
858                 _set_L2CR(0);
859                 _set_L2CR(0x80080000);
860
861                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
862                 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
863                 request_irq(28, hdpu_smp_cpu1_int_handler,
864                             SA_INTERRUPT, hdpu_smp1, 0);
865         }
866
867 }
868
869 void __devinit hdpu_tben_give()
870 {
871         volatile unsigned long *val = 0;
872
873         /* By writing 0 to the TBEN_BASE, the timebases is frozen */
874         val = ioremap(HDPU_TBEN_BASE, 4);
875         *val = 0;
876         mb();
877
878         spin_lock(&timebase_lock);
879         timebase_upper = get_tbu();
880         timebase_lower = get_tbl();
881         spin_unlock(&timebase_lock);
882
883         while (timebase_upper || timebase_lower)
884                 barrier();
885
886         /* By writing 1 to the TBEN_BASE, the timebases is thawed */
887         *val = 1;
888         mb();
889
890         iounmap(val);
891
892 }
893
894 void __devinit hdpu_tben_take()
895 {
896         while (!(timebase_upper || timebase_lower))
897                 barrier();
898
899         spin_lock(&timebase_lock);
900         set_tb(timebase_upper, timebase_lower);
901         timebase_upper = 0;
902         timebase_lower = 0;
903         spin_unlock(&timebase_lock);
904 }
905
906 static struct smp_ops_t hdpu_smp_ops = {
907         .message_pass = smp_hdpu_message_pass,
908         .probe = smp_hdpu_probe,
909         .kick_cpu = smp_hdpu_kick_cpu,
910         .setup_cpu = smp_hdpu_setup_cpu,
911         .give_timebase = hdpu_tben_give,
912         .take_timebase = hdpu_tben_take,
913 };
914 #endif                          /* CONFIG_SMP */
915
916 void __init
917 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
918               unsigned long r6, unsigned long r7)
919 {
920         parse_bootinfo(r3, r4, r5, r6, r7);
921
922         isa_mem_base = 0;
923
924         ppc_md.setup_arch = hdpu_setup_arch;
925         ppc_md.init = hdpu_init2;
926         ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
927         ppc_md.init_IRQ = hdpu_init_irq;
928         ppc_md.get_irq = mv64360_get_irq;
929         ppc_md.restart = hdpu_restart;
930         ppc_md.power_off = hdpu_power_off;
931         ppc_md.halt = hdpu_halt;
932         ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
933         ppc_md.calibrate_decr = hdpu_calibrate_decr;
934         ppc_md.setup_io_mappings = hdpu_map_io;
935
936         bh.p_base = CONFIG_MV64X60_NEW_BASE;
937         bh.v_base = (unsigned long *)bh.p_base;
938
939         hdpu_set_bat();
940
941 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
942         ppc_md.progress = hdpu_mpsc_progress;   /* embedded UART */
943         mv64x60_progress_init(bh.p_base);
944 #endif                          /* CONFIG_SERIAL_TEXT_DEBUG */
945
946 #ifdef CONFIG_SMP
947         smp_ops = &hdpu_smp_ops;
948 #endif                          /* CONFIG_SMP */
949
950 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
951         platform_notify = hdpu_platform_notify;
952 #endif
953         return;
954 }
955
956 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
957 /* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
958 void hdpu_mpsc_progress(char *s, unsigned short hex)
959 {
960         while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
961                mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
962         }
963         mv64x60_mpsc_progress(s, hex);
964         mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
965 }
966 #endif
967
968 static void hdpu_cpustate_set(unsigned char new_state)
969 {
970         unsigned int state = (new_state << 21);
971         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
972         mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
973 }
974
975 #ifdef CONFIG_MTD_PHYSMAP
976 static struct mtd_partition hdpu_partitions[] = {
977         {
978          .name = "Root FS",
979          .size = 0x03400000,
980          .offset = 0,
981          .mask_flags = 0,
982          },{
983          .name = "User FS",
984          .size = 0x00800000,
985          .offset = 0x03400000,
986          .mask_flags = 0,
987          },{
988          .name = "Kernel Image",
989          .size = 0x002C0000,
990          .offset = 0x03C00000,
991          .mask_flags = 0,
992          },{
993          .name = "bootEnv",
994          .size = 0x00040000,
995          .offset = 0x03EC0000,
996          .mask_flags = 0,
997          },{
998          .name = "bootROM",
999          .size = 0x00100000,
1000          .offset = 0x03F00000,
1001          .mask_flags = 0,
1002          }
1003 };
1004
1005 static int __init hdpu_setup_mtd(void)
1006 {
1007
1008         physmap_set_partitions(hdpu_partitions, 5);
1009         return 0;
1010 }
1011
1012 arch_initcall(hdpu_setup_mtd);
1013 #endif
1014
1015 #ifdef CONFIG_HDPU_FEATURES
1016
1017 static struct resource hdpu_cpustate_resources[] = {
1018         [0] = {
1019                .name = "addr base",
1020                .start = MV64x60_GPP_VALUE_SET,
1021                .end = MV64x60_GPP_VALUE_CLR + 1,
1022                .flags = IORESOURCE_MEM,
1023                },
1024 };
1025
1026 static struct resource hdpu_nexus_resources[] = {
1027         [0] = {
1028                .name = "nexus register",
1029                .start = HDPU_NEXUS_ID_BASE,
1030                .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
1031                .flags = IORESOURCE_MEM,
1032                },
1033 };
1034
1035 static struct platform_device hdpu_cpustate_device = {
1036         .name = HDPU_CPUSTATE_NAME,
1037         .id = 0,
1038         .num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
1039         .resource = hdpu_cpustate_resources,
1040 };
1041
1042 static struct platform_device hdpu_nexus_device = {
1043         .name = HDPU_NEXUS_NAME,
1044         .id = 0,
1045         .num_resources = ARRAY_SIZE(hdpu_nexus_resources),
1046         .resource = hdpu_nexus_resources,
1047 };
1048
1049 static int __init hdpu_add_pds(void)
1050 {
1051         platform_device_register(&hdpu_cpustate_device);
1052         platform_device_register(&hdpu_nexus_device);
1053         return 0;
1054 }
1055
1056 arch_initcall(hdpu_add_pds);
1057 #endif