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   1 /*
   2  *  linux/arch/arm/mm/mm-armv.c
   3  *
   4  *  Copyright (C) 1998-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  Page table sludge for ARM v3 and v4 processor architectures.
  11  */
  12 #include <linux/config.h>
  13 #include <linux/module.h>
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17 #include <linux/highmem.h>
  18 #include <linux/nodemask.h>
  19
  20 #include <asm/pgalloc.h>
  21 #include <asm/page.h>
  22 #include <asm/io.h>
  23 #include <asm/setup.h>
  24 #include <asm/tlbflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #define CPOLICY_UNCACHED        0
  29 #define CPOLICY_BUFFERED        1
  30 #define CPOLICY_WRITETHROUGH    2
  31 #define CPOLICY_WRITEBACK       3
  32 #define CPOLICY_WRITEALLOC      4
  33
  34 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  35 static unsigned int ecc_mask __initdata = 0;
  36 pgprot_t pgprot_kernel;
  37
  38 EXPORT_SYMBOL(pgprot_kernel);
  39
  40 pmd_t *top_pmd;
  41
  42 struct cachepolicy {
  43         const char      policy[16];
  44         unsigned int    cr_mask;
  45         unsigned int    pmd;
  46         unsigned int    pte;
  47 };
  48
  49 static struct cachepolicy cache_policies[] __initdata = {
  50         {
  51                 .policy         = "uncached",
  52                 .cr_mask        = CR_W|CR_C,
  53                 .pmd            = PMD_SECT_UNCACHED,
  54                 .pte            = 0,
  55         }, {
  56                 .policy         = "buffered",
  57                 .cr_mask        = CR_C,
  58                 .pmd            = PMD_SECT_BUFFERED,
  59                 .pte            = PTE_BUFFERABLE,
  60         }, {
  61                 .policy         = "writethrough",
  62                 .cr_mask        = 0,
  63                 .pmd            = PMD_SECT_WT,
  64                 .pte            = PTE_CACHEABLE,
  65         }, {
  66                 .policy         = "writeback",
  67                 .cr_mask        = 0,
  68                 .pmd            = PMD_SECT_WB,
  69                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  70         }, {
  71                 .policy         = "writealloc",
  72                 .cr_mask        = 0,
  73                 .pmd            = PMD_SECT_WBWA,
  74                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  75         }
  76 };
  77
  78 /*
  79  * These are useful for identifing cache coherency
  80  * problems by allowing the cache or the cache and
  81  * writebuffer to be turned off.  (Note: the write
  82  * buffer should not be on and the cache off).
  83  */
  84 static void __init early_cachepolicy(char **p)
  85 {
  86         int i;
  87
  88         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
  89                 int len = strlen(cache_policies[i].policy);
  90
  91                 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
  92                         cachepolicy = i;
  93                         cr_alignment &= ~cache_policies[i].cr_mask;
  94                         cr_no_alignment &= ~cache_policies[i].cr_mask;
  95                         *p += len;
  96                         break;
  97                 }
  98         }
  99         if (i == ARRAY_SIZE(cache_policies))
 100                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 101         flush_cache_all();
 102         set_cr(cr_alignment);
 103 }
 104
 105 static void __init early_nocache(char **__unused)
 106 {
 107         char *p = "buffered";
 108         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 109         early_cachepolicy(&p);
 110 }
 111
 112 static void __init early_nowrite(char **__unused)
 113 {
 114         char *p = "uncached";
 115         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 116         early_cachepolicy(&p);
 117 }
 118
 119 static void __init early_ecc(char **p)
 120 {
 121         if (memcmp(*p, "on", 2) == 0) {
 122                 ecc_mask = PMD_PROTECTION;
 123                 *p += 2;
 124         } else if (memcmp(*p, "off", 3) == 0) {
 125                 ecc_mask = 0;
 126                 *p += 3;
 127         }
 128 }
 129
 130 __early_param("nocache", early_nocache);
 131 __early_param("nowb", early_nowrite);
 132 __early_param("cachepolicy=", early_cachepolicy);
 133 __early_param("ecc=", early_ecc);
 134
 135 static int __init noalign_setup(char *__unused)
 136 {
 137         cr_alignment &= ~CR_A;
 138         cr_no_alignment &= ~CR_A;
 139         set_cr(cr_alignment);
 140         return 1;
 141 }
 142
 143 __setup("noalign", noalign_setup);
 144
 145 #define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
 146
 147 static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
 148 {
 149         return pmd_offset(pgd, virt);
 150 }
 151
 152 static inline pmd_t *pmd_off_k(unsigned long virt)
 153 {
 154         return pmd_off(pgd_offset_k(virt), virt);
 155 }
 156
 157 /*
 158  * need to get a 16k page for level 1
 159  */
 160 pgd_t *get_pgd_slow(struct mm_struct *mm)
 161 {
 162         pgd_t *new_pgd, *init_pgd;
 163         pmd_t *new_pmd, *init_pmd;
 164         pte_t *new_pte, *init_pte;
 165
 166         new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
 167         if (!new_pgd)
 168                 goto no_pgd;
 169
 170         memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
 171
 172         /*
 173          * Copy over the kernel and IO PGD entries
 174          */
 175         init_pgd = pgd_offset_k(0);
 176         memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
 177                        (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
 178
 179         clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
 180
 181         if (!vectors_high()) {
 182                 /*
 183                  * This lock is here just to satisfy pmd_alloc and pte_lock
 184                  */
 185                 spin_lock(&mm->page_table_lock);
 186
 187                 /*
 188                  * On ARM, first page must always be allocated since it
 189                  * contains the machine vectors.
 190                  */
 191                 new_pmd = pmd_alloc(mm, new_pgd, 0);
 192                 if (!new_pmd)
 193                         goto no_pmd;
 194
 195                 new_pte = pte_alloc_map(mm, new_pmd, 0);
 196                 if (!new_pte)
 197                         goto no_pte;
 198
 199                 init_pmd = pmd_offset(init_pgd, 0);
 200                 init_pte = pte_offset_map_nested(init_pmd, 0);
 201                 set_pte(new_pte, *init_pte);
 202                 pte_unmap_nested(init_pte);
 203                 pte_unmap(new_pte);
 204
 205                 spin_unlock(&mm->page_table_lock);
 206         }
 207
 208         return new_pgd;
 209
 210 no_pte:
 211         spin_unlock(&mm->page_table_lock);
 212         pmd_free(new_pmd);
 213         free_pages((unsigned long)new_pgd, 2);
 214         return NULL;
 215
 216 no_pmd:
 217         spin_unlock(&mm->page_table_lock);
 218         free_pages((unsigned long)new_pgd, 2);
 219         return NULL;
 220
 221 no_pgd:
 222         return NULL;
 223 }
 224
 225 void free_pgd_slow(pgd_t *pgd)
 226 {
 227         pmd_t *pmd;
 228         struct page *pte;
 229
 230         if (!pgd)
 231                 return;
 232
 233         /* pgd is always present and good */
 234         pmd = pmd_off(pgd, 0);
 235         if (pmd_none(*pmd))
 236                 goto free;
 237         if (pmd_bad(*pmd)) {
 238                 pmd_ERROR(*pmd);
 239                 pmd_clear(pmd);
 240                 goto free;
 241         }
 242
 243         pte = pmd_page(*pmd);
 244         pmd_clear(pmd);
 245         dec_page_state(nr_page_table_pages);
 246         pte_free(pte);
 247         pmd_free(pmd);
 248 free:
 249         free_pages((unsigned long) pgd, 2);
 250 }
 251
 252 /*
 253  * Create a SECTION PGD between VIRT and PHYS in domain
 254  * DOMAIN with protection PROT.  This operates on half-
 255  * pgdir entry increments.
 256  */
 257 static inline void
 258 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 259 {
 260         pmd_t *pmdp = pmd_off_k(virt);
 261
 262         if (virt & (1 << 20))
 263                 pmdp++;
 264
 265         *pmdp = __pmd(phys | prot);
 266         flush_pmd_entry(pmdp);
 267 }
 268
 269 /*
 270  * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
 271  */
 272 static inline void
 273 alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
 274 {
 275         int i;
 276
 277         for (i = 0; i < 16; i += 1) {
 278                 alloc_init_section(virt, phys & SUPERSECTION_MASK,
 279                                    prot | PMD_SECT_SUPER);
 280
 281                 virt += (PGDIR_SIZE / 2);
 282                 phys += (PGDIR_SIZE / 2);
 283         }
 284 }
 285
 286 /*
 287  * Add a PAGE mapping between VIRT and PHYS in domain
 288  * DOMAIN with protection PROT.  Note that due to the
 289  * way we map the PTEs, we must allocate two PTE_SIZE'd
 290  * blocks - one for the Linux pte table, and one for
 291  * the hardware pte table.
 292  */
 293 static inline void
 294 alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
 295 {
 296         pmd_t *pmdp = pmd_off_k(virt);
 297         pte_t *ptep;
 298
 299         if (pmd_none(*pmdp)) {
 300                 unsigned long pmdval;
 301                 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
 302                                                sizeof(pte_t));
 303
 304                 pmdval = __pa(ptep) | prot_l1;
 305                 pmdp[0] = __pmd(pmdval);
 306                 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
 307                 flush_pmd_entry(pmdp);
 308         }
 309         ptep = pte_offset_kernel(pmdp, virt);
 310
 311         set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 312 }
 313
 314 /*
 315  * Clear any PGD mapping.  On a two-level page table system,
 316  * the clearance is done by the middle-level functions (pmd)
 317  * rather than the top-level (pgd) functions.
 318  */
 319 static inline void clear_mapping(unsigned long virt)
 320 {
 321         pmd_clear(pmd_off_k(virt));
 322 }
 323
 324 struct mem_types {
 325         unsigned int    prot_pte;
 326         unsigned int    prot_l1;
 327         unsigned int    prot_sect;
 328         unsigned int    domain;
 329 };
 330
 331 static struct mem_types mem_types[] __initdata = {
 332         [MT_DEVICE] = {
 333                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 334                                 L_PTE_WRITE,
 335                 .prot_l1   = PMD_TYPE_TABLE,
 336                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 337                                 PMD_SECT_AP_WRITE,
 338                 .domain    = DOMAIN_IO,
 339         },
 340         [MT_CACHECLEAN] = {
 341                 .prot_sect = PMD_TYPE_SECT,
 342                 .domain    = DOMAIN_KERNEL,
 343         },
 344         [MT_MINICLEAN] = {
 345                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
 346                 .domain    = DOMAIN_KERNEL,
 347         },
 348         [MT_LOW_VECTORS] = {
 349                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 350                                 L_PTE_EXEC,
 351                 .prot_l1   = PMD_TYPE_TABLE,
 352                 .domain    = DOMAIN_USER,
 353         },
 354         [MT_HIGH_VECTORS] = {
 355                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 356                                 L_PTE_USER | L_PTE_EXEC,
 357                 .prot_l1   = PMD_TYPE_TABLE,
 358                 .domain    = DOMAIN_USER,
 359         },
 360         [MT_MEMORY] = {
 361                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 362                 .domain    = DOMAIN_KERNEL,
 363         },
 364         [MT_ROM] = {
 365                 .prot_sect = PMD_TYPE_SECT,
 366                 .domain    = DOMAIN_KERNEL,
 367         },
 368         [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
 369                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 370                                 L_PTE_WRITE,
 371                 .prot_l1   = PMD_TYPE_TABLE,
 372                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 373                                 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
 374                                 PMD_SECT_TEX(1),
 375                 .domain    = DOMAIN_IO,
 376         }
 377 };
 378
 379 /*
 380  * Adjust the PMD section entries according to the CPU in use.
 381  */
 382 static void __init build_mem_type_table(void)
 383 {
 384         struct cachepolicy *cp;
 385         unsigned int cr = get_cr();
 386         int cpu_arch = cpu_architecture();
 387         int i;
 388
 389 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 390         if (cachepolicy > CPOLICY_BUFFERED)
 391                 cachepolicy = CPOLICY_BUFFERED;
 392 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 393         if (cachepolicy > CPOLICY_WRITETHROUGH)
 394                 cachepolicy = CPOLICY_WRITETHROUGH;
 395 #endif
 396         if (cpu_arch < CPU_ARCH_ARMv5) {
 397                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 398                         cachepolicy = CPOLICY_WRITEBACK;
 399                 ecc_mask = 0;
 400         }
 401
 402         if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
 403                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 404                         if (mem_types[i].prot_l1)
 405                                 mem_types[i].prot_l1 |= PMD_BIT4;
 406                         if (mem_types[i].prot_sect)
 407                                 mem_types[i].prot_sect |= PMD_BIT4;
 408                 }
 409         }
 410
 411         /*
 412          * ARMv6 and above have extended page tables.
 413          */
 414         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 415                 /*
 416                  * bit 4 becomes XN which we must clear for the
 417                  * kernel memory mapping.
 418                  */
 419                 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;
 420                 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;
 421                 /*
 422                  * Mark cache clean areas and XIP ROM read only
 423                  * from SVC mode and no access from userspace.
 424                  */
 425                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 426                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 427                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 428
 429                 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
 430                 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 431         }
 432
 433         cp = &cache_policies[cachepolicy];
 434
 435         if (cpu_arch >= CPU_ARCH_ARMv5) {
 436                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
 437                 mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
 438         } else {
 439                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte;
 440                 mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte;
 441                 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
 442         }
 443
 444         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 445         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 446         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 447         mem_types[MT_ROM].prot_sect |= cp->pmd;
 448
 449         for (i = 0; i < 16; i++) {
 450                 unsigned long v = pgprot_val(protection_map[i]);
 451                 v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte;
 452                 protection_map[i] = __pgprot(v);
 453         }
 454
 455         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 456                                  L_PTE_DIRTY | L_PTE_WRITE |
 457                                  L_PTE_EXEC | cp->pte);
 458
 459         switch (cp->pmd) {
 460         case PMD_SECT_WT:
 461                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 462                 break;
 463         case PMD_SECT_WB:
 464         case PMD_SECT_WBWA:
 465                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 466                 break;
 467         }
 468         printk("Memory policy: ECC %sabled, Data cache %s\n",
 469                 ecc_mask ? "en" : "dis", cp->policy);
 470 }
 471
 472 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 473
 474 /*
 475  * Create the page directory entries and any necessary
 476  * page tables for the mapping specified by `md'.  We
 477  * are able to cope here with varying sizes and address
 478  * offsets, and we take full advantage of sections and
 479  * supersections.
 480  */
 481 static void __init create_mapping(struct map_desc *md)
 482 {
 483         unsigned long virt, length;
 484         int prot_sect, prot_l1, domain;
 485         pgprot_t prot_pte;
 486         long off;
 487
 488         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 489                 printk(KERN_WARNING "BUG: not creating mapping for "
 490                        "0x%08lx at 0x%08lx in user region\n",
 491                        md->physical, md->virtual);
 492                 return;
 493         }
 494
 495         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 496             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 497                 printk(KERN_WARNING "BUG: mapping for 0x%08lx at 0x%08lx "
 498                        "overlaps vmalloc space\n",
 499                        md->physical, md->virtual);
 500         }
 501
 502         domain    = mem_types[md->type].domain;
 503         prot_pte  = __pgprot(mem_types[md->type].prot_pte);
 504         prot_l1   = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
 505         prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
 506
 507         virt   = md->virtual;
 508         off    = md->physical - virt;
 509         length = md->length;
 510
 511         if (mem_types[md->type].prot_l1 == 0 &&
 512             (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
 513                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 514                        "be mapped using pages, ignoring.\n",
 515                        md->physical, md->virtual);
 516                 return;
 517         }
 518
 519         while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
 520                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 521
 522                 virt   += PAGE_SIZE;
 523                 length -= PAGE_SIZE;
 524         }
 525
 526         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 527          *      Since domain assignments can in fact be arbitrary, the
 528          *      'domain == 0' check below is required to insure that ARMv6
 529          *      supersections are only allocated for domain 0 regardless
 530          *      of the actual domain assignments in use.
 531          */
 532         if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) {
 533                 /* Align to supersection boundary */
 534                 while ((virt & ~SUPERSECTION_MASK || (virt + off) &
 535                         ~SUPERSECTION_MASK) && length >= (PGDIR_SIZE / 2)) {
 536                         alloc_init_section(virt, virt + off, prot_sect);
 537
 538                         virt   += (PGDIR_SIZE / 2);
 539                         length -= (PGDIR_SIZE / 2);
 540                 }
 541
 542                 while (length >= SUPERSECTION_SIZE) {
 543                         alloc_init_supersection(virt, virt + off, prot_sect);
 544
 545                         virt   += SUPERSECTION_SIZE;
 546                         length -= SUPERSECTION_SIZE;
 547                 }
 548         }
 549
 550         /*
 551          * A section mapping covers half a "pgdir" entry.
 552          */
 553         while (length >= (PGDIR_SIZE / 2)) {
 554                 alloc_init_section(virt, virt + off, prot_sect);
 555
 556                 virt   += (PGDIR_SIZE / 2);
 557                 length -= (PGDIR_SIZE / 2);
 558         }
 559
 560         while (length >= PAGE_SIZE) {
 561                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 562
 563                 virt   += PAGE_SIZE;
 564                 length -= PAGE_SIZE;
 565         }
 566 }
 567
 568 /*
 569  * In order to soft-boot, we need to insert a 1:1 mapping in place of
 570  * the user-mode pages.  This will then ensure that we have predictable
 571  * results when turning the mmu off
 572  */
 573 void setup_mm_for_reboot(char mode)
 574 {
 575         unsigned long pmdval;
 576         pgd_t *pgd;
 577         pmd_t *pmd;
 578         int i;
 579         int cpu_arch = cpu_architecture();
 580
 581         if (current->mm && current->mm->pgd)
 582                 pgd = current->mm->pgd;
 583         else
 584                 pgd = init_mm.pgd;
 585
 586         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
 587                 pmdval = (i << PGDIR_SHIFT) |
 588                          PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
 589                          PMD_TYPE_SECT;
 590                 if (cpu_arch <= CPU_ARCH_ARMv5TEJ)
 591                         pmdval |= PMD_BIT4;
 592                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
 593                 pmd[0] = __pmd(pmdval);
 594                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
 595                 flush_pmd_entry(pmd);
 596         }
 597 }
 598
 599 extern void _stext, _etext;
 600
 601 /*
 602  * Setup initial mappings.  We use the page we allocated for zero page to hold
 603  * the mappings, which will get overwritten by the vectors in traps_init().
 604  * The mappings must be in virtual address order.
 605  */
 606 void __init memtable_init(struct meminfo *mi)
 607 {
 608         struct map_desc *init_maps, *p, *q;
 609         unsigned long address = 0;
 610         int i;
 611
 612         build_mem_type_table();
 613
 614         init_maps = p = alloc_bootmem_low_pages(PAGE_SIZE);
 615
 616 #ifdef CONFIG_XIP_KERNEL
 617         p->physical   = CONFIG_XIP_PHYS_ADDR & PMD_MASK;
 618         p->virtual    = (unsigned long)&_stext & PMD_MASK;
 619         p->length     = ((unsigned long)&_etext - p->virtual + ~PMD_MASK) & PMD_MASK;
 620         p->type       = MT_ROM;
 621         p ++;
 622 #endif
 623
 624         for (i = 0; i < mi->nr_banks; i++) {
 625                 if (mi->bank[i].size == 0)
 626                         continue;
 627
 628                 p->physical   = mi->bank[i].start;
 629                 p->virtual    = __phys_to_virt(p->physical);
 630                 p->length     = mi->bank[i].size;
 631                 p->type       = MT_MEMORY;
 632                 p ++;
 633         }
 634
 635 #ifdef FLUSH_BASE
 636         p->physical   = FLUSH_BASE_PHYS;
 637         p->virtual    = FLUSH_BASE;
 638         p->length     = PGDIR_SIZE;
 639         p->type       = MT_CACHECLEAN;
 640         p ++;
 641 #endif
 642
 643 #ifdef FLUSH_BASE_MINICACHE
 644         p->physical   = FLUSH_BASE_PHYS + PGDIR_SIZE;
 645         p->virtual    = FLUSH_BASE_MINICACHE;
 646         p->length     = PGDIR_SIZE;
 647         p->type       = MT_MINICLEAN;
 648         p ++;
 649 #endif
 650
 651         /*
 652          * Go through the initial mappings, but clear out any
 653          * pgdir entries that are not in the description.
 654          */
 655         q = init_maps;
 656         do {
 657                 if (address < q->virtual || q == p) {
 658                         clear_mapping(address);
 659                         address += PGDIR_SIZE;
 660                 } else {
 661                         create_mapping(q);
 662
 663                         address = q->virtual + q->length;
 664                         address = (address + PGDIR_SIZE - 1) & PGDIR_MASK;
 665
 666                         q ++;
 667                 }
 668         } while (address != 0);
 669
 670         /*
 671          * Create a mapping for the machine vectors at the high-vectors
 672          * location (0xffff0000).  If we aren't using high-vectors, also
 673          * create a mapping at the low-vectors virtual address.
 674          */
 675         init_maps->physical   = virt_to_phys(init_maps);
 676         init_maps->virtual    = 0xffff0000;
 677         init_maps->length     = PAGE_SIZE;
 678         init_maps->type       = MT_HIGH_VECTORS;
 679         create_mapping(init_maps);
 680
 681         if (!vectors_high()) {
 682                 init_maps->virtual = 0;
 683                 init_maps->type = MT_LOW_VECTORS;
 684                 create_mapping(init_maps);
 685         }
 686
 687         flush_cache_all();
 688         local_flush_tlb_all();
 689
 690         top_pmd = pmd_off_k(0xffff0000);
 691 }
 692
 693 /*
 694  * Create the architecture specific mappings
 695  */
 696 void __init iotable_init(struct map_desc *io_desc, int nr)
 697 {
 698         int i;
 699
 700         for (i = 0; i < nr; i++)
 701                 create_mapping(io_desc + i);
 702 }