git.oblomov.eu Git - linux-2.6/blob - sound/pci/intel8x0.c

   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/moduleparam.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/ac97_codec.h>
  40 #include <sound/info.h>
  41 #include <sound/initval.h>
  42 /* for 440MX workaround */
  43 #include <asm/pgtable.h>
  44 #include <asm/cacheflush.h>
  45
  46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  50                 "{Intel,82901AB-ICH0},"
  51                 "{Intel,82801BA-ICH2},"
  52                 "{Intel,82801CA-ICH3},"
  53                 "{Intel,82801DB-ICH4},"
  54                 "{Intel,ICH5},"
  55                 "{Intel,ICH6},"
  56                 "{Intel,ICH7},"
  57                 "{Intel,6300ESB},"
  58                 "{Intel,ESB2},"
  59                 "{Intel,MX440},"
  60                 "{SiS,SI7012},"
  61                 "{NVidia,nForce Audio},"
  62                 "{NVidia,nForce2 Audio},"
  63                 "{AMD,AMD768},"
  64                 "{AMD,AMD8111},"
  65                 "{ALI,M5455}}");
  66
  67 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  68 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  69 static int ac97_clock = 0;
  70 static char *ac97_quirk;
  71 static int buggy_semaphore;
  72 static int buggy_irq = -1; /* auto-check */
  73 static int xbox;
  74
  75 module_param(index, int, 0444);
  76 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  77 module_param(id, charp, 0444);
  78 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  79 module_param(ac97_clock, int, 0444);
  80 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  81 module_param(ac97_quirk, charp, 0444);
  82 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  83 module_param(buggy_semaphore, bool, 0444);
  84 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  85 module_param(buggy_irq, bool, 0444);
  86 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  87 module_param(xbox, bool, 0444);
  88 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  89
  90 /* just for backward compatibility */
  91 static int enable;
  92 module_param(enable, bool, 0444);
  93 static int joystick;
  94 module_param(joystick, int, 0444);
  95
  96 /*
  97  *  Direct registers
  98  */
  99 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 100
 101 #define ICHREG(x) ICH_REG_##x
 102
 103 #define DEFINE_REGSET(name,base) \
 104 enum { \
 105         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 106         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 107         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 108         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 109         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 110         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 111         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 112 };
 113
 114 /* busmaster blocks */
 115 DEFINE_REGSET(OFF, 0);          /* offset */
 116 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 117 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 118 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 119
 120 /* ICH4 busmaster blocks */
 121 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 122 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 123 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 124
 125 /* values for each busmaster block */
 126
 127 /* LVI */
 128 #define ICH_REG_LVI_MASK                0x1f
 129
 130 /* SR */
 131 #define ICH_FIFOE                       0x10    /* FIFO error */
 132 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 133 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 134 #define ICH_CELV                        0x02    /* current equals last valid */
 135 #define ICH_DCH                         0x01    /* DMA controller halted */
 136
 137 /* PIV */
 138 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 139
 140 /* CR */
 141 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 142 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 143 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 144 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 145 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 146
 147
 148 /* global block */
 149 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 150 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 151 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 152 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 153 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 154 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 155 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 156 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 157 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 158 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 159 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 160 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 161 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 162 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 163 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 164 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 165 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 166 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 167 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 168 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 169 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 170 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 171 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 172 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 173 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 174 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 175 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 176 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 177 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 178 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 179 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 180 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 181 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 182 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 183 #define   ICH_RCS               0x00008000      /* read completion status */
 184 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 185 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 186 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 187 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 188 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 189 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 190 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 191 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 192 #define   ICH_POINT             0x00000040      /* playback interrupt */
 193 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 194 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 195 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 196 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 197 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 198 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 199 #define   ICH_CAS               0x01            /* codec access semaphore */
 200 #define ICH_REG_SDM             0x80
 201 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 202 #define   ICH_DI2L_SHIFT        6
 203 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 204 #define   ICH_DI1L_SHIFT        4
 205 #define   ICH_SE                0x00000008      /* steer enable */
 206 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 207
 208 #define ICH_MAX_FRAGS           32              /* max hw frags */
 209
 210
 211 /*
 212  * registers for Ali5455
 213  */
 214
 215 /* ALi 5455 busmaster blocks */
 216 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 217 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 218 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 219 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 220 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 221 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 222 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 223 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 224 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 225 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 226 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 227
 228 enum {
 229         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 230         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 231         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 232         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 233         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 234         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 235         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 236         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 237         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 238         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 239         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 240         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 241         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 242         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 243         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 244         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 245         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 246         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 247         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 248         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 249         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 250 };
 251
 252 #define ALI_CAS_SEM_BUSY        0x80000000
 253 #define ALI_CPR_ADDR_SECONDARY  0x100
 254 #define ALI_CPR_ADDR_READ       0x80
 255 #define ALI_CSPSR_CODEC_READY   0x08
 256 #define ALI_CSPSR_READ_OK       0x02
 257 #define ALI_CSPSR_WRITE_OK      0x01
 258
 259 /* interrupts for the whole chip by interrupt status register finish */
 260
 261 #define ALI_INT_MICIN2          (1<<26)
 262 #define ALI_INT_PCMIN2          (1<<25)
 263 #define ALI_INT_I2SIN           (1<<24)
 264 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 265 #define ALI_INT_SPDIFIN         (1<<22)
 266 #define ALI_INT_LFEOUT          (1<<21)
 267 #define ALI_INT_CENTEROUT       (1<<20)
 268 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 269 #define ALI_INT_MICIN           (1<<18)
 270 #define ALI_INT_PCMOUT          (1<<17)
 271 #define ALI_INT_PCMIN           (1<<16)
 272 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 273 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 274 #define ALI_INT_GPIO            (1<<1)
 275 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 276                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 277
 278 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 279 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 280 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 281 #define ICH_ALI_SC_IN_BITS      (3<<18)
 282 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 283 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 284 #define ICH_ALI_SC_PCM_4        (1<<8)
 285 #define ICH_ALI_SC_PCM_6        (2<<8)
 286 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 287
 288 #define ICH_ALI_SS_SEC_ID       (3<<5)
 289 #define ICH_ALI_SS_PRI_ID       (3<<3)
 290
 291 #define ICH_ALI_IF_AC97SP       (1<<21)
 292 #define ICH_ALI_IF_MC           (1<<20)
 293 #define ICH_ALI_IF_PI           (1<<19)
 294 #define ICH_ALI_IF_MC2          (1<<18)
 295 #define ICH_ALI_IF_PI2          (1<<17)
 296 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 297 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 298 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 299 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 300 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 301 #define ICH_ALI_IF_PO           (1<<1)
 302
 303 /*
 304  *
 305  */
 306
 307 enum {
 308         ICHD_PCMIN,
 309         ICHD_PCMOUT,
 310         ICHD_MIC,
 311         ICHD_MIC2,
 312         ICHD_PCM2IN,
 313         ICHD_SPBAR,
 314         ICHD_LAST = ICHD_SPBAR
 315 };
 316 enum {
 317         NVD_PCMIN,
 318         NVD_PCMOUT,
 319         NVD_MIC,
 320         NVD_SPBAR,
 321         NVD_LAST = NVD_SPBAR
 322 };
 323 enum {
 324         ALID_PCMIN,
 325         ALID_PCMOUT,
 326         ALID_MIC,
 327         ALID_AC97SPDIFOUT,
 328         ALID_SPDIFIN,
 329         ALID_SPDIFOUT,
 330         ALID_LAST = ALID_SPDIFOUT
 331 };
 332
 333 #define get_ichdev(substream) (substream->runtime->private_data)
 334
 335 struct ichdev {
 336         unsigned int ichd;                      /* ich device number */
 337         unsigned long reg_offset;               /* offset to bmaddr */
 338         u32 *bdbar;                             /* CPU address (32bit) */
 339         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 340         struct snd_pcm_substream *substream;
 341         unsigned int physbuf;                   /* physical address (32bit) */
 342         unsigned int size;
 343         unsigned int fragsize;
 344         unsigned int fragsize1;
 345         unsigned int position;
 346         unsigned int pos_shift;
 347         int frags;
 348         int lvi;
 349         int lvi_frag;
 350         int civ;
 351         int ack;
 352         int ack_reload;
 353         unsigned int ack_bit;
 354         unsigned int roff_sr;
 355         unsigned int roff_picb;
 356         unsigned int int_sta_mask;              /* interrupt status mask */
 357         unsigned int ali_slot;                  /* ALI DMA slot */
 358         struct ac97_pcm *pcm;
 359         int pcm_open_flag;
 360         unsigned int page_attr_changed: 1;
 361         unsigned int suspended: 1;
 362 };
 363
 364 struct intel8x0 {
 365         unsigned int device_type;
 366
 367         int irq;
 368
 369         unsigned int mmio;
 370         unsigned long addr;
 371         void __iomem *remap_addr;
 372         unsigned int bm_mmio;
 373         unsigned long bmaddr;
 374         void __iomem *remap_bmaddr;
 375
 376         struct pci_dev *pci;
 377         struct snd_card *card;
 378
 379         int pcm_devs;
 380         struct snd_pcm *pcm[6];
 381         struct ichdev ichd[6];
 382
 383         unsigned multi4: 1,
 384                  multi6: 1,
 385                  dra: 1,
 386                  smp20bit: 1;
 387         unsigned in_ac97_init: 1,
 388                  in_sdin_init: 1;
 389         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 390         unsigned fix_nocache: 1;        /* workaround for 440MX */
 391         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 392         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 393         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 394
 395         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 396         unsigned int sdm_saved; /* SDM reg value */
 397
 398         struct snd_ac97_bus *ac97_bus;
 399         struct snd_ac97 *ac97[3];
 400         unsigned int ac97_sdin[3];
 401
 402         spinlock_t reg_lock;
 403
 404         u32 bdbars_count;
 405         struct snd_dma_buffer bdbars;
 406         u32 int_sta_reg;                /* interrupt status register */
 407         u32 int_sta_mask;               /* interrupt status mask */
 408 };
 409
 410 static struct pci_device_id snd_intel8x0_ids[] = {
 411         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 412         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 413         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 414         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 415         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 416         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 417         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 418         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 419         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 420         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
 421         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 422         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 423         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 424         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 425         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 426         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 427         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 428         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 429         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 430         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 431         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 432         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 433         { 0, }
 434 };
 435
 436 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 437
 438 /*
 439  *  Lowlevel I/O - busmaster
 440  */
 441
 442 static u8 igetbyte(struct intel8x0 *chip, u32 offset)
 443 {
 444         if (chip->bm_mmio)
 445                 return readb(chip->remap_bmaddr + offset);
 446         else
 447                 return inb(chip->bmaddr + offset);
 448 }
 449
 450 static u16 igetword(struct intel8x0 *chip, u32 offset)
 451 {
 452         if (chip->bm_mmio)
 453                 return readw(chip->remap_bmaddr + offset);
 454         else
 455                 return inw(chip->bmaddr + offset);
 456 }
 457
 458 static u32 igetdword(struct intel8x0 *chip, u32 offset)
 459 {
 460         if (chip->bm_mmio)
 461                 return readl(chip->remap_bmaddr + offset);
 462         else
 463                 return inl(chip->bmaddr + offset);
 464 }
 465
 466 static void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 467 {
 468         if (chip->bm_mmio)
 469                 writeb(val, chip->remap_bmaddr + offset);
 470         else
 471                 outb(val, chip->bmaddr + offset);
 472 }
 473
 474 static void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 475 {
 476         if (chip->bm_mmio)
 477                 writew(val, chip->remap_bmaddr + offset);
 478         else
 479                 outw(val, chip->bmaddr + offset);
 480 }
 481
 482 static void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 483 {
 484         if (chip->bm_mmio)
 485                 writel(val, chip->remap_bmaddr + offset);
 486         else
 487                 outl(val, chip->bmaddr + offset);
 488 }
 489
 490 /*
 491  *  Lowlevel I/O - AC'97 registers
 492  */
 493
 494 static u16 iagetword(struct intel8x0 *chip, u32 offset)
 495 {
 496         if (chip->mmio)
 497                 return readw(chip->remap_addr + offset);
 498         else
 499                 return inw(chip->addr + offset);
 500 }
 501
 502 static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 503 {
 504         if (chip->mmio)
 505                 writew(val, chip->remap_addr + offset);
 506         else
 507                 outw(val, chip->addr + offset);
 508 }
 509
 510 /*
 511  *  Basic I/O
 512  */
 513
 514 /*
 515  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 516  */
 517
 518 /* return the GLOB_STA bit for the corresponding codec */
 519 static unsigned int get_ich_codec_bit(struct intel8x0 *chip, unsigned int codec)
 520 {
 521         static unsigned int codec_bit[3] = {
 522                 ICH_PCR, ICH_SCR, ICH_TCR
 523         };
 524         snd_assert(codec < 3, return ICH_PCR);
 525         if (chip->device_type == DEVICE_INTEL_ICH4)
 526                 codec = chip->ac97_sdin[codec];
 527         return codec_bit[codec];
 528 }
 529
 530 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 531 {
 532         int time;
 533
 534         if (codec > 2)
 535                 return -EIO;
 536         if (chip->in_sdin_init) {
 537                 /* we don't know the ready bit assignment at the moment */
 538                 /* so we check any */
 539                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
 540         } else {
 541                 codec = get_ich_codec_bit(chip, codec);
 542         }
 543
 544         /* codec ready ? */
 545         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 546                 return -EIO;
 547
 548         if (chip->buggy_semaphore)
 549                 return 0; /* just ignore ... */
 550
 551         /* Anyone holding a semaphore for 1 msec should be shot... */
 552         time = 100;
 553         do {
 554                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 555                         return 0;
 556                 udelay(10);
 557         } while (time--);
 558
 559         /* access to some forbidden (non existant) ac97 registers will not
 560          * reset the semaphore. So even if you don't get the semaphore, still
 561          * continue the access. We don't need the semaphore anyway. */
 562         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 563                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 564         iagetword(chip, 0);     /* clear semaphore flag */
 565         /* I don't care about the semaphore */
 566         return -EBUSY;
 567 }
 568
 569 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 570                                      unsigned short reg,
 571                                      unsigned short val)
 572 {
 573         struct intel8x0 *chip = ac97->private_data;
 574
 575         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 576                 if (! chip->in_ac97_init)
 577                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 578         }
 579         iaputword(chip, reg + ac97->num * 0x80, val);
 580 }
 581
 582 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 583                                               unsigned short reg)
 584 {
 585         struct intel8x0 *chip = ac97->private_data;
 586         unsigned short res;
 587         unsigned int tmp;
 588
 589         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 590                 if (! chip->in_ac97_init)
 591                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 592                 res = 0xffff;
 593         } else {
 594                 res = iagetword(chip, reg + ac97->num * 0x80);
 595                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 596                         /* reset RCS and preserve other R/WC bits */
 597                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 598                                   ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 599                         if (! chip->in_ac97_init)
 600                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 601                         res = 0xffff;
 602                 }
 603         }
 604         return res;
 605 }
 606
 607 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int codec)
 608 {
 609         unsigned int tmp;
 610
 611         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 612                 iagetword(chip, codec * 0x80);
 613                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 614                         /* reset RCS and preserve other R/WC bits */
 615                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 616                                   ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 617                 }
 618         }
 619 }
 620
 621 /*
 622  * access to AC97 for Ali5455
 623  */
 624 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 625 {
 626         int count = 0;
 627         for (count = 0; count < 0x7f; count++) {
 628                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 629                 if (val & mask)
 630                         return 0;
 631         }
 632         if (! chip->in_ac97_init)
 633                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 634         return -EBUSY;
 635 }
 636
 637 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 638 {
 639         int time = 100;
 640         if (chip->buggy_semaphore)
 641                 return 0; /* just ignore ... */
 642         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 643                 udelay(1);
 644         if (! time && ! chip->in_ac97_init)
 645                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 646         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 647 }
 648
 649 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 650 {
 651         struct intel8x0 *chip = ac97->private_data;
 652         unsigned short data = 0xffff;
 653
 654         if (snd_intel8x0_ali_codec_semaphore(chip))
 655                 goto __err;
 656         reg |= ALI_CPR_ADDR_READ;
 657         if (ac97->num)
 658                 reg |= ALI_CPR_ADDR_SECONDARY;
 659         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 660         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 661                 goto __err;
 662         data = igetword(chip, ICHREG(ALI_SPR));
 663  __err:
 664         return data;
 665 }
 666
 667 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 668                                          unsigned short val)
 669 {
 670         struct intel8x0 *chip = ac97->private_data;
 671
 672         if (snd_intel8x0_ali_codec_semaphore(chip))
 673                 return;
 674         iputword(chip, ICHREG(ALI_CPR), val);
 675         if (ac97->num)
 676                 reg |= ALI_CPR_ADDR_SECONDARY;
 677         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 678         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 679 }
 680
 681
 682 /*
 683  * DMA I/O
 684  */
 685 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 686 {
 687         int idx;
 688         u32 *bdbar = ichdev->bdbar;
 689         unsigned long port = ichdev->reg_offset;
 690
 691         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 692         if (ichdev->size == ichdev->fragsize) {
 693                 ichdev->ack_reload = ichdev->ack = 2;
 694                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 695                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 696                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 697                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 698                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 699                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 700                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 701                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 702                 }
 703                 ichdev->frags = 2;
 704         } else {
 705                 ichdev->ack_reload = ichdev->ack = 1;
 706                 ichdev->fragsize1 = ichdev->fragsize;
 707                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 708                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 709                                                      (((idx >> 1) * ichdev->fragsize) %
 710                                                       ichdev->size));
 711                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 712                                                      ichdev->fragsize >> ichdev->pos_shift);
 713 #if 0
 714                         printk("bdbar[%i] = 0x%x [0x%x]\n",
 715                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 716 #endif
 717                 }
 718                 ichdev->frags = ichdev->size / ichdev->fragsize;
 719         }
 720         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 721         ichdev->civ = 0;
 722         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 723         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 724         ichdev->position = 0;
 725 #if 0
 726         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 727                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 728 #endif
 729         /* clear interrupts */
 730         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 731 }
 732
 733 #ifdef __i386__
 734 /*
 735  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 736  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 737  * the pages as non-cached.  For details, see the errata in
 738  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 739  */
 740 static void fill_nocache(void *buf, int size, int nocache)
 741 {
 742         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 743         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
 744         global_flush_tlb();
 745 }
 746 #else
 747 #define fill_nocache(buf,size,nocache)
 748 #endif
 749
 750 /*
 751  *  Interrupt handler
 752  */
 753
 754 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 755 {
 756         unsigned long port = ichdev->reg_offset;
 757         int status, civ, i, step;
 758         int ack = 0;
 759
 760         spin_lock(&chip->reg_lock);
 761         status = igetbyte(chip, port + ichdev->roff_sr);
 762         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 763         if (!(status & ICH_BCIS)) {
 764                 step = 0;
 765         } else if (civ == ichdev->civ) {
 766                 // snd_printd("civ same %d\n", civ);
 767                 step = 1;
 768                 ichdev->civ++;
 769                 ichdev->civ &= ICH_REG_LVI_MASK;
 770         } else {
 771                 step = civ - ichdev->civ;
 772                 if (step < 0)
 773                         step += ICH_REG_LVI_MASK + 1;
 774                 // if (step != 1)
 775                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 776                 ichdev->civ = civ;
 777         }
 778
 779         ichdev->position += step * ichdev->fragsize1;
 780         if (! chip->in_measurement)
 781                 ichdev->position %= ichdev->size;
 782         ichdev->lvi += step;
 783         ichdev->lvi &= ICH_REG_LVI_MASK;
 784         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 785         for (i = 0; i < step; i++) {
 786                 ichdev->lvi_frag++;
 787                 ichdev->lvi_frag %= ichdev->frags;
 788                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 789 #if 0
 790         printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 791                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 792                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 793                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 794 #endif
 795                 if (--ichdev->ack == 0) {
 796                         ichdev->ack = ichdev->ack_reload;
 797                         ack = 1;
 798                 }
 799         }
 800         spin_unlock(&chip->reg_lock);
 801         if (ack && ichdev->substream) {
 802                 snd_pcm_period_elapsed(ichdev->substream);
 803         }
 804         iputbyte(chip, port + ichdev->roff_sr,
 805                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 806 }
 807
 808 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 809 {
 810         struct intel8x0 *chip = dev_id;
 811         struct ichdev *ichdev;
 812         unsigned int status;
 813         unsigned int i;
 814
 815         status = igetdword(chip, chip->int_sta_reg);
 816         if (status == 0xffffffff)       /* we are not yet resumed */
 817                 return IRQ_NONE;
 818
 819         if ((status & chip->int_sta_mask) == 0) {
 820                 if (status) {
 821                         /* ack */
 822                         iputdword(chip, chip->int_sta_reg, status);
 823                         if (! chip->buggy_irq)
 824                                 status = 0;
 825                 }
 826                 return IRQ_RETVAL(status);
 827         }
 828
 829         for (i = 0; i < chip->bdbars_count; i++) {
 830                 ichdev = &chip->ichd[i];
 831                 if (status & ichdev->int_sta_mask)
 832                         snd_intel8x0_update(chip, ichdev);
 833         }
 834
 835         /* ack them */
 836         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 837
 838         return IRQ_HANDLED;
 839 }
 840
 841 /*
 842  *  PCM part
 843  */
 844
 845 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 846 {
 847         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 848         struct ichdev *ichdev = get_ichdev(substream);
 849         unsigned char val = 0;
 850         unsigned long port = ichdev->reg_offset;
 851
 852         switch (cmd) {
 853         case SNDRV_PCM_TRIGGER_RESUME:
 854                 ichdev->suspended = 0;
 855                 /* fallthru */
 856         case SNDRV_PCM_TRIGGER_START:
 857                 val = ICH_IOCE | ICH_STARTBM;
 858                 break;
 859         case SNDRV_PCM_TRIGGER_SUSPEND:
 860                 ichdev->suspended = 1;
 861                 /* fallthru */
 862         case SNDRV_PCM_TRIGGER_STOP:
 863                 val = 0;
 864                 break;
 865         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 866                 val = ICH_IOCE;
 867                 break;
 868         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 869                 val = ICH_IOCE | ICH_STARTBM;
 870                 break;
 871         default:
 872                 return -EINVAL;
 873         }
 874         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 875         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 876                 /* wait until DMA stopped */
 877                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 878                 /* reset whole DMA things */
 879                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 880         }
 881         return 0;
 882 }
 883
 884 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 885 {
 886         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 887         struct ichdev *ichdev = get_ichdev(substream);
 888         unsigned long port = ichdev->reg_offset;
 889         static int fiforeg[] = {
 890                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 891         };
 892         unsigned int val, fifo;
 893
 894         val = igetdword(chip, ICHREG(ALI_DMACR));
 895         switch (cmd) {
 896         case SNDRV_PCM_TRIGGER_RESUME:
 897                 ichdev->suspended = 0;
 898                 /* fallthru */
 899         case SNDRV_PCM_TRIGGER_START:
 900         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 901                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 902                         /* clear FIFO for synchronization of channels */
 903                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 904                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 905                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 906                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 907                 }
 908                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 909                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 910                 /* start DMA */
 911                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 912                 break;
 913         case SNDRV_PCM_TRIGGER_SUSPEND:
 914                 ichdev->suspended = 1;
 915                 /* fallthru */
 916         case SNDRV_PCM_TRIGGER_STOP:
 917         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 918                 /* pause */
 919                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 920                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 921                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 922                         ;
 923                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 924                         break;
 925                 /* reset whole DMA things */
 926                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 927                 /* clear interrupts */
 928                 iputbyte(chip, port + ICH_REG_OFF_SR,
 929                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 930                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 931                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 932                 break;
 933         default:
 934                 return -EINVAL;
 935         }
 936         return 0;
 937 }
 938
 939 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 940                                   struct snd_pcm_hw_params *hw_params)
 941 {
 942         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 943         struct ichdev *ichdev = get_ichdev(substream);
 944         struct snd_pcm_runtime *runtime = substream->runtime;
 945         int dbl = params_rate(hw_params) > 48000;
 946         int err;
 947
 948         if (chip->fix_nocache && ichdev->page_attr_changed) {
 949                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 950                 ichdev->page_attr_changed = 0;
 951         }
 952         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 953         if (err < 0)
 954                 return err;
 955         if (chip->fix_nocache) {
 956                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 957                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 958                         ichdev->page_attr_changed = 1;
 959                 }
 960         }
 961         if (ichdev->pcm_open_flag) {
 962                 snd_ac97_pcm_close(ichdev->pcm);
 963                 ichdev->pcm_open_flag = 0;
 964         }
 965         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 966                                 params_channels(hw_params),
 967                                 ichdev->pcm->r[dbl].slots);
 968         if (err >= 0) {
 969                 ichdev->pcm_open_flag = 1;
 970                 /* Force SPDIF setting */
 971                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 972                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 973                                           params_rate(hw_params));
 974         }
 975         return err;
 976 }
 977
 978 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 979 {
 980         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 981         struct ichdev *ichdev = get_ichdev(substream);
 982
 983         if (ichdev->pcm_open_flag) {
 984                 snd_ac97_pcm_close(ichdev->pcm);
 985                 ichdev->pcm_open_flag = 0;
 986         }
 987         if (chip->fix_nocache && ichdev->page_attr_changed) {
 988                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 989                 ichdev->page_attr_changed = 0;
 990         }
 991         return snd_pcm_lib_free_pages(substream);
 992 }
 993
 994 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 995                                        struct snd_pcm_runtime *runtime)
 996 {
 997         unsigned int cnt;
 998         int dbl = runtime->rate > 48000;
 999
1000         spin_lock_irq(&chip->reg_lock);
1001         switch (chip->device_type) {
1002         case DEVICE_ALI:
1003                 cnt = igetdword(chip, ICHREG(ALI_SCR));
1004                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1005                 if (runtime->channels == 4 || dbl)
1006                         cnt |= ICH_ALI_SC_PCM_4;
1007                 else if (runtime->channels == 6)
1008                         cnt |= ICH_ALI_SC_PCM_6;
1009                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1010                 break;
1011         case DEVICE_SIS:
1012                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1013                 cnt &= ~ICH_SIS_PCM_246_MASK;
1014                 if (runtime->channels == 4 || dbl)
1015                         cnt |= ICH_SIS_PCM_4;
1016                 else if (runtime->channels == 6)
1017                         cnt |= ICH_SIS_PCM_6;
1018                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1019                 break;
1020         default:
1021                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1022                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1023                 if (runtime->channels == 4 || dbl)
1024                         cnt |= ICH_PCM_4;
1025                 else if (runtime->channels == 6)
1026                         cnt |= ICH_PCM_6;
1027                 if (chip->device_type == DEVICE_NFORCE) {
1028                         /* reset to 2ch once to keep the 6 channel data in alignment,
1029                          * to start from Front Left always
1030                          */
1031                         if (cnt & ICH_PCM_246_MASK) {
1032                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1033                                 spin_unlock_irq(&chip->reg_lock);
1034                                 msleep(50); /* grrr... */
1035                                 spin_lock_irq(&chip->reg_lock);
1036                         }
1037                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1038                         if (runtime->sample_bits > 16)
1039                                 cnt |= ICH_PCM_20BIT;
1040                 }
1041                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1042                 break;
1043         }
1044         spin_unlock_irq(&chip->reg_lock);
1045 }
1046
1047 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1048 {
1049         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1050         struct snd_pcm_runtime *runtime = substream->runtime;
1051         struct ichdev *ichdev = get_ichdev(substream);
1052
1053         ichdev->physbuf = runtime->dma_addr;
1054         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1055         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1056         if (ichdev->ichd == ICHD_PCMOUT) {
1057                 snd_intel8x0_setup_pcm_out(chip, runtime);
1058                 if (chip->device_type == DEVICE_INTEL_ICH4)
1059                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1060         }
1061         snd_intel8x0_setup_periods(chip, ichdev);
1062         return 0;
1063 }
1064
1065 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1066 {
1067         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1068         struct ichdev *ichdev = get_ichdev(substream);
1069         size_t ptr1, ptr;
1070         int civ, timeout = 100;
1071         unsigned int position;
1072
1073         spin_lock(&chip->reg_lock);
1074         do {
1075                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1076                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1077                 position = ichdev->position;
1078                 if (ptr1 == 0) {
1079                         udelay(10);
1080                         continue;
1081                 }
1082                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1083                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1084                         break;
1085         } while (timeout--);
1086         ptr1 <<= ichdev->pos_shift;
1087         ptr = ichdev->fragsize1 - ptr1;
1088         ptr += position;
1089         spin_unlock(&chip->reg_lock);
1090         if (ptr >= ichdev->size)
1091                 return 0;
1092         return bytes_to_frames(substream->runtime, ptr);
1093 }
1094
1095 static struct snd_pcm_hardware snd_intel8x0_stream =
1096 {
1097         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099                                  SNDRV_PCM_INFO_MMAP_VALID |
1100                                  SNDRV_PCM_INFO_PAUSE |
1101                                  SNDRV_PCM_INFO_RESUME),
1102         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1103         .rates =                SNDRV_PCM_RATE_48000,
1104         .rate_min =             48000,
1105         .rate_max =             48000,
1106         .channels_min =         2,
1107         .channels_max =         2,
1108         .buffer_bytes_max =     128 * 1024,
1109         .period_bytes_min =     32,
1110         .period_bytes_max =     128 * 1024,
1111         .periods_min =          1,
1112         .periods_max =          1024,
1113         .fifo_size =            0,
1114 };
1115
1116 static unsigned int channels4[] = {
1117         2, 4,
1118 };
1119
1120 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1121         .count = ARRAY_SIZE(channels4),
1122         .list = channels4,
1123         .mask = 0,
1124 };
1125
1126 static unsigned int channels6[] = {
1127         2, 4, 6,
1128 };
1129
1130 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1131         .count = ARRAY_SIZE(channels6),
1132         .list = channels6,
1133         .mask = 0,
1134 };
1135
1136 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1137 {
1138         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1139         struct snd_pcm_runtime *runtime = substream->runtime;
1140         int err;
1141
1142         ichdev->substream = substream;
1143         runtime->hw = snd_intel8x0_stream;
1144         runtime->hw.rates = ichdev->pcm->rates;
1145         snd_pcm_limit_hw_rates(runtime);
1146         if (chip->device_type == DEVICE_SIS) {
1147                 runtime->hw.buffer_bytes_max = 64*1024;
1148                 runtime->hw.period_bytes_max = 64*1024;
1149         }
1150         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1151                 return err;
1152         runtime->private_data = ichdev;
1153         return 0;
1154 }
1155
1156 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1157 {
1158         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1159         struct snd_pcm_runtime *runtime = substream->runtime;
1160         int err;
1161
1162         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1163         if (err < 0)
1164                 return err;
1165
1166         if (chip->multi6) {
1167                 runtime->hw.channels_max = 6;
1168                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1169                                            &hw_constraints_channels6);
1170         } else if (chip->multi4) {
1171                 runtime->hw.channels_max = 4;
1172                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1173                                            &hw_constraints_channels4);
1174         }
1175         if (chip->dra) {
1176                 snd_ac97_pcm_double_rate_rules(runtime);
1177         }
1178         if (chip->smp20bit) {
1179                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1180                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1181         }
1182         return 0;
1183 }
1184
1185 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1186 {
1187         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1188
1189         chip->ichd[ICHD_PCMOUT].substream = NULL;
1190         return 0;
1191 }
1192
1193 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1194 {
1195         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1196
1197         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1198 }
1199
1200 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1201 {
1202         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1203
1204         chip->ichd[ICHD_PCMIN].substream = NULL;
1205         return 0;
1206 }
1207
1208 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1209 {
1210         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1211
1212         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1213 }
1214
1215 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1216 {
1217         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1218
1219         chip->ichd[ICHD_MIC].substream = NULL;
1220         return 0;
1221 }
1222
1223 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1224 {
1225         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226
1227         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1228 }
1229
1230 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1231 {
1232         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1233
1234         chip->ichd[ICHD_MIC2].substream = NULL;
1235         return 0;
1236 }
1237
1238 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1239 {
1240         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241
1242         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1243 }
1244
1245 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1246 {
1247         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1248
1249         chip->ichd[ICHD_PCM2IN].substream = NULL;
1250         return 0;
1251 }
1252
1253 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1254 {
1255         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1257
1258         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1259 }
1260
1261 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1262 {
1263         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1264         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1265
1266         chip->ichd[idx].substream = NULL;
1267         return 0;
1268 }
1269
1270 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1271 {
1272         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1273         unsigned int val;
1274
1275         spin_lock_irq(&chip->reg_lock);
1276         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1277         val |= ICH_ALI_IF_AC97SP;
1278         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1279         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1280         spin_unlock_irq(&chip->reg_lock);
1281
1282         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1283 }
1284
1285 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1286 {
1287         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1288         unsigned int val;
1289
1290         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1291         spin_lock_irq(&chip->reg_lock);
1292         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1293         val &= ~ICH_ALI_IF_AC97SP;
1294         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1295         spin_unlock_irq(&chip->reg_lock);
1296
1297         return 0;
1298 }
1299
1300 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1301 {
1302         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1303
1304         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1305 }
1306
1307 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1308 {
1309         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1310
1311         chip->ichd[ALID_SPDIFIN].substream = NULL;
1312         return 0;
1313 }
1314
1315 #if 0 // NYI
1316 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1317 {
1318         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1319
1320         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1321 }
1322
1323 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1324 {
1325         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1326
1327         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1328         return 0;
1329 }
1330 #endif
1331
1332 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1333         .open =         snd_intel8x0_playback_open,
1334         .close =        snd_intel8x0_playback_close,
1335         .ioctl =        snd_pcm_lib_ioctl,
1336         .hw_params =    snd_intel8x0_hw_params,
1337         .hw_free =      snd_intel8x0_hw_free,
1338         .prepare =      snd_intel8x0_pcm_prepare,
1339         .trigger =      snd_intel8x0_pcm_trigger,
1340         .pointer =      snd_intel8x0_pcm_pointer,
1341 };
1342
1343 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1344         .open =         snd_intel8x0_capture_open,
1345         .close =        snd_intel8x0_capture_close,
1346         .ioctl =        snd_pcm_lib_ioctl,
1347         .hw_params =    snd_intel8x0_hw_params,
1348         .hw_free =      snd_intel8x0_hw_free,
1349         .prepare =      snd_intel8x0_pcm_prepare,
1350         .trigger =      snd_intel8x0_pcm_trigger,
1351         .pointer =      snd_intel8x0_pcm_pointer,
1352 };
1353
1354 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1355         .open =         snd_intel8x0_mic_open,
1356         .close =        snd_intel8x0_mic_close,
1357         .ioctl =        snd_pcm_lib_ioctl,
1358         .hw_params =    snd_intel8x0_hw_params,
1359         .hw_free =      snd_intel8x0_hw_free,
1360         .prepare =      snd_intel8x0_pcm_prepare,
1361         .trigger =      snd_intel8x0_pcm_trigger,
1362         .pointer =      snd_intel8x0_pcm_pointer,
1363 };
1364
1365 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1366         .open =         snd_intel8x0_mic2_open,
1367         .close =        snd_intel8x0_mic2_close,
1368         .ioctl =        snd_pcm_lib_ioctl,
1369         .hw_params =    snd_intel8x0_hw_params,
1370         .hw_free =      snd_intel8x0_hw_free,
1371         .prepare =      snd_intel8x0_pcm_prepare,
1372         .trigger =      snd_intel8x0_pcm_trigger,
1373         .pointer =      snd_intel8x0_pcm_pointer,
1374 };
1375
1376 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1377         .open =         snd_intel8x0_capture2_open,
1378         .close =        snd_intel8x0_capture2_close,
1379         .ioctl =        snd_pcm_lib_ioctl,
1380         .hw_params =    snd_intel8x0_hw_params,
1381         .hw_free =      snd_intel8x0_hw_free,
1382         .prepare =      snd_intel8x0_pcm_prepare,
1383         .trigger =      snd_intel8x0_pcm_trigger,
1384         .pointer =      snd_intel8x0_pcm_pointer,
1385 };
1386
1387 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1388         .open =         snd_intel8x0_spdif_open,
1389         .close =        snd_intel8x0_spdif_close,
1390         .ioctl =        snd_pcm_lib_ioctl,
1391         .hw_params =    snd_intel8x0_hw_params,
1392         .hw_free =      snd_intel8x0_hw_free,
1393         .prepare =      snd_intel8x0_pcm_prepare,
1394         .trigger =      snd_intel8x0_pcm_trigger,
1395         .pointer =      snd_intel8x0_pcm_pointer,
1396 };
1397
1398 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1399         .open =         snd_intel8x0_playback_open,
1400         .close =        snd_intel8x0_playback_close,
1401         .ioctl =        snd_pcm_lib_ioctl,
1402         .hw_params =    snd_intel8x0_hw_params,
1403         .hw_free =      snd_intel8x0_hw_free,
1404         .prepare =      snd_intel8x0_pcm_prepare,
1405         .trigger =      snd_intel8x0_ali_trigger,
1406         .pointer =      snd_intel8x0_pcm_pointer,
1407 };
1408
1409 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1410         .open =         snd_intel8x0_capture_open,
1411         .close =        snd_intel8x0_capture_close,
1412         .ioctl =        snd_pcm_lib_ioctl,
1413         .hw_params =    snd_intel8x0_hw_params,
1414         .hw_free =      snd_intel8x0_hw_free,
1415         .prepare =      snd_intel8x0_pcm_prepare,
1416         .trigger =      snd_intel8x0_ali_trigger,
1417         .pointer =      snd_intel8x0_pcm_pointer,
1418 };
1419
1420 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1421         .open =         snd_intel8x0_mic_open,
1422         .close =        snd_intel8x0_mic_close,
1423         .ioctl =        snd_pcm_lib_ioctl,
1424         .hw_params =    snd_intel8x0_hw_params,
1425         .hw_free =      snd_intel8x0_hw_free,
1426         .prepare =      snd_intel8x0_pcm_prepare,
1427         .trigger =      snd_intel8x0_ali_trigger,
1428         .pointer =      snd_intel8x0_pcm_pointer,
1429 };
1430
1431 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1432         .open =         snd_intel8x0_ali_ac97spdifout_open,
1433         .close =        snd_intel8x0_ali_ac97spdifout_close,
1434         .ioctl =        snd_pcm_lib_ioctl,
1435         .hw_params =    snd_intel8x0_hw_params,
1436         .hw_free =      snd_intel8x0_hw_free,
1437         .prepare =      snd_intel8x0_pcm_prepare,
1438         .trigger =      snd_intel8x0_ali_trigger,
1439         .pointer =      snd_intel8x0_pcm_pointer,
1440 };
1441
1442 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1443         .open =         snd_intel8x0_ali_spdifin_open,
1444         .close =        snd_intel8x0_ali_spdifin_close,
1445         .ioctl =        snd_pcm_lib_ioctl,
1446         .hw_params =    snd_intel8x0_hw_params,
1447         .hw_free =      snd_intel8x0_hw_free,
1448         .prepare =      snd_intel8x0_pcm_prepare,
1449         .trigger =      snd_intel8x0_pcm_trigger,
1450         .pointer =      snd_intel8x0_pcm_pointer,
1451 };
1452
1453 #if 0 // NYI
1454 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1455         .open =         snd_intel8x0_ali_spdifout_open,
1456         .close =        snd_intel8x0_ali_spdifout_close,
1457         .ioctl =        snd_pcm_lib_ioctl,
1458         .hw_params =    snd_intel8x0_hw_params,
1459         .hw_free =      snd_intel8x0_hw_free,
1460         .prepare =      snd_intel8x0_pcm_prepare,
1461         .trigger =      snd_intel8x0_pcm_trigger,
1462         .pointer =      snd_intel8x0_pcm_pointer,
1463 };
1464 #endif // NYI
1465
1466 struct ich_pcm_table {
1467         char *suffix;
1468         struct snd_pcm_ops *playback_ops;
1469         struct snd_pcm_ops *capture_ops;
1470         size_t prealloc_size;
1471         size_t prealloc_max_size;
1472         int ac97_idx;
1473 };
1474
1475 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1476                                        struct ich_pcm_table *rec)
1477 {
1478         struct snd_pcm *pcm;
1479         int err;
1480         char name[32];
1481
1482         if (rec->suffix)
1483                 sprintf(name, "Intel ICH - %s", rec->suffix);
1484         else
1485                 strcpy(name, "Intel ICH");
1486         err = snd_pcm_new(chip->card, name, device,
1487                           rec->playback_ops ? 1 : 0,
1488                           rec->capture_ops ? 1 : 0, &pcm);
1489         if (err < 0)
1490                 return err;
1491
1492         if (rec->playback_ops)
1493                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1494         if (rec->capture_ops)
1495                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1496
1497         pcm->private_data = chip;
1498         pcm->info_flags = 0;
1499         if (rec->suffix)
1500                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1501         else
1502                 strcpy(pcm->name, chip->card->shortname);
1503         chip->pcm[device] = pcm;
1504
1505         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1506                                               snd_dma_pci_data(chip->pci),
1507                                               rec->prealloc_size, rec->prealloc_max_size);
1508
1509         return 0;
1510 }
1511
1512 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1513         {
1514                 .playback_ops = &snd_intel8x0_playback_ops,
1515                 .capture_ops = &snd_intel8x0_capture_ops,
1516                 .prealloc_size = 64 * 1024,
1517                 .prealloc_max_size = 128 * 1024,
1518         },
1519         {
1520                 .suffix = "MIC ADC",
1521                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1522                 .prealloc_size = 0,
1523                 .prealloc_max_size = 128 * 1024,
1524                 .ac97_idx = ICHD_MIC,
1525         },
1526         {
1527                 .suffix = "MIC2 ADC",
1528                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1529                 .prealloc_size = 0,
1530                 .prealloc_max_size = 128 * 1024,
1531                 .ac97_idx = ICHD_MIC2,
1532         },
1533         {
1534                 .suffix = "ADC2",
1535                 .capture_ops = &snd_intel8x0_capture2_ops,
1536                 .prealloc_size = 0,
1537                 .prealloc_max_size = 128 * 1024,
1538                 .ac97_idx = ICHD_PCM2IN,
1539         },
1540         {
1541                 .suffix = "IEC958",
1542                 .playback_ops = &snd_intel8x0_spdif_ops,
1543                 .prealloc_size = 64 * 1024,
1544                 .prealloc_max_size = 128 * 1024,
1545                 .ac97_idx = ICHD_SPBAR,
1546         },
1547 };
1548
1549 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1550         {
1551                 .playback_ops = &snd_intel8x0_playback_ops,
1552                 .capture_ops = &snd_intel8x0_capture_ops,
1553                 .prealloc_size = 64 * 1024,
1554                 .prealloc_max_size = 128 * 1024,
1555         },
1556         {
1557                 .suffix = "MIC ADC",
1558                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1559                 .prealloc_size = 0,
1560                 .prealloc_max_size = 128 * 1024,
1561                 .ac97_idx = NVD_MIC,
1562         },
1563         {
1564                 .suffix = "IEC958",
1565                 .playback_ops = &snd_intel8x0_spdif_ops,
1566                 .prealloc_size = 64 * 1024,
1567                 .prealloc_max_size = 128 * 1024,
1568                 .ac97_idx = NVD_SPBAR,
1569         },
1570 };
1571
1572 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1573         {
1574                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1575                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1576                 .prealloc_size = 64 * 1024,
1577                 .prealloc_max_size = 128 * 1024,
1578         },
1579         {
1580                 .suffix = "MIC ADC",
1581                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1582                 .prealloc_size = 0,
1583                 .prealloc_max_size = 128 * 1024,
1584                 .ac97_idx = ALID_MIC,
1585         },
1586         {
1587                 .suffix = "IEC958",
1588                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1589                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1590                 .prealloc_size = 64 * 1024,
1591                 .prealloc_max_size = 128 * 1024,
1592                 .ac97_idx = ALID_AC97SPDIFOUT,
1593         },
1594 #if 0 // NYI
1595         {
1596                 .suffix = "HW IEC958",
1597                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1598                 .prealloc_size = 64 * 1024,
1599                 .prealloc_max_size = 128 * 1024,
1600         },
1601 #endif
1602 };
1603
1604 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1605 {
1606         int i, tblsize, device, err;
1607         struct ich_pcm_table *tbl, *rec;
1608
1609         switch (chip->device_type) {
1610         case DEVICE_INTEL_ICH4:
1611                 tbl = intel_pcms;
1612                 tblsize = ARRAY_SIZE(intel_pcms);
1613                 break;
1614         case DEVICE_NFORCE:
1615                 tbl = nforce_pcms;
1616                 tblsize = ARRAY_SIZE(nforce_pcms);
1617                 break;
1618         case DEVICE_ALI:
1619                 tbl = ali_pcms;
1620                 tblsize = ARRAY_SIZE(ali_pcms);
1621                 break;
1622         default:
1623                 tbl = intel_pcms;
1624                 tblsize = 2;
1625                 break;
1626         }
1627
1628         device = 0;
1629         for (i = 0; i < tblsize; i++) {
1630                 rec = tbl + i;
1631                 if (i > 0 && rec->ac97_idx) {
1632                         /* activate PCM only when associated AC'97 codec */
1633                         if (! chip->ichd[rec->ac97_idx].pcm)
1634                                 continue;
1635                 }
1636                 err = snd_intel8x0_pcm1(chip, device, rec);
1637                 if (err < 0)
1638                         return err;
1639                 device++;
1640         }
1641
1642         chip->pcm_devs = device;
1643         return 0;
1644 }
1645
1646
1647 /*
1648  *  Mixer part
1649  */
1650
1651 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1652 {
1653         struct intel8x0 *chip = bus->private_data;
1654         chip->ac97_bus = NULL;
1655 }
1656
1657 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1658 {
1659         struct intel8x0 *chip = ac97->private_data;
1660         chip->ac97[ac97->num] = NULL;
1661 }
1662
1663 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1664         /* front PCM */
1665         {
1666                 .exclusive = 1,
1667                 .r = {  {
1668                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1669                                          (1 << AC97_SLOT_PCM_RIGHT) |
1670                                          (1 << AC97_SLOT_PCM_CENTER) |
1671                                          (1 << AC97_SLOT_PCM_SLEFT) |
1672                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1673                                          (1 << AC97_SLOT_LFE)
1674                         },
1675                         {
1676                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1677                                          (1 << AC97_SLOT_PCM_RIGHT) |
1678                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1679                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1680                         }
1681                 }
1682         },
1683         /* PCM IN #1 */
1684         {
1685                 .stream = 1,
1686                 .exclusive = 1,
1687                 .r = {  {
1688                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1689                                          (1 << AC97_SLOT_PCM_RIGHT)
1690                         }
1691                 }
1692         },
1693         /* MIC IN #1 */
1694         {
1695                 .stream = 1,
1696                 .exclusive = 1,
1697                 .r = {  {
1698                                 .slots = (1 << AC97_SLOT_MIC)
1699                         }
1700                 }
1701         },
1702         /* S/PDIF PCM */
1703         {
1704                 .exclusive = 1,
1705                 .spdif = 1,
1706                 .r = {  {
1707                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1708                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1709                         }
1710                 }
1711         },
1712         /* PCM IN #2 */
1713         {
1714                 .stream = 1,
1715                 .exclusive = 1,
1716                 .r = {  {
1717                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1718                                          (1 << AC97_SLOT_PCM_RIGHT)
1719                         }
1720                 }
1721         },
1722         /* MIC IN #2 */
1723         {
1724                 .stream = 1,
1725                 .exclusive = 1,
1726                 .r = {  {
1727                                 .slots = (1 << AC97_SLOT_MIC)
1728                         }
1729                 }
1730         },
1731 };
1732
1733 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1734         {
1735                 .subvendor = 0x0e11,
1736                 .subdevice = 0x008a,
1737                 .name = "Compaq Evo W4000",     /* AD1885 */
1738                 .type = AC97_TUNE_HP_ONLY
1739         },
1740         {
1741                 .subvendor = 0x0e11,
1742                 .subdevice = 0x00b8,
1743                 .name = "Compaq Evo D510C",
1744                 .type = AC97_TUNE_HP_ONLY
1745         },
1746         {
1747                 .subvendor = 0x0e11,
1748                 .subdevice = 0x0860,
1749                 .name = "HP/Compaq nx7010",
1750                 .type = AC97_TUNE_MUTE_LED
1751         },
1752         {
1753                 .subvendor = 0x1014,
1754                 .subdevice = 0x1f00,
1755                 .name = "MS-9128",
1756                 .type = AC97_TUNE_ALC_JACK
1757         },
1758         {
1759                 .subvendor = 0x1014,
1760                 .subdevice = 0x0267,
1761                 .name = "IBM NetVista A30p",    /* AD1981B */
1762                 .type = AC97_TUNE_HP_ONLY
1763         },
1764         {
1765                 .subvendor = 0x1025,
1766                 .subdevice = 0x0083,
1767                 .name = "Acer Aspire 3003LCi",
1768                 .type = AC97_TUNE_HP_ONLY
1769         },
1770         {
1771                 .subvendor = 0x1028,
1772                 .subdevice = 0x00d8,
1773                 .name = "Dell Precision 530",   /* AD1885 */
1774                 .type = AC97_TUNE_HP_ONLY
1775         },
1776         {
1777                 .subvendor = 0x1028,
1778                 .subdevice = 0x010d,
1779                 .name = "Dell", /* which model?  AD1885 */
1780                 .type = AC97_TUNE_HP_ONLY
1781         },
1782         {
1783                 .subvendor = 0x1028,
1784                 .subdevice = 0x0126,
1785                 .name = "Dell Optiplex GX260",  /* AD1981A */
1786                 .type = AC97_TUNE_HP_ONLY
1787         },
1788         {
1789                 .subvendor = 0x1028,
1790                 .subdevice = 0x012c,
1791                 .name = "Dell Precision 650",   /* AD1981A */
1792                 .type = AC97_TUNE_HP_ONLY
1793         },
1794         {
1795                 .subvendor = 0x1028,
1796                 .subdevice = 0x012d,
1797                 .name = "Dell Precision 450",   /* AD1981B*/
1798                 .type = AC97_TUNE_HP_ONLY
1799         },
1800         {
1801                 .subvendor = 0x1028,
1802                 .subdevice = 0x0147,
1803                 .name = "Dell", /* which model?  AD1981B*/
1804                 .type = AC97_TUNE_HP_ONLY
1805         },
1806         {
1807                 .subvendor = 0x1028,
1808                 .subdevice = 0x0163,
1809                 .name = "Dell Unknown", /* STAC9750/51 */
1810                 .type = AC97_TUNE_HP_ONLY
1811         },
1812         {
1813                 .subvendor = 0x1028,
1814                 .subdevice = 0x0191,
1815                 .name = "Dell Inspiron 8600",
1816                 .type = AC97_TUNE_HP_ONLY
1817         },
1818         {
1819                 .subvendor = 0x103c,
1820                 .subdevice = 0x006d,
1821                 .name = "HP zv5000",
1822                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1823         },
1824         {       /* FIXME: which codec? */
1825                 .subvendor = 0x103c,
1826                 .subdevice = 0x00c3,
1827                 .name = "HP xw6000",
1828                 .type = AC97_TUNE_HP_ONLY
1829         },
1830         {
1831                 .subvendor = 0x103c,
1832                 .subdevice = 0x088c,
1833                 .name = "HP nc8000",
1834                 .type = AC97_TUNE_MUTE_LED
1835         },
1836         {
1837                 .subvendor = 0x103c,
1838                 .subdevice = 0x0890,
1839                 .name = "HP nc6000",
1840                 .type = AC97_TUNE_MUTE_LED
1841         },
1842         {
1843                 .subvendor = 0x103c,
1844                 .subdevice = 0x0934,
1845                 .name = "HP nx8220",
1846                 .type = AC97_TUNE_MUTE_LED
1847         },
1848         {
1849                 .subvendor = 0x103c,
1850                 .subdevice = 0x099c,
1851                 .name = "HP nx6110",    /* AD1981B */
1852                 .type = AC97_TUNE_HP_ONLY
1853         },
1854         {
1855                 .subvendor = 0x103c,
1856                 .subdevice = 0x129d,
1857                 .name = "HP xw8000",
1858                 .type = AC97_TUNE_HP_ONLY
1859         },
1860         {
1861                 .subvendor = 0x103c,
1862                 .subdevice = 0x0938,
1863                 .name = "HP nc4200",
1864                 .type = AC97_TUNE_HP_MUTE_LED
1865         },
1866         {
1867                 .subvendor = 0x103c,
1868                 .subdevice = 0x099c,
1869                 .name = "HP nc6120",
1870                 .type = AC97_TUNE_HP_MUTE_LED
1871         },
1872         {
1873                 .subvendor = 0x103c,
1874                 .subdevice = 0x0944,
1875                 .name = "HP nc6220",
1876                 .type = AC97_TUNE_HP_MUTE_LED
1877         },
1878         {
1879                 .subvendor = 0x103c,
1880                 .subdevice = 0x0934,
1881                 .name = "HP nc8220",
1882                 .type = AC97_TUNE_HP_MUTE_LED
1883         },
1884         {
1885                 .subvendor = 0x103c,
1886                 .subdevice = 0x12f1,
1887                 .name = "HP xw8200",    /* AD1981B*/
1888                 .type = AC97_TUNE_HP_ONLY
1889         },
1890         {
1891                 .subvendor = 0x103c,
1892                 .subdevice = 0x12f2,
1893                 .name = "HP xw6200",
1894                 .type = AC97_TUNE_HP_ONLY
1895         },
1896         {
1897                 .subvendor = 0x103c,
1898                 .subdevice = 0x3008,
1899                 .name = "HP xw4200",    /* AD1981B*/
1900                 .type = AC97_TUNE_HP_ONLY
1901         },
1902         {
1903                 .subvendor = 0x104d,
1904                 .subdevice = 0x8197,
1905                 .name = "Sony S1XP",
1906                 .type = AC97_TUNE_INV_EAPD
1907         },
1908         {
1909                 .subvendor = 0x1043,
1910                 .subdevice = 0x80f3,
1911                 .name = "ASUS ICH5/AD1985",
1912                 .type = AC97_TUNE_AD_SHARING
1913         },
1914         {
1915                 .subvendor = 0x10cf,
1916                 .subdevice = 0x11c3,
1917                 .name = "Fujitsu-Siemens E4010",
1918                 .type = AC97_TUNE_HP_ONLY
1919         },
1920         {
1921                 .subvendor = 0x10cf,
1922                 .subdevice = 0x1225,
1923                 .name = "Fujitsu-Siemens T3010",
1924                 .type = AC97_TUNE_HP_ONLY
1925         },
1926         {
1927                 .subvendor = 0x10cf,
1928                 .subdevice = 0x1253,
1929                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1930                 .type = AC97_TUNE_HP_ONLY
1931         },
1932         {
1933                 .subvendor = 0x10cf,
1934                 .subdevice = 0x12ec,
1935                 .name = "Fujitsu-Siemens 4010",
1936                 .type = AC97_TUNE_HP_ONLY
1937         },
1938         {
1939                 .subvendor = 0x10cf,
1940                 .subdevice = 0x12f2,
1941                 .name = "Fujitsu-Siemens Celsius H320",
1942                 .type = AC97_TUNE_SWAP_HP
1943         },
1944         {
1945                 .subvendor = 0x10f1,
1946                 .subdevice = 0x2665,
1947                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1948                 .type = AC97_TUNE_HP_ONLY
1949         },
1950         {
1951                 .subvendor = 0x10f1,
1952                 .subdevice = 0x2885,
1953                 .name = "AMD64 Mobo",   /* ALC650 */
1954                 .type = AC97_TUNE_HP_ONLY
1955         },
1956         {
1957                 .subvendor = 0x110a,
1958                 .subdevice = 0x0056,
1959                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1960                 .type = AC97_TUNE_HP_ONLY
1961         },
1962         {
1963                 .subvendor = 0x11d4,
1964                 .subdevice = 0x5375,
1965                 .name = "ADI AD1985 (discrete)",
1966                 .type = AC97_TUNE_HP_ONLY
1967         },
1968         {
1969                 .subvendor = 0x1462,
1970                 .subdevice = 0x5470,
1971                 .name = "MSI P4 ATX 645 Ultra",
1972                 .type = AC97_TUNE_HP_ONLY
1973         },
1974         {
1975                 .subvendor = 0x1734,
1976                 .subdevice = 0x0088,
1977                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1978                 .type = AC97_TUNE_HP_ONLY
1979         },
1980         {
1981                 .subvendor = 0x8086,
1982                 .subdevice = 0x2000,
1983                 .mask = 0xfff0,
1984                 .name = "Intel ICH5/AD1985",
1985                 .type = AC97_TUNE_AD_SHARING
1986         },
1987         {
1988                 .subvendor = 0x8086,
1989                 .subdevice = 0x4000,
1990                 .mask = 0xfff0,
1991                 .name = "Intel ICH5/AD1985",
1992                 .type = AC97_TUNE_AD_SHARING
1993         },
1994         {
1995                 .subvendor = 0x8086,
1996                 .subdevice = 0x4856,
1997                 .name = "Intel D845WN (82801BA)",
1998                 .type = AC97_TUNE_SWAP_HP
1999         },
2000         {
2001                 .subvendor = 0x8086,
2002                 .subdevice = 0x4d44,
2003                 .name = "Intel D850EMV2",       /* AD1885 */
2004                 .type = AC97_TUNE_HP_ONLY
2005         },
2006         {
2007                 .subvendor = 0x8086,
2008                 .subdevice = 0x4d56,
2009                 .name = "Intel ICH/AD1885",
2010                 .type = AC97_TUNE_HP_ONLY
2011         },
2012         {
2013                 .subvendor = 0x8086,
2014                 .subdevice = 0x6000,
2015                 .mask = 0xfff0,
2016                 .name = "Intel ICH5/AD1985",
2017                 .type = AC97_TUNE_AD_SHARING
2018         },
2019         {
2020                 .subvendor = 0x8086,
2021                 .subdevice = 0xe000,
2022                 .mask = 0xfff0,
2023                 .name = "Intel ICH5/AD1985",
2024                 .type = AC97_TUNE_AD_SHARING
2025         },
2026 #if 0 /* FIXME: this seems wrong on most boards */
2027         {
2028                 .subvendor = 0x8086,
2029                 .subdevice = 0xa000,
2030                 .mask = 0xfff0,
2031                 .name = "Intel ICH5/AD1985",
2032                 .type = AC97_TUNE_HP_ONLY
2033         },
2034 #endif
2035         { } /* terminator */
2036 };
2037
2038 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2039                                         const char *quirk_override)
2040 {
2041         struct snd_ac97_bus *pbus;
2042         struct snd_ac97_template ac97;
2043         int err;
2044         unsigned int i, codecs;
2045         unsigned int glob_sta = 0;
2046         struct snd_ac97_bus_ops *ops;
2047         static struct snd_ac97_bus_ops standard_bus_ops = {
2048                 .write = snd_intel8x0_codec_write,
2049                 .read = snd_intel8x0_codec_read,
2050         };
2051         static struct snd_ac97_bus_ops ali_bus_ops = {
2052                 .write = snd_intel8x0_ali_codec_write,
2053                 .read = snd_intel8x0_ali_codec_read,
2054         };
2055
2056         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2057         switch (chip->device_type) {
2058         case DEVICE_NFORCE:
2059                 chip->spdif_idx = NVD_SPBAR;
2060                 break;
2061         case DEVICE_ALI:
2062                 chip->spdif_idx = ALID_AC97SPDIFOUT;
2063                 break;
2064         case DEVICE_INTEL_ICH4:
2065                 chip->spdif_idx = ICHD_SPBAR;
2066                 break;
2067         };
2068
2069         chip->in_ac97_init = 1;
2070
2071         memset(&ac97, 0, sizeof(ac97));
2072         ac97.private_data = chip;
2073         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2074         ac97.scaps = AC97_SCAP_SKIP_MODEM;
2075         if (chip->xbox)
2076                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2077         if (chip->device_type != DEVICE_ALI) {
2078                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2079                 ops = &standard_bus_ops;
2080                 if (chip->device_type == DEVICE_INTEL_ICH4) {
2081                         codecs = 0;
2082                         if (glob_sta & ICH_PCR)
2083                                 codecs++;
2084                         if (glob_sta & ICH_SCR)
2085                                 codecs++;
2086                         if (glob_sta & ICH_TCR)
2087                                 codecs++;
2088                         chip->in_sdin_init = 1;
2089                         for (i = 0; i < codecs; i++) {
2090                                 snd_intel8x0_codec_read_test(chip, i);
2091                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2092                         }
2093                         chip->in_sdin_init = 0;
2094                 } else {
2095                         codecs = glob_sta & ICH_SCR ? 2 : 1;
2096                 }
2097         } else {
2098                 ops = &ali_bus_ops;
2099                 codecs = 1;
2100                 /* detect the secondary codec */
2101                 for (i = 0; i < 100; i++) {
2102                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2103                         if (reg & 0x40) {
2104                                 codecs = 2;
2105                                 break;
2106                         }
2107                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2108                         udelay(1);
2109                 }
2110         }
2111         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2112                 goto __err;
2113         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2114         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2115                 pbus->clock = ac97_clock;
2116         /* FIXME: my test board doesn't work well with VRA... */
2117         if (chip->device_type == DEVICE_ALI)
2118                 pbus->no_vra = 1;
2119         else
2120                 pbus->dra = 1;
2121         chip->ac97_bus = pbus;
2122
2123         ac97.pci = chip->pci;
2124         for (i = 0; i < codecs; i++) {
2125                 ac97.num = i;
2126                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2127                         if (err != -EACCES)
2128                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2129                         if (i == 0)
2130                                 goto __err;
2131                         continue;
2132                 }
2133         }
2134         /* tune up the primary codec */
2135         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2136         /* enable separate SDINs for ICH4 */
2137         if (chip->device_type == DEVICE_INTEL_ICH4)
2138                 pbus->isdin = 1;
2139         /* find the available PCM streams */
2140         i = ARRAY_SIZE(ac97_pcm_defs);
2141         if (chip->device_type != DEVICE_INTEL_ICH4)
2142                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2143         if (chip->spdif_idx < 0)
2144                 i--;            /* do not allocate S/PDIF */
2145         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2146         if (err < 0)
2147                 goto __err;
2148         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2149         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2150         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2151         if (chip->spdif_idx >= 0)
2152                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2153         if (chip->device_type == DEVICE_INTEL_ICH4) {
2154                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2155                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2156         }
2157         /* enable separate SDINs for ICH4 */
2158         if (chip->device_type == DEVICE_INTEL_ICH4) {
2159                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2160                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2161                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2162                 if (pcm) {
2163                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2164                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2165                         for (i = 1; i < 4; i++) {
2166                                 if (pcm->r[0].codec[i]) {
2167                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2168                                         break;
2169                                 }
2170                         }
2171                 } else {
2172                         tmp &= ~ICH_SE; /* steer disable */
2173                 }
2174                 iputbyte(chip, ICHREG(SDM), tmp);
2175         }
2176         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2177                 chip->multi4 = 1;
2178                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2179                         chip->multi6 = 1;
2180         }
2181         if (pbus->pcms[0].r[1].rslots[0]) {
2182                 chip->dra = 1;
2183         }
2184         if (chip->device_type == DEVICE_INTEL_ICH4) {
2185                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2186                         chip->smp20bit = 1;
2187         }
2188         if (chip->device_type == DEVICE_NFORCE) {
2189                 /* 48kHz only */
2190                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2191         }
2192         if (chip->device_type == DEVICE_INTEL_ICH4) {
2193                 /* use slot 10/11 for SPDIF */
2194                 u32 val;
2195                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2196                 val |= ICH_PCM_SPDIF_1011;
2197                 iputdword(chip, ICHREG(GLOB_CNT), val);
2198                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2199         }
2200         chip->in_ac97_init = 0;
2201         return 0;
2202
2203  __err:
2204         /* clear the cold-reset bit for the next chance */
2205         if (chip->device_type != DEVICE_ALI)
2206                 iputdword(chip, ICHREG(GLOB_CNT),
2207                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2208         return err;
2209 }
2210
2211
2212 /*
2213  *
2214  */
2215
2216 static void do_ali_reset(struct intel8x0 *chip)
2217 {
2218         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2219         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2220         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2221         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2222         iputdword(chip, ICHREG(ALI_INTERFACECR),
2223                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2224         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2225         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2226 }
2227
2228 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2229 {
2230         unsigned long end_time;
2231         unsigned int cnt, status, nstatus;
2232
2233         /* put logic to right state */
2234         /* first clear status bits */
2235         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2236         if (chip->device_type == DEVICE_NFORCE)
2237                 status |= ICH_NVSPINT;
2238         cnt = igetdword(chip, ICHREG(GLOB_STA));
2239         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2240
2241         /* ACLink on, 2 channels */
2242         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2243         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2244         /* finish cold or do warm reset */
2245         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2246         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2247         end_time = (jiffies + (HZ / 4)) + 1;
2248         do {
2249                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2250                         goto __ok;
2251                 schedule_timeout_uninterruptible(1);
2252         } while (time_after_eq(end_time, jiffies));
2253         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2254                    igetdword(chip, ICHREG(GLOB_CNT)));
2255         return -EIO;
2256
2257       __ok:
2258         if (probing) {
2259                 /* wait for any codec ready status.
2260                  * Once it becomes ready it should remain ready
2261                  * as long as we do not disable the ac97 link.
2262                  */
2263                 end_time = jiffies + HZ;
2264                 do {
2265                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2266                                 (ICH_PCR | ICH_SCR | ICH_TCR);
2267                         if (status)
2268                                 break;
2269                         schedule_timeout_uninterruptible(1);
2270                 } while (time_after_eq(end_time, jiffies));
2271                 if (! status) {
2272                         /* no codec is found */
2273                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2274                                    igetdword(chip, ICHREG(GLOB_STA)));
2275                         return -EIO;
2276                 }
2277
2278                 if (chip->device_type == DEVICE_INTEL_ICH4)
2279                         /* ICH4 can have three codecs */
2280                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2281                 else
2282                         /* others up to two codecs */
2283                         nstatus = ICH_PCR | ICH_SCR;
2284
2285                 /* wait for other codecs ready status. */
2286                 end_time = jiffies + HZ / 4;
2287                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2288                         schedule_timeout_uninterruptible(1);
2289                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2290                 }
2291
2292         } else {
2293                 /* resume phase */
2294                 int i;
2295                 status = 0;
2296                 for (i = 0; i < 3; i++)
2297                         if (chip->ac97[i])
2298                                 status |= get_ich_codec_bit(chip, i);
2299                 /* wait until all the probed codecs are ready */
2300                 end_time = jiffies + HZ;
2301                 do {
2302                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2303                                 (ICH_PCR | ICH_SCR | ICH_TCR);
2304                         if (status == nstatus)
2305                                 break;
2306                         schedule_timeout_uninterruptible(1);
2307                 } while (time_after_eq(end_time, jiffies));
2308         }
2309
2310         if (chip->device_type == DEVICE_SIS) {
2311                 /* unmute the output on SIS7012 */
2312                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2313         }
2314         if (chip->device_type == DEVICE_NFORCE) {
2315                 /* enable SPDIF interrupt */
2316                 unsigned int val;
2317                 pci_read_config_dword(chip->pci, 0x4c, &val);
2318                 val |= 0x1000000;
2319                 pci_write_config_dword(chip->pci, 0x4c, val);
2320         }
2321         return 0;
2322 }
2323
2324 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2325 {
2326         u32 reg;
2327         int i = 0;
2328
2329         reg = igetdword(chip, ICHREG(ALI_SCR));
2330         if ((reg & 2) == 0)     /* Cold required */
2331                 reg |= 2;
2332         else
2333                 reg |= 1;       /* Warm */
2334         reg &= ~0x80000000;     /* ACLink on */
2335         iputdword(chip, ICHREG(ALI_SCR), reg);
2336
2337         for (i = 0; i < HZ / 2; i++) {
2338                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2339                         goto __ok;
2340                 schedule_timeout_uninterruptible(1);
2341         }
2342         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2343         if (probing)
2344                 return -EIO;
2345
2346  __ok:
2347         for (i = 0; i < HZ / 2; i++) {
2348                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2349                 if (reg & 0x80) /* primary codec */
2350                         break;
2351                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2352                 schedule_timeout_uninterruptible(1);
2353         }
2354
2355         do_ali_reset(chip);
2356         return 0;
2357 }
2358
2359 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2360 {
2361         unsigned int i;
2362         int err;
2363
2364         if (chip->device_type != DEVICE_ALI) {
2365                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2366                         return err;
2367                 iagetword(chip, 0);     /* clear semaphore flag */
2368         } else {
2369                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2370                         return err;
2371         }
2372
2373         /* disable interrupts */
2374         for (i = 0; i < chip->bdbars_count; i++)
2375                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2376         /* reset channels */
2377         for (i = 0; i < chip->bdbars_count; i++)
2378                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2379         /* initialize Buffer Descriptor Lists */
2380         for (i = 0; i < chip->bdbars_count; i++)
2381                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2382                           chip->ichd[i].bdbar_addr);
2383         return 0;
2384 }
2385
2386 static int snd_intel8x0_free(struct intel8x0 *chip)
2387 {
2388         unsigned int i;
2389
2390         if (chip->irq < 0)
2391                 goto __hw_end;
2392         /* disable interrupts */
2393         for (i = 0; i < chip->bdbars_count; i++)
2394                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2395         /* reset channels */
2396         for (i = 0; i < chip->bdbars_count; i++)
2397                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2398         if (chip->device_type == DEVICE_NFORCE) {
2399                 /* stop the spdif interrupt */
2400                 unsigned int val;
2401                 pci_read_config_dword(chip->pci, 0x4c, &val);
2402                 val &= ~0x1000000;
2403                 pci_write_config_dword(chip->pci, 0x4c, val);
2404         }
2405         /* --- */
2406         synchronize_irq(chip->irq);
2407       __hw_end:
2408         if (chip->irq >= 0)
2409                 free_irq(chip->irq, chip);
2410         if (chip->bdbars.area) {
2411                 if (chip->fix_nocache)
2412                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2413                 snd_dma_free_pages(&chip->bdbars);
2414         }
2415         if (chip->remap_addr)
2416                 iounmap(chip->remap_addr);
2417         if (chip->remap_bmaddr)
2418                 iounmap(chip->remap_bmaddr);
2419         pci_release_regions(chip->pci);
2420         pci_disable_device(chip->pci);
2421         kfree(chip);
2422         return 0;
2423 }
2424
2425 #ifdef CONFIG_PM
2426 /*
2427  * power management
2428  */
2429 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2430 {
2431         struct snd_card *card = pci_get_drvdata(pci);
2432         struct intel8x0 *chip = card->private_data;
2433         int i;
2434
2435         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2436         for (i = 0; i < chip->pcm_devs; i++)
2437                 snd_pcm_suspend_all(chip->pcm[i]);
2438         /* clear nocache */
2439         if (chip->fix_nocache) {
2440                 for (i = 0; i < chip->bdbars_count; i++) {
2441                         struct ichdev *ichdev = &chip->ichd[i];
2442                         if (ichdev->substream && ichdev->page_attr_changed) {
2443                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2444                                 if (runtime->dma_area)
2445                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2446                         }
2447                 }
2448         }
2449         for (i = 0; i < 3; i++)
2450                 snd_ac97_suspend(chip->ac97[i]);
2451         if (chip->device_type == DEVICE_INTEL_ICH4)
2452                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2453
2454         if (chip->irq >= 0)
2455                 free_irq(chip->irq, chip);
2456         pci_disable_device(pci);
2457         pci_save_state(pci);
2458         return 0;
2459 }
2460
2461 static int intel8x0_resume(struct pci_dev *pci)
2462 {
2463         struct snd_card *card = pci_get_drvdata(pci);
2464         struct intel8x0 *chip = card->private_data;
2465         int i;
2466
2467         pci_restore_state(pci);
2468         pci_enable_device(pci);
2469         pci_set_master(pci);
2470         request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ,
2471                     card->shortname, chip);
2472         chip->irq = pci->irq;
2473         synchronize_irq(chip->irq);
2474         snd_intel8x0_chip_init(chip, 1);
2475
2476         /* re-initialize mixer stuff */
2477         if (chip->device_type == DEVICE_INTEL_ICH4) {
2478                 /* enable separate SDINs for ICH4 */
2479                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2480                 /* use slot 10/11 for SPDIF */
2481                 iputdword(chip, ICHREG(GLOB_CNT),
2482                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2483                           ICH_PCM_SPDIF_1011);
2484         }
2485
2486         /* refill nocache */
2487         if (chip->fix_nocache)
2488                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2489
2490         for (i = 0; i < 3; i++)
2491                 snd_ac97_resume(chip->ac97[i]);
2492
2493         /* refill nocache */
2494         if (chip->fix_nocache) {
2495                 for (i = 0; i < chip->bdbars_count; i++) {
2496                         struct ichdev *ichdev = &chip->ichd[i];
2497                         if (ichdev->substream && ichdev->page_attr_changed) {
2498                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2499                                 if (runtime->dma_area)
2500                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2501                         }
2502                 }
2503         }
2504
2505         /* resume status */
2506         for (i = 0; i < chip->bdbars_count; i++) {
2507                 struct ichdev *ichdev = &chip->ichd[i];
2508                 unsigned long port = ichdev->reg_offset;
2509                 if (! ichdev->substream || ! ichdev->suspended)
2510                         continue;
2511                 if (ichdev->ichd == ICHD_PCMOUT)
2512                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2513                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2514                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2515                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2516                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2517         }
2518
2519         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2520         return 0;
2521 }
2522 #endif /* CONFIG_PM */
2523
2524 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2525
2526 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2527 {
2528         struct snd_pcm_substream *subs;
2529         struct ichdev *ichdev;
2530         unsigned long port;
2531         unsigned long pos, t;
2532         struct timeval start_time, stop_time;
2533
2534         if (chip->ac97_bus->clock != 48000)
2535                 return; /* specified in module option */
2536
2537         subs = chip->pcm[0]->streams[0].substream;
2538         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2539                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2540                 return;
2541         }
2542         ichdev = &chip->ichd[ICHD_PCMOUT];
2543         ichdev->physbuf = subs->dma_buffer.addr;
2544         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2545         ichdev->substream = NULL; /* don't process interrupts */
2546
2547         /* set rate */
2548         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2549                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2550                 return;
2551         }
2552         snd_intel8x0_setup_periods(chip, ichdev);
2553         port = ichdev->reg_offset;
2554         spin_lock_irq(&chip->reg_lock);
2555         chip->in_measurement = 1;
2556         /* trigger */
2557         if (chip->device_type != DEVICE_ALI)
2558                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2559         else {
2560                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2561                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2562         }
2563         do_gettimeofday(&start_time);
2564         spin_unlock_irq(&chip->reg_lock);
2565         msleep(50);
2566         spin_lock_irq(&chip->reg_lock);
2567         /* check the position */
2568         pos = ichdev->fragsize1;
2569         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2570         pos += ichdev->position;
2571         chip->in_measurement = 0;
2572         do_gettimeofday(&stop_time);
2573         /* stop */
2574         if (chip->device_type == DEVICE_ALI) {
2575                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2576                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2577                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2578                         ;
2579         } else {
2580                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2581                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2582                         ;
2583         }
2584         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2585         spin_unlock_irq(&chip->reg_lock);
2586
2587         t = stop_time.tv_sec - start_time.tv_sec;
2588         t *= 1000000;
2589         t += stop_time.tv_usec - start_time.tv_usec;
2590         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2591         if (t == 0) {
2592                 snd_printk(KERN_ERR "?? calculation error..\n");
2593                 return;
2594         }
2595         pos = (pos / 4) * 1000;
2596         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2597         if (pos < 40000 || pos >= 60000)
2598                 /* abnormal value. hw problem? */
2599                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2600         else if (pos < 47500 || pos > 48500)
2601                 /* not 48000Hz, tuning the clock.. */
2602                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2603         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2604 }
2605
2606 #ifdef CONFIG_PROC_FS
2607 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2608                                    struct snd_info_buffer *buffer)
2609 {
2610         struct intel8x0 *chip = entry->private_data;
2611         unsigned int tmp;
2612
2613         snd_iprintf(buffer, "Intel8x0\n\n");
2614         if (chip->device_type == DEVICE_ALI)
2615                 return;
2616         tmp = igetdword(chip, ICHREG(GLOB_STA));
2617         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2618         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2619         if (chip->device_type == DEVICE_INTEL_ICH4)
2620                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2621         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2622                         tmp & ICH_PCR ? " primary" : "",
2623                         tmp & ICH_SCR ? " secondary" : "",
2624                         tmp & ICH_TCR ? " tertiary" : "",
2625                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2626         if (chip->device_type == DEVICE_INTEL_ICH4)
2627                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2628                         chip->ac97_sdin[0],
2629                         chip->ac97_sdin[1],
2630                         chip->ac97_sdin[2]);
2631 }
2632
2633 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2634 {
2635         struct snd_info_entry *entry;
2636
2637         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2638                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2639 }
2640 #else
2641 #define snd_intel8x0_proc_init(x)
2642 #endif
2643
2644 static int snd_intel8x0_dev_free(struct snd_device *device)
2645 {
2646         struct intel8x0 *chip = device->device_data;
2647         return snd_intel8x0_free(chip);
2648 }
2649
2650 struct ich_reg_info {
2651         unsigned int int_sta_mask;
2652         unsigned int offset;
2653 };
2654
2655 static int __devinit snd_intel8x0_create(struct snd_card *card,
2656                                          struct pci_dev *pci,
2657                                          unsigned long device_type,
2658                                          struct intel8x0 ** r_intel8x0)
2659 {
2660         struct intel8x0 *chip;
2661         int err;
2662         unsigned int i;
2663         unsigned int int_sta_masks;
2664         struct ichdev *ichdev;
2665         static struct snd_device_ops ops = {
2666                 .dev_free =     snd_intel8x0_dev_free,
2667         };
2668
2669         static unsigned int bdbars[] = {
2670                 3, /* DEVICE_INTEL */
2671                 6, /* DEVICE_INTEL_ICH4 */
2672                 3, /* DEVICE_SIS */
2673                 6, /* DEVICE_ALI */
2674                 4, /* DEVICE_NFORCE */
2675         };
2676         static struct ich_reg_info intel_regs[6] = {
2677                 { ICH_PIINT, 0 },
2678                 { ICH_POINT, 0x10 },
2679                 { ICH_MCINT, 0x20 },
2680                 { ICH_M2INT, 0x40 },
2681                 { ICH_P2INT, 0x50 },
2682                 { ICH_SPINT, 0x60 },
2683         };
2684         static struct ich_reg_info nforce_regs[4] = {
2685                 { ICH_PIINT, 0 },
2686                 { ICH_POINT, 0x10 },
2687                 { ICH_MCINT, 0x20 },
2688                 { ICH_NVSPINT, 0x70 },
2689         };
2690         static struct ich_reg_info ali_regs[6] = {
2691                 { ALI_INT_PCMIN, 0x40 },
2692                 { ALI_INT_PCMOUT, 0x50 },
2693                 { ALI_INT_MICIN, 0x60 },
2694                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2695                 { ALI_INT_SPDIFIN, 0xa0 },
2696                 { ALI_INT_SPDIFOUT, 0xb0 },
2697         };
2698         struct ich_reg_info *tbl;
2699
2700         *r_intel8x0 = NULL;
2701
2702         if ((err = pci_enable_device(pci)) < 0)
2703                 return err;
2704
2705         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2706         if (chip == NULL) {
2707                 pci_disable_device(pci);
2708                 return -ENOMEM;
2709         }
2710         spin_lock_init(&chip->reg_lock);
2711         chip->device_type = device_type;
2712         chip->card = card;
2713         chip->pci = pci;
2714         chip->irq = -1;
2715
2716         /* module parameters */
2717         chip->buggy_irq = buggy_irq;
2718         chip->buggy_semaphore = buggy_semaphore;
2719         if (xbox)
2720                 chip->xbox = 1;
2721
2722         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2723             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2724                 chip->fix_nocache = 1; /* enable workaround */
2725
2726         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2727                 kfree(chip);
2728                 pci_disable_device(pci);
2729                 return err;
2730         }
2731
2732         if (device_type == DEVICE_ALI) {
2733                 /* ALI5455 has no ac97 region */
2734                 chip->bmaddr = pci_resource_start(pci, 0);
2735                 goto port_inited;
2736         }
2737
2738         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2739                 chip->mmio = 1;
2740                 chip->addr = pci_resource_start(pci, 2);
2741                 chip->remap_addr = ioremap_nocache(chip->addr,
2742                                                    pci_resource_len(pci, 2));
2743                 if (chip->remap_addr == NULL) {
2744                         snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2745                         snd_intel8x0_free(chip);
2746                         return -EIO;
2747                 }
2748         } else {
2749                 chip->addr = pci_resource_start(pci, 0);
2750         }
2751         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2752                 chip->bm_mmio = 1;
2753                 chip->bmaddr = pci_resource_start(pci, 3);
2754                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2755                                                      pci_resource_len(pci, 3));
2756                 if (chip->remap_bmaddr == NULL) {
2757                         snd_printk(KERN_ERR "Controller space ioremap problem\n");
2758                         snd_intel8x0_free(chip);
2759                         return -EIO;
2760                 }
2761         } else {
2762                 chip->bmaddr = pci_resource_start(pci, 1);
2763         }
2764
2765  port_inited:
2766         chip->bdbars_count = bdbars[device_type];
2767
2768         /* initialize offsets */
2769         switch (device_type) {
2770         case DEVICE_NFORCE:
2771                 tbl = nforce_regs;
2772                 break;
2773         case DEVICE_ALI:
2774                 tbl = ali_regs;
2775                 break;
2776         default:
2777                 tbl = intel_regs;
2778                 break;
2779         }
2780         for (i = 0; i < chip->bdbars_count; i++) {
2781                 ichdev = &chip->ichd[i];
2782                 ichdev->ichd = i;
2783                 ichdev->reg_offset = tbl[i].offset;
2784                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2785                 if (device_type == DEVICE_SIS) {
2786                         /* SiS 7012 swaps the registers */
2787                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2788                         ichdev->roff_picb = ICH_REG_OFF_SR;
2789                 } else {
2790                         ichdev->roff_sr = ICH_REG_OFF_SR;
2791                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2792                 }
2793                 if (device_type == DEVICE_ALI)
2794                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2795                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2796                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2797         }
2798
2799         /* allocate buffer descriptor lists */
2800         /* the start of each lists must be aligned to 8 bytes */
2801         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2802                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2803                                 &chip->bdbars) < 0) {
2804                 snd_intel8x0_free(chip);
2805                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2806                 return -ENOMEM;
2807         }
2808         /* tables must be aligned to 8 bytes here, but the kernel pages
2809            are much bigger, so we don't care (on i386) */
2810         /* workaround for 440MX */
2811         if (chip->fix_nocache)
2812                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2813         int_sta_masks = 0;
2814         for (i = 0; i < chip->bdbars_count; i++) {
2815                 ichdev = &chip->ichd[i];
2816                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2817                         (i * ICH_MAX_FRAGS * 2);
2818                 ichdev->bdbar_addr = chip->bdbars.addr +
2819                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2820                 int_sta_masks |= ichdev->int_sta_mask;
2821         }
2822         chip->int_sta_reg = device_type == DEVICE_ALI ?
2823                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2824         chip->int_sta_mask = int_sta_masks;
2825
2826         /* request irq after initializaing int_sta_mask, etc */
2827         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2828                         SA_INTERRUPT|SA_SHIRQ, card->shortname, chip)) {
2829                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2830                 snd_intel8x0_free(chip);
2831                 return -EBUSY;
2832         }
2833         chip->irq = pci->irq;
2834         pci_set_master(pci);
2835         synchronize_irq(chip->irq);
2836
2837         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2838                 snd_intel8x0_free(chip);
2839                 return err;
2840         }
2841
2842         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2843                 snd_intel8x0_free(chip);
2844                 return err;
2845         }
2846
2847         snd_card_set_dev(card, &pci->dev);
2848
2849         *r_intel8x0 = chip;
2850         return 0;
2851 }
2852
2853 static struct shortname_table {
2854         unsigned int id;
2855         const char *s;
2856 } shortnames[] __devinitdata = {
2857         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2858         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2859         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2860         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2861         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2862         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2863         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2864         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2865         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2866         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2867         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2868         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2869         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2870         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2871         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2872         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2873         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2874         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2875         { 0x003a, "NVidia MCP04" },
2876         { 0x746d, "AMD AMD8111" },
2877         { 0x7445, "AMD AMD768" },
2878         { 0x5455, "ALi M5455" },
2879         { 0, NULL },
2880 };
2881
2882 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2883                                         const struct pci_device_id *pci_id)
2884 {
2885         struct snd_card *card;
2886         struct intel8x0 *chip;
2887         int err;
2888         struct shortname_table *name;
2889
2890         card = snd_card_new(index, id, THIS_MODULE, 0);
2891         if (card == NULL)
2892                 return -ENOMEM;
2893
2894         switch (pci_id->driver_data) {
2895         case DEVICE_NFORCE:
2896                 strcpy(card->driver, "NFORCE");
2897                 break;
2898         case DEVICE_INTEL_ICH4:
2899                 strcpy(card->driver, "ICH4");
2900                 break;
2901         default:
2902                 strcpy(card->driver, "ICH");
2903                 break;
2904         }
2905
2906         strcpy(card->shortname, "Intel ICH");
2907         for (name = shortnames; name->id; name++) {
2908                 if (pci->device == name->id) {
2909                         strcpy(card->shortname, name->s);
2910                         break;
2911                 }
2912         }
2913
2914         if (buggy_irq < 0) {
2915                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2916                  * Needs to return IRQ_HANDLED for unknown irqs.
2917                  */
2918                 if (pci_id->driver_data == DEVICE_NFORCE)
2919                         buggy_irq = 1;
2920                 else
2921                         buggy_irq = 0;
2922         }
2923
2924         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
2925                                        &chip)) < 0) {
2926                 snd_card_free(card);
2927                 return err;
2928         }
2929         card->private_data = chip;
2930
2931         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
2932                 snd_card_free(card);
2933                 return err;
2934         }
2935         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2936                 snd_card_free(card);
2937                 return err;
2938         }
2939
2940         snd_intel8x0_proc_init(chip);
2941
2942         snprintf(card->longname, sizeof(card->longname),
2943                  "%s with %s at %#lx, irq %i", card->shortname,
2944                  snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2945
2946         if (! ac97_clock)
2947                 intel8x0_measure_ac97_clock(chip);
2948
2949         if ((err = snd_card_register(card)) < 0) {
2950                 snd_card_free(card);
2951                 return err;
2952         }
2953         pci_set_drvdata(pci, card);
2954         return 0;
2955 }
2956
2957 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2958 {
2959         snd_card_free(pci_get_drvdata(pci));
2960         pci_set_drvdata(pci, NULL);
2961 }
2962
2963 static struct pci_driver driver = {
2964         .name = "Intel ICH",
2965         .id_table = snd_intel8x0_ids,
2966         .probe = snd_intel8x0_probe,
2967         .remove = __devexit_p(snd_intel8x0_remove),
2968 #ifdef CONFIG_PM
2969         .suspend = intel8x0_suspend,
2970         .resume = intel8x0_resume,
2971 #endif
2972 };
2973
2974
2975 static int __init alsa_card_intel8x0_init(void)
2976 {
2977         return pci_register_driver(&driver);
2978 }
2979
2980 static void __exit alsa_card_intel8x0_exit(void)
2981 {
2982         pci_unregister_driver(&driver);
2983 }
2984
2985 module_init(alsa_card_intel8x0_init)
2986 module_exit(alsa_card_intel8x0_exit)