Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6] / arch / powerpc / platforms / cell / setup.c
1 /*
2  *  linux/arch/powerpc/platforms/cell/cell_setup.c
3  *
4  *  Copyright (C) 1995  Linus Torvalds
5  *  Adapted from 'alpha' version by Gary Thomas
6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
7  *  Modified by PPC64 Team, IBM Corp
8  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version
13  * 2 of the License, or (at your option) any later version.
14  */
15 #undef DEBUG
16
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/slab.h>
23 #include <linux/user.h>
24 #include <linux/reboot.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/seq_file.h>
29 #include <linux/root_dev.h>
30 #include <linux/console.h>
31 #include <linux/mutex.h>
32 #include <linux/memory_hotplug.h>
33 #include <linux/of_platform.h>
34
35 #include <asm/mmu.h>
36 #include <asm/processor.h>
37 #include <asm/io.h>
38 #include <asm/kexec.h>
39 #include <asm/pgtable.h>
40 #include <asm/prom.h>
41 #include <asm/rtas.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/iommu.h>
44 #include <asm/dma.h>
45 #include <asm/machdep.h>
46 #include <asm/time.h>
47 #include <asm/nvram.h>
48 #include <asm/cputable.h>
49 #include <asm/ppc-pci.h>
50 #include <asm/irq.h>
51 #include <asm/spu.h>
52 #include <asm/spu_priv1.h>
53 #include <asm/udbg.h>
54 #include <asm/mpic.h>
55 #include <asm/cell-regs.h>
56
57 #include "interrupt.h"
58 #include "pervasive.h"
59 #include "ras.h"
60 #include "io-workarounds.h"
61
62 #ifdef DEBUG
63 #define DBG(fmt...) udbg_printf(fmt)
64 #else
65 #define DBG(fmt...)
66 #endif
67
68 static void cell_show_cpuinfo(struct seq_file *m)
69 {
70         struct device_node *root;
71         const char *model = "";
72
73         root = of_find_node_by_path("/");
74         if (root)
75                 model = of_get_property(root, "model", NULL);
76         seq_printf(m, "machine\t\t: CHRP %s\n", model);
77         of_node_put(root);
78 }
79
80 static void cell_progress(char *s, unsigned short hex)
81 {
82         printk("*** %04x : %s\n", hex, s ? s : "");
83 }
84
85 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
86 {
87         struct pci_controller *hose;
88         const char *s;
89         int i;
90
91         if (!machine_is(cell))
92                 return;
93
94         /* We're searching for a direct child of the PHB */
95         if (dev->bus->self != NULL || dev->devfn != 0)
96                 return;
97
98         hose = pci_bus_to_host(dev->bus);
99         if (hose == NULL)
100                 return;
101
102         /* Only on PCIE */
103         if (!of_device_is_compatible(hose->dn, "pciex"))
104                 return;
105
106         /* And only on axon */
107         s = of_get_property(hose->dn, "model", NULL);
108         if (!s || strcmp(s, "Axon") != 0)
109                 return;
110
111         for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
112                 dev->resource[i].start = dev->resource[i].end = 0;
113                 dev->resource[i].flags = 0;
114         }
115
116         printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
117                pci_name(dev));
118 }
119 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
120
121 static int __devinit cell_setup_phb(struct pci_controller *phb)
122 {
123         const char *model;
124         struct device_node *np;
125
126         int rc = rtas_setup_phb(phb);
127         if (rc)
128                 return rc;
129
130         np = phb->dn;
131         model = of_get_property(np, "model", NULL);
132         if (model == NULL || strcmp(np->name, "pci"))
133                 return 0;
134
135         /* Setup workarounds for spider */
136         if (strcmp(model, "Spider"))
137                 return 0;
138
139         iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
140                                   (void *)SPIDER_PCI_REG_BASE);
141         io_workaround_init();
142
143         return 0;
144 }
145
146 static int __init cell_publish_devices(void)
147 {
148         struct device_node *root = of_find_node_by_path("/");
149         struct device_node *np;
150         int node;
151
152         /* Publish OF platform devices for southbridge IOs */
153         of_platform_bus_probe(NULL, NULL, NULL);
154
155         /* On spider based blades, we need to manually create the OF
156          * platform devices for the PCI host bridges
157          */
158         for_each_child_of_node(root, np) {
159                 if (np->type == NULL || (strcmp(np->type, "pci") != 0 &&
160                                          strcmp(np->type, "pciex") != 0))
161                         continue;
162                 of_platform_device_create(np, NULL, NULL);
163         }
164
165         /* There is no device for the MIC memory controller, thus we create
166          * a platform device for it to attach the EDAC driver to.
167          */
168         for_each_online_node(node) {
169                 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
170                         continue;
171                 platform_device_register_simple("cbe-mic", node, NULL, 0);
172         }
173
174         return 0;
175 }
176 machine_subsys_initcall(cell, cell_publish_devices);
177
178 static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
179 {
180         struct mpic *mpic = desc->handler_data;
181         unsigned int virq;
182
183         virq = mpic_get_one_irq(mpic);
184         if (virq != NO_IRQ)
185                 generic_handle_irq(virq);
186         desc->chip->eoi(irq);
187 }
188
189 static void __init mpic_init_IRQ(void)
190 {
191         struct device_node *dn;
192         struct mpic *mpic;
193         unsigned int virq;
194
195         for (dn = NULL;
196              (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
197                 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
198                         continue;
199
200                 /* The MPIC driver will get everything it needs from the
201                  * device-tree, just pass 0 to all arguments
202                  */
203                 mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC     ");
204                 if (mpic == NULL)
205                         continue;
206                 mpic_init(mpic);
207
208                 virq = irq_of_parse_and_map(dn, 0);
209                 if (virq == NO_IRQ)
210                         continue;
211
212                 printk(KERN_INFO "%s : hooking up to IRQ %d\n",
213                        dn->full_name, virq);
214                 set_irq_data(virq, mpic);
215                 set_irq_chained_handler(virq, cell_mpic_cascade);
216         }
217 }
218
219
220 static void __init cell_init_irq(void)
221 {
222         iic_init_IRQ();
223         spider_init_IRQ();
224         mpic_init_IRQ();
225 }
226
227 static void __init cell_set_dabrx(void)
228 {
229         mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
230 }
231
232 static void __init cell_setup_arch(void)
233 {
234 #ifdef CONFIG_SPU_BASE
235         spu_priv1_ops = &spu_priv1_mmio_ops;
236         spu_management_ops = &spu_management_of_ops;
237 #endif
238
239         cbe_regs_init();
240
241         cell_set_dabrx();
242
243 #ifdef CONFIG_CBE_RAS
244         cbe_ras_init();
245 #endif
246
247 #ifdef CONFIG_SMP
248         smp_init_cell();
249 #endif
250         /* init to some ~sane value until calibrate_delay() runs */
251         loops_per_jiffy = 50000000;
252
253         /* Find and initialize PCI host bridges */
254         init_pci_config_tokens();
255
256         cbe_pervasive_init();
257 #ifdef CONFIG_DUMMY_CONSOLE
258         conswitchp = &dummy_con;
259 #endif
260
261         mmio_nvram_init();
262 }
263
264 static int __init cell_probe(void)
265 {
266         unsigned long root = of_get_flat_dt_root();
267
268         if (!of_flat_dt_is_compatible(root, "IBM,CBEA") &&
269             !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
270                 return 0;
271
272         hpte_init_native();
273
274         return 1;
275 }
276
277 define_machine(cell) {
278         .name                   = "Cell",
279         .probe                  = cell_probe,
280         .setup_arch             = cell_setup_arch,
281         .show_cpuinfo           = cell_show_cpuinfo,
282         .restart                = rtas_restart,
283         .power_off              = rtas_power_off,
284         .halt                   = rtas_halt,
285         .get_boot_time          = rtas_get_boot_time,
286         .get_rtc_time           = rtas_get_rtc_time,
287         .set_rtc_time           = rtas_set_rtc_time,
288         .calibrate_decr         = generic_calibrate_decr,
289         .progress               = cell_progress,
290         .init_IRQ               = cell_init_irq,
291         .pci_setup_phb          = cell_setup_phb,
292 #ifdef CONFIG_KEXEC
293         .machine_kexec          = default_machine_kexec,
294         .machine_kexec_prepare  = default_machine_kexec_prepare,
295         .machine_crash_shutdown = default_machine_crash_shutdown,
296 #endif
297 };