2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
44 #include <asm/cacheflush.h>
46 #ifndef CONFIG_ARCH_MXC
47 #include <asm/coldfire.h>
48 #include <asm/mcfsim.h>
53 #ifdef CONFIG_ARCH_MXC
54 #include <mach/hardware.h>
55 #define FEC_ALIGNMENT 0xf
57 #define FEC_ALIGNMENT 0x3
61 * Define the fixed address of the FEC hardware.
63 #if defined(CONFIG_M5272)
64 #define HAVE_mii_link_interrupt
66 static unsigned char fec_mac_default[] = {
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
71 * Some hardware gets it MAC address out of local flash memory.
72 * if this is non-zero then assume it is the address to get MAC from.
74 #if defined(CONFIG_NETtel)
75 #define FEC_FLASHMAC 0xf0006006
76 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
77 #define FEC_FLASHMAC 0xf0006000
78 #elif defined(CONFIG_CANCam)
79 #define FEC_FLASHMAC 0xf0020000
80 #elif defined (CONFIG_M5272C3)
81 #define FEC_FLASHMAC (0xffe04000 + 4)
82 #elif defined(CONFIG_MOD5272)
83 #define FEC_FLASHMAC 0xffc0406b
85 #define FEC_FLASHMAC 0
87 #endif /* CONFIG_M5272 */
89 /* Forward declarations of some structures to support different PHYs */
93 void (*funct)(uint mii_reg, struct net_device *dev);
100 const phy_cmd_t *config;
101 const phy_cmd_t *startup;
102 const phy_cmd_t *ack_int;
103 const phy_cmd_t *shutdown;
106 /* The number of Tx and Rx buffers. These are allocated from the page
107 * pool. The code may assume these are power of two, so it it best
108 * to keep them that size.
109 * We don't need to allocate pages for the transmitter. We just use
110 * the skbuffer directly.
112 #define FEC_ENET_RX_PAGES 8
113 #define FEC_ENET_RX_FRSIZE 2048
114 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
115 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
116 #define FEC_ENET_TX_FRSIZE 2048
117 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
118 #define TX_RING_SIZE 16 /* Must be power of two */
119 #define TX_RING_MOD_MASK 15 /* for this to work */
121 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
122 #error "FEC: descriptor ring size constants too large"
125 /* Interrupt events/masks. */
126 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
127 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
128 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
129 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
130 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
131 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
132 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
133 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
134 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
135 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
137 /* The FEC stores dest/src/type, data, and checksum for receive packets.
139 #define PKT_MAXBUF_SIZE 1518
140 #define PKT_MINBUF_SIZE 64
141 #define PKT_MAXBLR_SIZE 1520
145 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
146 * size bits. Other FEC hardware does not, so we need to take that into
147 * account when setting it.
149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
151 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
153 #define OPT_FRAME_SIZE 0
156 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
157 * tx_bd_base always point to the base of the buffer descriptors. The
158 * cur_rx and cur_tx point to the currently available buffer.
159 * The dirty_tx tracks the current buffer that is being sent by the
160 * controller. The cur_tx and dirty_tx are equal under both completely
161 * empty and completely full conditions. The empty/ready indicator in
162 * the buffer descriptor determines the actual condition.
164 struct fec_enet_private {
165 /* Hardware registers of the FEC device */
168 struct net_device *netdev;
172 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
173 unsigned char *tx_bounce[TX_RING_SIZE];
174 struct sk_buff* tx_skbuff[TX_RING_SIZE];
178 /* CPM dual port RAM relative addresses */
180 /* Address of Rx and Tx buffers */
181 struct bufdesc *rx_bd_base;
182 struct bufdesc *tx_bd_base;
183 /* The next free ring entry */
184 struct bufdesc *cur_rx, *cur_tx;
185 /* The ring entries to be free()ed */
186 struct bufdesc *dirty_tx;
189 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
191 /* hold while accessing the mii_list_t() elements */
198 phy_info_t const *phy;
199 struct work_struct phy_task;
202 uint mii_phy_task_queued;
213 static int fec_enet_open(struct net_device *dev);
214 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
215 static void fec_enet_mii(struct net_device *dev);
216 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
217 static void fec_enet_tx(struct net_device *dev);
218 static void fec_enet_rx(struct net_device *dev);
219 static int fec_enet_close(struct net_device *dev);
220 static void set_multicast_list(struct net_device *dev);
221 static void fec_restart(struct net_device *dev, int duplex);
222 static void fec_stop(struct net_device *dev);
223 static void fec_set_mac_address(struct net_device *dev);
226 /* MII processing. We keep this as simple as possible. Requests are
227 * placed on the list (if there is room). When the request is finished
228 * by the MII, an optional function may be called.
230 typedef struct mii_list {
232 void (*mii_func)(uint val, struct net_device *dev);
233 struct mii_list *mii_next;
237 static mii_list_t mii_cmds[NMII];
238 static mii_list_t *mii_free;
239 static mii_list_t *mii_head;
240 static mii_list_t *mii_tail;
242 static int mii_queue(struct net_device *dev, int request,
243 void (*func)(uint, struct net_device *));
245 /* Make MII read/write commands for the FEC */
246 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
247 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
251 /* Transmitter timeout */
252 #define TX_TIMEOUT (2 * HZ)
254 /* Register definitions for the PHY */
256 #define MII_REG_CR 0 /* Control Register */
257 #define MII_REG_SR 1 /* Status Register */
258 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
259 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
260 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
261 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
262 #define MII_REG_ANER 6 /* A-N Expansion Register */
263 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
264 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
266 /* values for phy_status */
268 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
269 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
270 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
271 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
272 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
273 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
274 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
276 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
277 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
278 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
279 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
280 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
281 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
282 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
283 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
287 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
289 struct fec_enet_private *fep = netdev_priv(dev);
291 unsigned short status;
295 /* Link is down or autonegotiation is in progress. */
299 spin_lock_irqsave(&fep->hw_lock, flags);
300 /* Fill in a Tx ring entry */
303 status = bdp->cbd_sc;
305 if (status & BD_ENET_TX_READY) {
306 /* Ooops. All transmit buffers are full. Bail out.
307 * This should not happen, since dev->tbusy should be set.
309 printk("%s: tx queue full!.\n", dev->name);
310 spin_unlock_irqrestore(&fep->hw_lock, flags);
314 /* Clear all of the status flags */
315 status &= ~BD_ENET_TX_STATS;
317 /* Set buffer length and buffer pointer */
318 bdp->cbd_bufaddr = __pa(skb->data);
319 bdp->cbd_datlen = skb->len;
322 * On some FEC implementations data must be aligned on
323 * 4-byte boundaries. Use bounce buffers to copy data
324 * and get it aligned. Ugh.
326 if (bdp->cbd_bufaddr & FEC_ALIGNMENT) {
328 index = bdp - fep->tx_bd_base;
329 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
330 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
333 /* Save skb pointer */
334 fep->tx_skbuff[fep->skb_cur] = skb;
336 dev->stats.tx_bytes += skb->len;
337 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
339 /* Push the data cache so the CPM does not get stale memory
342 dma_sync_single(NULL, bdp->cbd_bufaddr,
343 bdp->cbd_datlen, DMA_TO_DEVICE);
345 /* Send it on its way. Tell FEC it's ready, interrupt when done,
346 * it's the last BD of the frame, and to put the CRC on the end.
348 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
349 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
350 bdp->cbd_sc = status;
352 dev->trans_start = jiffies;
354 /* Trigger transmission start */
355 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
357 /* If this was the last BD in the ring, start at the beginning again. */
358 if (status & BD_ENET_TX_WRAP)
359 bdp = fep->tx_bd_base;
363 if (bdp == fep->dirty_tx) {
365 netif_stop_queue(dev);
370 spin_unlock_irqrestore(&fep->hw_lock, flags);
376 fec_timeout(struct net_device *dev)
378 struct fec_enet_private *fep = netdev_priv(dev);
380 printk("%s: transmit timed out.\n", dev->name);
381 dev->stats.tx_errors++;
382 #ifndef final_version
387 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
388 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
389 (unsigned long)fep->dirty_tx,
390 (unsigned long)fep->cur_rx);
392 bdp = fep->tx_bd_base;
393 printk(" tx: %u buffers\n", TX_RING_SIZE);
394 for (i = 0 ; i < TX_RING_SIZE; i++) {
395 printk(" %08x: %04x %04x %08x\n",
399 (int) bdp->cbd_bufaddr);
403 bdp = fep->rx_bd_base;
404 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
405 for (i = 0 ; i < RX_RING_SIZE; i++) {
406 printk(" %08x: %04x %04x %08x\n",
410 (int) bdp->cbd_bufaddr);
415 fec_restart(dev, fep->full_duplex);
416 netif_wake_queue(dev);
420 fec_enet_interrupt(int irq, void * dev_id)
422 struct net_device *dev = dev_id;
423 struct fec_enet_private *fep = netdev_priv(dev);
425 irqreturn_t ret = IRQ_NONE;
428 int_events = readl(fep->hwp + FEC_IEVENT);
429 writel(int_events, fep->hwp + FEC_IEVENT);
431 if (int_events & FEC_ENET_RXF) {
436 /* Transmit OK, or non-fatal error. Update the buffer
437 * descriptors. FEC handles all errors, we just discover
438 * them as part of the transmit process.
440 if (int_events & FEC_ENET_TXF) {
445 if (int_events & FEC_ENET_MII) {
450 } while (int_events);
457 fec_enet_tx(struct net_device *dev)
459 struct fec_enet_private *fep;
461 unsigned short status;
464 fep = netdev_priv(dev);
465 spin_lock_irq(&fep->hw_lock);
468 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
469 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
471 skb = fep->tx_skbuff[fep->skb_dirty];
472 /* Check for errors. */
473 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
474 BD_ENET_TX_RL | BD_ENET_TX_UN |
476 dev->stats.tx_errors++;
477 if (status & BD_ENET_TX_HB) /* No heartbeat */
478 dev->stats.tx_heartbeat_errors++;
479 if (status & BD_ENET_TX_LC) /* Late collision */
480 dev->stats.tx_window_errors++;
481 if (status & BD_ENET_TX_RL) /* Retrans limit */
482 dev->stats.tx_aborted_errors++;
483 if (status & BD_ENET_TX_UN) /* Underrun */
484 dev->stats.tx_fifo_errors++;
485 if (status & BD_ENET_TX_CSL) /* Carrier lost */
486 dev->stats.tx_carrier_errors++;
488 dev->stats.tx_packets++;
491 if (status & BD_ENET_TX_READY)
492 printk("HEY! Enet xmit interrupt and TX_READY.\n");
494 /* Deferred means some collisions occurred during transmit,
495 * but we eventually sent the packet OK.
497 if (status & BD_ENET_TX_DEF)
498 dev->stats.collisions++;
500 /* Free the sk buffer associated with this last transmit */
501 dev_kfree_skb_any(skb);
502 fep->tx_skbuff[fep->skb_dirty] = NULL;
503 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
505 /* Update pointer to next buffer descriptor to be transmitted */
506 if (status & BD_ENET_TX_WRAP)
507 bdp = fep->tx_bd_base;
511 /* Since we have freed up a buffer, the ring is no longer full
515 if (netif_queue_stopped(dev))
516 netif_wake_queue(dev);
520 spin_unlock_irq(&fep->hw_lock);
524 /* During a receive, the cur_rx points to the current incoming buffer.
525 * When we update through the ring, if the next incoming buffer has
526 * not been given to the system, we just set the empty indicator,
527 * effectively tossing the packet.
530 fec_enet_rx(struct net_device *dev)
532 struct fec_enet_private *fep = netdev_priv(dev);
534 unsigned short status;
543 spin_lock_irq(&fep->hw_lock);
545 /* First, grab all of the stats for the incoming packet.
546 * These get messed up if we get called due to a busy condition.
550 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
552 /* Since we have allocated space to hold a complete frame,
553 * the last indicator should be set.
555 if ((status & BD_ENET_RX_LAST) == 0)
556 printk("FEC ENET: rcv is not +last\n");
559 goto rx_processing_done;
561 /* Check for errors. */
562 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
563 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
564 dev->stats.rx_errors++;
565 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
566 /* Frame too long or too short. */
567 dev->stats.rx_length_errors++;
569 if (status & BD_ENET_RX_NO) /* Frame alignment */
570 dev->stats.rx_frame_errors++;
571 if (status & BD_ENET_RX_CR) /* CRC Error */
572 dev->stats.rx_crc_errors++;
573 if (status & BD_ENET_RX_OV) /* FIFO overrun */
574 dev->stats.rx_fifo_errors++;
577 /* Report late collisions as a frame error.
578 * On this error, the BD is closed, but we don't know what we
579 * have in the buffer. So, just drop this frame on the floor.
581 if (status & BD_ENET_RX_CL) {
582 dev->stats.rx_errors++;
583 dev->stats.rx_frame_errors++;
584 goto rx_processing_done;
587 /* Process the incoming frame. */
588 dev->stats.rx_packets++;
589 pkt_len = bdp->cbd_datlen;
590 dev->stats.rx_bytes += pkt_len;
591 data = (__u8*)__va(bdp->cbd_bufaddr);
593 dma_sync_single(NULL, (unsigned long)__pa(data),
594 pkt_len - 4, DMA_FROM_DEVICE);
596 /* This does 16 byte alignment, exactly what we need.
597 * The packet length includes FCS, but we don't want to
598 * include that when passing upstream as it messes up
599 * bridging applications.
601 skb = dev_alloc_skb(pkt_len - 4);
604 printk("%s: Memory squeeze, dropping packet.\n",
606 dev->stats.rx_dropped++;
608 skb_put(skb, pkt_len - 4); /* Make room */
609 skb_copy_to_linear_data(skb, data, pkt_len - 4);
610 skb->protocol = eth_type_trans(skb, dev);
614 /* Clear the status flags for this buffer */
615 status &= ~BD_ENET_RX_STATS;
617 /* Mark the buffer empty */
618 status |= BD_ENET_RX_EMPTY;
619 bdp->cbd_sc = status;
621 /* Update BD pointer to next entry */
622 if (status & BD_ENET_RX_WRAP)
623 bdp = fep->rx_bd_base;
626 /* Doing this here will keep the FEC running while we process
627 * incoming frames. On a heavily loaded network, we should be
628 * able to keep up at the expense of system resources.
630 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
634 spin_unlock_irq(&fep->hw_lock);
637 /* called from interrupt context */
639 fec_enet_mii(struct net_device *dev)
641 struct fec_enet_private *fep;
644 fep = netdev_priv(dev);
645 spin_lock_irq(&fep->mii_lock);
647 if ((mip = mii_head) == NULL) {
648 printk("MII and no head!\n");
652 if (mip->mii_func != NULL)
653 (*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev);
655 mii_head = mip->mii_next;
656 mip->mii_next = mii_free;
659 if ((mip = mii_head) != NULL)
660 writel(mip->mii_regval, fep->hwp + FEC_MII_DATA);
663 spin_unlock_irq(&fep->mii_lock);
667 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
669 struct fec_enet_private *fep;
674 /* Add PHY address to register command */
675 fep = netdev_priv(dev);
676 spin_lock_irqsave(&fep->mii_lock, flags);
678 regval |= fep->phy_addr << 23;
681 if ((mip = mii_free) != NULL) {
682 mii_free = mip->mii_next;
683 mip->mii_regval = regval;
684 mip->mii_func = func;
685 mip->mii_next = NULL;
687 mii_tail->mii_next = mip;
690 mii_head = mii_tail = mip;
691 writel(regval, fep->hwp + FEC_MII_DATA);
697 spin_unlock_irqrestore(&fep->mii_lock, flags);
701 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
706 for (; c->mii_data != mk_mii_end; c++)
707 mii_queue(dev, c->mii_data, c->funct);
710 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
712 struct fec_enet_private *fep = netdev_priv(dev);
713 volatile uint *s = &(fep->phy_status);
716 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
718 if (mii_reg & 0x0004)
719 status |= PHY_STAT_LINK;
720 if (mii_reg & 0x0010)
721 status |= PHY_STAT_FAULT;
722 if (mii_reg & 0x0020)
723 status |= PHY_STAT_ANC;
727 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
729 struct fec_enet_private *fep = netdev_priv(dev);
730 volatile uint *s = &(fep->phy_status);
733 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
735 if (mii_reg & 0x1000)
736 status |= PHY_CONF_ANE;
737 if (mii_reg & 0x4000)
738 status |= PHY_CONF_LOOP;
742 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
744 struct fec_enet_private *fep = netdev_priv(dev);
745 volatile uint *s = &(fep->phy_status);
748 status = *s & ~(PHY_CONF_SPMASK);
750 if (mii_reg & 0x0020)
751 status |= PHY_CONF_10HDX;
752 if (mii_reg & 0x0040)
753 status |= PHY_CONF_10FDX;
754 if (mii_reg & 0x0080)
755 status |= PHY_CONF_100HDX;
756 if (mii_reg & 0x00100)
757 status |= PHY_CONF_100FDX;
761 /* ------------------------------------------------------------------------- */
762 /* The Level one LXT970 is used by many boards */
764 #define MII_LXT970_MIRROR 16 /* Mirror register */
765 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
766 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
767 #define MII_LXT970_CONFIG 19 /* Configuration Register */
768 #define MII_LXT970_CSR 20 /* Chip Status Register */
770 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
772 struct fec_enet_private *fep = netdev_priv(dev);
773 volatile uint *s = &(fep->phy_status);
776 status = *s & ~(PHY_STAT_SPMASK);
777 if (mii_reg & 0x0800) {
778 if (mii_reg & 0x1000)
779 status |= PHY_STAT_100FDX;
781 status |= PHY_STAT_100HDX;
783 if (mii_reg & 0x1000)
784 status |= PHY_STAT_10FDX;
786 status |= PHY_STAT_10HDX;
791 static phy_cmd_t const phy_cmd_lxt970_config[] = {
792 { mk_mii_read(MII_REG_CR), mii_parse_cr },
793 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
796 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
797 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
798 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
801 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
802 /* read SR and ISR to acknowledge */
803 { mk_mii_read(MII_REG_SR), mii_parse_sr },
804 { mk_mii_read(MII_LXT970_ISR), NULL },
806 /* find out the current status */
807 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
810 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
811 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
814 static phy_info_t const phy_info_lxt970 = {
817 .config = phy_cmd_lxt970_config,
818 .startup = phy_cmd_lxt970_startup,
819 .ack_int = phy_cmd_lxt970_ack_int,
820 .shutdown = phy_cmd_lxt970_shutdown
823 /* ------------------------------------------------------------------------- */
824 /* The Level one LXT971 is used on some of my custom boards */
826 /* register definitions for the 971 */
828 #define MII_LXT971_PCR 16 /* Port Control Register */
829 #define MII_LXT971_SR2 17 /* Status Register 2 */
830 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
831 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
832 #define MII_LXT971_LCR 20 /* LED Control Register */
833 #define MII_LXT971_TCR 30 /* Transmit Control Register */
836 * I had some nice ideas of running the MDIO faster...
837 * The 971 should support 8MHz and I tried it, but things acted really
838 * weird, so 2.5 MHz ought to be enough for anyone...
841 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
843 struct fec_enet_private *fep = netdev_priv(dev);
844 volatile uint *s = &(fep->phy_status);
847 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
849 if (mii_reg & 0x0400) {
851 status |= PHY_STAT_LINK;
855 if (mii_reg & 0x0080)
856 status |= PHY_STAT_ANC;
857 if (mii_reg & 0x4000) {
858 if (mii_reg & 0x0200)
859 status |= PHY_STAT_100FDX;
861 status |= PHY_STAT_100HDX;
863 if (mii_reg & 0x0200)
864 status |= PHY_STAT_10FDX;
866 status |= PHY_STAT_10HDX;
868 if (mii_reg & 0x0008)
869 status |= PHY_STAT_FAULT;
874 static phy_cmd_t const phy_cmd_lxt971_config[] = {
875 /* limit to 10MBit because my prototype board
876 * doesn't work with 100. */
877 { mk_mii_read(MII_REG_CR), mii_parse_cr },
878 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
879 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
882 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
883 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
884 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
885 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
886 /* Somehow does the 971 tell me that the link is down
887 * the first read after power-up.
888 * read here to get a valid value in ack_int */
889 { mk_mii_read(MII_REG_SR), mii_parse_sr },
892 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
893 /* acknowledge the int before reading status ! */
894 { mk_mii_read(MII_LXT971_ISR), NULL },
895 /* find out the current status */
896 { mk_mii_read(MII_REG_SR), mii_parse_sr },
897 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
900 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
901 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
904 static phy_info_t const phy_info_lxt971 = {
907 .config = phy_cmd_lxt971_config,
908 .startup = phy_cmd_lxt971_startup,
909 .ack_int = phy_cmd_lxt971_ack_int,
910 .shutdown = phy_cmd_lxt971_shutdown
913 /* ------------------------------------------------------------------------- */
914 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
916 /* register definitions */
918 #define MII_QS6612_MCR 17 /* Mode Control Register */
919 #define MII_QS6612_FTR 27 /* Factory Test Register */
920 #define MII_QS6612_MCO 28 /* Misc. Control Register */
921 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
922 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
923 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
925 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
927 struct fec_enet_private *fep = netdev_priv(dev);
928 volatile uint *s = &(fep->phy_status);
931 status = *s & ~(PHY_STAT_SPMASK);
933 switch((mii_reg >> 2) & 7) {
934 case 1: status |= PHY_STAT_10HDX; break;
935 case 2: status |= PHY_STAT_100HDX; break;
936 case 5: status |= PHY_STAT_10FDX; break;
937 case 6: status |= PHY_STAT_100FDX; break;
943 static phy_cmd_t const phy_cmd_qs6612_config[] = {
944 /* The PHY powers up isolated on the RPX,
945 * so send a command to allow operation.
947 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
949 /* parse cr and anar to get some info */
950 { mk_mii_read(MII_REG_CR), mii_parse_cr },
951 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
954 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
955 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
956 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
959 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
960 /* we need to read ISR, SR and ANER to acknowledge */
961 { mk_mii_read(MII_QS6612_ISR), NULL },
962 { mk_mii_read(MII_REG_SR), mii_parse_sr },
963 { mk_mii_read(MII_REG_ANER), NULL },
965 /* read pcr to get info */
966 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
969 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
970 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
973 static phy_info_t const phy_info_qs6612 = {
976 .config = phy_cmd_qs6612_config,
977 .startup = phy_cmd_qs6612_startup,
978 .ack_int = phy_cmd_qs6612_ack_int,
979 .shutdown = phy_cmd_qs6612_shutdown
982 /* ------------------------------------------------------------------------- */
983 /* AMD AM79C874 phy */
985 /* register definitions for the 874 */
987 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
988 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
989 #define MII_AM79C874_DR 18 /* Diagnostic Register */
990 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
991 #define MII_AM79C874_MCR 21 /* ModeControl Register */
992 #define MII_AM79C874_DC 23 /* Disconnect Counter */
993 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
995 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
997 struct fec_enet_private *fep = netdev_priv(dev);
998 volatile uint *s = &(fep->phy_status);
1001 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1003 if (mii_reg & 0x0080)
1004 status |= PHY_STAT_ANC;
1005 if (mii_reg & 0x0400)
1006 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1008 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1013 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1014 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1015 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1016 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1019 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1020 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1021 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1022 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1025 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1026 /* find out the current status */
1027 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1028 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1029 /* we only need to read ISR to acknowledge */
1030 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1033 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1034 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1037 static phy_info_t const phy_info_am79c874 = {
1040 .config = phy_cmd_am79c874_config,
1041 .startup = phy_cmd_am79c874_startup,
1042 .ack_int = phy_cmd_am79c874_ack_int,
1043 .shutdown = phy_cmd_am79c874_shutdown
1047 /* ------------------------------------------------------------------------- */
1048 /* Kendin KS8721BL phy */
1050 /* register definitions for the 8721 */
1052 #define MII_KS8721BL_RXERCR 21
1053 #define MII_KS8721BL_ICSR 27
1054 #define MII_KS8721BL_PHYCR 31
1056 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1057 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1058 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1061 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1062 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1063 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1064 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1067 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1068 /* find out the current status */
1069 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1070 /* we only need to read ISR to acknowledge */
1071 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1074 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1075 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1078 static phy_info_t const phy_info_ks8721bl = {
1081 .config = phy_cmd_ks8721bl_config,
1082 .startup = phy_cmd_ks8721bl_startup,
1083 .ack_int = phy_cmd_ks8721bl_ack_int,
1084 .shutdown = phy_cmd_ks8721bl_shutdown
1087 /* ------------------------------------------------------------------------- */
1088 /* register definitions for the DP83848 */
1090 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1092 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1094 struct fec_enet_private *fep = netdev_priv(dev);
1095 volatile uint *s = &(fep->phy_status);
1097 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1100 if (mii_reg & 0x0001) {
1102 *s |= PHY_STAT_LINK;
1105 /* Status of link */
1106 if (mii_reg & 0x0010) /* Autonegotioation complete */
1108 if (mii_reg & 0x0002) { /* 10MBps? */
1109 if (mii_reg & 0x0004) /* Full Duplex? */
1110 *s |= PHY_STAT_10FDX;
1112 *s |= PHY_STAT_10HDX;
1113 } else { /* 100 Mbps? */
1114 if (mii_reg & 0x0004) /* Full Duplex? */
1115 *s |= PHY_STAT_100FDX;
1117 *s |= PHY_STAT_100HDX;
1119 if (mii_reg & 0x0008)
1120 *s |= PHY_STAT_FAULT;
1123 static phy_info_t phy_info_dp83848= {
1127 (const phy_cmd_t []) { /* config */
1128 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1129 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1130 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1133 (const phy_cmd_t []) { /* startup - enable interrupts */
1134 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1135 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1138 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1141 (const phy_cmd_t []) { /* shutdown */
1146 /* ------------------------------------------------------------------------- */
1148 static phy_info_t const * const phy_info[] = {
1158 /* ------------------------------------------------------------------------- */
1159 #ifdef HAVE_mii_link_interrupt
1161 mii_link_interrupt(int irq, void * dev_id);
1164 * This is specific to the MII interrupt setup of the M5272EVB.
1166 static void __inline__ fec_request_mii_intr(struct net_device *dev)
1168 if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0)
1169 printk("FEC: Could not allocate fec(MII) IRQ(66)!\n");
1172 static void __inline__ fec_disable_phy_intr(void)
1174 volatile unsigned long *icrp;
1175 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1179 static void __inline__ fec_phy_ack_intr(void)
1181 volatile unsigned long *icrp;
1182 /* Acknowledge the interrupt */
1183 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1188 static void __inline__ fec_get_mac(struct net_device *dev)
1190 struct fec_enet_private *fep = netdev_priv(dev);
1191 unsigned char *iap, tmpaddr[ETH_ALEN];
1195 * Get MAC address from FLASH.
1196 * If it is all 1's or 0's, use the default.
1198 iap = (unsigned char *)FEC_FLASHMAC;
1199 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1200 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1201 iap = fec_mac_default;
1202 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1203 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1204 iap = fec_mac_default;
1206 *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
1207 *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1211 memcpy(dev->dev_addr, iap, ETH_ALEN);
1213 /* Adjust MAC if using default MAC address */
1214 if (iap == fec_mac_default)
1215 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1219 /* ------------------------------------------------------------------------- */
1221 static void mii_display_status(struct net_device *dev)
1223 struct fec_enet_private *fep = netdev_priv(dev);
1224 volatile uint *s = &(fep->phy_status);
1226 if (!fep->link && !fep->old_link) {
1227 /* Link is still down - don't print anything */
1231 printk("%s: status: ", dev->name);
1234 printk("link down");
1238 switch(*s & PHY_STAT_SPMASK) {
1239 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1240 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1241 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1242 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1244 printk(", Unknown speed/duplex");
1247 if (*s & PHY_STAT_ANC)
1248 printk(", auto-negotiation complete");
1251 if (*s & PHY_STAT_FAULT)
1252 printk(", remote fault");
1257 static void mii_display_config(struct work_struct *work)
1259 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1260 struct net_device *dev = fep->netdev;
1261 uint status = fep->phy_status;
1264 ** When we get here, phy_task is already removed from
1265 ** the workqueue. It is thus safe to allow to reuse it.
1267 fep->mii_phy_task_queued = 0;
1268 printk("%s: config: auto-negotiation ", dev->name);
1270 if (status & PHY_CONF_ANE)
1275 if (status & PHY_CONF_100FDX)
1277 if (status & PHY_CONF_100HDX)
1279 if (status & PHY_CONF_10FDX)
1281 if (status & PHY_CONF_10HDX)
1283 if (!(status & PHY_CONF_SPMASK))
1284 printk(", No speed/duplex selected?");
1286 if (status & PHY_CONF_LOOP)
1287 printk(", loopback enabled");
1291 fep->sequence_done = 1;
1294 static void mii_relink(struct work_struct *work)
1296 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1297 struct net_device *dev = fep->netdev;
1301 ** When we get here, phy_task is already removed from
1302 ** the workqueue. It is thus safe to allow to reuse it.
1304 fep->mii_phy_task_queued = 0;
1305 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1306 mii_display_status(dev);
1307 fep->old_link = fep->link;
1312 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1314 fec_restart(dev, duplex);
1319 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1320 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1322 struct fec_enet_private *fep = netdev_priv(dev);
1325 * We cannot queue phy_task twice in the workqueue. It
1326 * would cause an endless loop in the workqueue.
1327 * Fortunately, if the last mii_relink entry has not yet been
1328 * executed now, it will do the job for the current interrupt,
1329 * which is just what we want.
1331 if (fep->mii_phy_task_queued)
1334 fep->mii_phy_task_queued = 1;
1335 INIT_WORK(&fep->phy_task, mii_relink);
1336 schedule_work(&fep->phy_task);
1339 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1340 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1342 struct fec_enet_private *fep = netdev_priv(dev);
1344 if (fep->mii_phy_task_queued)
1347 fep->mii_phy_task_queued = 1;
1348 INIT_WORK(&fep->phy_task, mii_display_config);
1349 schedule_work(&fep->phy_task);
1352 phy_cmd_t const phy_cmd_relink[] = {
1353 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1356 phy_cmd_t const phy_cmd_config[] = {
1357 { mk_mii_read(MII_REG_CR), mii_queue_config },
1361 /* Read remainder of PHY ID. */
1363 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1365 struct fec_enet_private *fep;
1368 fep = netdev_priv(dev);
1369 fep->phy_id |= (mii_reg & 0xffff);
1370 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1372 for(i = 0; phy_info[i]; i++) {
1373 if(phy_info[i]->id == (fep->phy_id >> 4))
1378 printk(" -- %s\n", phy_info[i]->name);
1380 printk(" -- unknown PHY!\n");
1382 fep->phy = phy_info[i];
1383 fep->phy_id_done = 1;
1386 /* Scan all of the MII PHY addresses looking for someone to respond
1387 * with a valid ID. This usually happens quickly.
1390 mii_discover_phy(uint mii_reg, struct net_device *dev)
1392 struct fec_enet_private *fep;
1395 fep = netdev_priv(dev);
1397 if (fep->phy_addr < 32) {
1398 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1400 /* Got first part of ID, now get remainder */
1401 fep->phy_id = phytype << 16;
1402 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1406 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1410 printk("FEC: No PHY device found.\n");
1411 /* Disable external MII interface */
1412 writel(0, fep->hwp + FEC_MII_SPEED);
1414 #ifdef HAVE_mii_link_interrupt
1415 fec_disable_phy_intr();
1420 /* This interrupt occurs when the PHY detects a link change */
1421 #ifdef HAVE_mii_link_interrupt
1423 mii_link_interrupt(int irq, void * dev_id)
1425 struct net_device *dev = dev_id;
1426 struct fec_enet_private *fep = netdev_priv(dev);
1430 mii_do_cmd(dev, fep->phy->ack_int);
1431 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1438 fec_enet_open(struct net_device *dev)
1440 struct fec_enet_private *fep = netdev_priv(dev);
1442 /* I should reset the ring buffers here, but I don't yet know
1443 * a simple way to do that.
1445 fec_set_mac_address(dev);
1447 fep->sequence_done = 0;
1451 mii_do_cmd(dev, fep->phy->ack_int);
1452 mii_do_cmd(dev, fep->phy->config);
1453 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1455 /* Poll until the PHY tells us its configuration
1457 * Request is initiated by mii_do_cmd above, but answer
1458 * comes by interrupt.
1459 * This should take about 25 usec per register at 2.5 MHz,
1460 * and we read approximately 5 registers.
1462 while(!fep->sequence_done)
1465 mii_do_cmd(dev, fep->phy->startup);
1467 /* Set the initial link state to true. A lot of hardware
1468 * based on this device does not implement a PHY interrupt,
1469 * so we are never notified of link change.
1473 fep->link = 1; /* lets just try it and see */
1474 /* no phy, go full duplex, it's most likely a hub chip */
1475 fec_restart(dev, 1);
1478 netif_start_queue(dev);
1484 fec_enet_close(struct net_device *dev)
1486 struct fec_enet_private *fep = netdev_priv(dev);
1488 /* Don't know what to do yet. */
1490 netif_stop_queue(dev);
1496 /* Set or clear the multicast filter for this adaptor.
1497 * Skeleton taken from sunlance driver.
1498 * The CPM Ethernet implementation allows Multicast as well as individual
1499 * MAC address filtering. Some of the drivers check to make sure it is
1500 * a group multicast address, and discard those that are not. I guess I
1501 * will do the same for now, but just remove the test if you want
1502 * individual filtering as well (do the upper net layers want or support
1503 * this kind of feature?).
1506 #define HASH_BITS 6 /* #bits in hash */
1507 #define CRC32_POLY 0xEDB88320
1509 static void set_multicast_list(struct net_device *dev)
1511 struct fec_enet_private *fep = netdev_priv(dev);
1512 struct dev_mc_list *dmi;
1513 unsigned int i, j, bit, data, crc, tmp;
1516 if (dev->flags & IFF_PROMISC) {
1517 tmp = readl(fep->hwp + FEC_R_CNTRL);
1519 writel(tmp, fep->hwp + FEC_R_CNTRL);
1523 tmp = readl(fep->hwp + FEC_R_CNTRL);
1525 writel(tmp, fep->hwp + FEC_R_CNTRL);
1527 if (dev->flags & IFF_ALLMULTI) {
1528 /* Catch all multicast addresses, so set the
1531 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1532 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1537 /* Clear filter and add the addresses in hash register
1539 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1540 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1544 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) {
1545 /* Only support group multicast for now */
1546 if (!(dmi->dmi_addr[0] & 1))
1549 /* calculate crc32 value of mac address */
1552 for (i = 0; i < dmi->dmi_addrlen; i++) {
1553 data = dmi->dmi_addr[i];
1554 for (bit = 0; bit < 8; bit++, data >>= 1) {
1556 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1560 /* only upper 6 bits (HASH_BITS) are used
1561 * which point to specific bit in he hash registers
1563 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1566 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1567 tmp |= 1 << (hash - 32);
1568 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1570 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1572 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1577 /* Set a MAC change in hardware. */
1579 fec_set_mac_address(struct net_device *dev)
1581 struct fec_enet_private *fep = netdev_priv(dev);
1583 /* Set station address. */
1584 writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
1585 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
1586 fep->hwp + FEC_ADDR_LOW);
1587 writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
1588 fep + FEC_ADDR_HIGH);
1592 * XXX: We need to clean up on failure exits here.
1594 * index is only used in legacy code
1596 int __init fec_enet_init(struct net_device *dev, int index)
1598 struct fec_enet_private *fep = netdev_priv(dev);
1599 unsigned long mem_addr;
1600 struct bufdesc *bdp, *cbd_base;
1603 /* Allocate memory for buffer descriptors. */
1604 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1607 printk("FEC: allocate descriptor memory failed?\n");
1611 spin_lock_init(&fep->hw_lock);
1612 spin_lock_init(&fep->mii_lock);
1615 fep->hwp = (void __iomem *)dev->base_addr;
1618 /* Whack a reset. We should wait for this. */
1619 writel(1, fep->hwp + FEC_ECNTRL);
1622 /* Set the Ethernet address */
1628 l = readl(fep->hwp + FEC_ADDR_LOW);
1629 dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
1630 dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
1631 dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
1632 dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
1633 l = readl(fep->hwp + FEC_ADDR_HIGH);
1634 dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
1635 dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
1639 /* Set receive and transmit descriptor base. */
1640 fep->rx_bd_base = cbd_base;
1641 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1643 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1644 fep->cur_rx = fep->rx_bd_base;
1646 fep->skb_cur = fep->skb_dirty = 0;
1648 /* Initialize the receive buffer descriptors. */
1649 bdp = fep->rx_bd_base;
1650 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1652 /* Allocate a page */
1653 mem_addr = __get_free_page(GFP_KERNEL);
1654 /* XXX: missing check for allocation failure */
1656 /* Initialize the BD for every fragment in the page */
1657 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1658 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1659 bdp->cbd_bufaddr = __pa(mem_addr);
1660 mem_addr += FEC_ENET_RX_FRSIZE;
1665 /* Set the last buffer to wrap */
1667 bdp->cbd_sc |= BD_SC_WRAP;
1669 /* ...and the same for transmit */
1670 bdp = fep->tx_bd_base;
1671 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
1672 if (j >= FEC_ENET_TX_FRPPG) {
1673 mem_addr = __get_free_page(GFP_KERNEL);
1676 mem_addr += FEC_ENET_TX_FRSIZE;
1679 fep->tx_bounce[i] = (unsigned char *) mem_addr;
1681 /* Initialize the BD for every fragment in the page */
1683 bdp->cbd_bufaddr = 0;
1687 /* Set the last buffer to wrap */
1689 bdp->cbd_sc |= BD_SC_WRAP;
1691 /* Set receive and transmit descriptor base */
1692 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1693 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1694 fep->hwp + FEC_X_DES_START);
1696 #ifdef HAVE_mii_link_interrupt
1697 fec_request_mii_intr(dev);
1700 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1701 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1702 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1703 writel(2, fep->hwp + FEC_ECNTRL);
1704 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1705 #ifndef CONFIG_M5272
1706 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1707 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1710 /* The FEC Ethernet specific entries in the device structure */
1711 dev->open = fec_enet_open;
1712 dev->hard_start_xmit = fec_enet_start_xmit;
1713 dev->tx_timeout = fec_timeout;
1714 dev->watchdog_timeo = TX_TIMEOUT;
1715 dev->stop = fec_enet_close;
1716 dev->set_multicast_list = set_multicast_list;
1718 for (i=0; i<NMII-1; i++)
1719 mii_cmds[i].mii_next = &mii_cmds[i+1];
1720 mii_free = mii_cmds;
1722 /* setup MII interface */
1723 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1724 writel(0, fep->hwp + FEC_X_CNTRL);
1726 /* Set MII speed to 2.5 MHz */
1727 fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999)
1728 / 2500000) / 2) & 0x3F) << 1;
1729 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1730 fec_restart(dev, 0);
1732 /* Clear and enable interrupts */
1733 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1734 writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII,
1735 fep->hwp + FEC_IMASK);
1737 /* Queue up command to detect the PHY and initialize the
1738 * remainder of the interface.
1740 fep->phy_id_done = 0;
1742 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1747 /* This function is called to start or restart the FEC during a link
1748 * change. This only happens when switching between half and full
1752 fec_restart(struct net_device *dev, int duplex)
1754 struct fec_enet_private *fep = netdev_priv(dev);
1755 struct bufdesc *bdp;
1758 /* Whack a reset. We should wait for this. */
1759 writel(1, fep->hwp + FEC_ECNTRL);
1762 /* Clear any outstanding interrupt. */
1763 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1765 /* Set station address. */
1766 fec_set_mac_address(dev);
1768 /* Reset all multicast. */
1769 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1770 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1772 /* Set maximum receive buffer size. */
1773 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1775 /* Set receive and transmit descriptor base. */
1776 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1777 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1778 fep->hwp + FEC_X_DES_START);
1780 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1781 fep->cur_rx = fep->rx_bd_base;
1783 /* Reset SKB transmit buffers. */
1784 fep->skb_cur = fep->skb_dirty = 0;
1785 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1786 if (fep->tx_skbuff[i]) {
1787 dev_kfree_skb_any(fep->tx_skbuff[i]);
1788 fep->tx_skbuff[i] = NULL;
1792 /* Initialize the receive buffer descriptors. */
1793 bdp = fep->rx_bd_base;
1794 for (i = 0; i < RX_RING_SIZE; i++) {
1796 /* Initialize the BD for every fragment in the page. */
1797 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1801 /* Set the last buffer to wrap */
1803 bdp->cbd_sc |= BD_SC_WRAP;
1805 /* ...and the same for transmit */
1806 bdp = fep->tx_bd_base;
1807 for (i = 0; i < TX_RING_SIZE; i++) {
1809 /* Initialize the BD for every fragment in the page. */
1811 bdp->cbd_bufaddr = 0;
1815 /* Set the last buffer to wrap */
1817 bdp->cbd_sc |= BD_SC_WRAP;
1819 /* Enable MII mode */
1821 /* MII enable / FD enable */
1822 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1823 writel(0x04, fep->hwp + FEC_X_CNTRL);
1825 /* MII enable / No Rcv on Xmit */
1826 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1827 writel(0x0, fep->hwp + FEC_X_CNTRL);
1829 fep->full_duplex = duplex;
1832 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1834 /* And last, enable the transmit and receive processing */
1835 writel(2, fep->hwp + FEC_ECNTRL);
1836 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1838 /* Enable interrupts we wish to service */
1839 writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII,
1840 fep->hwp + FEC_IMASK);
1844 fec_stop(struct net_device *dev)
1846 struct fec_enet_private *fep = netdev_priv(dev);
1848 /* We cannot expect a graceful transmit stop without link !!! */
1850 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1852 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1853 printk("fec_stop : Graceful transmit stop did not complete !\n");
1856 /* Whack a reset. We should wait for this. */
1857 writel(1, fep->hwp + FEC_ECNTRL);
1860 /* Clear outstanding MII command interrupts. */
1861 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1863 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1864 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1867 static int __devinit
1868 fec_probe(struct platform_device *pdev)
1870 struct fec_enet_private *fep;
1871 struct net_device *ndev;
1872 int i, irq, ret = 0;
1875 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1879 r = request_mem_region(r->start, resource_size(r), pdev->name);
1883 /* Init network device */
1884 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1888 SET_NETDEV_DEV(ndev, &pdev->dev);
1890 /* setup board info structure */
1891 fep = netdev_priv(ndev);
1892 memset(fep, 0, sizeof(*fep));
1894 ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
1896 if (!ndev->base_addr) {
1898 goto failed_ioremap;
1901 platform_set_drvdata(pdev, ndev);
1903 /* This device has up to three irqs on some platforms */
1904 for (i = 0; i < 3; i++) {
1905 irq = platform_get_irq(pdev, i);
1908 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1911 irq = platform_get_irq(pdev, i);
1912 free_irq(irq, ndev);
1919 fep->clk = clk_get(&pdev->dev, "fec_clk");
1920 if (IS_ERR(fep->clk)) {
1921 ret = PTR_ERR(fep->clk);
1924 clk_enable(fep->clk);
1926 ret = fec_enet_init(ndev, 0);
1930 ret = register_netdev(ndev);
1932 goto failed_register;
1938 clk_disable(fep->clk);
1941 for (i = 0; i < 3; i++) {
1942 irq = platform_get_irq(pdev, i);
1944 free_irq(irq, ndev);
1947 iounmap((void __iomem *)ndev->base_addr);
1954 static int __devexit
1955 fec_drv_remove(struct platform_device *pdev)
1957 struct net_device *ndev = platform_get_drvdata(pdev);
1958 struct fec_enet_private *fep = netdev_priv(ndev);
1960 platform_set_drvdata(pdev, NULL);
1963 clk_disable(fep->clk);
1965 iounmap((void __iomem *)ndev->base_addr);
1966 unregister_netdev(ndev);
1972 fec_suspend(struct platform_device *dev, pm_message_t state)
1974 struct net_device *ndev = platform_get_drvdata(dev);
1975 struct fec_enet_private *fep;
1978 fep = netdev_priv(ndev);
1979 if (netif_running(ndev)) {
1980 netif_device_detach(ndev);
1988 fec_resume(struct platform_device *dev)
1990 struct net_device *ndev = platform_get_drvdata(dev);
1993 if (netif_running(ndev)) {
1994 fec_enet_init(ndev, 0);
1995 netif_device_attach(ndev);
2001 static struct platform_driver fec_driver = {
2004 .owner = THIS_MODULE,
2007 .remove = __devexit_p(fec_drv_remove),
2008 .suspend = fec_suspend,
2009 .resume = fec_resume,
2013 fec_enet_module_init(void)
2015 printk(KERN_INFO "FEC Ethernet Driver\n");
2017 return platform_driver_register(&fec_driver);
2021 fec_enet_cleanup(void)
2023 platform_driver_unregister(&fec_driver);
2026 module_exit(fec_enet_cleanup);
2027 module_init(fec_enet_module_init);
2029 MODULE_LICENSE("GPL");