git.oblomov.eu Git - linux-2.6/blob - drivers/net/irda/w83977af_ir.c

   1 /*********************************************************************
   2  *
   3  * Filename:      w83977af_ir.c
   4  * Version:       1.0
   5  * Description:   FIR driver for the Winbond W83977AF Super I/O chip
   6  * Status:        Experimental.
   7  * Author:        Paul VanderSpek
   8  * Created at:    Wed Nov  4 11:46:16 1998
   9  * Modified at:   Fri Jan 28 12:10:59 2000
  10  * Modified by:   Dag Brattli <dagb@cs.uit.no>
  11  *
  12  *     Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
  13  *     Copyright (c) 1998-1999 Rebel.com
  14  *
  15  *     This program is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of
  18  *     the License, or (at your option) any later version.
  19  *
  20  *     Neither Paul VanderSpek nor Rebel.com admit liability nor provide
  21  *     warranty for any of this software. This material is provided "AS-IS"
  22  *     and at no charge.
  23  *
  24  *     If you find bugs in this file, its very likely that the same bug
  25  *     will also be in pc87108.c since the implementations are quite
  26  *     similar.
  27  *
  28  *     Notice that all functions that needs to access the chip in _any_
  29  *     way, must save BSR register on entry, and restore it on exit.
  30  *     It is _very_ important to follow this policy!
  31  *
  32  *         __u8 bank;
  33  *
  34  *         bank = inb( iobase+BSR);
  35  *
  36  *         do_your_stuff_here();
  37  *
  38  *         outb( bank, iobase+BSR);
  39  *
  40  ********************************************************************/
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/types.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/netdevice.h>
  47 #include <linux/ioport.h>
  48 #include <linux/delay.h>
  49 #include <linux/slab.h>
  50 #include <linux/init.h>
  51 #include <linux/rtnetlink.h>
  52 #include <linux/dma-mapping.h>
  53
  54 #include <asm/io.h>
  55 #include <asm/dma.h>
  56 #include <asm/byteorder.h>
  57
  58 #include <net/irda/irda.h>
  59 #include <net/irda/wrapper.h>
  60 #include <net/irda/irda_device.h>
  61 #include "w83977af.h"
  62 #include "w83977af_ir.h"
  63
  64 #ifdef  CONFIG_ARCH_NETWINDER            /* Adjust to NetWinder differences */
  65 #undef  CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */
  66 #define CONFIG_NETWINDER_RX_DMA_PROBLEMS /* Must have this one! */
  67 #endif
  68 #undef  CONFIG_USE_INTERNAL_TIMER  /* Just cannot make that timer work */
  69 #define CONFIG_USE_W977_PNP        /* Currently needed */
  70 #define PIO_MAX_SPEED       115200
  71
  72 static char *driver_name = "w83977af_ir";
  73 static int  qos_mtt_bits = 0x07;   /* 1 ms or more */
  74
  75 #define CHIP_IO_EXTENT 8
  76
  77 static unsigned int io[] = { 0x180, ~0, ~0, ~0 };
  78 #ifdef CONFIG_ARCH_NETWINDER             /* Adjust to NetWinder differences */
  79 static unsigned int irq[] = { 6, 0, 0, 0 };
  80 #else
  81 static unsigned int irq[] = { 11, 0, 0, 0 };
  82 #endif
  83 static unsigned int dma[] = { 1, 0, 0, 0 };
  84 static unsigned int efbase[] = { W977_EFIO_BASE, W977_EFIO2_BASE };
  85 static unsigned int efio = W977_EFIO_BASE;
  86
  87 static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
  88
  89 /* Some prototypes */
  90 static int  w83977af_open(int i, unsigned int iobase, unsigned int irq,
  91                           unsigned int dma);
  92 static int  w83977af_close(struct w83977af_ir *self);
  93 static int  w83977af_probe(int iobase, int irq, int dma);
  94 static int  w83977af_dma_receive(struct w83977af_ir *self);
  95 static int  w83977af_dma_receive_complete(struct w83977af_ir *self);
  96 static int  w83977af_hard_xmit(struct sk_buff *skb, struct net_device *dev);
  97 static int  w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
  98 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
  99 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed);
 100 static int  w83977af_is_receiving(struct w83977af_ir *self);
 101
 102 static int  w83977af_net_open(struct net_device *dev);
 103 static int  w83977af_net_close(struct net_device *dev);
 104 static int  w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 105 static struct net_device_stats *w83977af_net_get_stats(struct net_device *dev);
 106
 107 /*
 108  * Function w83977af_init ()
 109  *
 110  *    Initialize chip. Just try to find out how many chips we are dealing with
 111  *    and where they are
 112  */
 113 static int __init w83977af_init(void)
 114 {
 115         int i;
 116
 117         IRDA_DEBUG(0, "%s()\n", __FUNCTION__ );
 118
 119         for (i=0; (io[i] < 2000) && (i < 4); i++) {
 120                 if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
 121                         return 0;
 122         }
 123         return -ENODEV;
 124 }
 125
 126 /*
 127  * Function w83977af_cleanup ()
 128  *
 129  *    Close all configured chips
 130  *
 131  */
 132 static void __exit w83977af_cleanup(void)
 133 {
 134         int i;
 135
 136         IRDA_DEBUG(4, "%s()\n", __FUNCTION__ );
 137
 138         for (i=0; i < 4; i++) {
 139                 if (dev_self[i])
 140                         w83977af_close(dev_self[i]);
 141         }
 142 }
 143
 144 /*
 145  * Function w83977af_open (iobase, irq)
 146  *
 147  *    Open driver instance
 148  *
 149  */
 150 int w83977af_open(int i, unsigned int iobase, unsigned int irq,
 151                   unsigned int dma)
 152 {
 153         struct net_device *dev;
 154         struct w83977af_ir *self;
 155         int err;
 156
 157         IRDA_DEBUG(0, "%s()\n", __FUNCTION__ );
 158
 159         /* Lock the port that we need */
 160         if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) {
 161                 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
 162                       __FUNCTION__ , iobase);
 163                 return -ENODEV;
 164         }
 165
 166         if (w83977af_probe(iobase, irq, dma) == -1) {
 167                 err = -1;
 168                 goto err_out;
 169         }
 170         /*
 171          *  Allocate new instance of the driver
 172          */
 173         dev = alloc_irdadev(sizeof(struct w83977af_ir));
 174         if (dev == NULL) {
 175                 printk( KERN_ERR "IrDA: Can't allocate memory for "
 176                         "IrDA control block!\n");
 177                 err = -ENOMEM;
 178                 goto err_out;
 179         }
 180
 181         self = dev->priv;
 182         spin_lock_init(&self->lock);
 183
 184
 185         /* Initialize IO */
 186         self->io.fir_base   = iobase;
 187         self->io.irq       = irq;
 188         self->io.fir_ext   = CHIP_IO_EXTENT;
 189         self->io.dma       = dma;
 190         self->io.fifo_size = 32;
 191
 192         /* Initialize QoS for this device */
 193         irda_init_max_qos_capabilies(&self->qos);
 194
 195         /* The only value we must override it the baudrate */
 196
 197         /* FIXME: The HP HDLS-1100 does not support 1152000! */
 198         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 199                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 200
 201         /* The HP HDLS-1100 needs 1 ms according to the specs */
 202         self->qos.min_turn_time.bits = qos_mtt_bits;
 203         irda_qos_bits_to_value(&self->qos);
 204
 205         /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 206         self->rx_buff.truesize = 14384;
 207         self->tx_buff.truesize = 4000;
 208
 209         /* Allocate memory if needed */
 210         self->rx_buff.head =
 211                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 212                                    &self->rx_buff_dma, GFP_KERNEL);
 213         if (self->rx_buff.head == NULL) {
 214                 err = -ENOMEM;
 215                 goto err_out1;
 216         }
 217
 218         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 219
 220         self->tx_buff.head =
 221                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 222                                    &self->tx_buff_dma, GFP_KERNEL);
 223         if (self->tx_buff.head == NULL) {
 224                 err = -ENOMEM;
 225                 goto err_out2;
 226         }
 227         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 228
 229         self->rx_buff.in_frame = FALSE;
 230         self->rx_buff.state = OUTSIDE_FRAME;
 231         self->tx_buff.data = self->tx_buff.head;
 232         self->rx_buff.data = self->rx_buff.head;
 233         self->netdev = dev;
 234
 235         /* Keep track of module usage */
 236         SET_MODULE_OWNER(dev);
 237
 238         /* Override the network functions we need to use */
 239         dev->hard_start_xmit = w83977af_hard_xmit;
 240         dev->open            = w83977af_net_open;
 241         dev->stop            = w83977af_net_close;
 242         dev->do_ioctl        = w83977af_net_ioctl;
 243         dev->get_stats       = w83977af_net_get_stats;
 244
 245         err = register_netdev(dev);
 246         if (err) {
 247                 IRDA_ERROR("%s(), register_netdevice() failed!\n", __FUNCTION__);
 248                 goto err_out3;
 249         }
 250         IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
 251
 252         /* Need to store self somewhere */
 253         dev_self[i] = self;
 254
 255         return 0;
 256 err_out3:
 257         dma_free_coherent(NULL, self->tx_buff.truesize,
 258                           self->tx_buff.head, self->tx_buff_dma);
 259 err_out2:
 260         dma_free_coherent(NULL, self->rx_buff.truesize,
 261                           self->rx_buff.head, self->rx_buff_dma);
 262 err_out1:
 263         free_netdev(dev);
 264 err_out:
 265         release_region(iobase, CHIP_IO_EXTENT);
 266         return err;
 267 }
 268
 269 /*
 270  * Function w83977af_close (self)
 271  *
 272  *    Close driver instance
 273  *
 274  */
 275 static int w83977af_close(struct w83977af_ir *self)
 276 {
 277         int iobase;
 278
 279         IRDA_DEBUG(0, "%s()\n", __FUNCTION__ );
 280
 281         iobase = self->io.fir_base;
 282
 283 #ifdef CONFIG_USE_W977_PNP
 284         /* enter PnP configuration mode */
 285         w977_efm_enter(efio);
 286
 287         w977_select_device(W977_DEVICE_IR, efio);
 288
 289         /* Deactivate device */
 290         w977_write_reg(0x30, 0x00, efio);
 291
 292         w977_efm_exit(efio);
 293 #endif /* CONFIG_USE_W977_PNP */
 294
 295         /* Remove netdevice */
 296         unregister_netdev(self->netdev);
 297
 298         /* Release the PORT that this driver is using */
 299         IRDA_DEBUG(0 , "%s(), Releasing Region %03x\n",
 300               __FUNCTION__ , self->io.fir_base);
 301         release_region(self->io.fir_base, self->io.fir_ext);
 302
 303         if (self->tx_buff.head)
 304                 dma_free_coherent(NULL, self->tx_buff.truesize,
 305                                   self->tx_buff.head, self->tx_buff_dma);
 306
 307         if (self->rx_buff.head)
 308                 dma_free_coherent(NULL, self->rx_buff.truesize,
 309                                   self->rx_buff.head, self->rx_buff_dma);
 310
 311         free_netdev(self->netdev);
 312
 313         return 0;
 314 }
 315
 316 int w83977af_probe( int iobase, int irq, int dma)
 317 {
 318         int version;
 319         int i;
 320
 321         for (i=0; i < 2; i++) {
 322                 IRDA_DEBUG( 0, "%s()\n", __FUNCTION__ );
 323 #ifdef CONFIG_USE_W977_PNP
 324                 /* Enter PnP configuration mode */
 325                 w977_efm_enter(efbase[i]);
 326
 327                 w977_select_device(W977_DEVICE_IR, efbase[i]);
 328
 329                 /* Configure PnP port, IRQ, and DMA channel */
 330                 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
 331                 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
 332
 333                 w977_write_reg(0x70, irq, efbase[i]);
 334 #ifdef CONFIG_ARCH_NETWINDER
 335                 /* Netwinder uses 1 higher than Linux */
 336                 w977_write_reg(0x74, dma+1, efbase[i]);
 337 #else
 338                 w977_write_reg(0x74, dma, efbase[i]);
 339 #endif /*CONFIG_ARCH_NETWINDER */
 340                 w977_write_reg(0x75, 0x04, efbase[i]);  /* Disable Tx DMA */
 341
 342                 /* Set append hardware CRC, enable IR bank selection */
 343                 w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
 344
 345                 /* Activate device */
 346                 w977_write_reg(0x30, 0x01, efbase[i]);
 347
 348                 w977_efm_exit(efbase[i]);
 349 #endif /* CONFIG_USE_W977_PNP */
 350                 /* Disable Advanced mode */
 351                 switch_bank(iobase, SET2);
 352                 outb(iobase+2, 0x00);
 353
 354                 /* Turn on UART (global) interrupts */
 355                 switch_bank(iobase, SET0);
 356                 outb(HCR_EN_IRQ, iobase+HCR);
 357
 358                 /* Switch to advanced mode */
 359                 switch_bank(iobase, SET2);
 360                 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
 361
 362                 /* Set default IR-mode */
 363                 switch_bank(iobase, SET0);
 364                 outb(HCR_SIR, iobase+HCR);
 365
 366                 /* Read the Advanced IR ID */
 367                 switch_bank(iobase, SET3);
 368                 version = inb(iobase+AUID);
 369
 370                 /* Should be 0x1? */
 371                 if (0x10 == (version & 0xf0)) {
 372                         efio = efbase[i];
 373
 374                         /* Set FIFO size to 32 */
 375                         switch_bank(iobase, SET2);
 376                         outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
 377
 378                         /* Set FIFO threshold to TX17, RX16 */
 379                         switch_bank(iobase, SET0);
 380                         outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
 381                              UFR_EN_FIFO,iobase+UFR);
 382
 383                         /* Receiver frame length */
 384                         switch_bank(iobase, SET4);
 385                         outb(2048 & 0xff, iobase+6);
 386                         outb((2048 >> 8) & 0x1f, iobase+7);
 387
 388                         /*
 389                          * Init HP HSDL-1100 transceiver.
 390                          *
 391                          * Set IRX_MSL since we have 2 * receive paths IRRX,
 392                          * and IRRXH. Clear IRSL0D since we want IRSL0 * to
 393                          * be a input pin used for IRRXH
 394                          *
 395                          *   IRRX  pin 37 connected to receiver
 396                          *   IRTX  pin 38 connected to transmitter
 397                          *   FIRRX pin 39 connected to receiver      (IRSL0)
 398                          *   CIRRX pin 40 connected to pin 37
 399                          */
 400                         switch_bank(iobase, SET7);
 401                         outb(0x40, iobase+7);
 402
 403                         IRDA_MESSAGE("W83977AF (IR) driver loaded. "
 404                                      "Version: 0x%02x\n", version);
 405
 406                         return 0;
 407                 } else {
 408                         /* Try next extented function register address */
 409                         IRDA_DEBUG( 0, "%s(), Wrong chip version", __FUNCTION__ );
 410                 }
 411         }
 412         return -1;
 413 }
 414
 415 void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
 416 {
 417         int ir_mode = HCR_SIR;
 418         int iobase;
 419         __u8 set;
 420
 421         iobase = self->io.fir_base;
 422
 423         /* Update accounting for new speed */
 424         self->io.speed = speed;
 425
 426         /* Save current bank */
 427         set = inb(iobase+SSR);
 428
 429         /* Disable interrupts */
 430         switch_bank(iobase, SET0);
 431         outb(0, iobase+ICR);
 432
 433         /* Select Set 2 */
 434         switch_bank(iobase, SET2);
 435         outb(0x00, iobase+ABHL);
 436
 437         switch (speed) {
 438         case 9600:   outb(0x0c, iobase+ABLL); break;
 439         case 19200:  outb(0x06, iobase+ABLL); break;
 440         case 38400:  outb(0x03, iobase+ABLL); break;
 441         case 57600:  outb(0x02, iobase+ABLL); break;
 442         case 115200: outb(0x01, iobase+ABLL); break;
 443         case 576000:
 444                 ir_mode = HCR_MIR_576;
 445                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__ );
 446                 break;
 447         case 1152000:
 448                 ir_mode = HCR_MIR_1152;
 449                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __FUNCTION__ );
 450                 break;
 451         case 4000000:
 452                 ir_mode = HCR_FIR;
 453                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __FUNCTION__ );
 454                 break;
 455         default:
 456                 ir_mode = HCR_FIR;
 457                 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n", __FUNCTION__ , speed);
 458                 break;
 459         }
 460
 461         /* Set speed mode */
 462         switch_bank(iobase, SET0);
 463         outb(ir_mode, iobase+HCR);
 464
 465         /* set FIFO size to 32 */
 466         switch_bank(iobase, SET2);
 467         outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
 468
 469         /* set FIFO threshold to TX17, RX16 */
 470         switch_bank(iobase, SET0);
 471         outb(0x00, iobase+UFR);        /* Reset */
 472         outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */
 473         outb(0xa7, iobase+UFR);
 474
 475         netif_wake_queue(self->netdev);
 476
 477         /* Enable some interrupts so we can receive frames */
 478         switch_bank(iobase, SET0);
 479         if (speed > PIO_MAX_SPEED) {
 480                 outb(ICR_EFSFI, iobase+ICR);
 481                 w83977af_dma_receive(self);
 482         } else
 483                 outb(ICR_ERBRI, iobase+ICR);
 484
 485         /* Restore SSR */
 486         outb(set, iobase+SSR);
 487 }
 488
 489 /*
 490  * Function w83977af_hard_xmit (skb, dev)
 491  *
 492  *    Sets up a DMA transfer to send the current frame.
 493  *
 494  */
 495 int w83977af_hard_xmit(struct sk_buff *skb, struct net_device *dev)
 496 {
 497         struct w83977af_ir *self;
 498         __s32 speed;
 499         int iobase;
 500         __u8 set;
 501         int mtt;
 502
 503         self = (struct w83977af_ir *) dev->priv;
 504
 505         iobase = self->io.fir_base;
 506
 507         IRDA_DEBUG(4, "%s(%ld), skb->len=%d\n", __FUNCTION__ , jiffies,
 508                    (int) skb->len);
 509
 510         /* Lock transmit buffer */
 511         netif_stop_queue(dev);
 512
 513         /* Check if we need to change the speed */
 514         speed = irda_get_next_speed(skb);
 515         if ((speed != self->io.speed) && (speed != -1)) {
 516                 /* Check for empty frame */
 517                 if (!skb->len) {
 518                         w83977af_change_speed(self, speed);
 519                         dev->trans_start = jiffies;
 520                         dev_kfree_skb(skb);
 521                         return 0;
 522                 } else
 523                         self->new_speed = speed;
 524         }
 525
 526         /* Save current set */
 527         set = inb(iobase+SSR);
 528
 529         /* Decide if we should use PIO or DMA transfer */
 530         if (self->io.speed > PIO_MAX_SPEED) {
 531                 self->tx_buff.data = self->tx_buff.head;
 532                 memcpy(self->tx_buff.data, skb->data, skb->len);
 533                 self->tx_buff.len = skb->len;
 534
 535                 mtt = irda_get_mtt(skb);
 536 #ifdef CONFIG_USE_INTERNAL_TIMER
 537                 if (mtt > 50) {
 538                         /* Adjust for timer resolution */
 539                         mtt /= 1000+1;
 540
 541                         /* Setup timer */
 542                         switch_bank(iobase, SET4);
 543                         outb(mtt & 0xff, iobase+TMRL);
 544                         outb((mtt >> 8) & 0x0f, iobase+TMRH);
 545
 546                         /* Start timer */
 547                         outb(IR_MSL_EN_TMR, iobase+IR_MSL);
 548                         self->io.direction = IO_XMIT;
 549
 550                         /* Enable timer interrupt */
 551                         switch_bank(iobase, SET0);
 552                         outb(ICR_ETMRI, iobase+ICR);
 553                 } else {
 554 #endif
 555                         IRDA_DEBUG(4, "%s(%ld), mtt=%d\n", __FUNCTION__ , jiffies, mtt);
 556                         if (mtt)
 557                                 udelay(mtt);
 558
 559                         /* Enable DMA interrupt */
 560                         switch_bank(iobase, SET0);
 561                         outb(ICR_EDMAI, iobase+ICR);
 562                         w83977af_dma_write(self, iobase);
 563 #ifdef CONFIG_USE_INTERNAL_TIMER
 564                 }
 565 #endif
 566         } else {
 567                 self->tx_buff.data = self->tx_buff.head;
 568                 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 569                                                    self->tx_buff.truesize);
 570
 571                 /* Add interrupt on tx low level (will fire immediately) */
 572                 switch_bank(iobase, SET0);
 573                 outb(ICR_ETXTHI, iobase+ICR);
 574         }
 575         dev->trans_start = jiffies;
 576         dev_kfree_skb(skb);
 577
 578         /* Restore set register */
 579         outb(set, iobase+SSR);
 580
 581         return 0;
 582 }
 583
 584 /*
 585  * Function w83977af_dma_write (self, iobase)
 586  *
 587  *    Send frame using DMA
 588  *
 589  */
 590 static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
 591 {
 592         __u8 set;
 593 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
 594         unsigned long flags;
 595         __u8 hcr;
 596 #endif
 597         IRDA_DEBUG(4, "%s(), len=%d\n", __FUNCTION__ , self->tx_buff.len);
 598
 599         /* Save current set */
 600         set = inb(iobase+SSR);
 601
 602         /* Disable DMA */
 603         switch_bank(iobase, SET0);
 604         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 605
 606         /* Choose transmit DMA channel  */
 607         switch_bank(iobase, SET2);
 608         outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
 609 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
 610         spin_lock_irqsave(&self->lock, flags);
 611
 612         disable_dma(self->io.dma);
 613         clear_dma_ff(self->io.dma);
 614         set_dma_mode(self->io.dma, DMA_MODE_READ);
 615         set_dma_addr(self->io.dma, self->tx_buff_dma);
 616         set_dma_count(self->io.dma, self->tx_buff.len);
 617 #else
 618         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
 619                        DMA_MODE_WRITE);
 620 #endif
 621         self->io.direction = IO_XMIT;
 622
 623         /* Enable DMA */
 624         switch_bank(iobase, SET0);
 625 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
 626         hcr = inb(iobase+HCR);
 627         outb(hcr | HCR_EN_DMA, iobase+HCR);
 628         enable_dma(self->io.dma);
 629         spin_unlock_irqrestore(&self->lock, flags);
 630 #else
 631         outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
 632 #endif
 633
 634         /* Restore set register */
 635         outb(set, iobase+SSR);
 636 }
 637
 638 /*
 639  * Function w83977af_pio_write (iobase, buf, len, fifo_size)
 640  *
 641  *
 642  *
 643  */
 644 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
 645 {
 646         int actual = 0;
 647         __u8 set;
 648
 649         IRDA_DEBUG(4, "%s()\n", __FUNCTION__ );
 650
 651         /* Save current bank */
 652         set = inb(iobase+SSR);
 653
 654         switch_bank(iobase, SET0);
 655         if (!(inb_p(iobase+USR) & USR_TSRE)) {
 656                 IRDA_DEBUG(4,
 657                            "%s(), warning, FIFO not empty yet!\n", __FUNCTION__  );
 658
 659                 fifo_size -= 17;
 660                 IRDA_DEBUG(4, "%s(), %d bytes left in tx fifo\n",
 661                            __FUNCTION__ , fifo_size);
 662         }
 663
 664         /* Fill FIFO with current frame */
 665         while ((fifo_size-- > 0) && (actual < len)) {
 666                 /* Transmit next byte */
 667                 outb(buf[actual++], iobase+TBR);
 668         }
 669
 670         IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
 671                    __FUNCTION__ , fifo_size, actual, len);
 672
 673         /* Restore bank */
 674         outb(set, iobase+SSR);
 675
 676         return actual;
 677 }
 678
 679 /*
 680  * Function w83977af_dma_xmit_complete (self)
 681  *
 682  *    The transfer of a frame in finished. So do the necessary things
 683  *
 684  *
 685  */
 686 static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
 687 {
 688         int iobase;
 689         __u8 set;
 690
 691         IRDA_DEBUG(4, "%s(%ld)\n", __FUNCTION__ , jiffies);
 692
 693         IRDA_ASSERT(self != NULL, return;);
 694
 695         iobase = self->io.fir_base;
 696
 697         /* Save current set */
 698         set = inb(iobase+SSR);
 699
 700         /* Disable DMA */
 701         switch_bank(iobase, SET0);
 702         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 703
 704         /* Check for underrrun! */
 705         if (inb(iobase+AUDR) & AUDR_UNDR) {
 706                 IRDA_DEBUG(0, "%s(), Transmit underrun!\n", __FUNCTION__ );
 707
 708                 self->stats.tx_errors++;
 709                 self->stats.tx_fifo_errors++;
 710
 711                 /* Clear bit, by writing 1 to it */
 712                 outb(AUDR_UNDR, iobase+AUDR);
 713         } else
 714                 self->stats.tx_packets++;
 715
 716
 717         if (self->new_speed) {
 718                 w83977af_change_speed(self, self->new_speed);
 719                 self->new_speed = 0;
 720         }
 721
 722         /* Unlock tx_buff and request another frame */
 723         /* Tell the network layer, that we want more frames */
 724         netif_wake_queue(self->netdev);
 725
 726         /* Restore set */
 727         outb(set, iobase+SSR);
 728 }
 729
 730 /*
 731  * Function w83977af_dma_receive (self)
 732  *
 733  *    Get ready for receiving a frame. The device will initiate a DMA
 734  *    if it starts to receive a frame.
 735  *
 736  */
 737 int w83977af_dma_receive(struct w83977af_ir *self)
 738 {
 739         int iobase;
 740         __u8 set;
 741 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
 742         unsigned long flags;
 743         __u8 hcr;
 744 #endif
 745         IRDA_ASSERT(self != NULL, return -1;);
 746
 747         IRDA_DEBUG(4, "%s\n", __FUNCTION__ );
 748
 749         iobase= self->io.fir_base;
 750
 751         /* Save current set */
 752         set = inb(iobase+SSR);
 753
 754         /* Disable DMA */
 755         switch_bank(iobase, SET0);
 756         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 757
 758         /* Choose DMA Rx, DMA Fairness, and Advanced mode */
 759         switch_bank(iobase, SET2);
 760         outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL,
 761              iobase+ADCR1);
 762
 763         self->io.direction = IO_RECV;
 764         self->rx_buff.data = self->rx_buff.head;
 765
 766 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
 767         spin_lock_irqsave(&self->lock, flags);
 768
 769         disable_dma(self->io.dma);
 770         clear_dma_ff(self->io.dma);
 771         set_dma_mode(self->io.dma, DMA_MODE_READ);
 772         set_dma_addr(self->io.dma, self->rx_buff_dma);
 773         set_dma_count(self->io.dma, self->rx_buff.truesize);
 774 #else
 775         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
 776                        DMA_MODE_READ);
 777 #endif
 778         /*
 779          * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
 780          * important that we don't reset the Tx FIFO since it might not
 781          * be finished transmitting yet
 782          */
 783         switch_bank(iobase, SET0);
 784         outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
 785         self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
 786
 787         /* Enable DMA */
 788         switch_bank(iobase, SET0);
 789 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
 790         hcr = inb(iobase+HCR);
 791         outb(hcr | HCR_EN_DMA, iobase+HCR);
 792         enable_dma(self->io.dma);
 793         spin_unlock_irqrestore(&self->lock, flags);
 794 #else
 795         outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
 796 #endif
 797         /* Restore set */
 798         outb(set, iobase+SSR);
 799
 800         return 0;
 801 }
 802
 803 /*
 804  * Function w83977af_receive_complete (self)
 805  *
 806  *    Finished with receiving a frame
 807  *
 808  */
 809 int w83977af_dma_receive_complete(struct w83977af_ir *self)
 810 {
 811         struct sk_buff *skb;
 812         struct st_fifo *st_fifo;
 813         int len;
 814         int iobase;
 815         __u8 set;
 816         __u8 status;
 817
 818         IRDA_DEBUG(4, "%s\n", __FUNCTION__ );
 819
 820         st_fifo = &self->st_fifo;
 821
 822         iobase = self->io.fir_base;
 823
 824         /* Save current set */
 825         set = inb(iobase+SSR);
 826
 827         iobase = self->io.fir_base;
 828
 829         /* Read status FIFO */
 830         switch_bank(iobase, SET5);
 831         while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
 832                 st_fifo->entries[st_fifo->tail].status = status;
 833
 834                 st_fifo->entries[st_fifo->tail].len  = inb(iobase+RFLFL);
 835                 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
 836
 837                 st_fifo->tail++;
 838                 st_fifo->len++;
 839         }
 840
 841         while (st_fifo->len) {
 842                 /* Get first entry */
 843                 status = st_fifo->entries[st_fifo->head].status;
 844                 len    = st_fifo->entries[st_fifo->head].len;
 845                 st_fifo->head++;
 846                 st_fifo->len--;
 847
 848                 /* Check for errors */
 849                 if (status & FS_FO_ERR_MSK) {
 850                         if (status & FS_FO_LST_FR) {
 851                                 /* Add number of lost frames to stats */
 852                                 self->stats.rx_errors += len;
 853                         } else {
 854                                 /* Skip frame */
 855                                 self->stats.rx_errors++;
 856
 857                                 self->rx_buff.data += len;
 858
 859                                 if (status & FS_FO_MX_LEX)
 860                                         self->stats.rx_length_errors++;
 861
 862                                 if (status & FS_FO_PHY_ERR)
 863                                         self->stats.rx_frame_errors++;
 864
 865                                 if (status & FS_FO_CRC_ERR)
 866                                         self->stats.rx_crc_errors++;
 867                         }
 868                         /* The errors below can be reported in both cases */
 869                         if (status & FS_FO_RX_OV)
 870                                 self->stats.rx_fifo_errors++;
 871
 872                         if (status & FS_FO_FSF_OV)
 873                                 self->stats.rx_fifo_errors++;
 874
 875                 } else {
 876                         /* Check if we have transferred all data to memory */
 877                         switch_bank(iobase, SET0);
 878                         if (inb(iobase+USR) & USR_RDR) {
 879 #ifdef CONFIG_USE_INTERNAL_TIMER
 880                                 /* Put this entry back in fifo */
 881                                 st_fifo->head--;
 882                                 st_fifo->len++;
 883                                 st_fifo->entries[st_fifo->head].status = status;
 884                                 st_fifo->entries[st_fifo->head].len = len;
 885
 886                                 /* Restore set register */
 887                                 outb(set, iobase+SSR);
 888
 889                                 return FALSE;   /* I'll be back! */
 890 #else
 891                                 udelay(80); /* Should be enough!? */
 892 #endif
 893                         }
 894
 895                         skb = dev_alloc_skb(len+1);
 896                         if (skb == NULL)  {
 897                                 printk(KERN_INFO
 898                                        "%s(), memory squeeze, dropping frame.\n", __FUNCTION__);
 899                                 /* Restore set register */
 900                                 outb(set, iobase+SSR);
 901
 902                                 return FALSE;
 903                         }
 904
 905                         /*  Align to 20 bytes */
 906                         skb_reserve(skb, 1);
 907
 908                         /* Copy frame without CRC */
 909                         if (self->io.speed < 4000000) {
 910                                 skb_put(skb, len-2);
 911                                 memcpy(skb->data, self->rx_buff.data, len-2);
 912                         } else {
 913                                 skb_put(skb, len-4);
 914                                 memcpy(skb->data, self->rx_buff.data, len-4);
 915                         }
 916
 917                         /* Move to next frame */
 918                         self->rx_buff.data += len;
 919                         self->stats.rx_packets++;
 920
 921                         skb->dev = self->netdev;
 922                         skb->mac.raw  = skb->data;
 923                         skb->protocol = htons(ETH_P_IRDA);
 924                         netif_rx(skb);
 925                         self->netdev->last_rx = jiffies;
 926                 }
 927         }
 928         /* Restore set register */
 929         outb(set, iobase+SSR);
 930
 931         return TRUE;
 932 }
 933
 934 /*
 935  * Function pc87108_pio_receive (self)
 936  *
 937  *    Receive all data in receiver FIFO
 938  *
 939  */
 940 static void w83977af_pio_receive(struct w83977af_ir *self)
 941 {
 942         __u8 byte = 0x00;
 943         int iobase;
 944
 945         IRDA_DEBUG(4, "%s()\n", __FUNCTION__ );
 946
 947         IRDA_ASSERT(self != NULL, return;);
 948
 949         iobase = self->io.fir_base;
 950
 951         /*  Receive all characters in Rx FIFO */
 952         do {
 953                 byte = inb(iobase+RBR);
 954                 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
 955                                   byte);
 956         } while (inb(iobase+USR) & USR_RDR); /* Data available */
 957 }
 958
 959 /*
 960  * Function w83977af_sir_interrupt (self, eir)
 961  *
 962  *    Handle SIR interrupt
 963  *
 964  */
 965 static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
 966 {
 967         int actual;
 968         __u8 new_icr = 0;
 969         __u8 set;
 970         int iobase;
 971
 972         IRDA_DEBUG(4, "%s(), isr=%#x\n", __FUNCTION__ , isr);
 973
 974         iobase = self->io.fir_base;
 975         /* Transmit FIFO low on data */
 976         if (isr & ISR_TXTH_I) {
 977                 /* Write data left in transmit buffer */
 978                 actual = w83977af_pio_write(self->io.fir_base,
 979                                             self->tx_buff.data,
 980                                             self->tx_buff.len,
 981                                             self->io.fifo_size);
 982
 983                 self->tx_buff.data += actual;
 984                 self->tx_buff.len  -= actual;
 985
 986                 self->io.direction = IO_XMIT;
 987
 988                 /* Check if finished */
 989                 if (self->tx_buff.len > 0) {
 990                         new_icr |= ICR_ETXTHI;
 991                 } else {
 992                         set = inb(iobase+SSR);
 993                         switch_bank(iobase, SET0);
 994                         outb(AUDR_SFEND, iobase+AUDR);
 995                         outb(set, iobase+SSR);
 996
 997                         self->stats.tx_packets++;
 998
 999                         /* Feed me more packets */
1000                         netif_wake_queue(self->netdev);
1001                         new_icr |= ICR_ETBREI;
1002                 }
1003         }
1004         /* Check if transmission has completed */
1005         if (isr & ISR_TXEMP_I) {
1006                 /* Check if we need to change the speed? */
1007                 if (self->new_speed) {
1008                         IRDA_DEBUG(2,
1009                                    "%s(), Changing speed!\n", __FUNCTION__ );
1010                         w83977af_change_speed(self, self->new_speed);
1011                         self->new_speed = 0;
1012                 }
1013
1014                 /* Turn around and get ready to receive some data */
1015                 self->io.direction = IO_RECV;
1016                 new_icr |= ICR_ERBRI;
1017         }
1018
1019         /* Rx FIFO threshold or timeout */
1020         if (isr & ISR_RXTH_I) {
1021                 w83977af_pio_receive(self);
1022
1023                 /* Keep receiving */
1024                 new_icr |= ICR_ERBRI;
1025         }
1026         return new_icr;
1027 }
1028
1029 /*
1030  * Function pc87108_fir_interrupt (self, eir)
1031  *
1032  *    Handle MIR/FIR interrupt
1033  *
1034  */
1035 static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
1036 {
1037         __u8 new_icr = 0;
1038         __u8 set;
1039         int iobase;
1040
1041         iobase = self->io.fir_base;
1042         set = inb(iobase+SSR);
1043
1044         /* End of frame detected in FIFO */
1045         if (isr & (ISR_FEND_I|ISR_FSF_I)) {
1046                 if (w83977af_dma_receive_complete(self)) {
1047
1048                         /* Wait for next status FIFO interrupt */
1049                         new_icr |= ICR_EFSFI;
1050                 } else {
1051                         /* DMA not finished yet */
1052
1053                         /* Set timer value, resolution 1 ms */
1054                         switch_bank(iobase, SET4);
1055                         outb(0x01, iobase+TMRL); /* 1 ms */
1056                         outb(0x00, iobase+TMRH);
1057
1058                         /* Start timer */
1059                         outb(IR_MSL_EN_TMR, iobase+IR_MSL);
1060
1061                         new_icr |= ICR_ETMRI;
1062                 }
1063         }
1064         /* Timer finished */
1065         if (isr & ISR_TMR_I) {
1066                 /* Disable timer */
1067                 switch_bank(iobase, SET4);
1068                 outb(0, iobase+IR_MSL);
1069
1070                 /* Clear timer event */
1071                 /* switch_bank(iobase, SET0); */
1072 /*              outb(ASCR_CTE, iobase+ASCR); */
1073
1074                 /* Check if this is a TX timer interrupt */
1075                 if (self->io.direction == IO_XMIT) {
1076                         w83977af_dma_write(self, iobase);
1077
1078                         new_icr |= ICR_EDMAI;
1079                 } else {
1080                         /* Check if DMA has now finished */
1081                         w83977af_dma_receive_complete(self);
1082
1083                         new_icr |= ICR_EFSFI;
1084                 }
1085         }
1086         /* Finished with DMA */
1087         if (isr & ISR_DMA_I) {
1088                 w83977af_dma_xmit_complete(self);
1089
1090                 /* Check if there are more frames to be transmitted */
1091                 /* if (irda_device_txqueue_empty(self)) { */
1092
1093                 /* Prepare for receive
1094                  *
1095                  * ** Netwinder Tx DMA likes that we do this anyway **
1096                  */
1097                 w83977af_dma_receive(self);
1098                 new_icr = ICR_EFSFI;
1099                /* } */
1100         }
1101
1102         /* Restore set */
1103         outb(set, iobase+SSR);
1104
1105         return new_icr;
1106 }
1107
1108 /*
1109  * Function w83977af_interrupt (irq, dev_id, regs)
1110  *
1111  *    An interrupt from the chip has arrived. Time to do some work
1112  *
1113  */
1114 static irqreturn_t w83977af_interrupt(int irq, void *dev_id,
1115                                         struct pt_regs *regs)
1116 {
1117         struct net_device *dev = (struct net_device *) dev_id;
1118         struct w83977af_ir *self;
1119         __u8 set, icr, isr;
1120         int iobase;
1121
1122         if (!dev) {
1123                 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1124                         driver_name, irq);
1125                 return IRQ_NONE;
1126         }
1127         self = (struct w83977af_ir *) dev->priv;
1128
1129         iobase = self->io.fir_base;
1130
1131         /* Save current bank */
1132         set = inb(iobase+SSR);
1133         switch_bank(iobase, SET0);
1134
1135         icr = inb(iobase+ICR);
1136         isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
1137
1138         outb(0, iobase+ICR); /* Disable interrupts */
1139
1140         if (isr) {
1141                 /* Dispatch interrupt handler for the current speed */
1142                 if (self->io.speed > PIO_MAX_SPEED )
1143                         icr = w83977af_fir_interrupt(self, isr);
1144                 else
1145                         icr = w83977af_sir_interrupt(self, isr);
1146         }
1147
1148         outb(icr, iobase+ICR);    /* Restore (new) interrupts */
1149         outb(set, iobase+SSR);    /* Restore bank register */
1150         return IRQ_RETVAL(isr);
1151 }
1152
1153 /*
1154  * Function w83977af_is_receiving (self)
1155  *
1156  *    Return TRUE is we are currently receiving a frame
1157  *
1158  */
1159 static int w83977af_is_receiving(struct w83977af_ir *self)
1160 {
1161         int status = FALSE;
1162         int iobase;
1163         __u8 set;
1164
1165         IRDA_ASSERT(self != NULL, return FALSE;);
1166
1167         if (self->io.speed > 115200) {
1168                 iobase = self->io.fir_base;
1169
1170                 /* Check if rx FIFO is not empty */
1171                 set = inb(iobase+SSR);
1172                 switch_bank(iobase, SET2);
1173                 if ((inb(iobase+RXFDTH) & 0x3f) != 0) {
1174                         /* We are receiving something */
1175                         status =  TRUE;
1176                 }
1177                 outb(set, iobase+SSR);
1178         } else
1179                 status = (self->rx_buff.state != OUTSIDE_FRAME);
1180
1181         return status;
1182 }
1183
1184 /*
1185  * Function w83977af_net_open (dev)
1186  *
1187  *    Start the device
1188  *
1189  */
1190 static int w83977af_net_open(struct net_device *dev)
1191 {
1192         struct w83977af_ir *self;
1193         int iobase;
1194         char hwname[32];
1195         __u8 set;
1196
1197         IRDA_DEBUG(0, "%s()\n", __FUNCTION__ );
1198
1199         IRDA_ASSERT(dev != NULL, return -1;);
1200         self = (struct w83977af_ir *) dev->priv;
1201
1202         IRDA_ASSERT(self != NULL, return 0;);
1203
1204         iobase = self->io.fir_base;
1205
1206         if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
1207                         (void *) dev)) {
1208                 return -EAGAIN;
1209         }
1210         /*
1211          * Always allocate the DMA channel after the IRQ,
1212          * and clean up on failure.
1213          */
1214         if (request_dma(self->io.dma, dev->name)) {
1215                 free_irq(self->io.irq, self);
1216                 return -EAGAIN;
1217         }
1218
1219         /* Save current set */
1220         set = inb(iobase+SSR);
1221
1222         /* Enable some interrupts so we can receive frames again */
1223         switch_bank(iobase, SET0);
1224         if (self->io.speed > 115200) {
1225                 outb(ICR_EFSFI, iobase+ICR);
1226                 w83977af_dma_receive(self);
1227         } else
1228                 outb(ICR_ERBRI, iobase+ICR);
1229
1230         /* Restore bank register */
1231         outb(set, iobase+SSR);
1232
1233         /* Ready to play! */
1234         netif_start_queue(dev);
1235
1236         /* Give self a hardware name */
1237         sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base);
1238
1239         /*
1240          * Open new IrLAP layer instance, now that everything should be
1241          * initialized properly
1242          */
1243         self->irlap = irlap_open(dev, &self->qos, hwname);
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * Function w83977af_net_close (dev)
1250  *
1251  *    Stop the device
1252  *
1253  */
1254 static int w83977af_net_close(struct net_device *dev)
1255 {
1256         struct w83977af_ir *self;
1257         int iobase;
1258         __u8 set;
1259
1260         IRDA_DEBUG(0, "%s()\n", __FUNCTION__ );
1261
1262         IRDA_ASSERT(dev != NULL, return -1;);
1263
1264         self = (struct w83977af_ir *) dev->priv;
1265
1266         IRDA_ASSERT(self != NULL, return 0;);
1267
1268         iobase = self->io.fir_base;
1269
1270         /* Stop device */
1271         netif_stop_queue(dev);
1272
1273         /* Stop and remove instance of IrLAP */
1274         if (self->irlap)
1275                 irlap_close(self->irlap);
1276         self->irlap = NULL;
1277
1278         disable_dma(self->io.dma);
1279
1280         /* Save current set */
1281         set = inb(iobase+SSR);
1282
1283         /* Disable interrupts */
1284         switch_bank(iobase, SET0);
1285         outb(0, iobase+ICR);
1286
1287         free_irq(self->io.irq, dev);
1288         free_dma(self->io.dma);
1289
1290         /* Restore bank register */
1291         outb(set, iobase+SSR);
1292
1293         return 0;
1294 }
1295
1296 /*
1297  * Function w83977af_net_ioctl (dev, rq, cmd)
1298  *
1299  *    Process IOCTL commands for this device
1300  *
1301  */
1302 static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1303 {
1304         struct if_irda_req *irq = (struct if_irda_req *) rq;
1305         struct w83977af_ir *self;
1306         unsigned long flags;
1307         int ret = 0;
1308
1309         IRDA_ASSERT(dev != NULL, return -1;);
1310
1311         self = dev->priv;
1312
1313         IRDA_ASSERT(self != NULL, return -1;);
1314
1315         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__ , dev->name, cmd);
1316
1317         spin_lock_irqsave(&self->lock, flags);
1318
1319         switch (cmd) {
1320         case SIOCSBANDWIDTH: /* Set bandwidth */
1321                 if (!capable(CAP_NET_ADMIN)) {
1322                         ret = -EPERM;
1323                         goto out;
1324                 }
1325                 w83977af_change_speed(self, irq->ifr_baudrate);
1326                 break;
1327         case SIOCSMEDIABUSY: /* Set media busy */
1328                 if (!capable(CAP_NET_ADMIN)) {
1329                         ret = -EPERM;
1330                         goto out;
1331                 }
1332                 irda_device_set_media_busy(self->netdev, TRUE);
1333                 break;
1334         case SIOCGRECEIVING: /* Check if we are receiving right now */
1335                 irq->ifr_receiving = w83977af_is_receiving(self);
1336                 break;
1337         default:
1338                 ret = -EOPNOTSUPP;
1339         }
1340 out:
1341         spin_unlock_irqrestore(&self->lock, flags);
1342         return ret;
1343 }
1344
1345 static struct net_device_stats *w83977af_net_get_stats(struct net_device *dev)
1346 {
1347         struct w83977af_ir *self = (struct w83977af_ir *) dev->priv;
1348
1349         return &self->stats;
1350 }
1351
1352 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
1353 MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
1354 MODULE_LICENSE("GPL");
1355
1356
1357 module_param(qos_mtt_bits, int, 0);
1358 MODULE_PARM_DESC(qos_mtt_bits, "Mimimum Turn Time");
1359 module_param_array(io, int, NULL, 0);
1360 MODULE_PARM_DESC(io, "Base I/O addresses");
1361 module_param_array(irq, int, NULL, 0);
1362 MODULE_PARM_DESC(irq, "IRQ lines");
1363
1364 /*
1365  * Function init_module (void)
1366  *
1367  *
1368  *
1369  */
1370 module_init(w83977af_init);
1371
1372 /*
1373  * Function cleanup_module (void)
1374  *
1375  *
1376  *
1377  */
1378 module_exit(w83977af_cleanup);