git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/calib.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18
  19 /* We can tune this as we go by monitoring really low values */
  20 #define ATH9K_NF_TOO_LOW        -60
  21
  22 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
  23  * is incorrect and we should use the static NF value. Later we can try to
  24  * find out why they are reporting these values */
  25
  26 static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
  27 {
  28         if (nf > ATH9K_NF_TOO_LOW) {
  29                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
  30                         "noise floor value detected (%d) is "
  31                         "lower than what we think is a "
  32                         "reasonable value (%d)\n",
  33                         nf, ATH9K_NF_TOO_LOW);
  34                 return false;
  35         }
  36         return true;
  37 }
  38
  39 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
  40 {
  41         int16_t nfval;
  42         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
  43         int i, j;
  44
  45         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
  46                 sort[i] = nfCalBuffer[i];
  47
  48         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
  49                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
  50                         if (sort[j] > sort[j - 1]) {
  51                                 nfval = sort[j];
  52                                 sort[j] = sort[j - 1];
  53                                 sort[j - 1] = nfval;
  54                         }
  55                 }
  56         }
  57         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
  58
  59         return nfval;
  60 }
  61
  62 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
  63                                               int16_t *nfarray)
  64 {
  65         int i;
  66
  67         for (i = 0; i < NUM_NF_READINGS; i++) {
  68                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
  69
  70                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
  71                         h[i].currIndex = 0;
  72
  73                 if (h[i].invalidNFcount > 0) {
  74                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
  75                             nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
  76                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
  77                         } else {
  78                                 h[i].invalidNFcount--;
  79                                 h[i].privNF = nfarray[i];
  80                         }
  81                 } else {
  82                         h[i].privNF =
  83                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
  84                 }
  85         }
  86         return;
  87 }
  88
  89 static void ath9k_hw_do_getnf(struct ath_hw *ah,
  90                               int16_t nfarray[NUM_NF_READINGS])
  91 {
  92         int16_t nf;
  93
  94         if (AR_SREV_9280_10_OR_LATER(ah))
  95                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
  96         else
  97                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
  98
  99         if (nf & 0x100)
 100                 nf = 0 - ((nf ^ 0x1ff) + 1);
 101         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 102                 "NF calibrated [ctl] [chain 0] is %d\n", nf);
 103         nfarray[0] = nf;
 104
 105         if (!AR_SREV_9285(ah)) {
 106                 if (AR_SREV_9280_10_OR_LATER(ah))
 107                         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
 108                                         AR9280_PHY_CH1_MINCCA_PWR);
 109                 else
 110                         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
 111                                         AR_PHY_CH1_MINCCA_PWR);
 112
 113                 if (nf & 0x100)
 114                         nf = 0 - ((nf ^ 0x1ff) + 1);
 115                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 116                                 "NF calibrated [ctl] [chain 1] is %d\n", nf);
 117                 nfarray[1] = nf;
 118
 119                 if (!AR_SREV_9280(ah)) {
 120                         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
 121                                         AR_PHY_CH2_MINCCA_PWR);
 122                         if (nf & 0x100)
 123                                 nf = 0 - ((nf ^ 0x1ff) + 1);
 124                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 125                                 "NF calibrated [ctl] [chain 2] is %d\n", nf);
 126                         nfarray[2] = nf;
 127                 }
 128         }
 129
 130         if (AR_SREV_9280_10_OR_LATER(ah))
 131                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
 132                         AR9280_PHY_EXT_MINCCA_PWR);
 133         else
 134                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
 135                         AR_PHY_EXT_MINCCA_PWR);
 136
 137         if (nf & 0x100)
 138                 nf = 0 - ((nf ^ 0x1ff) + 1);
 139         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 140                 "NF calibrated [ext] [chain 0] is %d\n", nf);
 141         nfarray[3] = nf;
 142
 143         if (!AR_SREV_9285(ah)) {
 144                 if (AR_SREV_9280_10_OR_LATER(ah))
 145                         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
 146                                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
 147                 else
 148                         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
 149                                         AR_PHY_CH1_EXT_MINCCA_PWR);
 150
 151                 if (nf & 0x100)
 152                         nf = 0 - ((nf ^ 0x1ff) + 1);
 153                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 154                                 "NF calibrated [ext] [chain 1] is %d\n", nf);
 155                 nfarray[4] = nf;
 156
 157                 if (!AR_SREV_9280(ah)) {
 158                         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
 159                                         AR_PHY_CH2_EXT_MINCCA_PWR);
 160                         if (nf & 0x100)
 161                                 nf = 0 - ((nf ^ 0x1ff) + 1);
 162                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 163                                 "NF calibrated [ext] [chain 2] is %d\n", nf);
 164                         nfarray[5] = nf;
 165                 }
 166         }
 167 }
 168
 169 static bool getNoiseFloorThresh(struct ath_hw *ah,
 170                                 enum ieee80211_band band,
 171                                 int16_t *nft)
 172 {
 173         switch (band) {
 174         case IEEE80211_BAND_5GHZ:
 175                 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
 176                 break;
 177         case IEEE80211_BAND_2GHZ:
 178                 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
 179                 break;
 180         default:
 181                 BUG_ON(1);
 182                 return false;
 183         }
 184
 185         return true;
 186 }
 187
 188 static void ath9k_hw_setup_calibration(struct ath_hw *ah,
 189                                        struct hal_cal_list *currCal)
 190 {
 191         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
 192                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
 193                       currCal->calData->calCountMax);
 194
 195         switch (currCal->calData->calType) {
 196         case IQ_MISMATCH_CAL:
 197                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
 198                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 199                         "starting IQ Mismatch Calibration\n");
 200                 break;
 201         case ADC_GAIN_CAL:
 202                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
 203                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 204                         "starting ADC Gain Calibration\n");
 205                 break;
 206         case ADC_DC_CAL:
 207                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
 208                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 209                         "starting ADC DC Calibration\n");
 210                 break;
 211         case ADC_DC_INIT_CAL:
 212                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
 213                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 214                         "starting Init ADC DC Calibration\n");
 215                 break;
 216         }
 217
 218         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 219                     AR_PHY_TIMING_CTRL4_DO_CAL);
 220 }
 221
 222 static void ath9k_hw_reset_calibration(struct ath_hw *ah,
 223                                        struct hal_cal_list *currCal)
 224 {
 225         int i;
 226
 227         ath9k_hw_setup_calibration(ah, currCal);
 228
 229         currCal->calState = CAL_RUNNING;
 230
 231         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 232                 ah->meas0.sign[i] = 0;
 233                 ah->meas1.sign[i] = 0;
 234                 ah->meas2.sign[i] = 0;
 235                 ah->meas3.sign[i] = 0;
 236         }
 237
 238         ah->cal_samples = 0;
 239 }
 240
 241 static void ath9k_hw_per_calibration(struct ath_hw *ah,
 242                                      struct ath9k_channel *ichan,
 243                                      u8 rxchainmask,
 244                                      struct hal_cal_list *currCal,
 245                                      bool *isCalDone)
 246 {
 247         *isCalDone = false;
 248
 249         if (currCal->calState == CAL_RUNNING) {
 250                 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 251                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
 252
 253                         currCal->calData->calCollect(ah);
 254                         ah->cal_samples++;
 255
 256                         if (ah->cal_samples >= currCal->calData->calNumSamples) {
 257                                 int i, numChains = 0;
 258                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 259                                         if (rxchainmask & (1 << i))
 260                                                 numChains++;
 261                                 }
 262
 263                                 currCal->calData->calPostProc(ah, numChains);
 264                                 ichan->CalValid |= currCal->calData->calType;
 265                                 currCal->calState = CAL_DONE;
 266                                 *isCalDone = true;
 267                         } else {
 268                                 ath9k_hw_setup_calibration(ah, currCal);
 269                         }
 270                 }
 271         } else if (!(ichan->CalValid & currCal->calData->calType)) {
 272                 ath9k_hw_reset_calibration(ah, currCal);
 273         }
 274 }
 275
 276 /* Assumes you are talking about the currently configured channel */
 277 static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
 278                                      enum hal_cal_types calType)
 279 {
 280         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
 281
 282         switch (calType & ah->supp_cals) {
 283         case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
 284                 return true;
 285         case ADC_GAIN_CAL:
 286         case ADC_DC_CAL:
 287                 if (conf->channel->band == IEEE80211_BAND_5GHZ &&
 288                   conf_is_ht20(conf))
 289                         return true;
 290                 break;
 291         }
 292         return false;
 293 }
 294
 295 static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
 296 {
 297         int i;
 298
 299         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 300                 ah->totalPowerMeasI[i] +=
 301                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 302                 ah->totalPowerMeasQ[i] +=
 303                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 304                 ah->totalIqCorrMeas[i] +=
 305                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 306                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 307                         "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
 308                         ah->cal_samples, i, ah->totalPowerMeasI[i],
 309                         ah->totalPowerMeasQ[i],
 310                         ah->totalIqCorrMeas[i]);
 311         }
 312 }
 313
 314 static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
 315 {
 316         int i;
 317
 318         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 319                 ah->totalAdcIOddPhase[i] +=
 320                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 321                 ah->totalAdcIEvenPhase[i] +=
 322                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 323                 ah->totalAdcQOddPhase[i] +=
 324                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 325                 ah->totalAdcQEvenPhase[i] +=
 326                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 327
 328                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 329                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 330                         "oddq=0x%08x; evenq=0x%08x;\n",
 331                         ah->cal_samples, i,
 332                         ah->totalAdcIOddPhase[i],
 333                         ah->totalAdcIEvenPhase[i],
 334                         ah->totalAdcQOddPhase[i],
 335                         ah->totalAdcQEvenPhase[i]);
 336         }
 337 }
 338
 339 static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
 340 {
 341         int i;
 342
 343         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 344                 ah->totalAdcDcOffsetIOddPhase[i] +=
 345                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 346                 ah->totalAdcDcOffsetIEvenPhase[i] +=
 347                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 348                 ah->totalAdcDcOffsetQOddPhase[i] +=
 349                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 350                 ah->totalAdcDcOffsetQEvenPhase[i] +=
 351                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 352
 353                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 354                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 355                         "oddq=0x%08x; evenq=0x%08x;\n",
 356                         ah->cal_samples, i,
 357                         ah->totalAdcDcOffsetIOddPhase[i],
 358                         ah->totalAdcDcOffsetIEvenPhase[i],
 359                         ah->totalAdcDcOffsetQOddPhase[i],
 360                         ah->totalAdcDcOffsetQEvenPhase[i]);
 361         }
 362 }
 363
 364 static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
 365 {
 366         u32 powerMeasQ, powerMeasI, iqCorrMeas;
 367         u32 qCoffDenom, iCoffDenom;
 368         int32_t qCoff, iCoff;
 369         int iqCorrNeg, i;
 370
 371         for (i = 0; i < numChains; i++) {
 372                 powerMeasI = ah->totalPowerMeasI[i];
 373                 powerMeasQ = ah->totalPowerMeasQ[i];
 374                 iqCorrMeas = ah->totalIqCorrMeas[i];
 375
 376                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 377                         "Starting IQ Cal and Correction for Chain %d\n",
 378                         i);
 379
 380                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 381                         "Orignal: Chn %diq_corr_meas = 0x%08x\n",
 382                         i, ah->totalIqCorrMeas[i]);
 383
 384                 iqCorrNeg = 0;
 385
 386                 if (iqCorrMeas > 0x80000000) {
 387                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
 388                         iqCorrNeg = 1;
 389                 }
 390
 391                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 392                         "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
 393                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 394                         "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
 395                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
 396                         iqCorrNeg);
 397
 398                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
 399                 qCoffDenom = powerMeasQ / 64;
 400
 401                 if (powerMeasQ != 0) {
 402                         iCoff = iqCorrMeas / iCoffDenom;
 403                         qCoff = powerMeasI / qCoffDenom - 64;
 404                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 405                                 "Chn %d iCoff = 0x%08x\n", i, iCoff);
 406                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 407                                 "Chn %d qCoff = 0x%08x\n", i, qCoff);
 408
 409                         iCoff = iCoff & 0x3f;
 410                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 411                                 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
 412                         if (iqCorrNeg == 0x0)
 413                                 iCoff = 0x40 - iCoff;
 414
 415                         if (qCoff > 15)
 416                                 qCoff = 15;
 417                         else if (qCoff <= -16)
 418                                 qCoff = 16;
 419
 420                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 421                                 "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
 422                                 i, iCoff, qCoff);
 423
 424                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 425                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
 426                                       iCoff);
 427                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 428                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
 429                                       qCoff);
 430                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 431                                 "IQ Cal and Correction done for Chain %d\n",
 432                                 i);
 433                 }
 434         }
 435
 436         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 437                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
 438 }
 439
 440 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
 441 {
 442         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
 443         u32 qGainMismatch, iGainMismatch, val, i;
 444
 445         for (i = 0; i < numChains; i++) {
 446                 iOddMeasOffset = ah->totalAdcIOddPhase[i];
 447                 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
 448                 qOddMeasOffset = ah->totalAdcQOddPhase[i];
 449                 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 450
 451                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 452                         "Starting ADC Gain Cal for Chain %d\n", i);
 453
 454                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 455                         "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
 456                         iOddMeasOffset);
 457                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 458                         "Chn %d pwr_meas_even_i = 0x%08x\n", i,
 459                         iEvenMeasOffset);
 460                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 461                         "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
 462                         qOddMeasOffset);
 463                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 464                         "Chn %d pwr_meas_even_q = 0x%08x\n", i,
 465                         qEvenMeasOffset);
 466
 467                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
 468                         iGainMismatch =
 469                                 ((iEvenMeasOffset * 32) /
 470                                  iOddMeasOffset) & 0x3f;
 471                         qGainMismatch =
 472                                 ((qOddMeasOffset * 32) /
 473                                  qEvenMeasOffset) & 0x3f;
 474
 475                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 476                                 "Chn %d gain_mismatch_i = 0x%08x\n", i,
 477                                 iGainMismatch);
 478                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 479                                 "Chn %d gain_mismatch_q = 0x%08x\n", i,
 480                                 qGainMismatch);
 481
 482                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 483                         val &= 0xfffff000;
 484                         val |= (qGainMismatch) | (iGainMismatch << 6);
 485                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 486
 487                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 488                                 "ADC Gain Cal done for Chain %d\n", i);
 489                 }
 490         }
 491
 492         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 493                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 494                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
 495 }
 496
 497 static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
 498 {
 499         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
 500         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
 501         const struct hal_percal_data *calData =
 502                 ah->cal_list_curr->calData;
 503         u32 numSamples =
 504                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
 505
 506         for (i = 0; i < numChains; i++) {
 507                 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
 508                 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
 509                 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
 510                 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 511
 512                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 513                         "Starting ADC DC Offset Cal for Chain %d\n", i);
 514
 515                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 516                         "Chn %d pwr_meas_odd_i = %d\n", i,
 517                         iOddMeasOffset);
 518                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 519                         "Chn %d pwr_meas_even_i = %d\n", i,
 520                         iEvenMeasOffset);
 521                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 522                         "Chn %d pwr_meas_odd_q = %d\n", i,
 523                         qOddMeasOffset);
 524                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 525                         "Chn %d pwr_meas_even_q = %d\n", i,
 526                         qEvenMeasOffset);
 527
 528                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
 529                                numSamples) & 0x1ff;
 530                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
 531                                numSamples) & 0x1ff;
 532
 533                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 534                         "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
 535                         iDcMismatch);
 536                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 537                         "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
 538                         qDcMismatch);
 539
 540                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 541                 val &= 0xc0000fff;
 542                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
 543                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 544
 545                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 546                         "ADC DC Offset Cal done for Chain %d\n", i);
 547         }
 548
 549         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 550                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 551                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 552 }
 553
 554 /* This is done for the currently configured channel */
 555 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
 556 {
 557         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
 558         struct hal_cal_list *currCal = ah->cal_list_curr;
 559
 560         if (!ah->curchan)
 561                 return true;
 562
 563         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
 564                 return true;
 565
 566         if (currCal == NULL)
 567                 return true;
 568
 569         if (currCal->calState != CAL_DONE) {
 570                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 571                         "Calibration state incorrect, %d\n",
 572                         currCal->calState);
 573                 return true;
 574         }
 575
 576         if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
 577                 return true;
 578
 579         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 580                 "Resetting Cal %d state for channel %u\n",
 581                 currCal->calData->calType, conf->channel->center_freq);
 582
 583         ah->curchan->CalValid &= ~currCal->calData->calType;
 584         currCal->calState = CAL_WAITING;
 585
 586         return false;
 587 }
 588
 589 void ath9k_hw_start_nfcal(struct ath_hw *ah)
 590 {
 591         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 592                     AR_PHY_AGC_CONTROL_ENABLE_NF);
 593         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 594                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
 595         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 596 }
 597
 598 void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
 599 {
 600         struct ath9k_nfcal_hist *h;
 601         int i, j;
 602         int32_t val;
 603         const u32 ar5416_cca_regs[6] = {
 604                 AR_PHY_CCA,
 605                 AR_PHY_CH1_CCA,
 606                 AR_PHY_CH2_CCA,
 607                 AR_PHY_EXT_CCA,
 608                 AR_PHY_CH1_EXT_CCA,
 609                 AR_PHY_CH2_EXT_CCA
 610         };
 611         u8 chainmask;
 612
 613         if (AR_SREV_9285(ah))
 614                 chainmask = 0x9;
 615         else if (AR_SREV_9280(ah))
 616                 chainmask = 0x1B;
 617         else
 618                 chainmask = 0x3F;
 619
 620         h = ah->nfCalHist;
 621
 622         for (i = 0; i < NUM_NF_READINGS; i++) {
 623                 if (chainmask & (1 << i)) {
 624                         val = REG_READ(ah, ar5416_cca_regs[i]);
 625                         val &= 0xFFFFFE00;
 626                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
 627                         REG_WRITE(ah, ar5416_cca_regs[i], val);
 628                 }
 629         }
 630
 631         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 632                     AR_PHY_AGC_CONTROL_ENABLE_NF);
 633         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 634                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
 635         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 636
 637         for (j = 0; j < 1000; j++) {
 638                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
 639                      AR_PHY_AGC_CONTROL_NF) == 0)
 640                         break;
 641                 udelay(10);
 642         }
 643
 644         for (i = 0; i < NUM_NF_READINGS; i++) {
 645                 if (chainmask & (1 << i)) {
 646                         val = REG_READ(ah, ar5416_cca_regs[i]);
 647                         val &= 0xFFFFFE00;
 648                         val |= (((u32) (-50) << 1) & 0x1ff);
 649                         REG_WRITE(ah, ar5416_cca_regs[i], val);
 650                 }
 651         }
 652 }
 653
 654 int16_t ath9k_hw_getnf(struct ath_hw *ah,
 655                        struct ath9k_channel *chan)
 656 {
 657         int16_t nf, nfThresh;
 658         int16_t nfarray[NUM_NF_READINGS] = { 0 };
 659         struct ath9k_nfcal_hist *h;
 660         struct ieee80211_channel *c = chan->chan;
 661
 662         chan->channelFlags &= (~CHANNEL_CW_INT);
 663         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
 664                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 665                         "NF did not complete in calibration window\n");
 666                 nf = 0;
 667                 chan->rawNoiseFloor = nf;
 668                 return chan->rawNoiseFloor;
 669         } else {
 670                 ath9k_hw_do_getnf(ah, nfarray);
 671                 nf = nfarray[0];
 672                 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
 673                     && nf > nfThresh) {
 674                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 675                                 "noise floor failed detected; "
 676                                 "detected %d, threshold %d\n",
 677                                 nf, nfThresh);
 678                         chan->channelFlags |= CHANNEL_CW_INT;
 679                 }
 680         }
 681
 682         h = ah->nfCalHist;
 683
 684         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
 685         chan->rawNoiseFloor = h[0].privNF;
 686
 687         return chan->rawNoiseFloor;
 688 }
 689
 690 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
 691 {
 692         int i, j;
 693
 694         for (i = 0; i < NUM_NF_READINGS; i++) {
 695                 ah->nfCalHist[i].currIndex = 0;
 696                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
 697                 ah->nfCalHist[i].invalidNFcount =
 698                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
 699                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
 700                         ah->nfCalHist[i].nfCalBuffer[j] =
 701                                 AR_PHY_CCA_MAX_GOOD_VALUE;
 702                 }
 703         }
 704 }
 705
 706 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
 707 {
 708         s16 nf;
 709
 710         if (chan->rawNoiseFloor == 0)
 711                 nf = -96;
 712         else
 713                 nf = chan->rawNoiseFloor;
 714
 715         if (!ath9k_hw_nf_in_range(ah, nf))
 716                 nf = ATH_DEFAULT_NOISE_FLOOR;
 717
 718         return nf;
 719 }
 720
 721 static void ath9k_olc_temp_compensation(struct ath_hw *ah)
 722 {
 723         u32 rddata, i;
 724         int delta, currPDADC, regval;
 725
 726         rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
 727
 728         currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
 729
 730         if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
 731                 delta = (currPDADC - ah->initPDADC + 4) / 8;
 732         else
 733                 delta = (currPDADC - ah->initPDADC + 5) / 10;
 734
 735         if (delta != ah->PDADCdelta) {
 736                 ah->PDADCdelta = delta;
 737                 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
 738                         regval = ah->originalGain[i] - delta;
 739                         if (regval < 0)
 740                                 regval = 0;
 741
 742                         REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4,
 743                                         AR_PHY_TX_GAIN, regval);
 744                 }
 745         }
 746 }
 747
 748 static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
 749 {
 750
 751         u32 regVal;
 752         int i, offset, offs_6_1, offs_0;
 753         u32 ccomp_org, reg_field;
 754         u32 regList[][2] = {
 755                 { 0x786c, 0 },
 756                 { 0x7854, 0 },
 757                 { 0x7820, 0 },
 758                 { 0x7824, 0 },
 759                 { 0x7868, 0 },
 760                 { 0x783c, 0 },
 761                 { 0x7838, 0 },
 762         };
 763
 764         if (AR_SREV_9285_11(ah)) {
 765                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
 766                 udelay(10);
 767         }
 768
 769         for (i = 0; i < ARRAY_SIZE(regList); i++)
 770                 regList[i][1] = REG_READ(ah, regList[i][0]);
 771
 772         regVal = REG_READ(ah, 0x7834);
 773         regVal &= (~(0x1));
 774         REG_WRITE(ah, 0x7834, regVal);
 775         regVal = REG_READ(ah, 0x9808);
 776         regVal |= (0x1 << 27);
 777         REG_WRITE(ah, 0x9808, regVal);
 778
 779         REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
 780         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
 781         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
 782         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
 783         REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
 784         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
 785         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
 786         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);
 787         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
 788         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
 789         REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
 790         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
 791         ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
 792         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);
 793
 794         REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
 795         udelay(30);
 796         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
 797         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
 798
 799         for (i = 6; i > 0; i--) {
 800                 regVal = REG_READ(ah, 0x7834);
 801                 regVal |= (1 << (19 + i));
 802                 REG_WRITE(ah, 0x7834, regVal);
 803                 udelay(1);
 804                 regVal = REG_READ(ah, 0x7834);
 805                 regVal &= (~(0x1 << (19 + i)));
 806                 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
 807                 regVal |= (reg_field << (19 + i));
 808                 REG_WRITE(ah, 0x7834, regVal);
 809         }
 810
 811         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
 812         udelay(1);
 813         reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
 814         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
 815         offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
 816         offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
 817
 818         offset = (offs_6_1<<1) | offs_0;
 819         offset = offset - 0;
 820         offs_6_1 = offset>>1;
 821         offs_0 = offset & 1;
 822
 823         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
 824         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
 825
 826         regVal = REG_READ(ah, 0x7834);
 827         regVal |= 0x1;
 828         REG_WRITE(ah, 0x7834, regVal);
 829         regVal = REG_READ(ah, 0x9808);
 830         regVal &= (~(0x1 << 27));
 831         REG_WRITE(ah, 0x9808, regVal);
 832
 833         for (i = 0; i < ARRAY_SIZE(regList); i++)
 834                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 835
 836         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
 837
 838         if (AR_SREV_9285_11(ah))
 839                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
 840
 841 }
 842
 843 bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
 844                         u8 rxchainmask, bool longcal,
 845                         bool *isCalDone)
 846 {
 847         struct hal_cal_list *currCal = ah->cal_list_curr;
 848
 849         *isCalDone = true;
 850
 851         if (currCal &&
 852             (currCal->calState == CAL_RUNNING ||
 853              currCal->calState == CAL_WAITING)) {
 854                 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
 855                                          isCalDone);
 856                 if (*isCalDone) {
 857                         ah->cal_list_curr = currCal = currCal->calNext;
 858
 859                         if (currCal->calState == CAL_WAITING) {
 860                                 *isCalDone = false;
 861                                 ath9k_hw_reset_calibration(ah, currCal);
 862                         }
 863                 }
 864         }
 865
 866         if (longcal) {
 867                 if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
 868                         ath9k_hw_9285_pa_cal(ah);
 869
 870                 if (OLC_FOR_AR9280_20_LATER)
 871                         ath9k_olc_temp_compensation(ah);
 872                 ath9k_hw_getnf(ah, chan);
 873                 ath9k_hw_loadnf(ah, ah->curchan);
 874                 ath9k_hw_start_nfcal(ah);
 875
 876                 if (chan->channelFlags & CHANNEL_CW_INT)
 877                         chan->channelFlags &= ~CHANNEL_CW_INT;
 878         }
 879
 880         return true;
 881 }
 882
 883 static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
 884 {
 885         REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 886         if (chan->channelFlags & CHANNEL_HT20) {
 887                 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 888                 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
 889                 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 890                             AR_PHY_AGC_CONTROL_FLTR_CAL);
 891                 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
 892                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
 893                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
 894                                   AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
 895                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset "
 896                                 "calibration failed to complete in "
 897                                 "1ms; noisy ??\n");
 898                         return false;
 899                 }
 900                 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
 901                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 902                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 903         }
 904         REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 905         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 906         REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
 907         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
 908         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
 909                           0, AH_WAIT_TIMEOUT)) {
 910                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration "
 911                                 "failed to complete in 1ms; noisy ??\n");
 912                 return false;
 913         }
 914
 915         REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 916         REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 917         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 918
 919         return true;
 920 }
 921
 922 bool ath9k_hw_init_cal(struct ath_hw *ah,
 923                        struct ath9k_channel *chan)
 924 {
 925         if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
 926                 if (!ar9285_clc(ah, chan))
 927                         return false;
 928         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 929                 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 930                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 931                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 932
 933                 /* Kick off the cal */
 934                 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 935                                 REG_READ(ah, AR_PHY_AGC_CONTROL) |
 936                                 AR_PHY_AGC_CONTROL_CAL);
 937
 938                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
 939                                         AR_PHY_AGC_CONTROL_CAL, 0,
 940                                         AH_WAIT_TIMEOUT)) {
 941                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 942                                 "offset calibration failed to complete in 1ms; "
 943                                 "noisy environment?\n");
 944                         return false;
 945                 }
 946
 947                 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 948                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 949                 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 950         }
 951
 952         /* Calibrate the AGC */
 953         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 954                         REG_READ(ah, AR_PHY_AGC_CONTROL) |
 955                         AR_PHY_AGC_CONTROL_CAL);
 956
 957         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
 958                                 0, AH_WAIT_TIMEOUT)) {
 959                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 960                         "offset calibration failed to complete in 1ms; "
 961                         "noisy environment?\n");
 962                 return false;
 963         }
 964
 965         if (AR_SREV_9280_10_OR_LATER(ah)) {
 966                 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 967                 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 968         }
 969
 970         /* Do PA Calibration */
 971         if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
 972                 ath9k_hw_9285_pa_cal(ah);
 973
 974         /* Do NF Calibration */
 975         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 976                         REG_READ(ah, AR_PHY_AGC_CONTROL) |
 977                         AR_PHY_AGC_CONTROL_NF);
 978
 979         ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
 980
 981         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
 982                 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
 983                         INIT_CAL(&ah->adcgain_caldata);
 984                         INSERT_CAL(ah, &ah->adcgain_caldata);
 985                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 986                                         "enabling ADC Gain Calibration.\n");
 987                 }
 988                 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
 989                         INIT_CAL(&ah->adcdc_caldata);
 990                         INSERT_CAL(ah, &ah->adcdc_caldata);
 991                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 992                                         "enabling ADC DC Calibration.\n");
 993                 }
 994                 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
 995                         INIT_CAL(&ah->iq_caldata);
 996                         INSERT_CAL(ah, &ah->iq_caldata);
 997                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 998                                         "enabling IQ Calibration.\n");
 999                 }
1000
1001                 ah->cal_list_curr = ah->cal_list;
1002
1003                 if (ah->cal_list_curr)
1004                         ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1005         }
1006
1007         chan->CalValid = 0;
1008
1009         return true;
1010 }
1011
1012 const struct hal_percal_data iq_cal_multi_sample = {
1013         IQ_MISMATCH_CAL,
1014         MAX_CAL_SAMPLES,
1015         PER_MIN_LOG_COUNT,
1016         ath9k_hw_iqcal_collect,
1017         ath9k_hw_iqcalibrate
1018 };
1019 const struct hal_percal_data iq_cal_single_sample = {
1020         IQ_MISMATCH_CAL,
1021         MIN_CAL_SAMPLES,
1022         PER_MAX_LOG_COUNT,
1023         ath9k_hw_iqcal_collect,
1024         ath9k_hw_iqcalibrate
1025 };
1026 const struct hal_percal_data adc_gain_cal_multi_sample = {
1027         ADC_GAIN_CAL,
1028         MAX_CAL_SAMPLES,
1029         PER_MIN_LOG_COUNT,
1030         ath9k_hw_adc_gaincal_collect,
1031         ath9k_hw_adc_gaincal_calibrate
1032 };
1033 const struct hal_percal_data adc_gain_cal_single_sample = {
1034         ADC_GAIN_CAL,
1035         MIN_CAL_SAMPLES,
1036         PER_MAX_LOG_COUNT,
1037         ath9k_hw_adc_gaincal_collect,
1038         ath9k_hw_adc_gaincal_calibrate
1039 };
1040 const struct hal_percal_data adc_dc_cal_multi_sample = {
1041         ADC_DC_CAL,
1042         MAX_CAL_SAMPLES,
1043         PER_MIN_LOG_COUNT,
1044         ath9k_hw_adc_dccal_collect,
1045         ath9k_hw_adc_dccal_calibrate
1046 };
1047 const struct hal_percal_data adc_dc_cal_single_sample = {
1048         ADC_DC_CAL,
1049         MIN_CAL_SAMPLES,
1050         PER_MAX_LOG_COUNT,
1051         ath9k_hw_adc_dccal_collect,
1052         ath9k_hw_adc_dccal_calibrate
1053 };
1054 const struct hal_percal_data adc_init_dc_cal = {
1055         ADC_DC_INIT_CAL,
1056         MIN_CAL_SAMPLES,
1057         INIT_LOG_COUNT,
1058         ath9k_hw_adc_dccal_collect,
1059         ath9k_hw_adc_dccal_calibrate
1060 };