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   1 /*
   2  *  This file contains the power_save function for 970-family CPUs.
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/threads.h>
  11 #include <asm/processor.h>
  12 #include <asm/page.h>
  13 #include <asm/cputable.h>
  14 #include <asm/thread_info.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17
  18 #undef DEBUG
  19
  20         .text
  21
  22 _GLOBAL(power4_idle)
  23 BEGIN_FTR_SECTION
  24         blr
  25 END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
  26         /* Now check if user or arch enabled NAP mode */
  27         LOAD_REG_ADDRBASE(r3,powersave_nap)
  28         lwz     r4,ADDROFF(powersave_nap)(r3)
  29         cmpwi   0,r4,0
  30         beqlr
  31
  32         /* Go to NAP now */
  33         mfmsr   r7
  34         rldicl  r0,r7,48,1
  35         rotldi  r0,r0,16
  36         mtmsrd  r0,1                    /* hard-disable interrupts */
  37         li      r0,1
  38         stb     r0,PACASOFTIRQEN(r13)   /* we'll hard-enable shortly */
  39         stb     r0,PACAHARDIRQEN(r13)
  40 BEGIN_FTR_SECTION
  41         DSSALL
  42         sync
  43 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  44         clrrdi  r9,r1,THREAD_SHIFT      /* current thread_info */
  45         ld      r8,TI_LOCAL_FLAGS(r9)   /* set napping bit */
  46         ori     r8,r8,_TLF_NAPPING      /* so when we take an exception */
  47         std     r8,TI_LOCAL_FLAGS(r9)   /* it will return to our caller */
  48         ori     r7,r7,MSR_EE
  49         oris    r7,r7,MSR_POW@h
  50 1:      sync
  51         isync
  52         mtmsrd  r7
  53         isync
  54         b       1b
  55
  56 _GLOBAL(power4_cpu_offline_powersave)
  57         /* Go to NAP now */
  58         mfmsr   r7
  59         rldicl  r0,r7,48,1
  60         rotldi  r0,r0,16
  61         mtmsrd  r0,1                    /* hard-disable interrupts */
  62         li      r0,1
  63         li      r6,0
  64         stb     r0,PACAHARDIRQEN(r13)   /* we'll hard-enable shortly */
  65         stb     r6,PACASOFTIRQEN(r13)   /* soft-disable irqs */
  66 BEGIN_FTR_SECTION
  67         DSSALL
  68         sync
  69 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  70         ori     r7,r7,MSR_EE
  71         oris    r7,r7,MSR_POW@h
  72         sync
  73         isync
  74         mtmsrd  r7
  75         isync
  76         blr