Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[linux-2.6] / drivers / mtd / nand / pxa3xx_nand.c
1 /*
2  * drivers/mtd/nand/pxa3xx_nand.c
3  *
4  * Copyright © 2005 Intel Corporation
5  * Copyright © 2006 Marvell International Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/io.h>
22 #include <linux/irq.h>
23
24 #include <mach/dma.h>
25 #include <mach/pxa3xx_nand.h>
26
27 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
28
29 /* registers and bit definitions */
30 #define NDCR            (0x00) /* Control register */
31 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
32 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
33 #define NDSR            (0x14) /* Status Register */
34 #define NDPCR           (0x18) /* Page Count Register */
35 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
36 #define NDBDR1          (0x20) /* Bad Block Register 1 */
37 #define NDDB            (0x40) /* Data Buffer */
38 #define NDCB0           (0x48) /* Command Buffer0 */
39 #define NDCB1           (0x4C) /* Command Buffer1 */
40 #define NDCB2           (0x50) /* Command Buffer2 */
41
42 #define NDCR_SPARE_EN           (0x1 << 31)
43 #define NDCR_ECC_EN             (0x1 << 30)
44 #define NDCR_DMA_EN             (0x1 << 29)
45 #define NDCR_ND_RUN             (0x1 << 28)
46 #define NDCR_DWIDTH_C           (0x1 << 27)
47 #define NDCR_DWIDTH_M           (0x1 << 26)
48 #define NDCR_PAGE_SZ            (0x1 << 24)
49 #define NDCR_NCSX               (0x1 << 23)
50 #define NDCR_ND_MODE            (0x3 << 21)
51 #define NDCR_NAND_MODE          (0x0)
52 #define NDCR_CLR_PG_CNT         (0x1 << 20)
53 #define NDCR_CLR_ECC            (0x1 << 19)
54 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
55 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
56
57 #define NDCR_RA_START           (0x1 << 15)
58 #define NDCR_PG_PER_BLK         (0x1 << 14)
59 #define NDCR_ND_ARB_EN          (0x1 << 12)
60
61 #define NDSR_MASK               (0xfff)
62 #define NDSR_RDY                (0x1 << 11)
63 #define NDSR_CS0_PAGED          (0x1 << 10)
64 #define NDSR_CS1_PAGED          (0x1 << 9)
65 #define NDSR_CS0_CMDD           (0x1 << 8)
66 #define NDSR_CS1_CMDD           (0x1 << 7)
67 #define NDSR_CS0_BBD            (0x1 << 6)
68 #define NDSR_CS1_BBD            (0x1 << 5)
69 #define NDSR_DBERR              (0x1 << 4)
70 #define NDSR_SBERR              (0x1 << 3)
71 #define NDSR_WRDREQ             (0x1 << 2)
72 #define NDSR_RDDREQ             (0x1 << 1)
73 #define NDSR_WRCMDREQ           (0x1)
74
75 #define NDCB0_AUTO_RS           (0x1 << 25)
76 #define NDCB0_CSEL              (0x1 << 24)
77 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
78 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
79 #define NDCB0_NC                (0x1 << 20)
80 #define NDCB0_DBC               (0x1 << 19)
81 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
82 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
83 #define NDCB0_CMD2_MASK         (0xff << 8)
84 #define NDCB0_CMD1_MASK         (0xff)
85 #define NDCB0_ADDR_CYC_SHIFT    (16)
86
87 /* dma-able I/O address for the NAND data and commands */
88 #define NDCB0_DMA_ADDR          (0x43100048)
89 #define NDDB_DMA_ADDR           (0x43100040)
90
91 /* macros for registers read/write */
92 #define nand_writel(info, off, val)     \
93         __raw_writel((val), (info)->mmio_base + (off))
94
95 #define nand_readl(info, off)           \
96         __raw_readl((info)->mmio_base + (off))
97
98 /* error code and state */
99 enum {
100         ERR_NONE        = 0,
101         ERR_DMABUSERR   = -1,
102         ERR_SENDCMD     = -2,
103         ERR_DBERR       = -3,
104         ERR_BBERR       = -4,
105 };
106
107 enum {
108         STATE_READY     = 0,
109         STATE_CMD_HANDLE,
110         STATE_DMA_READING,
111         STATE_DMA_WRITING,
112         STATE_DMA_DONE,
113         STATE_PIO_READING,
114         STATE_PIO_WRITING,
115 };
116
117 struct pxa3xx_nand_info {
118         struct nand_chip        nand_chip;
119
120         struct platform_device   *pdev;
121         const struct pxa3xx_nand_flash *flash_info;
122
123         struct clk              *clk;
124         void __iomem            *mmio_base;
125
126         unsigned int            buf_start;
127         unsigned int            buf_count;
128
129         /* DMA information */
130         int                     drcmr_dat;
131         int                     drcmr_cmd;
132
133         unsigned char           *data_buff;
134         dma_addr_t              data_buff_phys;
135         size_t                  data_buff_size;
136         int                     data_dma_ch;
137         struct pxa_dma_desc     *data_desc;
138         dma_addr_t              data_desc_addr;
139
140         uint32_t                reg_ndcr;
141
142         /* saved column/page_addr during CMD_SEQIN */
143         int                     seqin_column;
144         int                     seqin_page_addr;
145
146         /* relate to the command */
147         unsigned int            state;
148
149         int                     use_ecc;        /* use HW ECC ? */
150         int                     use_dma;        /* use DMA ? */
151
152         size_t                  data_size;      /* data size in FIFO */
153         int                     retcode;
154         struct completion       cmd_complete;
155
156         /* generated NDCBx register values */
157         uint32_t                ndcb0;
158         uint32_t                ndcb1;
159         uint32_t                ndcb2;
160
161         /* calculated from pxa3xx_nand_flash data */
162         size_t          oob_size;
163         size_t          read_id_bytes;
164
165         unsigned int    col_addr_cycles;
166         unsigned int    row_addr_cycles;
167 };
168
169 static int use_dma = 1;
170 module_param(use_dma, bool, 0444);
171 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
172
173 /*
174  * Default NAND flash controller configuration setup by the
175  * bootloader. This configuration is used only when pdata->keep_config is set
176  */
177 static struct pxa3xx_nand_timing default_timing;
178 static struct pxa3xx_nand_flash default_flash;
179
180 static struct pxa3xx_nand_cmdset smallpage_cmdset = {
181         .read1          = 0x0000,
182         .read2          = 0x0050,
183         .program        = 0x1080,
184         .read_status    = 0x0070,
185         .read_id        = 0x0090,
186         .erase          = 0xD060,
187         .reset          = 0x00FF,
188         .lock           = 0x002A,
189         .unlock         = 0x2423,
190         .lock_status    = 0x007A,
191 };
192
193 static struct pxa3xx_nand_cmdset largepage_cmdset = {
194         .read1          = 0x3000,
195         .read2          = 0x0050,
196         .program        = 0x1080,
197         .read_status    = 0x0070,
198         .read_id        = 0x0090,
199         .erase          = 0xD060,
200         .reset          = 0x00FF,
201         .lock           = 0x002A,
202         .unlock         = 0x2423,
203         .lock_status    = 0x007A,
204 };
205
206 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
207 static struct pxa3xx_nand_timing samsung512MbX16_timing = {
208         .tCH    = 10,
209         .tCS    = 0,
210         .tWH    = 20,
211         .tWP    = 40,
212         .tRH    = 30,
213         .tRP    = 40,
214         .tR     = 11123,
215         .tWHR   = 110,
216         .tAR    = 10,
217 };
218
219 static struct pxa3xx_nand_flash samsung512MbX16 = {
220         .timing         = &samsung512MbX16_timing,
221         .cmdset         = &smallpage_cmdset,
222         .page_per_block = 32,
223         .page_size      = 512,
224         .flash_width    = 16,
225         .dfc_width      = 16,
226         .num_blocks     = 4096,
227         .chip_id        = 0x46ec,
228 };
229
230 static struct pxa3xx_nand_timing micron_timing = {
231         .tCH    = 10,
232         .tCS    = 25,
233         .tWH    = 15,
234         .tWP    = 25,
235         .tRH    = 15,
236         .tRP    = 25,
237         .tR     = 25000,
238         .tWHR   = 60,
239         .tAR    = 10,
240 };
241
242 static struct pxa3xx_nand_flash micron1GbX8 = {
243         .timing         = &micron_timing,
244         .cmdset         = &largepage_cmdset,
245         .page_per_block = 64,
246         .page_size      = 2048,
247         .flash_width    = 8,
248         .dfc_width      = 8,
249         .num_blocks     = 1024,
250         .chip_id        = 0xa12c,
251 };
252
253 static struct pxa3xx_nand_flash micron1GbX16 = {
254         .timing         = &micron_timing,
255         .cmdset         = &largepage_cmdset,
256         .page_per_block = 64,
257         .page_size      = 2048,
258         .flash_width    = 16,
259         .dfc_width      = 16,
260         .num_blocks     = 1024,
261         .chip_id        = 0xb12c,
262 };
263
264 static struct pxa3xx_nand_timing stm2GbX16_timing = {
265         .tCH = 10,
266         .tCS = 35,
267         .tWH = 15,
268         .tWP = 25,
269         .tRH = 15,
270         .tRP = 25,
271         .tR = 25000,
272         .tWHR = 60,
273         .tAR = 10,
274 };
275
276 static struct pxa3xx_nand_flash stm2GbX16 = {
277         .timing = &stm2GbX16_timing,
278         .cmdset = &largepage_cmdset,
279         .page_per_block = 64,
280         .page_size = 2048,
281         .flash_width = 16,
282         .dfc_width = 16,
283         .num_blocks = 2048,
284         .chip_id = 0xba20,
285 };
286
287 static struct pxa3xx_nand_flash *builtin_flash_types[] = {
288         &samsung512MbX16,
289         &micron1GbX8,
290         &micron1GbX16,
291         &stm2GbX16,
292 };
293 #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
294
295 #define NDTR0_tCH(c)    (min((c), 7) << 19)
296 #define NDTR0_tCS(c)    (min((c), 7) << 16)
297 #define NDTR0_tWH(c)    (min((c), 7) << 11)
298 #define NDTR0_tWP(c)    (min((c), 7) << 8)
299 #define NDTR0_tRH(c)    (min((c), 7) << 3)
300 #define NDTR0_tRP(c)    (min((c), 7) << 0)
301
302 #define NDTR1_tR(c)     (min((c), 65535) << 16)
303 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
304 #define NDTR1_tAR(c)    (min((c), 15) << 0)
305
306 #define tCH_NDTR0(r)    (((r) >> 19) & 0x7)
307 #define tCS_NDTR0(r)    (((r) >> 16) & 0x7)
308 #define tWH_NDTR0(r)    (((r) >> 11) & 0x7)
309 #define tWP_NDTR0(r)    (((r) >> 8) & 0x7)
310 #define tRH_NDTR0(r)    (((r) >> 3) & 0x7)
311 #define tRP_NDTR0(r)    (((r) >> 0) & 0x7)
312
313 #define tR_NDTR1(r)     (((r) >> 16) & 0xffff)
314 #define tWHR_NDTR1(r)   (((r) >> 4) & 0xf)
315 #define tAR_NDTR1(r)    (((r) >> 0) & 0xf)
316
317 /* convert nano-seconds to nand flash controller clock cycles */
318 #define ns2cycle(ns, clk)       (int)(((ns) * (clk / 1000000) / 1000) - 1)
319
320 /* convert nand flash controller clock cycles to nano-seconds */
321 #define cycle2ns(c, clk)        ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
322
323 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
324                                    const struct pxa3xx_nand_timing *t)
325 {
326         unsigned long nand_clk = clk_get_rate(info->clk);
327         uint32_t ndtr0, ndtr1;
328
329         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
330                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
331                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
332                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
333                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
334                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
335
336         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
337                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
338                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
339
340         nand_writel(info, NDTR0CS0, ndtr0);
341         nand_writel(info, NDTR1CS0, ndtr1);
342 }
343
344 #define WAIT_EVENT_TIMEOUT      10
345
346 static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
347 {
348         int timeout = WAIT_EVENT_TIMEOUT;
349         uint32_t ndsr;
350
351         while (timeout--) {
352                 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
353                 if (ndsr & event) {
354                         nand_writel(info, NDSR, ndsr);
355                         return 0;
356                 }
357                 udelay(10);
358         }
359
360         return -ETIMEDOUT;
361 }
362
363 static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
364                         uint16_t cmd, int column, int page_addr)
365 {
366         const struct pxa3xx_nand_flash *f = info->flash_info;
367         const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
368
369         /* calculate data size */
370         switch (f->page_size) {
371         case 2048:
372                 info->data_size = (info->use_ecc) ? 2088 : 2112;
373                 break;
374         case 512:
375                 info->data_size = (info->use_ecc) ? 520 : 528;
376                 break;
377         default:
378                 return -EINVAL;
379         }
380
381         /* generate values for NDCBx registers */
382         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
383         info->ndcb1 = 0;
384         info->ndcb2 = 0;
385         info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
386
387         if (info->col_addr_cycles == 2) {
388                 /* large block, 2 cycles for column address
389                  * row address starts from 3rd cycle
390                  */
391                 info->ndcb1 |= page_addr << 16;
392                 if (info->row_addr_cycles == 3)
393                         info->ndcb2 = (page_addr >> 16) & 0xff;
394         } else
395                 /* small block, 1 cycles for column address
396                  * row address starts from 2nd cycle
397                  */
398                 info->ndcb1 = page_addr << 8;
399
400         if (cmd == cmdset->program)
401                 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
402
403         return 0;
404 }
405
406 static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
407                         uint16_t cmd, int page_addr)
408 {
409         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
410         info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
411         info->ndcb1 = page_addr;
412         info->ndcb2 = 0;
413         return 0;
414 }
415
416 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
417 {
418         const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
419
420         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
421         info->ndcb1 = 0;
422         info->ndcb2 = 0;
423
424         if (cmd == cmdset->read_id) {
425                 info->ndcb0 |= NDCB0_CMD_TYPE(3);
426                 info->data_size = 8;
427         } else if (cmd == cmdset->read_status) {
428                 info->ndcb0 |= NDCB0_CMD_TYPE(4);
429                 info->data_size = 8;
430         } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
431                    cmd == cmdset->unlock) {
432                 info->ndcb0 |= NDCB0_CMD_TYPE(5);
433         } else
434                 return -EINVAL;
435
436         return 0;
437 }
438
439 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
440 {
441         uint32_t ndcr;
442
443         ndcr = nand_readl(info, NDCR);
444         nand_writel(info, NDCR, ndcr & ~int_mask);
445 }
446
447 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
448 {
449         uint32_t ndcr;
450
451         ndcr = nand_readl(info, NDCR);
452         nand_writel(info, NDCR, ndcr | int_mask);
453 }
454
455 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
456  * otherwise, it does not work
457  */
458 static int write_cmd(struct pxa3xx_nand_info *info)
459 {
460         uint32_t ndcr;
461
462         /* clear status bits and run */
463         nand_writel(info, NDSR, NDSR_MASK);
464
465         ndcr = info->reg_ndcr;
466
467         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
468         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
469         ndcr |= NDCR_ND_RUN;
470
471         nand_writel(info, NDCR, ndcr);
472
473         if (wait_for_event(info, NDSR_WRCMDREQ)) {
474                 printk(KERN_ERR "timed out writing command\n");
475                 return -ETIMEDOUT;
476         }
477
478         nand_writel(info, NDCB0, info->ndcb0);
479         nand_writel(info, NDCB0, info->ndcb1);
480         nand_writel(info, NDCB0, info->ndcb2);
481         return 0;
482 }
483
484 static int handle_data_pio(struct pxa3xx_nand_info *info)
485 {
486         int ret, timeout = CHIP_DELAY_TIMEOUT;
487
488         switch (info->state) {
489         case STATE_PIO_WRITING:
490                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
491                                 info->data_size << 2);
492
493                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
494
495                 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
496                 if (!ret) {
497                         printk(KERN_ERR "program command time out\n");
498                         return -1;
499                 }
500                 break;
501         case STATE_PIO_READING:
502                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
503                                 info->data_size << 2);
504                 break;
505         default:
506                 printk(KERN_ERR "%s: invalid state %d\n", __func__,
507                                 info->state);
508                 return -EINVAL;
509         }
510
511         info->state = STATE_READY;
512         return 0;
513 }
514
515 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
516 {
517         struct pxa_dma_desc *desc = info->data_desc;
518         int dma_len = ALIGN(info->data_size, 32);
519
520         desc->ddadr = DDADR_STOP;
521         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
522
523         if (dir_out) {
524                 desc->dsadr = info->data_buff_phys;
525                 desc->dtadr = NDDB_DMA_ADDR;
526                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
527         } else {
528                 desc->dtadr = info->data_buff_phys;
529                 desc->dsadr = NDDB_DMA_ADDR;
530                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
531         }
532
533         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
534         DDADR(info->data_dma_ch) = info->data_desc_addr;
535         DCSR(info->data_dma_ch) |= DCSR_RUN;
536 }
537
538 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
539 {
540         struct pxa3xx_nand_info *info = data;
541         uint32_t dcsr;
542
543         dcsr = DCSR(channel);
544         DCSR(channel) = dcsr;
545
546         if (dcsr & DCSR_BUSERR) {
547                 info->retcode = ERR_DMABUSERR;
548                 complete(&info->cmd_complete);
549         }
550
551         if (info->state == STATE_DMA_WRITING) {
552                 info->state = STATE_DMA_DONE;
553                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
554         } else {
555                 info->state = STATE_READY;
556                 complete(&info->cmd_complete);
557         }
558 }
559
560 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
561 {
562         struct pxa3xx_nand_info *info = devid;
563         unsigned int status;
564
565         status = nand_readl(info, NDSR);
566
567         if (status & (NDSR_RDDREQ | NDSR_DBERR)) {
568                 if (status & NDSR_DBERR)
569                         info->retcode = ERR_DBERR;
570
571                 disable_int(info, NDSR_RDDREQ | NDSR_DBERR);
572
573                 if (info->use_dma) {
574                         info->state = STATE_DMA_READING;
575                         start_data_dma(info, 0);
576                 } else {
577                         info->state = STATE_PIO_READING;
578                         complete(&info->cmd_complete);
579                 }
580         } else if (status & NDSR_WRDREQ) {
581                 disable_int(info, NDSR_WRDREQ);
582                 if (info->use_dma) {
583                         info->state = STATE_DMA_WRITING;
584                         start_data_dma(info, 1);
585                 } else {
586                         info->state = STATE_PIO_WRITING;
587                         complete(&info->cmd_complete);
588                 }
589         } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
590                 if (status & NDSR_CS0_BBD)
591                         info->retcode = ERR_BBERR;
592
593                 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
594                 info->state = STATE_READY;
595                 complete(&info->cmd_complete);
596         }
597         nand_writel(info, NDSR, status);
598         return IRQ_HANDLED;
599 }
600
601 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
602 {
603         uint32_t ndcr;
604         int ret, timeout = CHIP_DELAY_TIMEOUT;
605
606         if (write_cmd(info)) {
607                 info->retcode = ERR_SENDCMD;
608                 goto fail_stop;
609         }
610
611         info->state = STATE_CMD_HANDLE;
612
613         enable_int(info, event);
614
615         ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
616         if (!ret) {
617                 printk(KERN_ERR "command execution timed out\n");
618                 info->retcode = ERR_SENDCMD;
619                 goto fail_stop;
620         }
621
622         if (info->use_dma == 0 && info->data_size > 0)
623                 if (handle_data_pio(info))
624                         goto fail_stop;
625
626         return 0;
627
628 fail_stop:
629         ndcr = nand_readl(info, NDCR);
630         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
631         udelay(10);
632         return -ETIMEDOUT;
633 }
634
635 static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
636 {
637         struct pxa3xx_nand_info *info = mtd->priv;
638         return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
639 }
640
641 static inline int is_buf_blank(uint8_t *buf, size_t len)
642 {
643         for (; len > 0; len--)
644                 if (*buf++ != 0xff)
645                         return 0;
646         return 1;
647 }
648
649 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
650                                 int column, int page_addr)
651 {
652         struct pxa3xx_nand_info *info = mtd->priv;
653         const struct pxa3xx_nand_flash *flash_info = info->flash_info;
654         const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
655         int ret;
656
657         info->use_dma = (use_dma) ? 1 : 0;
658         info->use_ecc = 0;
659         info->data_size = 0;
660         info->state = STATE_READY;
661
662         init_completion(&info->cmd_complete);
663
664         switch (command) {
665         case NAND_CMD_READOOB:
666                 /* disable HW ECC to get all the OOB data */
667                 info->buf_count = mtd->writesize + mtd->oobsize;
668                 info->buf_start = mtd->writesize + column;
669
670                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
671                         break;
672
673                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR);
674
675                 /* We only are OOB, so if the data has error, does not matter */
676                 if (info->retcode == ERR_DBERR)
677                         info->retcode = ERR_NONE;
678                 break;
679
680         case NAND_CMD_READ0:
681                 info->use_ecc = 1;
682                 info->retcode = ERR_NONE;
683                 info->buf_start = column;
684                 info->buf_count = mtd->writesize + mtd->oobsize;
685                 memset(info->data_buff, 0xFF, info->buf_count);
686
687                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
688                         break;
689
690                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR);
691
692                 if (info->retcode == ERR_DBERR) {
693                         /* for blank page (all 0xff), HW will calculate its ECC as
694                          * 0, which is different from the ECC information within
695                          * OOB, ignore such double bit errors
696                          */
697                         if (is_buf_blank(info->data_buff, mtd->writesize))
698                                 info->retcode = ERR_NONE;
699                 }
700                 break;
701         case NAND_CMD_SEQIN:
702                 info->buf_start = column;
703                 info->buf_count = mtd->writesize + mtd->oobsize;
704                 memset(info->data_buff, 0xff, info->buf_count);
705
706                 /* save column/page_addr for next CMD_PAGEPROG */
707                 info->seqin_column = column;
708                 info->seqin_page_addr = page_addr;
709                 break;
710         case NAND_CMD_PAGEPROG:
711                 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
712
713                 if (prepare_read_prog_cmd(info, cmdset->program,
714                                 info->seqin_column, info->seqin_page_addr))
715                         break;
716
717                 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
718                 break;
719         case NAND_CMD_ERASE1:
720                 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
721                         break;
722
723                 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
724                 break;
725         case NAND_CMD_ERASE2:
726                 break;
727         case NAND_CMD_READID:
728         case NAND_CMD_STATUS:
729                 info->use_dma = 0;      /* force PIO read */
730                 info->buf_start = 0;
731                 info->buf_count = (command == NAND_CMD_READID) ?
732                                 info->read_id_bytes : 1;
733
734                 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
735                                 cmdset->read_id : cmdset->read_status))
736                         break;
737
738                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
739                 break;
740         case NAND_CMD_RESET:
741                 if (prepare_other_cmd(info, cmdset->reset))
742                         break;
743
744                 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
745                 if (ret == 0) {
746                         int timeout = 2;
747                         uint32_t ndcr;
748
749                         while (timeout--) {
750                                 if (nand_readl(info, NDSR) & NDSR_RDY)
751                                         break;
752                                 msleep(10);
753                         }
754
755                         ndcr = nand_readl(info, NDCR);
756                         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
757                 }
758                 break;
759         default:
760                 printk(KERN_ERR "non-supported command.\n");
761                 break;
762         }
763
764         if (info->retcode == ERR_DBERR) {
765                 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
766                 info->retcode = ERR_NONE;
767         }
768 }
769
770 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
771 {
772         struct pxa3xx_nand_info *info = mtd->priv;
773         char retval = 0xFF;
774
775         if (info->buf_start < info->buf_count)
776                 /* Has just send a new command? */
777                 retval = info->data_buff[info->buf_start++];
778
779         return retval;
780 }
781
782 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
783 {
784         struct pxa3xx_nand_info *info = mtd->priv;
785         u16 retval = 0xFFFF;
786
787         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
788                 retval = *((u16 *)(info->data_buff+info->buf_start));
789                 info->buf_start += 2;
790         }
791         return retval;
792 }
793
794 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
795 {
796         struct pxa3xx_nand_info *info = mtd->priv;
797         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
798
799         memcpy(buf, info->data_buff + info->buf_start, real_len);
800         info->buf_start += real_len;
801 }
802
803 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
804                 const uint8_t *buf, int len)
805 {
806         struct pxa3xx_nand_info *info = mtd->priv;
807         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
808
809         memcpy(info->data_buff + info->buf_start, buf, real_len);
810         info->buf_start += real_len;
811 }
812
813 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
814                 const uint8_t *buf, int len)
815 {
816         return 0;
817 }
818
819 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
820 {
821         return;
822 }
823
824 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
825 {
826         struct pxa3xx_nand_info *info = mtd->priv;
827
828         /* pxa3xx_nand_send_command has waited for command complete */
829         if (this->state == FL_WRITING || this->state == FL_ERASING) {
830                 if (info->retcode == ERR_NONE)
831                         return 0;
832                 else {
833                         /*
834                          * any error make it return 0x01 which will tell
835                          * the caller the erase and write fail
836                          */
837                         return 0x01;
838                 }
839         }
840
841         return 0;
842 }
843
844 static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
845 {
846         return;
847 }
848
849 static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
850                 const uint8_t *dat, uint8_t *ecc_code)
851 {
852         return 0;
853 }
854
855 static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
856                 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
857 {
858         struct pxa3xx_nand_info *info = mtd->priv;
859         /*
860          * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
861          * consider it as a ecc error which will tell the caller the
862          * read fail We have distinguish all the errors, but the
863          * nand_read_ecc only check this function return value
864          */
865         if (info->retcode != ERR_NONE)
866                 return -1;
867
868         return 0;
869 }
870
871 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
872 {
873         const struct pxa3xx_nand_flash *f = info->flash_info;
874         const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
875         uint32_t ndcr;
876         uint8_t  id_buff[8];
877
878         if (prepare_other_cmd(info, cmdset->read_id)) {
879                 printk(KERN_ERR "failed to prepare command\n");
880                 return -EINVAL;
881         }
882
883         /* Send command */
884         if (write_cmd(info))
885                 goto fail_timeout;
886
887         /* Wait for CMDDM(command done successfully) */
888         if (wait_for_event(info, NDSR_RDDREQ))
889                 goto fail_timeout;
890
891         __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
892         *id = id_buff[0] | (id_buff[1] << 8);
893         return 0;
894
895 fail_timeout:
896         ndcr = nand_readl(info, NDCR);
897         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
898         udelay(10);
899         return -ETIMEDOUT;
900 }
901
902 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
903                                     const struct pxa3xx_nand_flash *f)
904 {
905         struct platform_device *pdev = info->pdev;
906         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
907         uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
908
909         if (f->page_size != 2048 && f->page_size != 512)
910                 return -EINVAL;
911
912         if (f->flash_width != 16 && f->flash_width != 8)
913                 return -EINVAL;
914
915         /* calculate flash information */
916         info->oob_size = (f->page_size == 2048) ? 64 : 16;
917         info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
918
919         /* calculate addressing information */
920         info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
921
922         if (f->num_blocks * f->page_per_block > 65536)
923                 info->row_addr_cycles = 3;
924         else
925                 info->row_addr_cycles = 2;
926
927         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
928         ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
929         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
930         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
931         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
932         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
933
934         ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
935         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
936
937         info->reg_ndcr = ndcr;
938
939         pxa3xx_nand_set_timing(info, f->timing);
940         info->flash_info = f;
941         return 0;
942 }
943
944 static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
945                                       struct pxa3xx_nand_timing *t)
946 {
947         unsigned long nand_clk = clk_get_rate(info->clk);
948         uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
949         uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
950
951         t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
952         t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
953         t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
954         t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
955         t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
956         t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
957
958         t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
959         t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
960         t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
961 }
962
963 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
964 {
965         uint32_t ndcr = nand_readl(info, NDCR);
966         struct nand_flash_dev *type = NULL;
967         uint32_t id = -1;
968         int i;
969
970         default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
971         default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
972         default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
973         default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
974
975         if (default_flash.page_size == 2048)
976                 default_flash.cmdset = &largepage_cmdset;
977         else
978                 default_flash.cmdset = &smallpage_cmdset;
979
980         /* set info fields needed to __readid */
981         info->flash_info = &default_flash;
982         info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
983         info->reg_ndcr = ndcr;
984
985         if (__readid(info, &id))
986                 return -ENODEV;
987
988         /* Lookup the flash id */
989         id = (id >> 8) & 0xff;          /* device id is byte 2 */
990         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
991                 if (id == nand_flash_ids[i].id) {
992                         type =  &nand_flash_ids[i];
993                         break;
994                 }
995         }
996
997         if (!type)
998                 return -ENODEV;
999
1000         /* fill the missing flash information */
1001         i = __ffs(default_flash.page_per_block * default_flash.page_size);
1002         default_flash.num_blocks = type->chipsize << (20 - i);
1003
1004         info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
1005
1006         /* calculate addressing information */
1007         info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
1008
1009         if (default_flash.num_blocks * default_flash.page_per_block > 65536)
1010                 info->row_addr_cycles = 3;
1011         else
1012                 info->row_addr_cycles = 2;
1013
1014         pxa3xx_nand_detect_timing(info, &default_timing);
1015         default_flash.timing = &default_timing;
1016
1017         return 0;
1018 }
1019
1020 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
1021                                     const struct pxa3xx_nand_platform_data *pdata)
1022 {
1023         const struct pxa3xx_nand_flash *f;
1024         uint32_t id = -1;
1025         int i;
1026
1027         if (pdata->keep_config)
1028                 if (pxa3xx_nand_detect_config(info) == 0)
1029                         return 0;
1030
1031         for (i = 0; i<pdata->num_flash; ++i) {
1032                 f = pdata->flash + i;
1033
1034                 if (pxa3xx_nand_config_flash(info, f))
1035                         continue;
1036
1037                 if (__readid(info, &id))
1038                         continue;
1039
1040                 if (id == f->chip_id)
1041                         return 0;
1042         }
1043
1044 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
1045         for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
1046
1047                 f = builtin_flash_types[i];
1048
1049                 if (pxa3xx_nand_config_flash(info, f))
1050                         continue;
1051
1052                 if (__readid(info, &id))
1053                         continue;
1054
1055                 if (id == f->chip_id)
1056                         return 0;
1057         }
1058 #endif
1059
1060         dev_warn(&info->pdev->dev,
1061                  "failed to detect configured nand flash; found %04x instead of\n",
1062                  id);
1063         return -ENODEV;
1064 }
1065
1066 /* the maximum possible buffer size for large page with OOB data
1067  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
1068  * data buffer and the DMA descriptor
1069  */
1070 #define MAX_BUFF_SIZE   PAGE_SIZE
1071
1072 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1073 {
1074         struct platform_device *pdev = info->pdev;
1075         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
1076
1077         if (use_dma == 0) {
1078                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
1079                 if (info->data_buff == NULL)
1080                         return -ENOMEM;
1081                 return 0;
1082         }
1083
1084         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
1085                                 &info->data_buff_phys, GFP_KERNEL);
1086         if (info->data_buff == NULL) {
1087                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
1088                 return -ENOMEM;
1089         }
1090
1091         info->data_buff_size = MAX_BUFF_SIZE;
1092         info->data_desc = (void *)info->data_buff + data_desc_offset;
1093         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
1094
1095         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
1096                                 pxa3xx_nand_data_dma_irq, info);
1097         if (info->data_dma_ch < 0) {
1098                 dev_err(&pdev->dev, "failed to request data dma\n");
1099                 dma_free_coherent(&pdev->dev, info->data_buff_size,
1100                                 info->data_buff, info->data_buff_phys);
1101                 return info->data_dma_ch;
1102         }
1103
1104         return 0;
1105 }
1106
1107 static struct nand_ecclayout hw_smallpage_ecclayout = {
1108         .eccbytes = 6,
1109         .eccpos = {8, 9, 10, 11, 12, 13 },
1110         .oobfree = { {2, 6} }
1111 };
1112
1113 static struct nand_ecclayout hw_largepage_ecclayout = {
1114         .eccbytes = 24,
1115         .eccpos = {
1116                 40, 41, 42, 43, 44, 45, 46, 47,
1117                 48, 49, 50, 51, 52, 53, 54, 55,
1118                 56, 57, 58, 59, 60, 61, 62, 63},
1119         .oobfree = { {2, 38} }
1120 };
1121
1122 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1123                                  struct pxa3xx_nand_info *info)
1124 {
1125         const struct pxa3xx_nand_flash *f = info->flash_info;
1126         struct nand_chip *this = &info->nand_chip;
1127
1128         this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
1129
1130         this->waitfunc          = pxa3xx_nand_waitfunc;
1131         this->select_chip       = pxa3xx_nand_select_chip;
1132         this->dev_ready         = pxa3xx_nand_dev_ready;
1133         this->cmdfunc           = pxa3xx_nand_cmdfunc;
1134         this->read_word         = pxa3xx_nand_read_word;
1135         this->read_byte         = pxa3xx_nand_read_byte;
1136         this->read_buf          = pxa3xx_nand_read_buf;
1137         this->write_buf         = pxa3xx_nand_write_buf;
1138         this->verify_buf        = pxa3xx_nand_verify_buf;
1139
1140         this->ecc.mode          = NAND_ECC_HW;
1141         this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
1142         this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
1143         this->ecc.correct       = pxa3xx_nand_ecc_correct;
1144         this->ecc.size          = f->page_size;
1145
1146         if (f->page_size == 2048)
1147                 this->ecc.layout = &hw_largepage_ecclayout;
1148         else
1149                 this->ecc.layout = &hw_smallpage_ecclayout;
1150
1151         this->chip_delay = 25;
1152 }
1153
1154 static int pxa3xx_nand_probe(struct platform_device *pdev)
1155 {
1156         struct pxa3xx_nand_platform_data *pdata;
1157         struct pxa3xx_nand_info *info;
1158         struct nand_chip *this;
1159         struct mtd_info *mtd;
1160         struct resource *r;
1161         int ret = 0, irq;
1162
1163         pdata = pdev->dev.platform_data;
1164
1165         if (!pdata) {
1166                 dev_err(&pdev->dev, "no platform data defined\n");
1167                 return -ENODEV;
1168         }
1169
1170         mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1171                         GFP_KERNEL);
1172         if (!mtd) {
1173                 dev_err(&pdev->dev, "failed to allocate memory\n");
1174                 return -ENOMEM;
1175         }
1176
1177         info = (struct pxa3xx_nand_info *)(&mtd[1]);
1178         info->pdev = pdev;
1179
1180         this = &info->nand_chip;
1181         mtd->priv = info;
1182         mtd->owner = THIS_MODULE;
1183
1184         info->clk = clk_get(&pdev->dev, NULL);
1185         if (IS_ERR(info->clk)) {
1186                 dev_err(&pdev->dev, "failed to get nand clock\n");
1187                 ret = PTR_ERR(info->clk);
1188                 goto fail_free_mtd;
1189         }
1190         clk_enable(info->clk);
1191
1192         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1193         if (r == NULL) {
1194                 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1195                 ret = -ENXIO;
1196                 goto fail_put_clk;
1197         }
1198         info->drcmr_dat = r->start;
1199
1200         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1201         if (r == NULL) {
1202                 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1203                 ret = -ENXIO;
1204                 goto fail_put_clk;
1205         }
1206         info->drcmr_cmd = r->start;
1207
1208         irq = platform_get_irq(pdev, 0);
1209         if (irq < 0) {
1210                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1211                 ret = -ENXIO;
1212                 goto fail_put_clk;
1213         }
1214
1215         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1216         if (r == NULL) {
1217                 dev_err(&pdev->dev, "no IO memory resource defined\n");
1218                 ret = -ENODEV;
1219                 goto fail_put_clk;
1220         }
1221
1222         r = request_mem_region(r->start, resource_size(r), pdev->name);
1223         if (r == NULL) {
1224                 dev_err(&pdev->dev, "failed to request memory resource\n");
1225                 ret = -EBUSY;
1226                 goto fail_put_clk;
1227         }
1228
1229         info->mmio_base = ioremap(r->start, resource_size(r));
1230         if (info->mmio_base == NULL) {
1231                 dev_err(&pdev->dev, "ioremap() failed\n");
1232                 ret = -ENODEV;
1233                 goto fail_free_res;
1234         }
1235
1236         ret = pxa3xx_nand_init_buff(info);
1237         if (ret)
1238                 goto fail_free_io;
1239
1240         ret = request_irq(IRQ_NAND, pxa3xx_nand_irq, IRQF_DISABLED,
1241                                 pdev->name, info);
1242         if (ret < 0) {
1243                 dev_err(&pdev->dev, "failed to request IRQ\n");
1244                 goto fail_free_buf;
1245         }
1246
1247         ret = pxa3xx_nand_detect_flash(info, pdata);
1248         if (ret) {
1249                 dev_err(&pdev->dev, "failed to detect flash\n");
1250                 ret = -ENODEV;
1251                 goto fail_free_irq;
1252         }
1253
1254         pxa3xx_nand_init_mtd(mtd, info);
1255
1256         platform_set_drvdata(pdev, mtd);
1257
1258         if (nand_scan(mtd, 1)) {
1259                 dev_err(&pdev->dev, "failed to scan nand\n");
1260                 ret = -ENXIO;
1261                 goto fail_free_irq;
1262         }
1263
1264         return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1265
1266 fail_free_irq:
1267         free_irq(IRQ_NAND, info);
1268 fail_free_buf:
1269         if (use_dma) {
1270                 pxa_free_dma(info->data_dma_ch);
1271                 dma_free_coherent(&pdev->dev, info->data_buff_size,
1272                         info->data_buff, info->data_buff_phys);
1273         } else
1274                 kfree(info->data_buff);
1275 fail_free_io:
1276         iounmap(info->mmio_base);
1277 fail_free_res:
1278         release_mem_region(r->start, resource_size(r));
1279 fail_put_clk:
1280         clk_disable(info->clk);
1281         clk_put(info->clk);
1282 fail_free_mtd:
1283         kfree(mtd);
1284         return ret;
1285 }
1286
1287 static int pxa3xx_nand_remove(struct platform_device *pdev)
1288 {
1289         struct mtd_info *mtd = platform_get_drvdata(pdev);
1290         struct pxa3xx_nand_info *info = mtd->priv;
1291         struct resource *r;
1292
1293         platform_set_drvdata(pdev, NULL);
1294
1295         del_mtd_device(mtd);
1296         del_mtd_partitions(mtd);
1297         free_irq(IRQ_NAND, info);
1298         if (use_dma) {
1299                 pxa_free_dma(info->data_dma_ch);
1300                 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1301                                 info->data_buff, info->data_buff_phys);
1302         } else
1303                 kfree(info->data_buff);
1304
1305         iounmap(info->mmio_base);
1306         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1307         release_mem_region(r->start, resource_size(r));
1308
1309         clk_disable(info->clk);
1310         clk_put(info->clk);
1311
1312         kfree(mtd);
1313         return 0;
1314 }
1315
1316 #ifdef CONFIG_PM
1317 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1318 {
1319         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1320         struct pxa3xx_nand_info *info = mtd->priv;
1321
1322         if (info->state != STATE_READY) {
1323                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1324                 return -EAGAIN;
1325         }
1326
1327         return 0;
1328 }
1329
1330 static int pxa3xx_nand_resume(struct platform_device *pdev)
1331 {
1332         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1333         struct pxa3xx_nand_info *info = mtd->priv;
1334
1335         clk_enable(info->clk);
1336
1337         return pxa3xx_nand_config_flash(info, info->flash_info);
1338 }
1339 #else
1340 #define pxa3xx_nand_suspend     NULL
1341 #define pxa3xx_nand_resume      NULL
1342 #endif
1343
1344 static struct platform_driver pxa3xx_nand_driver = {
1345         .driver = {
1346                 .name   = "pxa3xx-nand",
1347         },
1348         .probe          = pxa3xx_nand_probe,
1349         .remove         = pxa3xx_nand_remove,
1350         .suspend        = pxa3xx_nand_suspend,
1351         .resume         = pxa3xx_nand_resume,
1352 };
1353
1354 static int __init pxa3xx_nand_init(void)
1355 {
1356         return platform_driver_register(&pxa3xx_nand_driver);
1357 }
1358 module_init(pxa3xx_nand_init);
1359
1360 static void __exit pxa3xx_nand_exit(void)
1361 {
1362         platform_driver_unregister(&pxa3xx_nand_driver);
1363 }
1364 module_exit(pxa3xx_nand_exit);
1365
1366 MODULE_LICENSE("GPL");
1367 MODULE_DESCRIPTION("PXA3xx NAND controller driver");