Merge branches 'release' and 'ppc-workaround' into release
[linux-2.6] / arch / powerpc / boot / dts / mpc8544ds.dts
1 /*
2  * MPC8544 DS Device Tree Source
3  *
4  * Copyright 2007 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 / {
13         model = "MPC8544DS";
14         compatible = "MPC8544DS", "MPC85xxDS";
15         #address-cells = <1>;
16         #size-cells = <1>;
17
18         aliases {
19                 ethernet0 = &enet0;
20                 ethernet1 = &enet1;
21                 serial0 = &serial0;
22                 serial1 = &serial1;
23                 pci0 = &pci0;
24                 pci1 = &pci1;
25                 pci2 = &pci2;
26                 pci3 = &pci3;
27         };
28
29         cpus {
30                 #cpus = <1>;
31                 #address-cells = <1>;
32                 #size-cells = <0>;
33
34                 PowerPC,8544@0 {
35                         device_type = "cpu";
36                         reg = <0>;
37                         d-cache-line-size = <20>;       // 32 bytes
38                         i-cache-line-size = <20>;       // 32 bytes
39                         d-cache-size = <8000>;          // L1, 32K
40                         i-cache-size = <8000>;          // L1, 32K
41                         timebase-frequency = <0>;
42                         bus-frequency = <0>;
43                         clock-frequency = <0>;
44                 };
45         };
46
47         memory {
48                 device_type = "memory";
49                 reg = <00000000 00000000>;      // Filled by U-Boot
50         };
51
52         soc8544@e0000000 {
53                 #address-cells = <1>;
54                 #size-cells = <1>;
55                 device_type = "soc";
56
57                 ranges = <00000000 e0000000 00100000>;
58                 reg = <e0000000 00001000>;      // CCSRBAR 1M
59                 bus-frequency = <0>;            // Filled out by uboot.
60
61                 memory-controller@2000 {
62                         compatible = "fsl,8544-memory-controller";
63                         reg = <2000 1000>;
64                         interrupt-parent = <&mpic>;
65                         interrupts = <12 2>;
66                 };
67
68                 l2-cache-controller@20000 {
69                         compatible = "fsl,8544-l2-cache-controller";
70                         reg = <20000 1000>;
71                         cache-line-size = <20>; // 32 bytes
72                         cache-size = <40000>;   // L2, 256K
73                         interrupt-parent = <&mpic>;
74                         interrupts = <10 2>;
75                 };
76
77                 i2c@3000 {
78                         #address-cells = <1>;
79                         #size-cells = <0>;
80                         cell-index = <0>;
81                         compatible = "fsl-i2c";
82                         reg = <3000 100>;
83                         interrupts = <2b 2>;
84                         interrupt-parent = <&mpic>;
85                         dfsrr;
86                 };
87
88                 i2c@3100 {
89                         #address-cells = <1>;
90                         #size-cells = <0>;
91                         cell-index = <1>;
92                         compatible = "fsl-i2c";
93                         reg = <3100 100>;
94                         interrupts = <2b 2>;
95                         interrupt-parent = <&mpic>;
96                         dfsrr;
97                 };
98
99                 mdio@24520 {
100                         #address-cells = <1>;
101                         #size-cells = <0>;
102                         compatible = "fsl,gianfar-mdio";
103                         reg = <24520 20>;
104
105                         phy0: ethernet-phy@0 {
106                                 interrupt-parent = <&mpic>;
107                                 interrupts = <a 1>;
108                                 reg = <0>;
109                                 device_type = "ethernet-phy";
110                         };
111                         phy1: ethernet-phy@1 {
112                                 interrupt-parent = <&mpic>;
113                                 interrupts = <a 1>;
114                                 reg = <1>;
115                                 device_type = "ethernet-phy";
116                         };
117                 };
118
119                 enet0: ethernet@24000 {
120                         cell-index = <0>;
121                         device_type = "network";
122                         model = "TSEC";
123                         compatible = "gianfar";
124                         reg = <24000 1000>;
125                         local-mac-address = [ 00 00 00 00 00 00 ];
126                         interrupts = <1d 2 1e 2 22 2>;
127                         interrupt-parent = <&mpic>;
128                         phy-handle = <&phy0>;
129                         phy-connection-type = "rgmii-id";
130                 };
131
132                 enet1: ethernet@26000 {
133                         cell-index = <1>;
134                         device_type = "network";
135                         model = "TSEC";
136                         compatible = "gianfar";
137                         reg = <26000 1000>;
138                         local-mac-address = [ 00 00 00 00 00 00 ];
139                         interrupts = <1f 2 20 2 21 2>;
140                         interrupt-parent = <&mpic>;
141                         phy-handle = <&phy1>;
142                         phy-connection-type = "rgmii-id";
143                 };
144
145                 serial0: serial@4500 {
146                         cell-index = <0>;
147                         device_type = "serial";
148                         compatible = "ns16550";
149                         reg = <4500 100>;
150                         clock-frequency = <0>;
151                         interrupts = <2a 2>;
152                         interrupt-parent = <&mpic>;
153                 };
154
155                 serial1: serial@4600 {
156                         cell-index = <1>;
157                         device_type = "serial";
158                         compatible = "ns16550";
159                         reg = <4600 100>;
160                         clock-frequency = <0>;
161                         interrupts = <2a 2>;
162                         interrupt-parent = <&mpic>;
163                 };
164
165                 global-utilities@e0000 {        //global utilities block
166                         compatible = "fsl,mpc8548-guts";
167                         reg = <e0000 1000>;
168                         fsl,has-rstcr;
169                 };
170
171                 mpic: pic@40000 {
172                         clock-frequency = <0>;
173                         interrupt-controller;
174                         #address-cells = <0>;
175                         #interrupt-cells = <2>;
176                         reg = <40000 40000>;
177                         compatible = "chrp,open-pic";
178                         device_type = "open-pic";
179                         big-endian;
180                 };
181         };
182
183         pci0: pci@e0008000 {
184                 cell-index = <0>;
185                 compatible = "fsl,mpc8540-pci";
186                 device_type = "pci";
187                 interrupt-map-mask = <f800 0 0 7>;
188                 interrupt-map = <
189
190                         /* IDSEL 0x11 J17 Slot 1 */
191                         8800 0 0 1 &mpic 2 1
192                         8800 0 0 2 &mpic 3 1
193                         8800 0 0 3 &mpic 4 1
194                         8800 0 0 4 &mpic 1 1
195
196                         /* IDSEL 0x12 J16 Slot 2 */
197
198                         9000 0 0 1 &mpic 3 1
199                         9000 0 0 2 &mpic 4 1
200                         9000 0 0 3 &mpic 2 1
201                         9000 0 0 4 &mpic 1 1>;
202
203                 interrupt-parent = <&mpic>;
204                 interrupts = <18 2>;
205                 bus-range = <0 ff>;
206                 ranges = <02000000 0 c0000000 c0000000 0 20000000
207                           01000000 0 00000000 e1000000 0 00010000>;
208                 clock-frequency = <3f940aa>;
209                 #interrupt-cells = <1>;
210                 #size-cells = <2>;
211                 #address-cells = <3>;
212                 reg = <e0008000 1000>;
213         };
214
215         pci1: pcie@e0009000 {
216                 cell-index = <1>;
217                 compatible = "fsl,mpc8548-pcie";
218                 device_type = "pci";
219                 #interrupt-cells = <1>;
220                 #size-cells = <2>;
221                 #address-cells = <3>;
222                 reg = <e0009000 1000>;
223                 bus-range = <0 ff>;
224                 ranges = <02000000 0 80000000 80000000 0 20000000
225                           01000000 0 00000000 e1010000 0 00010000>;
226                 clock-frequency = <1fca055>;
227                 interrupt-parent = <&mpic>;
228                 interrupts = <1a 2>;
229                 interrupt-map-mask = <f800 0 0 7>;
230                 interrupt-map = <
231                         /* IDSEL 0x0 */
232                         0000 0 0 1 &mpic 4 1
233                         0000 0 0 2 &mpic 5 1
234                         0000 0 0 3 &mpic 6 1
235                         0000 0 0 4 &mpic 7 1
236                         >;
237                 pcie@0 {
238                         reg = <0 0 0 0 0>;
239                         #size-cells = <2>;
240                         #address-cells = <3>;
241                         device_type = "pci";
242                         ranges = <02000000 0 80000000
243                                   02000000 0 80000000
244                                   0 20000000
245
246                                   01000000 0 00000000
247                                   01000000 0 00000000
248                                   0 00010000>;
249                 };
250         };
251
252         pci2: pcie@e000a000 {
253                 cell-index = <2>;
254                 compatible = "fsl,mpc8548-pcie";
255                 device_type = "pci";
256                 #interrupt-cells = <1>;
257                 #size-cells = <2>;
258                 #address-cells = <3>;
259                 reg = <e000a000 1000>;
260                 bus-range = <0 ff>;
261                 ranges = <02000000 0 a0000000 a0000000 0 10000000
262                           01000000 0 00000000 e1020000 0 00010000>;
263                 clock-frequency = <1fca055>;
264                 interrupt-parent = <&mpic>;
265                 interrupts = <19 2>;
266                 interrupt-map-mask = <f800 0 0 7>;
267                 interrupt-map = <
268                         /* IDSEL 0x0 */
269                         0000 0 0 1 &mpic 0 1
270                         0000 0 0 2 &mpic 1 1
271                         0000 0 0 3 &mpic 2 1
272                         0000 0 0 4 &mpic 3 1
273                         >;
274                 pcie@0 {
275                         reg = <0 0 0 0 0>;
276                         #size-cells = <2>;
277                         #address-cells = <3>;
278                         device_type = "pci";
279                         ranges = <02000000 0 a0000000
280                                   02000000 0 a0000000
281                                   0 10000000
282
283                                   01000000 0 00000000
284                                   01000000 0 00000000
285                                   0 00010000>;
286                 };
287         };
288
289         pci3: pcie@e000b000 {
290                 cell-index = <3>;
291                 compatible = "fsl,mpc8548-pcie";
292                 device_type = "pci";
293                 #interrupt-cells = <1>;
294                 #size-cells = <2>;
295                 #address-cells = <3>;
296                 reg = <e000b000 1000>;
297                 bus-range = <0 ff>;
298                 ranges = <02000000 0 b0000000 b0000000 0 00100000
299                           01000000 0 00000000 b0100000 0 00100000>;
300                 clock-frequency = <1fca055>;
301                 interrupt-parent = <&mpic>;
302                 interrupts = <1b 2>;
303                 interrupt-map-mask = <ff00 0 0 1>;
304                 interrupt-map = <
305                         // IDSEL 0x1c  USB
306                         e000 0 0 1 &i8259 c 2
307                         e100 0 0 2 &i8259 9 2
308                         e200 0 0 3 &i8259 a 2
309                         e300 0 0 4 &i8259 b 2
310
311                         // IDSEL 0x1d  Audio
312                         e800 0 0 1 &i8259 6 2
313
314                         // IDSEL 0x1e Legacy
315                         f000 0 0 1 &i8259 7 2
316                         f100 0 0 1 &i8259 7 2
317
318                         // IDSEL 0x1f IDE/SATA
319                         f800 0 0 1 &i8259 e 2
320                         f900 0 0 1 &i8259 5 2
321                 >;
322
323                 pcie@0 {
324                         reg = <0 0 0 0 0>;
325                         #size-cells = <2>;
326                         #address-cells = <3>;
327                         device_type = "pci";
328                         ranges = <02000000 0 b0000000
329                                   02000000 0 b0000000
330                                   0 00100000
331
332                                   01000000 0 00000000
333                                   01000000 0 00000000
334                                   0 00100000>;
335
336                         uli1575@0 {
337                                 reg = <0 0 0 0 0>;
338                                 #size-cells = <2>;
339                                 #address-cells = <3>;
340                                 ranges = <02000000 0 b0000000
341                                           02000000 0 b0000000
342                                           0 00100000
343
344                                           01000000 0 00000000
345                                           01000000 0 00000000
346                                           0 00100000>;
347                                 isa@1e {
348                                         device_type = "isa";
349                                         #interrupt-cells = <2>;
350                                         #size-cells = <1>;
351                                         #address-cells = <2>;
352                                         reg = <f000 0 0 0 0>;
353                                         ranges = <1 0
354                                                   01000000 0 0
355                                                   00001000>;
356                                         interrupt-parent = <&i8259>;
357
358                                         i8259: interrupt-controller@20 {
359                                                 reg = <1 20 2
360                                                        1 a0 2
361                                                        1 4d0 2>;
362                                                 interrupt-controller;
363                                                 device_type = "interrupt-controller";
364                                                 #address-cells = <0>;
365                                                 #interrupt-cells = <2>;
366                                                 compatible = "chrp,iic";
367                                                 interrupts = <9 2>;
368                                                 interrupt-parent = <&mpic>;
369                                         };
370
371                                         i8042@60 {
372                                                 #size-cells = <0>;
373                                                 #address-cells = <1>;
374                                                 reg = <1 60 1 1 64 1>;
375                                                 interrupts = <1 3 c 3>;
376                                                 interrupt-parent = <&i8259>;
377
378                                                 keyboard@0 {
379                                                         reg = <0>;
380                                                         compatible = "pnpPNP,303";
381                                                 };
382
383                                                 mouse@1 {
384                                                         reg = <1>;
385                                                         compatible = "pnpPNP,f03";
386                                                 };
387                                         };
388
389                                         rtc@70 {
390                                                 compatible = "pnpPNP,b00";
391                                                 reg = <1 70 2>;
392                                         };
393
394                                         gpio@400 {
395                                                 reg = <1 400 80>;
396                                         };
397                                 };
398                         };
399                 };
400         };
401 };