Merge commit 's3c-iis-header' into HEAD
[linux-2.6] / drivers / serial / jsm / jsm_neo.c
1 /************************************************************************
2  * Copyright 2003 Digi International (www.digi.com)
3  *
4  * Copyright (C) 2004 IBM Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14  * PURPOSE.  See the GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
19  * MA  02111-1307, USA.
20  *
21  * Contact Information:
22  * Scott H Kilau <Scott_Kilau@digi.com>
23  * Wendy Xiong   <wendyx@us.ibm.com>
24  *
25  ***********************************************************************/
26 #include <linux/delay.h>        /* For udelay */
27 #include <linux/serial_reg.h>   /* For the various UART offsets */
28 #include <linux/tty.h>
29 #include <linux/pci.h>
30 #include <asm/io.h>
31
32 #include "jsm.h"                /* Driver main header file */
33
34 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
35
36 /*
37  * This function allows calls to ensure that all outstanding
38  * PCI writes have been completed, by doing a PCI read against
39  * a non-destructive, read-only location on the Neo card.
40  *
41  * In this case, we are reading the DVID (Read-only Device Identification)
42  * value of the Neo card.
43  */
44 static inline void neo_pci_posting_flush(struct jsm_board *bd)
45 {
46       readb(bd->re_map_membase + 0x8D);
47 }
48
49 static void neo_set_cts_flow_control(struct jsm_channel *ch)
50 {
51         u8 ier, efr;
52         ier = readb(&ch->ch_neo_uart->ier);
53         efr = readb(&ch->ch_neo_uart->efr);
54
55         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
56
57         /* Turn on auto CTS flow control */
58         ier |= (UART_17158_IER_CTSDSR);
59         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
60
61         /* Turn off auto Xon flow control */
62         efr &= ~(UART_17158_EFR_IXON);
63
64         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
65         writeb(0, &ch->ch_neo_uart->efr);
66
67         /* Turn on UART enhanced bits */
68         writeb(efr, &ch->ch_neo_uart->efr);
69
70         /* Turn on table D, with 8 char hi/low watermarks */
71         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
72
73         /* Feed the UART our trigger levels */
74         writeb(8, &ch->ch_neo_uart->tfifo);
75         ch->ch_t_tlevel = 8;
76
77         writeb(ier, &ch->ch_neo_uart->ier);
78 }
79
80 static void neo_set_rts_flow_control(struct jsm_channel *ch)
81 {
82         u8 ier, efr;
83         ier = readb(&ch->ch_neo_uart->ier);
84         efr = readb(&ch->ch_neo_uart->efr);
85
86         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
87
88         /* Turn on auto RTS flow control */
89         ier |= (UART_17158_IER_RTSDTR);
90         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
91
92         /* Turn off auto Xoff flow control */
93         ier &= ~(UART_17158_IER_XOFF);
94         efr &= ~(UART_17158_EFR_IXOFF);
95
96         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
97         writeb(0, &ch->ch_neo_uart->efr);
98
99         /* Turn on UART enhanced bits */
100         writeb(efr, &ch->ch_neo_uart->efr);
101
102         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
103         ch->ch_r_watermark = 4;
104
105         writeb(56, &ch->ch_neo_uart->rfifo);
106         ch->ch_r_tlevel = 56;
107
108         writeb(ier, &ch->ch_neo_uart->ier);
109
110         /*
111          * From the Neo UART spec sheet:
112          * The auto RTS/DTR function must be started by asserting
113          * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
114          * it is enabled.
115          */
116         ch->ch_mostat |= (UART_MCR_RTS);
117 }
118
119
120 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
121 {
122         u8 ier, efr;
123         ier = readb(&ch->ch_neo_uart->ier);
124         efr = readb(&ch->ch_neo_uart->efr);
125
126         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
127
128         /* Turn off auto CTS flow control */
129         ier &= ~(UART_17158_IER_CTSDSR);
130         efr &= ~(UART_17158_EFR_CTSDSR);
131
132         /* Turn on auto Xon flow control */
133         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
134
135         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136         writeb(0, &ch->ch_neo_uart->efr);
137
138         /* Turn on UART enhanced bits */
139         writeb(efr, &ch->ch_neo_uart->efr);
140
141         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
142         ch->ch_r_watermark = 4;
143
144         writeb(32, &ch->ch_neo_uart->rfifo);
145         ch->ch_r_tlevel = 32;
146
147         /* Tell UART what start/stop chars it should be looking for */
148         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
149         writeb(0, &ch->ch_neo_uart->xonchar2);
150
151         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
152         writeb(0, &ch->ch_neo_uart->xoffchar2);
153
154         writeb(ier, &ch->ch_neo_uart->ier);
155 }
156
157 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
158 {
159         u8 ier, efr;
160         ier = readb(&ch->ch_neo_uart->ier);
161         efr = readb(&ch->ch_neo_uart->efr);
162
163         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
164
165         /* Turn off auto RTS flow control */
166         ier &= ~(UART_17158_IER_RTSDTR);
167         efr &= ~(UART_17158_EFR_RTSDTR);
168
169         /* Turn on auto Xoff flow control */
170         ier |= (UART_17158_IER_XOFF);
171         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
172
173         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174         writeb(0, &ch->ch_neo_uart->efr);
175
176         /* Turn on UART enhanced bits */
177         writeb(efr, &ch->ch_neo_uart->efr);
178
179         /* Turn on table D, with 8 char hi/low watermarks */
180         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
181
182         writeb(8, &ch->ch_neo_uart->tfifo);
183         ch->ch_t_tlevel = 8;
184
185         /* Tell UART what start/stop chars it should be looking for */
186         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
187         writeb(0, &ch->ch_neo_uart->xonchar2);
188
189         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
190         writeb(0, &ch->ch_neo_uart->xoffchar2);
191
192         writeb(ier, &ch->ch_neo_uart->ier);
193 }
194
195 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
196 {
197         u8 ier, efr;
198         ier = readb(&ch->ch_neo_uart->ier);
199         efr = readb(&ch->ch_neo_uart->efr);
200
201         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
202
203         /* Turn off auto RTS flow control */
204         ier &= ~(UART_17158_IER_RTSDTR);
205         efr &= ~(UART_17158_EFR_RTSDTR);
206
207         /* Turn off auto Xoff flow control */
208         ier &= ~(UART_17158_IER_XOFF);
209         if (ch->ch_c_iflag & IXON)
210                 efr &= ~(UART_17158_EFR_IXOFF);
211         else
212                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
213
214         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
215         writeb(0, &ch->ch_neo_uart->efr);
216
217         /* Turn on UART enhanced bits */
218         writeb(efr, &ch->ch_neo_uart->efr);
219
220         /* Turn on table D, with 8 char hi/low watermarks */
221         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
222
223         ch->ch_r_watermark = 0;
224
225         writeb(16, &ch->ch_neo_uart->tfifo);
226         ch->ch_t_tlevel = 16;
227
228         writeb(16, &ch->ch_neo_uart->rfifo);
229         ch->ch_r_tlevel = 16;
230
231         writeb(ier, &ch->ch_neo_uart->ier);
232 }
233
234 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
235 {
236         u8 ier, efr;
237         ier = readb(&ch->ch_neo_uart->ier);
238         efr = readb(&ch->ch_neo_uart->efr);
239
240         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
241
242         /* Turn off auto CTS flow control */
243         ier &= ~(UART_17158_IER_CTSDSR);
244         efr &= ~(UART_17158_EFR_CTSDSR);
245
246         /* Turn off auto Xon flow control */
247         if (ch->ch_c_iflag & IXOFF)
248                 efr &= ~(UART_17158_EFR_IXON);
249         else
250                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
251
252         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
253         writeb(0, &ch->ch_neo_uart->efr);
254
255         /* Turn on UART enhanced bits */
256         writeb(efr, &ch->ch_neo_uart->efr);
257
258         /* Turn on table D, with 8 char hi/low watermarks */
259         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
260
261         ch->ch_r_watermark = 0;
262
263         writeb(16, &ch->ch_neo_uart->tfifo);
264         ch->ch_t_tlevel = 16;
265
266         writeb(16, &ch->ch_neo_uart->rfifo);
267         ch->ch_r_tlevel = 16;
268
269         writeb(ier, &ch->ch_neo_uart->ier);
270 }
271
272 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
273 {
274
275         /* if hardware flow control is set, then skip this whole thing */
276         if (ch->ch_c_cflag & CRTSCTS)
277                 return;
278
279         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
280
281         /* Tell UART what start/stop chars it should be looking for */
282         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
283         writeb(0, &ch->ch_neo_uart->xonchar2);
284
285         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
286         writeb(0, &ch->ch_neo_uart->xoffchar2);
287 }
288
289 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
290 {
291         int qleft = 0;
292         u8 linestatus = 0;
293         u8 error_mask = 0;
294         int n = 0;
295         int total = 0;
296         u16 head;
297         u16 tail;
298
299         if (!ch)
300                 return;
301
302         /* cache head and tail of queue */
303         head = ch->ch_r_head & RQUEUEMASK;
304         tail = ch->ch_r_tail & RQUEUEMASK;
305
306         /* Get our cached LSR */
307         linestatus = ch->ch_cached_lsr;
308         ch->ch_cached_lsr = 0;
309
310         /* Store how much space we have left in the queue */
311         if ((qleft = tail - head - 1) < 0)
312                 qleft += RQUEUEMASK + 1;
313
314         /*
315          * If the UART is not in FIFO mode, force the FIFO copy to
316          * NOT be run, by setting total to 0.
317          *
318          * On the other hand, if the UART IS in FIFO mode, then ask
319          * the UART to give us an approximation of data it has RX'ed.
320          */
321         if (!(ch->ch_flags & CH_FIFO_ENABLED))
322                 total = 0;
323         else {
324                 total = readb(&ch->ch_neo_uart->rfifo);
325
326                 /*
327                  * EXAR chip bug - RX FIFO COUNT - Fudge factor.
328                  *
329                  * This resolves a problem/bug with the Exar chip that sometimes
330                  * returns a bogus value in the rfifo register.
331                  * The count can be any where from 0-3 bytes "off".
332                  * Bizarre, but true.
333                  */
334                 total -= 3;
335         }
336
337         /*
338          * Finally, bound the copy to make sure we don't overflow
339          * our own queue...
340          * The byte by byte copy loop below this loop this will
341          * deal with the queue overflow possibility.
342          */
343         total = min(total, qleft);
344
345         while (total > 0) {
346                 /*
347                  * Grab the linestatus register, we need to check
348                  * to see if there are any errors in the FIFO.
349                  */
350                 linestatus = readb(&ch->ch_neo_uart->lsr);
351
352                 /*
353                  * Break out if there is a FIFO error somewhere.
354                  * This will allow us to go byte by byte down below,
355                  * finding the exact location of the error.
356                  */
357                 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
358                         break;
359
360                 /* Make sure we don't go over the end of our queue */
361                 n = min(((u32) total), (RQUEUESIZE - (u32) head));
362
363                 /*
364                  * Cut down n even further if needed, this is to fix
365                  * a problem with memcpy_fromio() with the Neo on the
366                  * IBM pSeries platform.
367                  * 15 bytes max appears to be the magic number.
368                  */
369                 n = min((u32) n, (u32) 12);
370
371                 /*
372                  * Since we are grabbing the linestatus register, which
373                  * will reset some bits after our read, we need to ensure
374                  * we don't miss our TX FIFO emptys.
375                  */
376                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
377                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
378
379                 linestatus = 0;
380
381                 /* Copy data from uart to the queue */
382                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
383                 /*
384                  * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
385                  * that all the data currently in the FIFO is free of
386                  * breaks and parity/frame/orun errors.
387                  */
388                 memset(ch->ch_equeue + head, 0, n);
389
390                 /* Add to and flip head if needed */
391                 head = (head + n) & RQUEUEMASK;
392                 total -= n;
393                 qleft -= n;
394                 ch->ch_rxcount += n;
395         }
396
397         /*
398          * Create a mask to determine whether we should
399          * insert the character (if any) into our queue.
400          */
401         if (ch->ch_c_iflag & IGNBRK)
402                 error_mask |= UART_LSR_BI;
403
404         /*
405          * Now cleanup any leftover bytes still in the UART.
406          * Also deal with any possible queue overflow here as well.
407          */
408         while (1) {
409
410                 /*
411                  * Its possible we have a linestatus from the loop above
412                  * this, so we "OR" on any extra bits.
413                  */
414                 linestatus |= readb(&ch->ch_neo_uart->lsr);
415
416                 /*
417                  * If the chip tells us there is no more data pending to
418                  * be read, we can then leave.
419                  * But before we do, cache the linestatus, just in case.
420                  */
421                 if (!(linestatus & UART_LSR_DR)) {
422                         ch->ch_cached_lsr = linestatus;
423                         break;
424                 }
425
426                 /* No need to store this bit */
427                 linestatus &= ~UART_LSR_DR;
428
429                 /*
430                  * Since we are grabbing the linestatus register, which
431                  * will reset some bits after our read, we need to ensure
432                  * we don't miss our TX FIFO emptys.
433                  */
434                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
435                         linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
436                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
437                 }
438
439                 /*
440                  * Discard character if we are ignoring the error mask.
441                  */
442                 if (linestatus & error_mask) {
443                         u8 discard;
444                         linestatus = 0;
445                         memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
446                         continue;
447                 }
448
449                 /*
450                  * If our queue is full, we have no choice but to drop some data.
451                  * The assumption is that HWFLOW or SWFLOW should have stopped
452                  * things way way before we got to this point.
453                  *
454                  * I decided that I wanted to ditch the oldest data first,
455                  * I hope thats okay with everyone? Yes? Good.
456                  */
457                 while (qleft < 1) {
458                         jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
459                                 "Queue full, dropping DATA:%x LSR:%x\n",
460                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
461
462                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
463                         ch->ch_err_overrun++;
464                         qleft++;
465                 }
466
467                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
468                 ch->ch_equeue[head] = (u8) linestatus;
469
470                 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
471                                 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
472
473                 /* Ditch any remaining linestatus value. */
474                 linestatus = 0;
475
476                 /* Add to and flip head if needed */
477                 head = (head + 1) & RQUEUEMASK;
478
479                 qleft--;
480                 ch->ch_rxcount++;
481         }
482
483         /*
484          * Write new final heads to channel structure.
485          */
486         ch->ch_r_head = head & RQUEUEMASK;
487         ch->ch_e_head = head & EQUEUEMASK;
488         jsm_input(ch);
489 }
490
491 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
492 {
493         u16 head;
494         u16 tail;
495         int n;
496         int s;
497         int qlen;
498         u32 len_written = 0;
499
500         if (!ch)
501                 return;
502
503         /* No data to write to the UART */
504         if (ch->ch_w_tail == ch->ch_w_head)
505                 return;
506
507         /* If port is "stopped", don't send any data to the UART */
508         if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
509                 return;
510         /*
511          * If FIFOs are disabled. Send data directly to txrx register
512          */
513         if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
514                 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
515
516                 ch->ch_cached_lsr |= lsrbits;
517                 if (ch->ch_cached_lsr & UART_LSR_THRE) {
518                         ch->ch_cached_lsr &= ~(UART_LSR_THRE);
519
520                         writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
521                         jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
522                                         "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]);
523                         ch->ch_w_tail++;
524                         ch->ch_w_tail &= WQUEUEMASK;
525                         ch->ch_txcount++;
526                 }
527                 return;
528         }
529
530         /*
531          * We have to do it this way, because of the EXAR TXFIFO count bug.
532          */
533         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
534                 return;
535
536         len_written = 0;
537         n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
538
539         /* cache head and tail of queue */
540         head = ch->ch_w_head & WQUEUEMASK;
541         tail = ch->ch_w_tail & WQUEUEMASK;
542         qlen = (head - tail) & WQUEUEMASK;
543
544         /* Find minimum of the FIFO space, versus queue length */
545         n = min(n, qlen);
546
547         while (n > 0) {
548
549                 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
550                 s = min(s, n);
551
552                 if (s <= 0)
553                         break;
554
555                 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
556                 /* Add and flip queue if needed */
557                 tail = (tail + s) & WQUEUEMASK;
558                 n -= s;
559                 ch->ch_txcount += s;
560                 len_written += s;
561         }
562
563         /* Update the final tail */
564         ch->ch_w_tail = tail & WQUEUEMASK;
565
566         if (len_written >= ch->ch_t_tlevel)
567                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
568
569         if (!jsm_tty_write(&ch->uart_port))
570                 uart_write_wakeup(&ch->uart_port);
571 }
572
573 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
574 {
575         u8 msignals = signals;
576
577         jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
578                         "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
579
580         /* Scrub off lower bits. They signify delta's, which I don't care about */
581         /* Keep DDCD and DDSR though */
582         msignals &= 0xf8;
583
584         if (msignals & UART_MSR_DDCD)
585                 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
586         if (msignals & UART_MSR_DDSR)
587                 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
588         if (msignals & UART_MSR_DCD)
589                 ch->ch_mistat |= UART_MSR_DCD;
590         else
591                 ch->ch_mistat &= ~UART_MSR_DCD;
592
593         if (msignals & UART_MSR_DSR)
594                 ch->ch_mistat |= UART_MSR_DSR;
595         else
596                 ch->ch_mistat &= ~UART_MSR_DSR;
597
598         if (msignals & UART_MSR_RI)
599                 ch->ch_mistat |= UART_MSR_RI;
600         else
601                 ch->ch_mistat &= ~UART_MSR_RI;
602
603         if (msignals & UART_MSR_CTS)
604                 ch->ch_mistat |= UART_MSR_CTS;
605         else
606                 ch->ch_mistat &= ~UART_MSR_CTS;
607
608         jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
609                         "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
610                 ch->ch_portnum,
611                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
612                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
613                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
614                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
615                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
616                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
617 }
618
619 /* Make the UART raise any of the output signals we want up */
620 static void neo_assert_modem_signals(struct jsm_channel *ch)
621 {
622         u8 out;
623
624         if (!ch)
625                 return;
626
627         out = ch->ch_mostat;
628
629         writeb(out, &ch->ch_neo_uart->mcr);
630
631         /* flush write operation */
632         neo_pci_posting_flush(ch->ch_bd);
633 }
634
635 /*
636  * Flush the WRITE FIFO on the Neo.
637  *
638  * NOTE: Channel lock MUST be held before calling this function!
639  */
640 static void neo_flush_uart_write(struct jsm_channel *ch)
641 {
642         u8 tmp = 0;
643         int i = 0;
644
645         if (!ch)
646                 return;
647
648         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
649
650         for (i = 0; i < 10; i++) {
651
652                 /* Check to see if the UART feels it completely flushed the FIFO. */
653                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
654                 if (tmp & 4) {
655                         jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
656                                         "Still flushing TX UART... i: %d\n", i);
657                         udelay(10);
658                 }
659                 else
660                         break;
661         }
662
663         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
664 }
665
666
667 /*
668  * Flush the READ FIFO on the Neo.
669  *
670  * NOTE: Channel lock MUST be held before calling this function!
671  */
672 static void neo_flush_uart_read(struct jsm_channel *ch)
673 {
674         u8 tmp = 0;
675         int i = 0;
676
677         if (!ch)
678                 return;
679
680         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
681
682         for (i = 0; i < 10; i++) {
683
684                 /* Check to see if the UART feels it completely flushed the FIFO. */
685                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
686                 if (tmp & 2) {
687                         jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
688                                         "Still flushing RX UART... i: %d\n", i);
689                         udelay(10);
690                 }
691                 else
692                         break;
693         }
694 }
695
696 /*
697  * No locks are assumed to be held when calling this function.
698  */
699 static void neo_clear_break(struct jsm_channel *ch, int force)
700 {
701         unsigned long lock_flags;
702
703         spin_lock_irqsave(&ch->ch_lock, lock_flags);
704
705         /* Turn break off, and unset some variables */
706         if (ch->ch_flags & CH_BREAK_SENDING) {
707                 u8 temp = readb(&ch->ch_neo_uart->lcr);
708                 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
709
710                 ch->ch_flags &= ~(CH_BREAK_SENDING);
711                 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
712                                 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
713
714                 /* flush write operation */
715                 neo_pci_posting_flush(ch->ch_bd);
716         }
717         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
718 }
719
720 /*
721  * Parse the ISR register.
722  */
723 static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
724 {
725         struct jsm_channel *ch;
726         u8 isr;
727         u8 cause;
728         unsigned long lock_flags;
729
730         if (!brd)
731                 return;
732
733         if (port > brd->maxports)
734                 return;
735
736         ch = brd->channels[port];
737         if (!ch)
738                 return;
739
740         /* Here we try to figure out what caused the interrupt to happen */
741         while (1) {
742
743                 isr = readb(&ch->ch_neo_uart->isr_fcr);
744
745                 /* Bail if no pending interrupt */
746                 if (isr & UART_IIR_NO_INT)
747                         break;
748
749                 /*
750                  * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
751                  */
752                 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
753
754                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
755                                 "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
756
757                 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
758                         /* Read data from uart -> queue */
759                         neo_copy_data_from_uart_to_queue(ch);
760
761                         /* Call our tty layer to enforce queue flow control if needed. */
762                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
763                         jsm_check_queue_flow_control(ch);
764                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
765                 }
766
767                 if (isr & UART_IIR_THRI) {
768                         /* Transfer data (if any) from Write Queue -> UART. */
769                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
770                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
771                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
772                         neo_copy_data_from_queue_to_uart(ch);
773                 }
774
775                 if (isr & UART_17158_IIR_XONXOFF) {
776                         cause = readb(&ch->ch_neo_uart->xoffchar1);
777
778                         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
779                                         "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
780
781                         /*
782                          * Since the UART detected either an XON or
783                          * XOFF match, we need to figure out which
784                          * one it was, so we can suspend or resume data flow.
785                          */
786                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
787                         if (cause == UART_17158_XON_DETECT) {
788                                 /* Is output stopped right now, if so, resume it */
789                                 if (brd->channels[port]->ch_flags & CH_STOP) {
790                                         ch->ch_flags &= ~(CH_STOP);
791                                 }
792                                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
793                                                 "Port %d. XON detected in incoming data\n", port);
794                         }
795                         else if (cause == UART_17158_XOFF_DETECT) {
796                                 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
797                                         ch->ch_flags |= CH_STOP;
798                                         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
799                                                         "Setting CH_STOP\n");
800                                 }
801                                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
802                                                 "Port: %d. XOFF detected in incoming data\n", port);
803                         }
804                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
805                 }
806
807                 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
808                         /*
809                          * If we get here, this means the hardware is doing auto flow control.
810                          * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
811                          */
812                         cause = readb(&ch->ch_neo_uart->mcr);
813
814                         /* Which pin is doing auto flow? RTS or DTR? */
815                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
816                         if ((cause & 0x4) == 0) {
817                                 if (cause & UART_MCR_RTS)
818                                         ch->ch_mostat |= UART_MCR_RTS;
819                                 else
820                                         ch->ch_mostat &= ~(UART_MCR_RTS);
821                         } else {
822                                 if (cause & UART_MCR_DTR)
823                                         ch->ch_mostat |= UART_MCR_DTR;
824                                 else
825                                         ch->ch_mostat &= ~(UART_MCR_DTR);
826                         }
827                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
828                 }
829
830                 /* Parse any modem signal changes */
831                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
832                                 "MOD_STAT: sending to parse_modem_sigs\n");
833                 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
834         }
835 }
836
837 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
838 {
839         struct jsm_channel *ch;
840         int linestatus;
841         unsigned long lock_flags;
842
843         if (!brd)
844                 return;
845
846         if (port > brd->maxports)
847                 return;
848
849         ch = brd->channels[port];
850         if (!ch)
851                 return;
852
853         linestatus = readb(&ch->ch_neo_uart->lsr);
854
855         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
856                         "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
857
858         ch->ch_cached_lsr |= linestatus;
859
860         if (ch->ch_cached_lsr & UART_LSR_DR) {
861                 /* Read data from uart -> queue */
862                 neo_copy_data_from_uart_to_queue(ch);
863                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
864                 jsm_check_queue_flow_control(ch);
865                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
866         }
867
868         /*
869          * This is a special flag. It indicates that at least 1
870          * RX error (parity, framing, or break) has happened.
871          * Mark this in our struct, which will tell me that I have
872          *to do the special RX+LSR read for this FIFO load.
873          */
874         if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
875                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
876                         "%s:%d Port: %d Got an RX error, need to parse LSR\n",
877                         __FILE__, __LINE__, port);
878
879         /*
880          * The next 3 tests should *NOT* happen, as the above test
881          * should encapsulate all 3... At least, thats what Exar says.
882          */
883
884         if (linestatus & UART_LSR_PE) {
885                 ch->ch_err_parity++;
886                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
887                         "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
888         }
889
890         if (linestatus & UART_LSR_FE) {
891                 ch->ch_err_frame++;
892                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
893                         "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
894         }
895
896         if (linestatus & UART_LSR_BI) {
897                 ch->ch_err_break++;
898                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
899                         "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
900         }
901
902         if (linestatus & UART_LSR_OE) {
903                 /*
904                  * Rx Oruns. Exar says that an orun will NOT corrupt
905                  * the FIFO. It will just replace the holding register
906                  * with this new data byte. So basically just ignore this.
907                  * Probably we should eventually have an orun stat in our driver...
908                  */
909                 ch->ch_err_overrun++;
910                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
911                         "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
912         }
913
914         if (linestatus & UART_LSR_THRE) {
915                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
916                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
917                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
918
919                 /* Transfer data (if any) from Write Queue -> UART. */
920                 neo_copy_data_from_queue_to_uart(ch);
921         }
922         else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
923                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
924                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
925                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
926
927                 /* Transfer data (if any) from Write Queue -> UART. */
928                 neo_copy_data_from_queue_to_uart(ch);
929         }
930 }
931
932 /*
933  * neo_param()
934  * Send any/all changes to the line to the UART.
935  */
936 static void neo_param(struct jsm_channel *ch)
937 {
938         u8 lcr = 0;
939         u8 uart_lcr = 0;
940         u8 ier = 0;
941         u32 baud = 9600;
942         int quot = 0;
943         struct jsm_board *bd;
944
945         bd = ch->ch_bd;
946         if (!bd)
947                 return;
948
949         /*
950          * If baud rate is zero, flush queues, and set mval to drop DTR.
951          */
952         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
953                 ch->ch_r_head = ch->ch_r_tail = 0;
954                 ch->ch_e_head = ch->ch_e_tail = 0;
955                 ch->ch_w_head = ch->ch_w_tail = 0;
956
957                 neo_flush_uart_write(ch);
958                 neo_flush_uart_read(ch);
959
960                 ch->ch_flags |= (CH_BAUD0);
961                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
962                 neo_assert_modem_signals(ch);
963                 ch->ch_old_baud = 0;
964                 return;
965
966         } else if (ch->ch_custom_speed) {
967                         baud = ch->ch_custom_speed;
968                         if (ch->ch_flags & CH_BAUD0)
969                                 ch->ch_flags &= ~(CH_BAUD0);
970         } else {
971                 int i;
972                 unsigned int cflag;
973                 static struct {
974                         unsigned int rate;
975                         unsigned int cflag;
976                 } baud_rates[] = {
977                         { 921600, B921600 },
978                         { 460800, B460800 },
979                         { 230400, B230400 },
980                         { 115200, B115200 },
981                         {  57600, B57600  },
982                         {  38400, B38400  },
983                         {  19200, B19200  },
984                         {   9600, B9600   },
985                         {   4800, B4800   },
986                         {   2400, B2400   },
987                         {   1200, B1200   },
988                         {    600, B600    },
989                         {    300, B300    },
990                         {    200, B200    },
991                         {    150, B150    },
992                         {    134, B134    },
993                         {    110, B110    },
994                         {     75, B75     },
995                         {     50, B50     },
996                 };
997
998                 cflag = C_BAUD(ch->uart_port.info->port.tty);
999                 baud = 9600;
1000                 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
1001                         if (baud_rates[i].cflag == cflag) {
1002                                 baud = baud_rates[i].rate;
1003                                 break;
1004                         }
1005                 }
1006
1007                 if (ch->ch_flags & CH_BAUD0)
1008                         ch->ch_flags &= ~(CH_BAUD0);
1009         }
1010
1011         if (ch->ch_c_cflag & PARENB)
1012                 lcr |= UART_LCR_PARITY;
1013
1014         if (!(ch->ch_c_cflag & PARODD))
1015                 lcr |= UART_LCR_EPAR;
1016
1017         /*
1018          * Not all platforms support mark/space parity,
1019          * so this will hide behind an ifdef.
1020          */
1021 #ifdef CMSPAR
1022         if (ch->ch_c_cflag & CMSPAR)
1023                 lcr |= UART_LCR_SPAR;
1024 #endif
1025
1026         if (ch->ch_c_cflag & CSTOPB)
1027                 lcr |= UART_LCR_STOP;
1028
1029         switch (ch->ch_c_cflag & CSIZE) {
1030                 case CS5:
1031                         lcr |= UART_LCR_WLEN5;
1032                         break;
1033                 case CS6:
1034                         lcr |= UART_LCR_WLEN6;
1035                         break;
1036                 case CS7:
1037                         lcr |= UART_LCR_WLEN7;
1038                         break;
1039                 case CS8:
1040                 default:
1041                         lcr |= UART_LCR_WLEN8;
1042                 break;
1043         }
1044
1045         ier = readb(&ch->ch_neo_uart->ier);
1046         uart_lcr = readb(&ch->ch_neo_uart->lcr);
1047
1048         if (baud == 0)
1049                 baud = 9600;
1050
1051         quot = ch->ch_bd->bd_dividend / baud;
1052
1053         if (quot != 0) {
1054                 ch->ch_old_baud = baud;
1055                 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1056                 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1057                 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1058                 writeb(lcr, &ch->ch_neo_uart->lcr);
1059         }
1060
1061         if (uart_lcr != lcr)
1062                 writeb(lcr, &ch->ch_neo_uart->lcr);
1063
1064         if (ch->ch_c_cflag & CREAD)
1065                 ier |= (UART_IER_RDI | UART_IER_RLSI);
1066
1067         ier |= (UART_IER_THRI | UART_IER_MSI);
1068
1069         writeb(ier, &ch->ch_neo_uart->ier);
1070
1071         /* Set new start/stop chars */
1072         neo_set_new_start_stop_chars(ch);
1073
1074         if (ch->ch_c_cflag & CRTSCTS)
1075                 neo_set_cts_flow_control(ch);
1076         else if (ch->ch_c_iflag & IXON) {
1077                 /* If start/stop is set to disable, then we should disable flow control */
1078                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1079                         neo_set_no_output_flow_control(ch);
1080                 else
1081                         neo_set_ixon_flow_control(ch);
1082         }
1083         else
1084                 neo_set_no_output_flow_control(ch);
1085
1086         if (ch->ch_c_cflag & CRTSCTS)
1087                 neo_set_rts_flow_control(ch);
1088         else if (ch->ch_c_iflag & IXOFF) {
1089                 /* If start/stop is set to disable, then we should disable flow control */
1090                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1091                         neo_set_no_input_flow_control(ch);
1092                 else
1093                         neo_set_ixoff_flow_control(ch);
1094         }
1095         else
1096                 neo_set_no_input_flow_control(ch);
1097         /*
1098          * Adjust the RX FIFO Trigger level if baud is less than 9600.
1099          * Not exactly elegant, but this is needed because of the Exar chip's
1100          * delay on firing off the RX FIFO interrupt on slower baud rates.
1101          */
1102         if (baud < 9600) {
1103                 writeb(1, &ch->ch_neo_uart->rfifo);
1104                 ch->ch_r_tlevel = 1;
1105         }
1106
1107         neo_assert_modem_signals(ch);
1108
1109         /* Get current status of the modem signals now */
1110         neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1111         return;
1112 }
1113
1114 /*
1115  * jsm_neo_intr()
1116  *
1117  * Neo specific interrupt handler.
1118  */
1119 static irqreturn_t neo_intr(int irq, void *voidbrd)
1120 {
1121         struct jsm_board *brd = voidbrd;
1122         struct jsm_channel *ch;
1123         int port = 0;
1124         int type = 0;
1125         int current_port;
1126         u32 tmp;
1127         u32 uart_poll;
1128         unsigned long lock_flags;
1129         unsigned long lock_flags2;
1130         int outofloop_count = 0;
1131
1132         brd->intr_count++;
1133
1134         /* Lock out the slow poller from running on this board. */
1135         spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1136
1137         /*
1138          * Read in "extended" IRQ information from the 32bit Neo register.
1139          * Bits 0-7: What port triggered the interrupt.
1140          * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1141          */
1142         uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1143
1144         jsm_printk(INTR, INFO, &brd->pci_dev,
1145                 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1146
1147         if (!uart_poll) {
1148                 jsm_printk(INTR, INFO, &brd->pci_dev,
1149                         "Kernel interrupted to me, but no pending interrupts...\n");
1150                 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1151                 return IRQ_NONE;
1152         }
1153
1154         /* At this point, we have at least SOMETHING to service, dig further... */
1155
1156         current_port = 0;
1157
1158         /* Loop on each port */
1159         while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1160
1161                 tmp = uart_poll;
1162                 outofloop_count++;
1163
1164                 /* Check current port to see if it has interrupt pending */
1165                 if ((tmp & jsm_offset_table[current_port]) != 0) {
1166                         port = current_port;
1167                         type = tmp >> (8 + (port * 3));
1168                         type &= 0x7;
1169                 } else {
1170                         current_port++;
1171                         continue;
1172                 }
1173
1174                 jsm_printk(INTR, INFO, &brd->pci_dev,
1175                 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1176
1177                 /* Remove this port + type from uart_poll */
1178                 uart_poll &= ~(jsm_offset_table[port]);
1179
1180                 if (!type) {
1181                         /* If no type, just ignore it, and move onto next port */
1182                         jsm_printk(INTR, ERR, &brd->pci_dev,
1183                                 "Interrupt with no type! port: %d\n", port);
1184                         continue;
1185                 }
1186
1187                 /* Switch on type of interrupt we have */
1188                 switch (type) {
1189
1190                 case UART_17158_RXRDY_TIMEOUT:
1191                         /*
1192                          * RXRDY Time-out is cleared by reading data in the
1193                         * RX FIFO until it falls below the trigger level.
1194                          */
1195
1196                         /* Verify the port is in range. */
1197                         if (port > brd->nasync)
1198                                 continue;
1199
1200                         ch = brd->channels[port];
1201                         neo_copy_data_from_uart_to_queue(ch);
1202
1203                         /* Call our tty layer to enforce queue flow control if needed. */
1204                         spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1205                         jsm_check_queue_flow_control(ch);
1206                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1207
1208                         continue;
1209
1210                 case UART_17158_RX_LINE_STATUS:
1211                         /*
1212                          * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1213                          */
1214                         neo_parse_lsr(brd, port);
1215                         continue;
1216
1217                 case UART_17158_TXRDY:
1218                         /*
1219                          * TXRDY interrupt clears after reading ISR register for the UART channel.
1220                          */
1221
1222                         /*
1223                          * Yes, this is odd...
1224                          * Why would I check EVERY possibility of type of
1225                          * interrupt, when we know its TXRDY???
1226                          * Becuz for some reason, even tho we got triggered for TXRDY,
1227                          * it seems to be occassionally wrong. Instead of TX, which
1228                          * it should be, I was getting things like RXDY too. Weird.
1229                          */
1230                         neo_parse_isr(brd, port);
1231                         continue;
1232
1233                 case UART_17158_MSR:
1234                         /*
1235                          * MSR or flow control was seen.
1236                          */
1237                         neo_parse_isr(brd, port);
1238                         continue;
1239
1240                 default:
1241                         /*
1242                          * The UART triggered us with a bogus interrupt type.
1243                          * It appears the Exar chip, when REALLY bogged down, will throw
1244                          * these once and awhile.
1245                          * Its harmless, just ignore it and move on.
1246                          */
1247                         jsm_printk(INTR, ERR, &brd->pci_dev,
1248                                 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1249                         continue;
1250                 }
1251         }
1252
1253         spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1254
1255         jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1256         return IRQ_HANDLED;
1257 }
1258
1259 /*
1260  * Neo specific way of turning off the receiver.
1261  * Used as a way to enforce queue flow control when in
1262  * hardware flow control mode.
1263  */
1264 static void neo_disable_receiver(struct jsm_channel *ch)
1265 {
1266         u8 tmp = readb(&ch->ch_neo_uart->ier);
1267         tmp &= ~(UART_IER_RDI);
1268         writeb(tmp, &ch->ch_neo_uart->ier);
1269
1270         /* flush write operation */
1271         neo_pci_posting_flush(ch->ch_bd);
1272 }
1273
1274
1275 /*
1276  * Neo specific way of turning on the receiver.
1277  * Used as a way to un-enforce queue flow control when in
1278  * hardware flow control mode.
1279  */
1280 static void neo_enable_receiver(struct jsm_channel *ch)
1281 {
1282         u8 tmp = readb(&ch->ch_neo_uart->ier);
1283         tmp |= (UART_IER_RDI);
1284         writeb(tmp, &ch->ch_neo_uart->ier);
1285
1286         /* flush write operation */
1287         neo_pci_posting_flush(ch->ch_bd);
1288 }
1289
1290 static void neo_send_start_character(struct jsm_channel *ch)
1291 {
1292         if (!ch)
1293                 return;
1294
1295         if (ch->ch_startc != __DISABLED_CHAR) {
1296                 ch->ch_xon_sends++;
1297                 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1298
1299                 /* flush write operation */
1300                 neo_pci_posting_flush(ch->ch_bd);
1301         }
1302 }
1303
1304 static void neo_send_stop_character(struct jsm_channel *ch)
1305 {
1306         if (!ch)
1307                 return;
1308
1309         if (ch->ch_stopc != __DISABLED_CHAR) {
1310                 ch->ch_xoff_sends++;
1311                 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1312
1313                 /* flush write operation */
1314                 neo_pci_posting_flush(ch->ch_bd);
1315         }
1316 }
1317
1318 /*
1319  * neo_uart_init
1320  */
1321 static void neo_uart_init(struct jsm_channel *ch)
1322 {
1323         writeb(0, &ch->ch_neo_uart->ier);
1324         writeb(0, &ch->ch_neo_uart->efr);
1325         writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1326
1327         /* Clear out UART and FIFO */
1328         readb(&ch->ch_neo_uart->txrx);
1329         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1330         readb(&ch->ch_neo_uart->lsr);
1331         readb(&ch->ch_neo_uart->msr);
1332
1333         ch->ch_flags |= CH_FIFO_ENABLED;
1334
1335         /* Assert any signals we want up */
1336         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1337 }
1338
1339 /*
1340  * Make the UART completely turn off.
1341  */
1342 static void neo_uart_off(struct jsm_channel *ch)
1343 {
1344         /* Turn off UART enhanced bits */
1345         writeb(0, &ch->ch_neo_uart->efr);
1346
1347         /* Stop all interrupts from occurring. */
1348         writeb(0, &ch->ch_neo_uart->ier);
1349 }
1350
1351 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1352 {
1353         u8 left = 0;
1354         u8 lsr = readb(&ch->ch_neo_uart->lsr);
1355
1356         /* We must cache the LSR as some of the bits get reset once read... */
1357         ch->ch_cached_lsr |= lsr;
1358
1359         /* Determine whether the Transmitter is empty or not */
1360         if (!(lsr & UART_LSR_TEMT))
1361                 left = 1;
1362         else {
1363                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1364                 left = 0;
1365         }
1366
1367         return left;
1368 }
1369
1370 /* Channel lock MUST be held by the calling function! */
1371 static void neo_send_break(struct jsm_channel *ch)
1372 {
1373         /*
1374          * Set the time we should stop sending the break.
1375          * If we are already sending a break, toss away the existing
1376          * time to stop, and use this new value instead.
1377          */
1378
1379         /* Tell the UART to start sending the break */
1380         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1381                 u8 temp = readb(&ch->ch_neo_uart->lcr);
1382                 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1383                 ch->ch_flags |= (CH_BREAK_SENDING);
1384
1385                 /* flush write operation */
1386                 neo_pci_posting_flush(ch->ch_bd);
1387         }
1388 }
1389
1390 /*
1391  * neo_send_immediate_char.
1392  *
1393  * Sends a specific character as soon as possible to the UART,
1394  * jumping over any bytes that might be in the write queue.
1395  *
1396  * The channel lock MUST be held by the calling function.
1397  */
1398 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1399 {
1400         if (!ch)
1401                 return;
1402
1403         writeb(c, &ch->ch_neo_uart->txrx);
1404
1405         /* flush write operation */
1406         neo_pci_posting_flush(ch->ch_bd);
1407 }
1408
1409 struct board_ops jsm_neo_ops = {
1410         .intr                           = neo_intr,
1411         .uart_init                      = neo_uart_init,
1412         .uart_off                       = neo_uart_off,
1413         .param                          = neo_param,
1414         .assert_modem_signals           = neo_assert_modem_signals,
1415         .flush_uart_write               = neo_flush_uart_write,
1416         .flush_uart_read                = neo_flush_uart_read,
1417         .disable_receiver               = neo_disable_receiver,
1418         .enable_receiver                = neo_enable_receiver,
1419         .send_break                     = neo_send_break,
1420         .clear_break                    = neo_clear_break,
1421         .send_start_character           = neo_send_start_character,
1422         .send_stop_character            = neo_send_stop_character,
1423         .copy_data_from_queue_to_uart   = neo_copy_data_from_queue_to_uart,
1424         .get_uart_bytes_left            = neo_get_uart_bytes_left,
1425         .send_immediate_char            = neo_send_immediate_char
1426 };