2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
4 * Copyright (C) 2007 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
7 * Based on setup-sh7709.c
9 * Copyright (C) 2006 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/serial_sci.h>
25 /* interrupt sources */
26 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
28 DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
34 static struct intc_vect vectors[] __initdata = {
35 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
36 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
37 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
38 INTC_VECT(RTC, 0x4c0),
39 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
40 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
41 INTC_VECT(WDT, 0x560),
42 INTC_VECT(REF, 0x580),
43 INTC_VECT(REF, 0x5a0),
44 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7709)
47 /* IRQ0->5 are handled in setup-sh3.c */
48 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
49 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
50 INTC_VECT(ADC_ADI, 0x980),
51 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
52 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
54 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
55 defined(CONFIG_CPU_SUBTYPE_SH7709)
56 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
57 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
58 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
60 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
61 INTC_VECT(LCDC, 0x9a0),
62 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
66 static struct intc_prio_reg prio_registers[] __initdata = {
67 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
68 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
69 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
70 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
71 defined(CONFIG_CPU_SUBTYPE_SH7709)
72 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
73 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
74 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
76 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
77 defined(CONFIG_CPU_SUBTYPE_SH7709)
78 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
79 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
81 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
82 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
86 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
87 NULL, prio_registers, NULL);
89 static struct resource rtc_resources[] = {
92 .end = 0xfffffec0 + 0x1e,
93 .flags = IORESOURCE_IO,
97 .flags = IORESOURCE_IRQ,
101 static struct platform_device rtc_device = {
104 .num_resources = ARRAY_SIZE(rtc_resources),
105 .resource = rtc_resources,
108 static struct plat_sci_port sci_platform_data[] = {
110 .mapbase = 0xfffffe80,
111 .flags = UPF_BOOT_AUTOCONF,
113 .irqs = { 23, 23, 23, 0 },
115 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
116 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
117 defined(CONFIG_CPU_SUBTYPE_SH7709)
119 .mapbase = 0xa4000150,
120 .flags = UPF_BOOT_AUTOCONF,
122 .irqs = { 56, 56, 56, 56 },
125 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
126 defined(CONFIG_CPU_SUBTYPE_SH7709)
128 .mapbase = 0xa4000140,
129 .flags = UPF_BOOT_AUTOCONF,
131 .irqs = { 52, 52, 52, 52 },
139 static struct platform_device sci_device = {
143 .platform_data = sci_platform_data,
147 static struct platform_device *sh770x_devices[] __initdata = {
152 static int __init sh770x_devices_setup(void)
154 return platform_add_devices(sh770x_devices,
155 ARRAY_SIZE(sh770x_devices));
157 __initcall(sh770x_devices_setup);
159 void __init plat_irq_setup(void)
161 register_intc_controller(&intc_desc);
162 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
163 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
164 defined(CONFIG_CPU_SUBTYPE_SH7709)
165 plat_irq_setup_sh3();