Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg...
[linux-2.6] / drivers / video / aty / radeon_accel.c
1 #include "radeonfb.h"
2
3 /* the accelerated functions here are patterned after the 
4  * "ACCEL_MMIO" ifdef branches in XFree86
5  * --dte
6  */
7
8 static void radeon_fixup_offset(struct radeonfb_info *rinfo)
9 {
10         u32 local_base;
11
12         /* *** Ugly workaround *** */
13         /*
14          * On some platforms, the video memory is mapped at 0 in radeon chip space
15          * (like PPCs) by the firmware. X will always move it up so that it's seen
16          * by the chip to be at the same address as the PCI BAR.
17          * That means that when switching back from X, there is a mismatch between
18          * the offsets programmed into the engine. This means that potentially,
19          * accel operations done before radeonfb has a chance to re-init the engine
20          * will have incorrect offsets, and potentially trash system memory !
21          *
22          * The correct fix is for fbcon to never call any accel op before the engine
23          * has properly been re-initialized (by a call to set_var), but this is a
24          * complex fix. This workaround in the meantime, called before every accel
25          * operation, makes sure the offsets are in sync.
26          */
27
28         radeon_fifo_wait (1);
29         local_base = INREG(MC_FB_LOCATION) << 16;
30         if (local_base == rinfo->fb_local_base)
31                 return;
32
33         rinfo->fb_local_base = local_base;
34
35         radeon_fifo_wait (3);
36         OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
37                                      (rinfo->fb_local_base >> 10));
38         OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
39         OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
40 }
41
42 static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, 
43                                    const struct fb_fillrect *region)
44 {
45         radeon_fifo_wait(4);  
46   
47         OUTREG(DP_GUI_MASTER_CNTL,  
48                 rinfo->dp_gui_master_cntl  /* contains, like GMC_DST_32BPP */
49                 | GMC_BRUSH_SOLID_COLOR
50                 | ROP3_P);
51         if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
52                 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
53         else
54                 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
55         OUTREG(DP_WRITE_MSK, 0xffffffff);
56         OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
57
58         radeon_fifo_wait(2);  
59         OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
60         OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
61 }
62
63 void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
64 {
65         struct radeonfb_info *rinfo = info->par;
66         struct fb_fillrect modded;
67         int vxres, vyres;
68   
69         if (info->state != FBINFO_STATE_RUNNING)
70                 return;
71         if (info->flags & FBINFO_HWACCEL_DISABLED) {
72                 cfb_fillrect(info, region);
73                 return;
74         }
75
76         radeon_fixup_offset(rinfo);
77
78         vxres = info->var.xres_virtual;
79         vyres = info->var.yres_virtual;
80
81         memcpy(&modded, region, sizeof(struct fb_fillrect));
82
83         if(!modded.width || !modded.height ||
84            modded.dx >= vxres || modded.dy >= vyres)
85                 return;
86   
87         if(modded.dx + modded.width  > vxres) modded.width  = vxres - modded.dx;
88         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
89
90         radeonfb_prim_fillrect(rinfo, &modded);
91 }
92
93 static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo, 
94                                    const struct fb_copyarea *area)
95 {
96         int xdir, ydir;
97         u32 sx, sy, dx, dy, w, h;
98
99         w = area->width; h = area->height;
100         dx = area->dx; dy = area->dy;
101         sx = area->sx; sy = area->sy;
102         xdir = sx - dx;
103         ydir = sy - dy;
104
105         if ( xdir < 0 ) { sx += w-1; dx += w-1; }
106         if ( ydir < 0 ) { sy += h-1; dy += h-1; }
107
108         radeon_fifo_wait(3);
109         OUTREG(DP_GUI_MASTER_CNTL,
110                 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
111                 | GMC_BRUSH_NONE
112                 | GMC_SRC_DSTCOLOR
113                 | ROP3_S 
114                 | DP_SRC_SOURCE_MEMORY );
115         OUTREG(DP_WRITE_MSK, 0xffffffff);
116         OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
117                         | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
118
119         radeon_fifo_wait(3);
120         OUTREG(SRC_Y_X, (sy << 16) | sx);
121         OUTREG(DST_Y_X, (dy << 16) | dx);
122         OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
123 }
124
125
126 void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
127 {
128         struct radeonfb_info *rinfo = info->par;
129         struct fb_copyarea modded;
130         u32 vxres, vyres;
131         modded.sx = area->sx;
132         modded.sy = area->sy;
133         modded.dx = area->dx;
134         modded.dy = area->dy;
135         modded.width  = area->width;
136         modded.height = area->height;
137   
138         if (info->state != FBINFO_STATE_RUNNING)
139                 return;
140         if (info->flags & FBINFO_HWACCEL_DISABLED) {
141                 cfb_copyarea(info, area);
142                 return;
143         }
144
145         radeon_fixup_offset(rinfo);
146
147         vxres = info->var.xres_virtual;
148         vyres = info->var.yres_virtual;
149
150         if(!modded.width || !modded.height ||
151            modded.sx >= vxres || modded.sy >= vyres ||
152            modded.dx >= vxres || modded.dy >= vyres)
153                 return;
154   
155         if(modded.sx + modded.width > vxres)  modded.width = vxres - modded.sx;
156         if(modded.dx + modded.width > vxres)  modded.width = vxres - modded.dx;
157         if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
158         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
159   
160         radeonfb_prim_copyarea(rinfo, &modded);
161 }
162
163 void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
164 {
165         struct radeonfb_info *rinfo = info->par;
166
167         if (info->state != FBINFO_STATE_RUNNING)
168                 return;
169         radeon_engine_idle();
170
171         cfb_imageblit(info, image);
172 }
173
174 int radeonfb_sync(struct fb_info *info)
175 {
176         struct radeonfb_info *rinfo = info->par;
177
178         if (info->state != FBINFO_STATE_RUNNING)
179                 return 0;
180         radeon_engine_idle();
181
182         return 0;
183 }
184
185 void radeonfb_engine_reset(struct radeonfb_info *rinfo)
186 {
187         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
188         u32 host_path_cntl;
189
190         radeon_engine_flush (rinfo);
191
192         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
193         mclk_cntl = INPLL(MCLK_CNTL);
194
195         OUTPLL(MCLK_CNTL, (mclk_cntl |
196                            FORCEON_MCLKA |
197                            FORCEON_MCLKB |
198                            FORCEON_YCLKA |
199                            FORCEON_YCLKB |
200                            FORCEON_MC |
201                            FORCEON_AIC));
202
203         host_path_cntl = INREG(HOST_PATH_CNTL);
204         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
205
206         if (rinfo->family == CHIP_FAMILY_R300 ||
207             rinfo->family == CHIP_FAMILY_R350 ||
208             rinfo->family == CHIP_FAMILY_RV350) {
209                 u32 tmp;
210
211                 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
212                                          SOFT_RESET_CP |
213                                          SOFT_RESET_HI |
214                                          SOFT_RESET_E2));
215                 INREG(RBBM_SOFT_RESET);
216                 OUTREG(RBBM_SOFT_RESET, 0);
217                 tmp = INREG(RB2D_DSTCACHE_MODE);
218                 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
219         } else {
220                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
221                                         SOFT_RESET_CP |
222                                         SOFT_RESET_HI |
223                                         SOFT_RESET_SE |
224                                         SOFT_RESET_RE |
225                                         SOFT_RESET_PP |
226                                         SOFT_RESET_E2 |
227                                         SOFT_RESET_RB);
228                 INREG(RBBM_SOFT_RESET);
229                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
230                                         ~(SOFT_RESET_CP |
231                                           SOFT_RESET_HI |
232                                           SOFT_RESET_SE |
233                                           SOFT_RESET_RE |
234                                           SOFT_RESET_PP |
235                                           SOFT_RESET_E2 |
236                                           SOFT_RESET_RB));
237                 INREG(RBBM_SOFT_RESET);
238         }
239
240         OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
241         INREG(HOST_PATH_CNTL);
242         OUTREG(HOST_PATH_CNTL, host_path_cntl);
243
244         if (rinfo->family != CHIP_FAMILY_R300 &&
245             rinfo->family != CHIP_FAMILY_R350 &&
246             rinfo->family != CHIP_FAMILY_RV350)
247                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
248
249         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
250         OUTPLL(MCLK_CNTL, mclk_cntl);
251 }
252
253 void radeonfb_engine_init (struct radeonfb_info *rinfo)
254 {
255         unsigned long temp;
256
257         /* disable 3D engine */
258         OUTREG(RB3D_CNTL, 0);
259
260         radeonfb_engine_reset(rinfo);
261
262         radeon_fifo_wait (1);
263         if ((rinfo->family != CHIP_FAMILY_R300) &&
264             (rinfo->family != CHIP_FAMILY_R350) &&
265             (rinfo->family != CHIP_FAMILY_RV350))
266                 OUTREG(RB2D_DSTCACHE_MODE, 0);
267
268         radeon_fifo_wait (3);
269         /* We re-read MC_FB_LOCATION from card as it can have been
270          * modified by XFree drivers (ouch !)
271          */
272         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
273
274         OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
275                                      (rinfo->fb_local_base >> 10));
276         OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
277         OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
278
279         radeon_fifo_wait (1);
280 #if defined(__BIG_ENDIAN)
281         OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
282 #else
283         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
284 #endif
285         radeon_fifo_wait (2);
286         OUTREG(DEFAULT_SC_TOP_LEFT, 0);
287         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
288                                          DEFAULT_SC_BOTTOM_MAX));
289
290         temp = radeon_get_dstbpp(rinfo->depth);
291         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
292
293         radeon_fifo_wait (1);
294         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
295                                     GMC_BRUSH_SOLID_COLOR |
296                                     GMC_SRC_DATATYPE_COLOR));
297
298         radeon_fifo_wait (7);
299
300         /* clear line drawing regs */
301         OUTREG(DST_LINE_START, 0);
302         OUTREG(DST_LINE_END, 0);
303
304         /* set brush color regs */
305         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
306         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
307
308         /* set source color regs */
309         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
310         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
311
312         /* default write mask */
313         OUTREG(DP_WRITE_MSK, 0xffffffff);
314
315         radeon_engine_idle ();
316 }