i2c-piix4: Add support for the Broadcom HT1100 chipset
[linux-2.6] / drivers / i2c / busses / i2c-mpc.c
1 /*
2  * (C) Copyright 2003-2004
3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5  * This is a combined i2c adapter and algorithm driver for the
6  * MPC107/Tsi107 PowerPC northbridge and processors that include
7  * the same I2C unit (8240, 8245, 85xx).
8  *
9  * Release 0.8
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2. This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
22
23 #include <asm/io.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #define DRV_NAME "mpc-i2c"
30
31 #define MPC_I2C_FDR     0x04
32 #define MPC_I2C_CR      0x08
33 #define MPC_I2C_SR      0x0c
34 #define MPC_I2C_DR      0x10
35 #define MPC_I2C_DFSRR 0x14
36
37 #define CCR_MEN  0x80
38 #define CCR_MIEN 0x40
39 #define CCR_MSTA 0x20
40 #define CCR_MTX  0x10
41 #define CCR_TXAK 0x08
42 #define CCR_RSTA 0x04
43
44 #define CSR_MCF  0x80
45 #define CSR_MAAS 0x40
46 #define CSR_MBB  0x20
47 #define CSR_MAL  0x10
48 #define CSR_SRW  0x04
49 #define CSR_MIF  0x02
50 #define CSR_RXAK 0x01
51
52 struct mpc_i2c {
53         void __iomem *base;
54         u32 interrupt;
55         wait_queue_head_t queue;
56         struct i2c_adapter adap;
57         int irq;
58         u32 flags;
59 };
60
61 static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
62 {
63         writeb(x, i2c->base + MPC_I2C_CR);
64 }
65
66 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
67 {
68         struct mpc_i2c *i2c = dev_id;
69         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
70                 /* Read again to allow register to stabilise */
71                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
72                 writeb(0, i2c->base + MPC_I2C_SR);
73                 wake_up_interruptible(&i2c->queue);
74         }
75         return IRQ_HANDLED;
76 }
77
78 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
79  * the bus, because it wants to send ACK.
80  * Following sequence of enabling/disabling and sending start/stop generates
81  * the pulse, so it's all OK.
82  */
83 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
84 {
85         writeccr(i2c, 0);
86         udelay(30);
87         writeccr(i2c, CCR_MEN);
88         udelay(30);
89         writeccr(i2c, CCR_MSTA | CCR_MTX);
90         udelay(30);
91         writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
92         udelay(30);
93         writeccr(i2c, CCR_MEN);
94         udelay(30);
95 }
96
97 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
98 {
99         unsigned long orig_jiffies = jiffies;
100         u32 x;
101         int result = 0;
102
103         if (i2c->irq == NO_IRQ)
104         {
105                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
106                         schedule();
107                         if (time_after(jiffies, orig_jiffies + timeout)) {
108                                 pr_debug("I2C: timeout\n");
109                                 writeccr(i2c, 0);
110                                 result = -EIO;
111                                 break;
112                         }
113                 }
114                 x = readb(i2c->base + MPC_I2C_SR);
115                 writeb(0, i2c->base + MPC_I2C_SR);
116         } else {
117                 /* Interrupt mode */
118                 result = wait_event_interruptible_timeout(i2c->queue,
119                         (i2c->interrupt & CSR_MIF), timeout);
120
121                 if (unlikely(result < 0)) {
122                         pr_debug("I2C: wait interrupted\n");
123                         writeccr(i2c, 0);
124                 } else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
125                         pr_debug("I2C: wait timeout\n");
126                         writeccr(i2c, 0);
127                         result = -ETIMEDOUT;
128                 }
129
130                 x = i2c->interrupt;
131                 i2c->interrupt = 0;
132         }
133
134         if (result < 0)
135                 return result;
136
137         if (!(x & CSR_MCF)) {
138                 pr_debug("I2C: unfinished\n");
139                 return -EIO;
140         }
141
142         if (x & CSR_MAL) {
143                 pr_debug("I2C: MAL\n");
144                 return -EIO;
145         }
146
147         if (writing && (x & CSR_RXAK)) {
148                 pr_debug("I2C: No RXAK\n");
149                 /* generate stop */
150                 writeccr(i2c, CCR_MEN);
151                 return -EIO;
152         }
153         return 0;
154 }
155
156 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
157 {
158         /* Set clock and filters */
159         if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
160                 writeb(0x31, i2c->base + MPC_I2C_FDR);
161                 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
162         } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
163                 writeb(0x3f, i2c->base + MPC_I2C_FDR);
164         else
165                 writel(0x1031, i2c->base + MPC_I2C_FDR);
166 }
167
168 static void mpc_i2c_start(struct mpc_i2c *i2c)
169 {
170         /* Clear arbitration */
171         writeb(0, i2c->base + MPC_I2C_SR);
172         /* Start with MEN */
173         writeccr(i2c, CCR_MEN);
174 }
175
176 static void mpc_i2c_stop(struct mpc_i2c *i2c)
177 {
178         writeccr(i2c, CCR_MEN);
179 }
180
181 static int mpc_write(struct mpc_i2c *i2c, int target,
182                      const u8 * data, int length, int restart)
183 {
184         int i, result;
185         unsigned timeout = i2c->adap.timeout;
186         u32 flags = restart ? CCR_RSTA : 0;
187
188         /* Start with MEN */
189         if (!restart)
190                 writeccr(i2c, CCR_MEN);
191         /* Start as master */
192         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
193         /* Write target byte */
194         writeb((target << 1), i2c->base + MPC_I2C_DR);
195
196         result = i2c_wait(i2c, timeout, 1);
197         if (result < 0)
198                 return result;
199
200         for (i = 0; i < length; i++) {
201                 /* Write data byte */
202                 writeb(data[i], i2c->base + MPC_I2C_DR);
203
204                 result = i2c_wait(i2c, timeout, 1);
205                 if (result < 0)
206                         return result;
207         }
208
209         return 0;
210 }
211
212 static int mpc_read(struct mpc_i2c *i2c, int target,
213                     u8 * data, int length, int restart)
214 {
215         unsigned timeout = i2c->adap.timeout;
216         int i, result;
217         u32 flags = restart ? CCR_RSTA : 0;
218
219         /* Start with MEN */
220         if (!restart)
221                 writeccr(i2c, CCR_MEN);
222         /* Switch to read - restart */
223         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
224         /* Write target address byte - this time with the read flag set */
225         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
226
227         result = i2c_wait(i2c, timeout, 1);
228         if (result < 0)
229                 return result;
230
231         if (length) {
232                 if (length == 1)
233                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
234                 else
235                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
236                 /* Dummy read */
237                 readb(i2c->base + MPC_I2C_DR);
238         }
239
240         for (i = 0; i < length; i++) {
241                 result = i2c_wait(i2c, timeout, 0);
242                 if (result < 0)
243                         return result;
244
245                 /* Generate txack on next to last byte */
246                 if (i == length - 2)
247                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
248                 /* Generate stop on last byte */
249                 if (i == length - 1)
250                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
251                 data[i] = readb(i2c->base + MPC_I2C_DR);
252         }
253
254         return length;
255 }
256
257 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
258 {
259         struct i2c_msg *pmsg;
260         int i;
261         int ret = 0;
262         unsigned long orig_jiffies = jiffies;
263         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
264
265         mpc_i2c_start(i2c);
266
267         /* Allow bus up to 1s to become not busy */
268         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
269                 if (signal_pending(current)) {
270                         pr_debug("I2C: Interrupted\n");
271                         writeccr(i2c, 0);
272                         return -EINTR;
273                 }
274                 if (time_after(jiffies, orig_jiffies + HZ)) {
275                         pr_debug("I2C: timeout\n");
276                         if (readb(i2c->base + MPC_I2C_SR) ==
277                             (CSR_MCF | CSR_MBB | CSR_RXAK))
278                                 mpc_i2c_fixup(i2c);
279                         return -EIO;
280                 }
281                 schedule();
282         }
283
284         for (i = 0; ret >= 0 && i < num; i++) {
285                 pmsg = &msgs[i];
286                 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
287                          pmsg->flags & I2C_M_RD ? "read" : "write",
288                          pmsg->len, pmsg->addr, i + 1, num);
289                 if (pmsg->flags & I2C_M_RD)
290                         ret =
291                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
292                 else
293                         ret =
294                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
295         }
296         mpc_i2c_stop(i2c);
297         return (ret < 0) ? ret : num;
298 }
299
300 static u32 mpc_functionality(struct i2c_adapter *adap)
301 {
302         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
303 }
304
305 static const struct i2c_algorithm mpc_algo = {
306         .master_xfer = mpc_xfer,
307         .functionality = mpc_functionality,
308 };
309
310 static struct i2c_adapter mpc_ops = {
311         .owner = THIS_MODULE,
312         .name = "MPC adapter",
313         .algo = &mpc_algo,
314         .timeout = HZ,
315 };
316
317 static int __devinit fsl_i2c_probe(struct of_device *op, const struct of_device_id *match)
318 {
319         int result = 0;
320         struct mpc_i2c *i2c;
321
322         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
323         if (!i2c)
324                 return -ENOMEM;
325
326         if (of_get_property(op->node, "dfsrr", NULL))
327                 i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
328
329         if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
330                         of_device_is_compatible(op->node, "mpc5200-i2c"))
331                 i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
332
333         init_waitqueue_head(&i2c->queue);
334
335         i2c->base = of_iomap(op->node, 0);
336         if (!i2c->base) {
337                 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
338                 result = -ENOMEM;
339                 goto fail_map;
340         }
341
342         i2c->irq = irq_of_parse_and_map(op->node, 0);
343         if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
344                 result = request_irq(i2c->irq, mpc_i2c_isr,
345                                      IRQF_SHARED, "i2c-mpc", i2c);
346                 if (result < 0) {
347                         printk(KERN_ERR "i2c-mpc - failed to attach interrupt\n");
348                         goto fail_request;
349                 }
350         }
351         
352         mpc_i2c_setclock(i2c);
353
354         dev_set_drvdata(&op->dev, i2c);
355
356         i2c->adap = mpc_ops;
357         i2c_set_adapdata(&i2c->adap, i2c);
358         i2c->adap.dev.parent = &op->dev;
359
360         result = i2c_add_adapter(&i2c->adap);
361         if (result < 0) {
362                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
363                 goto fail_add;
364         }
365         of_register_i2c_devices(&i2c->adap, op->node);
366
367         return result;
368
369  fail_add:
370         dev_set_drvdata(&op->dev, NULL);
371         free_irq(i2c->irq, i2c);
372  fail_request:
373         irq_dispose_mapping(i2c->irq);
374         iounmap(i2c->base);
375  fail_map:
376         kfree(i2c);
377         return result;
378 };
379
380 static int __devexit fsl_i2c_remove(struct of_device *op)
381 {
382         struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
383
384         i2c_del_adapter(&i2c->adap);
385         dev_set_drvdata(&op->dev, NULL);
386
387         if (i2c->irq != NO_IRQ)
388                 free_irq(i2c->irq, i2c);
389
390         irq_dispose_mapping(i2c->irq);
391         iounmap(i2c->base);
392         kfree(i2c);
393         return 0;
394 };
395
396 static const struct of_device_id mpc_i2c_of_match[] = {
397         {.compatible = "fsl-i2c",},
398         {},
399 };
400 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
401
402
403 /* Structure for a device driver */
404 static struct of_platform_driver mpc_i2c_driver = {
405         .match_table    = mpc_i2c_of_match,
406         .probe          = fsl_i2c_probe,
407         .remove         = __devexit_p(fsl_i2c_remove),
408         .driver         = {
409                 .owner  = THIS_MODULE,
410                 .name   = DRV_NAME,
411         },
412 };
413
414 static int __init fsl_i2c_init(void)
415 {
416         int rv;
417
418         rv = of_register_platform_driver(&mpc_i2c_driver);
419         if (rv)
420                 printk(KERN_ERR DRV_NAME 
421                        " of_register_platform_driver failed (%i)\n", rv);
422         return rv;
423 }
424
425 static void __exit fsl_i2c_exit(void)
426 {
427         of_unregister_platform_driver(&mpc_i2c_driver);
428 }
429
430 module_init(fsl_i2c_init);
431 module_exit(fsl_i2c_exit);
432
433 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
434 MODULE_DESCRIPTION
435     ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
436 MODULE_LICENSE("GPL");