git.oblomov.eu Git - linux-2.6/blob - drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61 /*  NETIF_MSG_TX_QUEUED | */
  62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int wait_count = 30;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 udelay(100);
 135         } while (--wait_count);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_wait_cfg(qdev, bit);
 218         if (status) {
 219                 QPRINTK(qdev, IFUP, ERR,
 220                         "Timed out waiting for CFG to come ready.\n");
 221                 goto exit;
 222         }
 223
 224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 225         if (status)
 226                 goto exit;
 227         ql_write32(qdev, ICB_L, (u32) map);
 228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         pci_unmap_single(qdev->pdev, map, size, direction);
 241         return status;
 242 }
 243
 244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 246                         u32 *value)
 247 {
 248         u32 offset = 0;
 249         int status;
 250
 251         switch (type) {
 252         case MAC_ADDR_TYPE_MULTI_MAC:
 253         case MAC_ADDR_TYPE_CAM_MAC:
 254                 {
 255                         status =
 256                             ql_wait_reg_rdy(qdev,
 257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 258                         if (status)
 259                                 goto exit;
 260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 263                         status =
 264                             ql_wait_reg_rdy(qdev,
 265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 266                         if (status)
 267                                 goto exit;
 268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 269                         status =
 270                             ql_wait_reg_rdy(qdev,
 271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 272                         if (status)
 273                                 goto exit;
 274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 277                         status =
 278                             ql_wait_reg_rdy(qdev,
 279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 280                         if (status)
 281                                 goto exit;
 282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 284                                 status =
 285                                     ql_wait_reg_rdy(qdev,
 286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 287                                 if (status)
 288                                         goto exit;
 289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 292                                 status =
 293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 294                                                     MAC_ADDR_MR, 0);
 295                                 if (status)
 296                                         goto exit;
 297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 298                         }
 299                         break;
 300                 }
 301         case MAC_ADDR_TYPE_VLAN:
 302         case MAC_ADDR_TYPE_MULTI_FLTR:
 303         default:
 304                 QPRINTK(qdev, IFUP, CRIT,
 305                         "Address type %d not yet supported.\n", type);
 306                 status = -EPERM;
 307         }
 308 exit:
 309         return status;
 310 }
 311
 312 /* Set up a MAC, multicast or VLAN address for the
 313  * inbound frame matching.
 314  */
 315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 316                                u16 index)
 317 {
 318         u32 offset = 0;
 319         int status = 0;
 320
 321         switch (type) {
 322         case MAC_ADDR_TYPE_MULTI_MAC:
 323         case MAC_ADDR_TYPE_CAM_MAC:
 324                 {
 325                         u32 cam_output;
 326                         u32 upper = (addr[0] << 8) | addr[1];
 327                         u32 lower =
 328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 329                             (addr[5]);
 330
 331                         QPRINTK(qdev, IFUP, DEBUG,
 332                                 "Adding %s address %pM"
 333                                 " at index %d in the CAM.\n",
 334                                 ((type ==
 335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 336                                  "UNICAST"), addr, index);
 337
 338                         status =
 339                             ql_wait_reg_rdy(qdev,
 340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 341                         if (status)
 342                                 goto exit;
 343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 345                                    type);       /* type */
 346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 347                         status =
 348                             ql_wait_reg_rdy(qdev,
 349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 350                         if (status)
 351                                 goto exit;
 352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 354                                    type);       /* type */
 355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 356                         status =
 357                             ql_wait_reg_rdy(qdev,
 358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 359                         if (status)
 360                                 goto exit;
 361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 363                                    type);       /* type */
 364                         /* This field should also include the queue id
 365                            and possibly the function id.  Right now we hardcode
 366                            the route field to NIC core.
 367                          */
 368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 369                                 cam_output = (CAM_OUT_ROUTE_NIC |
 370                                               (qdev->
 371                                                func << CAM_OUT_FUNC_SHIFT) |
 372                                               (qdev->
 373                                                rss_ring_first_cq_id <<
 374                                                CAM_OUT_CQ_ID_SHIFT));
 375                                 if (qdev->vlgrp)
 376                                         cam_output |= CAM_OUT_RV;
 377                                 /* route to NIC core */
 378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 379                         }
 380                         break;
 381                 }
 382         case MAC_ADDR_TYPE_VLAN:
 383                 {
 384                         u32 enable_bit = *((u32 *) &addr[0]);
 385                         /* For VLAN, the addr actually holds a bit that
 386                          * either enables or disables the vlan id we are
 387                          * addressing. It's either MAC_ADDR_E on or off.
 388                          * That's bit-27 we're talking about.
 389                          */
 390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 391                                 (enable_bit ? "Adding" : "Removing"),
 392                                 index, (enable_bit ? "to" : "from"));
 393
 394                         status =
 395                             ql_wait_reg_rdy(qdev,
 396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 397                         if (status)
 398                                 goto exit;
 399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 401                                    type |       /* type */
 402                                    enable_bit); /* enable/disable */
 403                         break;
 404                 }
 405         case MAC_ADDR_TYPE_MULTI_FLTR:
 406         default:
 407                 QPRINTK(qdev, IFUP, CRIT,
 408                         "Address type %d not yet supported.\n", type);
 409                 status = -EPERM;
 410         }
 411 exit:
 412         return status;
 413 }
 414
 415 /* Get a specific frame routing value from the CAM.
 416  * Used for debug and reg dump.
 417  */
 418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 419 {
 420         int status = 0;
 421
 422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 423         if (status)
 424                 goto exit;
 425
 426         ql_write32(qdev, RT_IDX,
 427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 429         if (status)
 430                 goto exit;
 431         *value = ql_read32(qdev, RT_DATA);
 432 exit:
 433         return status;
 434 }
 435
 436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 437  * to route different frame types to various inbound queues.  We send broadcast/
 438  * multicast/error frames to the default queue for slow handling,
 439  * and CAM hit/RSS frames to the fast handling queues.
 440  */
 441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 442                               int enable)
 443 {
 444         int status = -EINVAL; /* Return error if no mask match. */
 445         u32 value = 0;
 446
 447         QPRINTK(qdev, IFUP, DEBUG,
 448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 449                 (enable ? "Adding" : "Removing"),
 450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 452                 ((index ==
 453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 467                 (enable ? "to" : "from"));
 468
 469         switch (mask) {
 470         case RT_IDX_CAM_HIT:
 471                 {
 472                         value = RT_IDX_DST_CAM_Q |      /* dest */
 473                             RT_IDX_TYPE_NICQ |  /* type */
 474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 475                         break;
 476                 }
 477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 478                 {
 479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 480                             RT_IDX_TYPE_NICQ |  /* type */
 481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 482                         break;
 483                 }
 484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 485                 {
 486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 487                             RT_IDX_TYPE_NICQ |  /* type */
 488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 489                         break;
 490                 }
 491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 492                 {
 493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 494                             RT_IDX_TYPE_NICQ |  /* type */
 495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 496                         break;
 497                 }
 498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 499                 {
 500                         value = RT_IDX_DST_CAM_Q |      /* dest */
 501                             RT_IDX_TYPE_NICQ |  /* type */
 502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 503                         break;
 504                 }
 505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 506                 {
 507                         value = RT_IDX_DST_CAM_Q |      /* dest */
 508                             RT_IDX_TYPE_NICQ |  /* type */
 509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 510                         break;
 511                 }
 512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 513                 {
 514                         value = RT_IDX_DST_RSS |        /* dest */
 515                             RT_IDX_TYPE_NICQ |  /* type */
 516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 517                         break;
 518                 }
 519         case 0:         /* Clear the E-bit on an entry. */
 520                 {
 521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 522                             RT_IDX_TYPE_NICQ |  /* type */
 523                             (index << RT_IDX_IDX_SHIFT);/* index */
 524                         break;
 525                 }
 526         default:
 527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 528                         mask);
 529                 status = -EPERM;
 530                 goto exit;
 531         }
 532
 533         if (value) {
 534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 535                 if (status)
 536                         goto exit;
 537                 value |= (enable ? RT_IDX_E : 0);
 538                 ql_write32(qdev, RT_IDX, value);
 539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 540         }
 541 exit:
 542         return status;
 543 }
 544
 545 static void ql_enable_interrupts(struct ql_adapter *qdev)
 546 {
 547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 548 }
 549
 550 static void ql_disable_interrupts(struct ql_adapter *qdev)
 551 {
 552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 553 }
 554
 555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 556  * Otherwise, we may have multiple outstanding workers and don't want to
 557  * enable until the last one finishes. In this case, the irq_cnt gets
 558  * incremented everytime we queue a worker and decremented everytime
 559  * a worker finishes.  Once it hits zero we enable the interrupt.
 560  */
 561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 562 {
 563         u32 var = 0;
 564         unsigned long hw_flags = 0;
 565         struct intr_context *ctx = qdev->intr_context + intr;
 566
 567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 568                 /* Always enable if we're MSIX multi interrupts and
 569                  * it's not the default (zeroeth) interrupt.
 570                  */
 571                 ql_write32(qdev, INTR_EN,
 572                            ctx->intr_en_mask);
 573                 var = ql_read32(qdev, STS);
 574                 return var;
 575         }
 576
 577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 579                 ql_write32(qdev, INTR_EN,
 580                            ctx->intr_en_mask);
 581                 var = ql_read32(qdev, STS);
 582         }
 583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 584         return var;
 585 }
 586
 587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 588 {
 589         u32 var = 0;
 590         unsigned long hw_flags;
 591         struct intr_context *ctx;
 592
 593         /* HW disables for us if we're MSIX multi interrupts and
 594          * it's not the default (zeroeth) interrupt.
 595          */
 596         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 597                 return 0;
 598
 599         ctx = qdev->intr_context + intr;
 600         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 601         if (!atomic_read(&ctx->irq_cnt)) {
 602                 ql_write32(qdev, INTR_EN,
 603                 ctx->intr_dis_mask);
 604                 var = ql_read32(qdev, STS);
 605         }
 606         atomic_inc(&ctx->irq_cnt);
 607         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 608         return var;
 609 }
 610
 611 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 612 {
 613         int i;
 614         for (i = 0; i < qdev->intr_count; i++) {
 615                 /* The enable call does a atomic_dec_and_test
 616                  * and enables only if the result is zero.
 617                  * So we precharge it here.
 618                  */
 619                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 620                         i == 0))
 621                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 622                 ql_enable_completion_interrupt(qdev, i);
 623         }
 624
 625 }
 626
 627 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
 628 {
 629         int status, i;
 630         u16 csum = 0;
 631         __le16 *flash = (__le16 *)&qdev->flash;
 632
 633         status = strncmp((char *)&qdev->flash, str, 4);
 634         if (status) {
 635                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
 636                 return  status;
 637         }
 638
 639         for (i = 0; i < size; i++)
 640                 csum += le16_to_cpu(*flash++);
 641
 642         if (csum)
 643                 QPRINTK(qdev, IFUP, ERR,
 644                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
 645
 646         return csum;
 647 }
 648
 649 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 650 {
 651         int status = 0;
 652         /* wait for reg to come ready */
 653         status = ql_wait_reg_rdy(qdev,
 654                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 655         if (status)
 656                 goto exit;
 657         /* set up for reg read */
 658         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 659         /* wait for reg to come ready */
 660         status = ql_wait_reg_rdy(qdev,
 661                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 662         if (status)
 663                 goto exit;
 664          /* This data is stored on flash as an array of
 665          * __le32.  Since ql_read32() returns cpu endian
 666          * we need to swap it back.
 667          */
 668         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 669 exit:
 670         return status;
 671 }
 672
 673 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
 674 {
 675         u32 i, size;
 676         int status;
 677         __le32 *p = (__le32 *)&qdev->flash;
 678         u32 offset;
 679
 680         /* Get flash offset for function and adjust
 681          * for dword access.
 682          */
 683         if (!qdev->func)
 684                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
 685         else
 686                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
 687
 688         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 689                 return -ETIMEDOUT;
 690
 691         size = sizeof(struct flash_params_8000) / sizeof(u32);
 692         for (i = 0; i < size; i++, p++) {
 693                 status = ql_read_flash_word(qdev, i+offset, p);
 694                 if (status) {
 695                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 696                         goto exit;
 697                 }
 698         }
 699
 700         status = ql_validate_flash(qdev,
 701                         sizeof(struct flash_params_8000) / sizeof(u16),
 702                         "8000");
 703         if (status) {
 704                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 705                 status = -EINVAL;
 706                 goto exit;
 707         }
 708
 709         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
 710                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
 711                 status = -EINVAL;
 712                 goto exit;
 713         }
 714
 715         memcpy(qdev->ndev->dev_addr,
 716                 qdev->flash.flash_params_8000.mac_addr,
 717                 qdev->ndev->addr_len);
 718
 719 exit:
 720         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 721         return status;
 722 }
 723
 724 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
 725 {
 726         int i;
 727         int status;
 728         __le32 *p = (__le32 *)&qdev->flash;
 729         u32 offset = 0;
 730         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
 731
 732         /* Second function's parameters follow the first
 733          * function's.
 734          */
 735         if (qdev->func)
 736                 offset = size;
 737
 738         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 739                 return -ETIMEDOUT;
 740
 741         for (i = 0; i < size; i++, p++) {
 742                 status = ql_read_flash_word(qdev, i+offset, p);
 743                 if (status) {
 744                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 745                         goto exit;
 746                 }
 747
 748         }
 749
 750         status = ql_validate_flash(qdev,
 751                         sizeof(struct flash_params_8012) / sizeof(u16),
 752                         "8012");
 753         if (status) {
 754                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 755                 status = -EINVAL;
 756                 goto exit;
 757         }
 758
 759         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
 760                 status = -EINVAL;
 761                 goto exit;
 762         }
 763
 764         memcpy(qdev->ndev->dev_addr,
 765                 qdev->flash.flash_params_8012.mac_addr,
 766                 qdev->ndev->addr_len);
 767
 768 exit:
 769         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 770         return status;
 771 }
 772
 773 /* xgmac register are located behind the xgmac_addr and xgmac_data
 774  * register pair.  Each read/write requires us to wait for the ready
 775  * bit before reading/writing the data.
 776  */
 777 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 778 {
 779         int status;
 780         /* wait for reg to come ready */
 781         status = ql_wait_reg_rdy(qdev,
 782                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 783         if (status)
 784                 return status;
 785         /* write the data to the data reg */
 786         ql_write32(qdev, XGMAC_DATA, data);
 787         /* trigger the write */
 788         ql_write32(qdev, XGMAC_ADDR, reg);
 789         return status;
 790 }
 791
 792 /* xgmac register are located behind the xgmac_addr and xgmac_data
 793  * register pair.  Each read/write requires us to wait for the ready
 794  * bit before reading/writing the data.
 795  */
 796 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 797 {
 798         int status = 0;
 799         /* wait for reg to come ready */
 800         status = ql_wait_reg_rdy(qdev,
 801                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 802         if (status)
 803                 goto exit;
 804         /* set up for reg read */
 805         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 806         /* wait for reg to come ready */
 807         status = ql_wait_reg_rdy(qdev,
 808                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 809         if (status)
 810                 goto exit;
 811         /* get the data */
 812         *data = ql_read32(qdev, XGMAC_DATA);
 813 exit:
 814         return status;
 815 }
 816
 817 /* This is used for reading the 64-bit statistics regs. */
 818 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 819 {
 820         int status = 0;
 821         u32 hi = 0;
 822         u32 lo = 0;
 823
 824         status = ql_read_xgmac_reg(qdev, reg, &lo);
 825         if (status)
 826                 goto exit;
 827
 828         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 829         if (status)
 830                 goto exit;
 831
 832         *data = (u64) lo | ((u64) hi << 32);
 833
 834 exit:
 835         return status;
 836 }
 837
 838 static int ql_8000_port_initialize(struct ql_adapter *qdev)
 839 {
 840         int status;
 841         status = ql_mb_get_fw_state(qdev);
 842         if (status)
 843                 goto exit;
 844         /* Wake up a worker to get/set the TX/RX frame sizes. */
 845         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
 846 exit:
 847         return status;
 848 }
 849
 850 /* Take the MAC Core out of reset.
 851  * Enable statistics counting.
 852  * Take the transmitter/receiver out of reset.
 853  * This functionality may be done in the MPI firmware at a
 854  * later date.
 855  */
 856 static int ql_8012_port_initialize(struct ql_adapter *qdev)
 857 {
 858         int status = 0;
 859         u32 data;
 860
 861         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 862                 /* Another function has the semaphore, so
 863                  * wait for the port init bit to come ready.
 864                  */
 865                 QPRINTK(qdev, LINK, INFO,
 866                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 867                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 868                 if (status) {
 869                         QPRINTK(qdev, LINK, CRIT,
 870                                 "Port initialize timed out.\n");
 871                 }
 872                 return status;
 873         }
 874
 875         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 876         /* Set the core reset. */
 877         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 878         if (status)
 879                 goto end;
 880         data |= GLOBAL_CFG_RESET;
 881         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 882         if (status)
 883                 goto end;
 884
 885         /* Clear the core reset and turn on jumbo for receiver. */
 886         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 887         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 888         data |= GLOBAL_CFG_TX_STAT_EN;
 889         data |= GLOBAL_CFG_RX_STAT_EN;
 890         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 891         if (status)
 892                 goto end;
 893
 894         /* Enable transmitter, and clear it's reset. */
 895         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 896         if (status)
 897                 goto end;
 898         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 899         data |= TX_CFG_EN;      /* Enable the transmitter. */
 900         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 901         if (status)
 902                 goto end;
 903
 904         /* Enable receiver and clear it's reset. */
 905         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 906         if (status)
 907                 goto end;
 908         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 909         data |= RX_CFG_EN;      /* Enable the receiver. */
 910         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 911         if (status)
 912                 goto end;
 913
 914         /* Turn on jumbo. */
 915         status =
 916             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 917         if (status)
 918                 goto end;
 919         status =
 920             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 921         if (status)
 922                 goto end;
 923
 924         /* Signal to the world that the port is enabled.        */
 925         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 926 end:
 927         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 928         return status;
 929 }
 930
 931 /* Get the next large buffer. */
 932 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 933 {
 934         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 935         rx_ring->lbq_curr_idx++;
 936         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 937                 rx_ring->lbq_curr_idx = 0;
 938         rx_ring->lbq_free_cnt++;
 939         return lbq_desc;
 940 }
 941
 942 /* Get the next small buffer. */
 943 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 944 {
 945         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 946         rx_ring->sbq_curr_idx++;
 947         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 948                 rx_ring->sbq_curr_idx = 0;
 949         rx_ring->sbq_free_cnt++;
 950         return sbq_desc;
 951 }
 952
 953 /* Update an rx ring index. */
 954 static void ql_update_cq(struct rx_ring *rx_ring)
 955 {
 956         rx_ring->cnsmr_idx++;
 957         rx_ring->curr_entry++;
 958         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 959                 rx_ring->cnsmr_idx = 0;
 960                 rx_ring->curr_entry = rx_ring->cq_base;
 961         }
 962 }
 963
 964 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 965 {
 966         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 967 }
 968
 969 /* Process (refill) a large buffer queue. */
 970 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 971 {
 972         u32 clean_idx = rx_ring->lbq_clean_idx;
 973         u32 start_idx = clean_idx;
 974         struct bq_desc *lbq_desc;
 975         u64 map;
 976         int i;
 977
 978         while (rx_ring->lbq_free_cnt > 16) {
 979                 for (i = 0; i < 16; i++) {
 980                         QPRINTK(qdev, RX_STATUS, DEBUG,
 981                                 "lbq: try cleaning clean_idx = %d.\n",
 982                                 clean_idx);
 983                         lbq_desc = &rx_ring->lbq[clean_idx];
 984                         if (lbq_desc->p.lbq_page == NULL) {
 985                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 986                                         "lbq: getting new page for index %d.\n",
 987                                         lbq_desc->index);
 988                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 989                                 if (lbq_desc->p.lbq_page == NULL) {
 990                                         rx_ring->lbq_clean_idx = clean_idx;
 991                                         QPRINTK(qdev, RX_STATUS, ERR,
 992                                                 "Couldn't get a page.\n");
 993                                         return;
 994                                 }
 995                                 map = pci_map_page(qdev->pdev,
 996                                                    lbq_desc->p.lbq_page,
 997                                                    0, PAGE_SIZE,
 998                                                    PCI_DMA_FROMDEVICE);
 999                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1000                                         rx_ring->lbq_clean_idx = clean_idx;
1001                                         put_page(lbq_desc->p.lbq_page);
1002                                         lbq_desc->p.lbq_page = NULL;
1003                                         QPRINTK(qdev, RX_STATUS, ERR,
1004                                                 "PCI mapping failed.\n");
1005                                         return;
1006                                 }
1007                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1008                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1009                                 *lbq_desc->addr = cpu_to_le64(map);
1010                         }
1011                         clean_idx++;
1012                         if (clean_idx == rx_ring->lbq_len)
1013                                 clean_idx = 0;
1014                 }
1015
1016                 rx_ring->lbq_clean_idx = clean_idx;
1017                 rx_ring->lbq_prod_idx += 16;
1018                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1019                         rx_ring->lbq_prod_idx = 0;
1020                 rx_ring->lbq_free_cnt -= 16;
1021         }
1022
1023         if (start_idx != clean_idx) {
1024                 QPRINTK(qdev, RX_STATUS, DEBUG,
1025                         "lbq: updating prod idx = %d.\n",
1026                         rx_ring->lbq_prod_idx);
1027                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1028                                 rx_ring->lbq_prod_idx_db_reg);
1029         }
1030 }
1031
1032 /* Process (refill) a small buffer queue. */
1033 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1034 {
1035         u32 clean_idx = rx_ring->sbq_clean_idx;
1036         u32 start_idx = clean_idx;
1037         struct bq_desc *sbq_desc;
1038         u64 map;
1039         int i;
1040
1041         while (rx_ring->sbq_free_cnt > 16) {
1042                 for (i = 0; i < 16; i++) {
1043                         sbq_desc = &rx_ring->sbq[clean_idx];
1044                         QPRINTK(qdev, RX_STATUS, DEBUG,
1045                                 "sbq: try cleaning clean_idx = %d.\n",
1046                                 clean_idx);
1047                         if (sbq_desc->p.skb == NULL) {
1048                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1049                                         "sbq: getting new skb for index %d.\n",
1050                                         sbq_desc->index);
1051                                 sbq_desc->p.skb =
1052                                     netdev_alloc_skb(qdev->ndev,
1053                                                      rx_ring->sbq_buf_size);
1054                                 if (sbq_desc->p.skb == NULL) {
1055                                         QPRINTK(qdev, PROBE, ERR,
1056                                                 "Couldn't get an skb.\n");
1057                                         rx_ring->sbq_clean_idx = clean_idx;
1058                                         return;
1059                                 }
1060                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1061                                 map = pci_map_single(qdev->pdev,
1062                                                      sbq_desc->p.skb->data,
1063                                                      rx_ring->sbq_buf_size /
1064                                                      2, PCI_DMA_FROMDEVICE);
1065                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1066                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1067                                         rx_ring->sbq_clean_idx = clean_idx;
1068                                         dev_kfree_skb_any(sbq_desc->p.skb);
1069                                         sbq_desc->p.skb = NULL;
1070                                         return;
1071                                 }
1072                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1073                                 pci_unmap_len_set(sbq_desc, maplen,
1074                                                   rx_ring->sbq_buf_size / 2);
1075                                 *sbq_desc->addr = cpu_to_le64(map);
1076                         }
1077
1078                         clean_idx++;
1079                         if (clean_idx == rx_ring->sbq_len)
1080                                 clean_idx = 0;
1081                 }
1082                 rx_ring->sbq_clean_idx = clean_idx;
1083                 rx_ring->sbq_prod_idx += 16;
1084                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1085                         rx_ring->sbq_prod_idx = 0;
1086                 rx_ring->sbq_free_cnt -= 16;
1087         }
1088
1089         if (start_idx != clean_idx) {
1090                 QPRINTK(qdev, RX_STATUS, DEBUG,
1091                         "sbq: updating prod idx = %d.\n",
1092                         rx_ring->sbq_prod_idx);
1093                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1094                                 rx_ring->sbq_prod_idx_db_reg);
1095         }
1096 }
1097
1098 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1099                                     struct rx_ring *rx_ring)
1100 {
1101         ql_update_sbq(qdev, rx_ring);
1102         ql_update_lbq(qdev, rx_ring);
1103 }
1104
1105 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1106  * fails at some stage, or from the interrupt when a tx completes.
1107  */
1108 static void ql_unmap_send(struct ql_adapter *qdev,
1109                           struct tx_ring_desc *tx_ring_desc, int mapped)
1110 {
1111         int i;
1112         for (i = 0; i < mapped; i++) {
1113                 if (i == 0 || (i == 7 && mapped > 7)) {
1114                         /*
1115                          * Unmap the skb->data area, or the
1116                          * external sglist (AKA the Outbound
1117                          * Address List (OAL)).
1118                          * If its the zeroeth element, then it's
1119                          * the skb->data area.  If it's the 7th
1120                          * element and there is more than 6 frags,
1121                          * then its an OAL.
1122                          */
1123                         if (i == 7) {
1124                                 QPRINTK(qdev, TX_DONE, DEBUG,
1125                                         "unmapping OAL area.\n");
1126                         }
1127                         pci_unmap_single(qdev->pdev,
1128                                          pci_unmap_addr(&tx_ring_desc->map[i],
1129                                                         mapaddr),
1130                                          pci_unmap_len(&tx_ring_desc->map[i],
1131                                                        maplen),
1132                                          PCI_DMA_TODEVICE);
1133                 } else {
1134                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1135                                 i);
1136                         pci_unmap_page(qdev->pdev,
1137                                        pci_unmap_addr(&tx_ring_desc->map[i],
1138                                                       mapaddr),
1139                                        pci_unmap_len(&tx_ring_desc->map[i],
1140                                                      maplen), PCI_DMA_TODEVICE);
1141                 }
1142         }
1143
1144 }
1145
1146 /* Map the buffers for this transmit.  This will return
1147  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1148  */
1149 static int ql_map_send(struct ql_adapter *qdev,
1150                        struct ob_mac_iocb_req *mac_iocb_ptr,
1151                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1152 {
1153         int len = skb_headlen(skb);
1154         dma_addr_t map;
1155         int frag_idx, err, map_idx = 0;
1156         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1157         int frag_cnt = skb_shinfo(skb)->nr_frags;
1158
1159         if (frag_cnt) {
1160                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1161         }
1162         /*
1163          * Map the skb buffer first.
1164          */
1165         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1166
1167         err = pci_dma_mapping_error(qdev->pdev, map);
1168         if (err) {
1169                 QPRINTK(qdev, TX_QUEUED, ERR,
1170                         "PCI mapping failed with error: %d\n", err);
1171
1172                 return NETDEV_TX_BUSY;
1173         }
1174
1175         tbd->len = cpu_to_le32(len);
1176         tbd->addr = cpu_to_le64(map);
1177         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1178         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1179         map_idx++;
1180
1181         /*
1182          * This loop fills the remainder of the 8 address descriptors
1183          * in the IOCB.  If there are more than 7 fragments, then the
1184          * eighth address desc will point to an external list (OAL).
1185          * When this happens, the remainder of the frags will be stored
1186          * in this list.
1187          */
1188         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1189                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1190                 tbd++;
1191                 if (frag_idx == 6 && frag_cnt > 7) {
1192                         /* Let's tack on an sglist.
1193                          * Our control block will now
1194                          * look like this:
1195                          * iocb->seg[0] = skb->data
1196                          * iocb->seg[1] = frag[0]
1197                          * iocb->seg[2] = frag[1]
1198                          * iocb->seg[3] = frag[2]
1199                          * iocb->seg[4] = frag[3]
1200                          * iocb->seg[5] = frag[4]
1201                          * iocb->seg[6] = frag[5]
1202                          * iocb->seg[7] = ptr to OAL (external sglist)
1203                          * oal->seg[0] = frag[6]
1204                          * oal->seg[1] = frag[7]
1205                          * oal->seg[2] = frag[8]
1206                          * oal->seg[3] = frag[9]
1207                          * oal->seg[4] = frag[10]
1208                          *      etc...
1209                          */
1210                         /* Tack on the OAL in the eighth segment of IOCB. */
1211                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1212                                              sizeof(struct oal),
1213                                              PCI_DMA_TODEVICE);
1214                         err = pci_dma_mapping_error(qdev->pdev, map);
1215                         if (err) {
1216                                 QPRINTK(qdev, TX_QUEUED, ERR,
1217                                         "PCI mapping outbound address list with error: %d\n",
1218                                         err);
1219                                 goto map_error;
1220                         }
1221
1222                         tbd->addr = cpu_to_le64(map);
1223                         /*
1224                          * The length is the number of fragments
1225                          * that remain to be mapped times the length
1226                          * of our sglist (OAL).
1227                          */
1228                         tbd->len =
1229                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1230                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1231                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1232                                            map);
1233                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1234                                           sizeof(struct oal));
1235                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1236                         map_idx++;
1237                 }
1238
1239                 map =
1240                     pci_map_page(qdev->pdev, frag->page,
1241                                  frag->page_offset, frag->size,
1242                                  PCI_DMA_TODEVICE);
1243
1244                 err = pci_dma_mapping_error(qdev->pdev, map);
1245                 if (err) {
1246                         QPRINTK(qdev, TX_QUEUED, ERR,
1247                                 "PCI mapping frags failed with error: %d.\n",
1248                                 err);
1249                         goto map_error;
1250                 }
1251
1252                 tbd->addr = cpu_to_le64(map);
1253                 tbd->len = cpu_to_le32(frag->size);
1254                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1255                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1256                                   frag->size);
1257
1258         }
1259         /* Save the number of segments we've mapped. */
1260         tx_ring_desc->map_cnt = map_idx;
1261         /* Terminate the last segment. */
1262         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1263         return NETDEV_TX_OK;
1264
1265 map_error:
1266         /*
1267          * If the first frag mapping failed, then i will be zero.
1268          * This causes the unmap of the skb->data area.  Otherwise
1269          * we pass in the number of frags that mapped successfully
1270          * so they can be umapped.
1271          */
1272         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1273         return NETDEV_TX_BUSY;
1274 }
1275
1276 static void ql_realign_skb(struct sk_buff *skb, int len)
1277 {
1278         void *temp_addr = skb->data;
1279
1280         /* Undo the skb_reserve(skb,32) we did before
1281          * giving to hardware, and realign data on
1282          * a 2-byte boundary.
1283          */
1284         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1285         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1286         skb_copy_to_linear_data(skb, temp_addr,
1287                 (unsigned int)len);
1288 }
1289
1290 /*
1291  * This function builds an skb for the given inbound
1292  * completion.  It will be rewritten for readability in the near
1293  * future, but for not it works well.
1294  */
1295 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1296                                        struct rx_ring *rx_ring,
1297                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1298 {
1299         struct bq_desc *lbq_desc;
1300         struct bq_desc *sbq_desc;
1301         struct sk_buff *skb = NULL;
1302         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1303        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1304
1305         /*
1306          * Handle the header buffer if present.
1307          */
1308         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1309             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1310                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1311                 /*
1312                  * Headers fit nicely into a small buffer.
1313                  */
1314                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1315                 pci_unmap_single(qdev->pdev,
1316                                 pci_unmap_addr(sbq_desc, mapaddr),
1317                                 pci_unmap_len(sbq_desc, maplen),
1318                                 PCI_DMA_FROMDEVICE);
1319                 skb = sbq_desc->p.skb;
1320                 ql_realign_skb(skb, hdr_len);
1321                 skb_put(skb, hdr_len);
1322                 sbq_desc->p.skb = NULL;
1323         }
1324
1325         /*
1326          * Handle the data buffer(s).
1327          */
1328         if (unlikely(!length)) {        /* Is there data too? */
1329                 QPRINTK(qdev, RX_STATUS, DEBUG,
1330                         "No Data buffer in this packet.\n");
1331                 return skb;
1332         }
1333
1334         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1335                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1336                         QPRINTK(qdev, RX_STATUS, DEBUG,
1337                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1338                         /*
1339                          * Data is less than small buffer size so it's
1340                          * stuffed in a small buffer.
1341                          * For this case we append the data
1342                          * from the "data" small buffer to the "header" small
1343                          * buffer.
1344                          */
1345                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1346                         pci_dma_sync_single_for_cpu(qdev->pdev,
1347                                                     pci_unmap_addr
1348                                                     (sbq_desc, mapaddr),
1349                                                     pci_unmap_len
1350                                                     (sbq_desc, maplen),
1351                                                     PCI_DMA_FROMDEVICE);
1352                         memcpy(skb_put(skb, length),
1353                                sbq_desc->p.skb->data, length);
1354                         pci_dma_sync_single_for_device(qdev->pdev,
1355                                                        pci_unmap_addr
1356                                                        (sbq_desc,
1357                                                         mapaddr),
1358                                                        pci_unmap_len
1359                                                        (sbq_desc,
1360                                                         maplen),
1361                                                        PCI_DMA_FROMDEVICE);
1362                 } else {
1363                         QPRINTK(qdev, RX_STATUS, DEBUG,
1364                                 "%d bytes in a single small buffer.\n", length);
1365                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1366                         skb = sbq_desc->p.skb;
1367                         ql_realign_skb(skb, length);
1368                         skb_put(skb, length);
1369                         pci_unmap_single(qdev->pdev,
1370                                          pci_unmap_addr(sbq_desc,
1371                                                         mapaddr),
1372                                          pci_unmap_len(sbq_desc,
1373                                                        maplen),
1374                                          PCI_DMA_FROMDEVICE);
1375                         sbq_desc->p.skb = NULL;
1376                 }
1377         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1378                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1379                         QPRINTK(qdev, RX_STATUS, DEBUG,
1380                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1381                         /*
1382                          * The data is in a single large buffer.  We
1383                          * chain it to the header buffer's skb and let
1384                          * it rip.
1385                          */
1386                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1387                         pci_unmap_page(qdev->pdev,
1388                                        pci_unmap_addr(lbq_desc,
1389                                                       mapaddr),
1390                                        pci_unmap_len(lbq_desc, maplen),
1391                                        PCI_DMA_FROMDEVICE);
1392                         QPRINTK(qdev, RX_STATUS, DEBUG,
1393                                 "Chaining page to skb.\n");
1394                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1395                                            0, length);
1396                         skb->len += length;
1397                         skb->data_len += length;
1398                         skb->truesize += length;
1399                         lbq_desc->p.lbq_page = NULL;
1400                 } else {
1401                         /*
1402                          * The headers and data are in a single large buffer. We
1403                          * copy it to a new skb and let it go. This can happen with
1404                          * jumbo mtu on a non-TCP/UDP frame.
1405                          */
1406                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1407                         skb = netdev_alloc_skb(qdev->ndev, length);
1408                         if (skb == NULL) {
1409                                 QPRINTK(qdev, PROBE, DEBUG,
1410                                         "No skb available, drop the packet.\n");
1411                                 return NULL;
1412                         }
1413                         pci_unmap_page(qdev->pdev,
1414                                        pci_unmap_addr(lbq_desc,
1415                                                       mapaddr),
1416                                        pci_unmap_len(lbq_desc, maplen),
1417                                        PCI_DMA_FROMDEVICE);
1418                         skb_reserve(skb, NET_IP_ALIGN);
1419                         QPRINTK(qdev, RX_STATUS, DEBUG,
1420                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1421                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1422                                            0, length);
1423                         skb->len += length;
1424                         skb->data_len += length;
1425                         skb->truesize += length;
1426                         length -= length;
1427                         lbq_desc->p.lbq_page = NULL;
1428                         __pskb_pull_tail(skb,
1429                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1430                                 VLAN_ETH_HLEN : ETH_HLEN);
1431                 }
1432         } else {
1433                 /*
1434                  * The data is in a chain of large buffers
1435                  * pointed to by a small buffer.  We loop
1436                  * thru and chain them to the our small header
1437                  * buffer's skb.
1438                  * frags:  There are 18 max frags and our small
1439                  *         buffer will hold 32 of them. The thing is,
1440                  *         we'll use 3 max for our 9000 byte jumbo
1441                  *         frames.  If the MTU goes up we could
1442                  *          eventually be in trouble.
1443                  */
1444                 int size, offset, i = 0;
1445                 __le64 *bq, bq_array[8];
1446                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1447                 pci_unmap_single(qdev->pdev,
1448                                  pci_unmap_addr(sbq_desc, mapaddr),
1449                                  pci_unmap_len(sbq_desc, maplen),
1450                                  PCI_DMA_FROMDEVICE);
1451                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1452                         /*
1453                          * This is an non TCP/UDP IP frame, so
1454                          * the headers aren't split into a small
1455                          * buffer.  We have to use the small buffer
1456                          * that contains our sg list as our skb to
1457                          * send upstairs. Copy the sg list here to
1458                          * a local buffer and use it to find the
1459                          * pages to chain.
1460                          */
1461                         QPRINTK(qdev, RX_STATUS, DEBUG,
1462                                 "%d bytes of headers & data in chain of large.\n", length);
1463                         skb = sbq_desc->p.skb;
1464                         bq = &bq_array[0];
1465                         memcpy(bq, skb->data, sizeof(bq_array));
1466                         sbq_desc->p.skb = NULL;
1467                         skb_reserve(skb, NET_IP_ALIGN);
1468                 } else {
1469                         QPRINTK(qdev, RX_STATUS, DEBUG,
1470                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1471                         bq = (__le64 *)sbq_desc->p.skb->data;
1472                 }
1473                 while (length > 0) {
1474                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1475                         pci_unmap_page(qdev->pdev,
1476                                        pci_unmap_addr(lbq_desc,
1477                                                       mapaddr),
1478                                        pci_unmap_len(lbq_desc,
1479                                                      maplen),
1480                                        PCI_DMA_FROMDEVICE);
1481                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1482                         offset = 0;
1483
1484                         QPRINTK(qdev, RX_STATUS, DEBUG,
1485                                 "Adding page %d to skb for %d bytes.\n",
1486                                 i, size);
1487                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1488                                            offset, size);
1489                         skb->len += size;
1490                         skb->data_len += size;
1491                         skb->truesize += size;
1492                         length -= size;
1493                         lbq_desc->p.lbq_page = NULL;
1494                         bq++;
1495                         i++;
1496                 }
1497                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1498                                 VLAN_ETH_HLEN : ETH_HLEN);
1499         }
1500         return skb;
1501 }
1502
1503 /* Process an inbound completion from an rx ring. */
1504 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1505                                    struct rx_ring *rx_ring,
1506                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1507 {
1508         struct net_device *ndev = qdev->ndev;
1509         struct sk_buff *skb = NULL;
1510
1511         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1512
1513         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1514         if (unlikely(!skb)) {
1515                 QPRINTK(qdev, RX_STATUS, DEBUG,
1516                         "No skb available, drop packet.\n");
1517                 return;
1518         }
1519
1520         prefetch(skb->data);
1521         skb->dev = ndev;
1522         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1523                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1524                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1525                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1526                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1527                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1528                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1529                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1530         }
1531         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1532                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1533         }
1534         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1535                 QPRINTK(qdev, RX_STATUS, ERR,
1536                         "Bad checksum for this %s packet.\n",
1537                         ((ib_mac_rsp->
1538                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1539                 skb->ip_summed = CHECKSUM_NONE;
1540         } else if (qdev->rx_csum &&
1541                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1542                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1543                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1544                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1545                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1546         }
1547         qdev->stats.rx_packets++;
1548         qdev->stats.rx_bytes += skb->len;
1549         skb->protocol = eth_type_trans(skb, ndev);
1550         skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1551         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1552                 QPRINTK(qdev, RX_STATUS, DEBUG,
1553                         "Passing a VLAN packet upstream.\n");
1554                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1555                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1556         } else {
1557                 QPRINTK(qdev, RX_STATUS, DEBUG,
1558                         "Passing a normal packet upstream.\n");
1559                 netif_receive_skb(skb);
1560         }
1561 }
1562
1563 /* Process an outbound completion from an rx ring. */
1564 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1565                                    struct ob_mac_iocb_rsp *mac_rsp)
1566 {
1567         struct tx_ring *tx_ring;
1568         struct tx_ring_desc *tx_ring_desc;
1569
1570         QL_DUMP_OB_MAC_RSP(mac_rsp);
1571         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1572         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1573         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1574         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1575         qdev->stats.tx_packets++;
1576         dev_kfree_skb(tx_ring_desc->skb);
1577         tx_ring_desc->skb = NULL;
1578
1579         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1580                                         OB_MAC_IOCB_RSP_S |
1581                                         OB_MAC_IOCB_RSP_L |
1582                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1583                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1584                         QPRINTK(qdev, TX_DONE, WARNING,
1585                                 "Total descriptor length did not match transfer length.\n");
1586                 }
1587                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1588                         QPRINTK(qdev, TX_DONE, WARNING,
1589                                 "Frame too short to be legal, not sent.\n");
1590                 }
1591                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1592                         QPRINTK(qdev, TX_DONE, WARNING,
1593                                 "Frame too long, but sent anyway.\n");
1594                 }
1595                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1596                         QPRINTK(qdev, TX_DONE, WARNING,
1597                                 "PCI backplane error. Frame not sent.\n");
1598                 }
1599         }
1600         atomic_inc(&tx_ring->tx_count);
1601 }
1602
1603 /* Fire up a handler to reset the MPI processor. */
1604 void ql_queue_fw_error(struct ql_adapter *qdev)
1605 {
1606         netif_stop_queue(qdev->ndev);
1607         netif_carrier_off(qdev->ndev);
1608         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1609 }
1610
1611 void ql_queue_asic_error(struct ql_adapter *qdev)
1612 {
1613         netif_stop_queue(qdev->ndev);
1614         netif_carrier_off(qdev->ndev);
1615         ql_disable_interrupts(qdev);
1616         /* Clear adapter up bit to signal the recovery
1617          * process that it shouldn't kill the reset worker
1618          * thread
1619          */
1620         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1621         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1622 }
1623
1624 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1625                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1626 {
1627         switch (ib_ae_rsp->event) {
1628         case MGMT_ERR_EVENT:
1629                 QPRINTK(qdev, RX_ERR, ERR,
1630                         "Management Processor Fatal Error.\n");
1631                 ql_queue_fw_error(qdev);
1632                 return;
1633
1634         case CAM_LOOKUP_ERR_EVENT:
1635                 QPRINTK(qdev, LINK, ERR,
1636                         "Multiple CAM hits lookup occurred.\n");
1637                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1638                 ql_queue_asic_error(qdev);
1639                 return;
1640
1641         case SOFT_ECC_ERROR_EVENT:
1642                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1643                 ql_queue_asic_error(qdev);
1644                 break;
1645
1646         case PCI_ERR_ANON_BUF_RD:
1647                 QPRINTK(qdev, RX_ERR, ERR,
1648                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1649                         ib_ae_rsp->q_id);
1650                 ql_queue_asic_error(qdev);
1651                 break;
1652
1653         default:
1654                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1655                         ib_ae_rsp->event);
1656                 ql_queue_asic_error(qdev);
1657                 break;
1658         }
1659 }
1660
1661 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1662 {
1663         struct ql_adapter *qdev = rx_ring->qdev;
1664         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1665         struct ob_mac_iocb_rsp *net_rsp = NULL;
1666         int count = 0;
1667
1668         /* While there are entries in the completion queue. */
1669         while (prod != rx_ring->cnsmr_idx) {
1670
1671                 QPRINTK(qdev, RX_STATUS, DEBUG,
1672                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1673                         prod, rx_ring->cnsmr_idx);
1674
1675                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1676                 rmb();
1677                 switch (net_rsp->opcode) {
1678
1679                 case OPCODE_OB_MAC_TSO_IOCB:
1680                 case OPCODE_OB_MAC_IOCB:
1681                         ql_process_mac_tx_intr(qdev, net_rsp);
1682                         break;
1683                 default:
1684                         QPRINTK(qdev, RX_STATUS, DEBUG,
1685                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1686                                 net_rsp->opcode);
1687                 }
1688                 count++;
1689                 ql_update_cq(rx_ring);
1690                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1691         }
1692         ql_write_cq_idx(rx_ring);
1693         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1694                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1695                 if (atomic_read(&tx_ring->queue_stopped) &&
1696                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1697                         /*
1698                          * The queue got stopped because the tx_ring was full.
1699                          * Wake it up, because it's now at least 25% empty.
1700                          */
1701                         netif_wake_queue(qdev->ndev);
1702         }
1703
1704         return count;
1705 }
1706
1707 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1708 {
1709         struct ql_adapter *qdev = rx_ring->qdev;
1710         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1711         struct ql_net_rsp_iocb *net_rsp;
1712         int count = 0;
1713
1714         /* While there are entries in the completion queue. */
1715         while (prod != rx_ring->cnsmr_idx) {
1716
1717                 QPRINTK(qdev, RX_STATUS, DEBUG,
1718                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1719                         prod, rx_ring->cnsmr_idx);
1720
1721                 net_rsp = rx_ring->curr_entry;
1722                 rmb();
1723                 switch (net_rsp->opcode) {
1724                 case OPCODE_IB_MAC_IOCB:
1725                         ql_process_mac_rx_intr(qdev, rx_ring,
1726                                                (struct ib_mac_iocb_rsp *)
1727                                                net_rsp);
1728                         break;
1729
1730                 case OPCODE_IB_AE_IOCB:
1731                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1732                                                 net_rsp);
1733                         break;
1734                 default:
1735                         {
1736                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1737                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1738                                         net_rsp->opcode);
1739                         }
1740                 }
1741                 count++;
1742                 ql_update_cq(rx_ring);
1743                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1744                 if (count == budget)
1745                         break;
1746         }
1747         ql_update_buffer_queues(qdev, rx_ring);
1748         ql_write_cq_idx(rx_ring);
1749         return count;
1750 }
1751
1752 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1753 {
1754         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1755         struct ql_adapter *qdev = rx_ring->qdev;
1756         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1757
1758         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1759                 rx_ring->cq_id);
1760
1761         if (work_done < budget) {
1762                 __napi_complete(napi);
1763                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1764         }
1765         return work_done;
1766 }
1767
1768 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1769 {
1770         struct ql_adapter *qdev = netdev_priv(ndev);
1771
1772         qdev->vlgrp = grp;
1773         if (grp) {
1774                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1775                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1776                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1777         } else {
1778                 QPRINTK(qdev, IFUP, DEBUG,
1779                         "Turning off VLAN in NIC_RCV_CFG.\n");
1780                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1781         }
1782 }
1783
1784 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1785 {
1786         struct ql_adapter *qdev = netdev_priv(ndev);
1787         u32 enable_bit = MAC_ADDR_E;
1788         int status;
1789
1790         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1791         if (status)
1792                 return;
1793         spin_lock(&qdev->hw_lock);
1794         if (ql_set_mac_addr_reg
1795             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1796                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1797         }
1798         spin_unlock(&qdev->hw_lock);
1799         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1800 }
1801
1802 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1803 {
1804         struct ql_adapter *qdev = netdev_priv(ndev);
1805         u32 enable_bit = 0;
1806         int status;
1807
1808         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1809         if (status)
1810                 return;
1811
1812         spin_lock(&qdev->hw_lock);
1813         if (ql_set_mac_addr_reg
1814             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1815                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1816         }
1817         spin_unlock(&qdev->hw_lock);
1818         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1819
1820 }
1821
1822 /* Worker thread to process a given rx_ring that is dedicated
1823  * to outbound completions.
1824  */
1825 static void ql_tx_clean(struct work_struct *work)
1826 {
1827         struct rx_ring *rx_ring =
1828             container_of(work, struct rx_ring, rx_work.work);
1829         ql_clean_outbound_rx_ring(rx_ring);
1830         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1831
1832 }
1833
1834 /* Worker thread to process a given rx_ring that is dedicated
1835  * to inbound completions.
1836  */
1837 static void ql_rx_clean(struct work_struct *work)
1838 {
1839         struct rx_ring *rx_ring =
1840             container_of(work, struct rx_ring, rx_work.work);
1841         ql_clean_inbound_rx_ring(rx_ring, 64);
1842         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1843 }
1844
1845 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1846 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1847 {
1848         struct rx_ring *rx_ring = dev_id;
1849         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1850                               &rx_ring->rx_work, 0);
1851         return IRQ_HANDLED;
1852 }
1853
1854 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1855 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1856 {
1857         struct rx_ring *rx_ring = dev_id;
1858         napi_schedule(&rx_ring->napi);
1859         return IRQ_HANDLED;
1860 }
1861
1862 /* This handles a fatal error, MPI activity, and the default
1863  * rx_ring in an MSI-X multiple vector environment.
1864  * In MSI/Legacy environment it also process the rest of
1865  * the rx_rings.
1866  */
1867 static irqreturn_t qlge_isr(int irq, void *dev_id)
1868 {
1869         struct rx_ring *rx_ring = dev_id;
1870         struct ql_adapter *qdev = rx_ring->qdev;
1871         struct intr_context *intr_context = &qdev->intr_context[0];
1872         u32 var;
1873         int i;
1874         int work_done = 0;
1875
1876         spin_lock(&qdev->hw_lock);
1877         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1878                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1879                 spin_unlock(&qdev->hw_lock);
1880                 return IRQ_NONE;
1881         }
1882         spin_unlock(&qdev->hw_lock);
1883
1884         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1885
1886         /*
1887          * Check for fatal error.
1888          */
1889         if (var & STS_FE) {
1890                 ql_queue_asic_error(qdev);
1891                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1892                 var = ql_read32(qdev, ERR_STS);
1893                 QPRINTK(qdev, INTR, ERR,
1894                         "Resetting chip. Error Status Register = 0x%x\n", var);
1895                 return IRQ_HANDLED;
1896         }
1897
1898         /*
1899          * Check MPI processor activity.
1900          */
1901         if (var & STS_PI) {
1902                 /*
1903                  * We've got an async event or mailbox completion.
1904                  * Handle it and clear the source of the interrupt.
1905                  */
1906                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1907                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1908                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1909                                       &qdev->mpi_work, 0);
1910                 work_done++;
1911         }
1912
1913         /*
1914          * Check the default queue and wake handler if active.
1915          */
1916         rx_ring = &qdev->rx_ring[0];
1917         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1918                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1919                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1920                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1921                                       &rx_ring->rx_work, 0);
1922                 work_done++;
1923         }
1924
1925         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1926                 /*
1927                  * Start the DPC for each active queue.
1928                  */
1929                 for (i = 1; i < qdev->rx_ring_count; i++) {
1930                         rx_ring = &qdev->rx_ring[i];
1931                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1932                             rx_ring->cnsmr_idx) {
1933                                 QPRINTK(qdev, INTR, INFO,
1934                                         "Waking handler for rx_ring[%d].\n", i);
1935                                 ql_disable_completion_interrupt(qdev,
1936                                                                 intr_context->
1937                                                                 intr);
1938                                 if (i < qdev->rss_ring_first_cq_id)
1939                                         queue_delayed_work_on(rx_ring->cpu,
1940                                                               qdev->q_workqueue,
1941                                                               &rx_ring->rx_work,
1942                                                               0);
1943                                 else
1944                                         napi_schedule(&rx_ring->napi);
1945                                 work_done++;
1946                         }
1947                 }
1948         }
1949         ql_enable_completion_interrupt(qdev, intr_context->intr);
1950         return work_done ? IRQ_HANDLED : IRQ_NONE;
1951 }
1952
1953 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1954 {
1955
1956         if (skb_is_gso(skb)) {
1957                 int err;
1958                 if (skb_header_cloned(skb)) {
1959                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1960                         if (err)
1961                                 return err;
1962                 }
1963
1964                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1965                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1966                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1967                 mac_iocb_ptr->total_hdrs_len =
1968                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1969                 mac_iocb_ptr->net_trans_offset =
1970                     cpu_to_le16(skb_network_offset(skb) |
1971                                 skb_transport_offset(skb)
1972                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1973                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1974                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1975                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1976                         struct iphdr *iph = ip_hdr(skb);
1977                         iph->check = 0;
1978                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1979                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1980                                                                  iph->daddr, 0,
1981                                                                  IPPROTO_TCP,
1982                                                                  0);
1983                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1984                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1985                         tcp_hdr(skb)->check =
1986                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1987                                              &ipv6_hdr(skb)->daddr,
1988                                              0, IPPROTO_TCP, 0);
1989                 }
1990                 return 1;
1991         }
1992         return 0;
1993 }
1994
1995 static void ql_hw_csum_setup(struct sk_buff *skb,
1996                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1997 {
1998         int len;
1999         struct iphdr *iph = ip_hdr(skb);
2000         __sum16 *check;
2001         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2002         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2003         mac_iocb_ptr->net_trans_offset =
2004                 cpu_to_le16(skb_network_offset(skb) |
2005                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2006
2007         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2008         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2009         if (likely(iph->protocol == IPPROTO_TCP)) {
2010                 check = &(tcp_hdr(skb)->check);
2011                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2012                 mac_iocb_ptr->total_hdrs_len =
2013                     cpu_to_le16(skb_transport_offset(skb) +
2014                                 (tcp_hdr(skb)->doff << 2));
2015         } else {
2016                 check = &(udp_hdr(skb)->check);
2017                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2018                 mac_iocb_ptr->total_hdrs_len =
2019                     cpu_to_le16(skb_transport_offset(skb) +
2020                                 sizeof(struct udphdr));
2021         }
2022         *check = ~csum_tcpudp_magic(iph->saddr,
2023                                     iph->daddr, len, iph->protocol, 0);
2024 }
2025
2026 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2027 {
2028         struct tx_ring_desc *tx_ring_desc;
2029         struct ob_mac_iocb_req *mac_iocb_ptr;
2030         struct ql_adapter *qdev = netdev_priv(ndev);
2031         int tso;
2032         struct tx_ring *tx_ring;
2033         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
2034
2035         tx_ring = &qdev->tx_ring[tx_ring_idx];
2036
2037         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2038                 QPRINTK(qdev, TX_QUEUED, INFO,
2039                         "%s: shutting down tx queue %d du to lack of resources.\n",
2040                         __func__, tx_ring_idx);
2041                 netif_stop_queue(ndev);
2042                 atomic_inc(&tx_ring->queue_stopped);
2043                 return NETDEV_TX_BUSY;
2044         }
2045         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2046         mac_iocb_ptr = tx_ring_desc->queue_entry;
2047         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2048
2049         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2050         mac_iocb_ptr->tid = tx_ring_desc->index;
2051         /* We use the upper 32-bits to store the tx queue for this IO.
2052          * When we get the completion we can use it to establish the context.
2053          */
2054         mac_iocb_ptr->txq_idx = tx_ring_idx;
2055         tx_ring_desc->skb = skb;
2056
2057         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2058
2059         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2060                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2061                         vlan_tx_tag_get(skb));
2062                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2063                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2064         }
2065         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2066         if (tso < 0) {
2067                 dev_kfree_skb_any(skb);
2068                 return NETDEV_TX_OK;
2069         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2070                 ql_hw_csum_setup(skb,
2071                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2072         }
2073         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2074                         NETDEV_TX_OK) {
2075                 QPRINTK(qdev, TX_QUEUED, ERR,
2076                                 "Could not map the segments.\n");
2077                 return NETDEV_TX_BUSY;
2078         }
2079         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2080         tx_ring->prod_idx++;
2081         if (tx_ring->prod_idx == tx_ring->wq_len)
2082                 tx_ring->prod_idx = 0;
2083         wmb();
2084
2085         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2086         ndev->trans_start = jiffies;
2087         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2088                 tx_ring->prod_idx, skb->len);
2089
2090         atomic_dec(&tx_ring->tx_count);
2091         return NETDEV_TX_OK;
2092 }
2093
2094 static void ql_free_shadow_space(struct ql_adapter *qdev)
2095 {
2096         if (qdev->rx_ring_shadow_reg_area) {
2097                 pci_free_consistent(qdev->pdev,
2098                                     PAGE_SIZE,
2099                                     qdev->rx_ring_shadow_reg_area,
2100                                     qdev->rx_ring_shadow_reg_dma);
2101                 qdev->rx_ring_shadow_reg_area = NULL;
2102         }
2103         if (qdev->tx_ring_shadow_reg_area) {
2104                 pci_free_consistent(qdev->pdev,
2105                                     PAGE_SIZE,
2106                                     qdev->tx_ring_shadow_reg_area,
2107                                     qdev->tx_ring_shadow_reg_dma);
2108                 qdev->tx_ring_shadow_reg_area = NULL;
2109         }
2110 }
2111
2112 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2113 {
2114         qdev->rx_ring_shadow_reg_area =
2115             pci_alloc_consistent(qdev->pdev,
2116                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2117         if (qdev->rx_ring_shadow_reg_area == NULL) {
2118                 QPRINTK(qdev, IFUP, ERR,
2119                         "Allocation of RX shadow space failed.\n");
2120                 return -ENOMEM;
2121         }
2122         qdev->tx_ring_shadow_reg_area =
2123             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2124                                  &qdev->tx_ring_shadow_reg_dma);
2125         if (qdev->tx_ring_shadow_reg_area == NULL) {
2126                 QPRINTK(qdev, IFUP, ERR,
2127                         "Allocation of TX shadow space failed.\n");
2128                 goto err_wqp_sh_area;
2129         }
2130         return 0;
2131
2132 err_wqp_sh_area:
2133         pci_free_consistent(qdev->pdev,
2134                             PAGE_SIZE,
2135                             qdev->rx_ring_shadow_reg_area,
2136                             qdev->rx_ring_shadow_reg_dma);
2137         return -ENOMEM;
2138 }
2139
2140 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2141 {
2142         struct tx_ring_desc *tx_ring_desc;
2143         int i;
2144         struct ob_mac_iocb_req *mac_iocb_ptr;
2145
2146         mac_iocb_ptr = tx_ring->wq_base;
2147         tx_ring_desc = tx_ring->q;
2148         for (i = 0; i < tx_ring->wq_len; i++) {
2149                 tx_ring_desc->index = i;
2150                 tx_ring_desc->skb = NULL;
2151                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2152                 mac_iocb_ptr++;
2153                 tx_ring_desc++;
2154         }
2155         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2156         atomic_set(&tx_ring->queue_stopped, 0);
2157 }
2158
2159 static void ql_free_tx_resources(struct ql_adapter *qdev,
2160                                  struct tx_ring *tx_ring)
2161 {
2162         if (tx_ring->wq_base) {
2163                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2164                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2165                 tx_ring->wq_base = NULL;
2166         }
2167         kfree(tx_ring->q);
2168         tx_ring->q = NULL;
2169 }
2170
2171 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2172                                  struct tx_ring *tx_ring)
2173 {
2174         tx_ring->wq_base =
2175             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2176                                  &tx_ring->wq_base_dma);
2177
2178         if ((tx_ring->wq_base == NULL)
2179             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2180                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2181                 return -ENOMEM;
2182         }
2183         tx_ring->q =
2184             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2185         if (tx_ring->q == NULL)
2186                 goto err;
2187
2188         return 0;
2189 err:
2190         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2191                             tx_ring->wq_base, tx_ring->wq_base_dma);
2192         return -ENOMEM;
2193 }
2194
2195 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2196 {
2197         int i;
2198         struct bq_desc *lbq_desc;
2199
2200         for (i = 0; i < rx_ring->lbq_len; i++) {
2201                 lbq_desc = &rx_ring->lbq[i];
2202                 if (lbq_desc->p.lbq_page) {
2203                         pci_unmap_page(qdev->pdev,
2204                                        pci_unmap_addr(lbq_desc, mapaddr),
2205                                        pci_unmap_len(lbq_desc, maplen),
2206                                        PCI_DMA_FROMDEVICE);
2207
2208                         put_page(lbq_desc->p.lbq_page);
2209                         lbq_desc->p.lbq_page = NULL;
2210                 }
2211         }
2212 }
2213
2214 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2215 {
2216         int i;
2217         struct bq_desc *sbq_desc;
2218
2219         for (i = 0; i < rx_ring->sbq_len; i++) {
2220                 sbq_desc = &rx_ring->sbq[i];
2221                 if (sbq_desc == NULL) {
2222                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2223                         return;
2224                 }
2225                 if (sbq_desc->p.skb) {
2226                         pci_unmap_single(qdev->pdev,
2227                                          pci_unmap_addr(sbq_desc, mapaddr),
2228                                          pci_unmap_len(sbq_desc, maplen),
2229                                          PCI_DMA_FROMDEVICE);
2230                         dev_kfree_skb(sbq_desc->p.skb);
2231                         sbq_desc->p.skb = NULL;
2232                 }
2233         }
2234 }
2235
2236 /* Free all large and small rx buffers associated
2237  * with the completion queues for this device.
2238  */
2239 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2240 {
2241         int i;
2242         struct rx_ring *rx_ring;
2243
2244         for (i = 0; i < qdev->rx_ring_count; i++) {
2245                 rx_ring = &qdev->rx_ring[i];
2246                 if (rx_ring->lbq)
2247                         ql_free_lbq_buffers(qdev, rx_ring);
2248                 if (rx_ring->sbq)
2249                         ql_free_sbq_buffers(qdev, rx_ring);
2250         }
2251 }
2252
2253 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2254 {
2255         struct rx_ring *rx_ring;
2256         int i;
2257
2258         for (i = 0; i < qdev->rx_ring_count; i++) {
2259                 rx_ring = &qdev->rx_ring[i];
2260                 if (rx_ring->type != TX_Q)
2261                         ql_update_buffer_queues(qdev, rx_ring);
2262         }
2263 }
2264
2265 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2266                                 struct rx_ring *rx_ring)
2267 {
2268         int i;
2269         struct bq_desc *lbq_desc;
2270         __le64 *bq = rx_ring->lbq_base;
2271
2272         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2273         for (i = 0; i < rx_ring->lbq_len; i++) {
2274                 lbq_desc = &rx_ring->lbq[i];
2275                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2276                 lbq_desc->index = i;
2277                 lbq_desc->addr = bq;
2278                 bq++;
2279         }
2280 }
2281
2282 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2283                                 struct rx_ring *rx_ring)
2284 {
2285         int i;
2286         struct bq_desc *sbq_desc;
2287         __le64 *bq = rx_ring->sbq_base;
2288
2289         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2290         for (i = 0; i < rx_ring->sbq_len; i++) {
2291                 sbq_desc = &rx_ring->sbq[i];
2292                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2293                 sbq_desc->index = i;
2294                 sbq_desc->addr = bq;
2295                 bq++;
2296         }
2297 }
2298
2299 static void ql_free_rx_resources(struct ql_adapter *qdev,
2300                                  struct rx_ring *rx_ring)
2301 {
2302         /* Free the small buffer queue. */
2303         if (rx_ring->sbq_base) {
2304                 pci_free_consistent(qdev->pdev,
2305                                     rx_ring->sbq_size,
2306                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2307                 rx_ring->sbq_base = NULL;
2308         }
2309
2310         /* Free the small buffer queue control blocks. */
2311         kfree(rx_ring->sbq);
2312         rx_ring->sbq = NULL;
2313
2314         /* Free the large buffer queue. */
2315         if (rx_ring->lbq_base) {
2316                 pci_free_consistent(qdev->pdev,
2317                                     rx_ring->lbq_size,
2318                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2319                 rx_ring->lbq_base = NULL;
2320         }
2321
2322         /* Free the large buffer queue control blocks. */
2323         kfree(rx_ring->lbq);
2324         rx_ring->lbq = NULL;
2325
2326         /* Free the rx queue. */
2327         if (rx_ring->cq_base) {
2328                 pci_free_consistent(qdev->pdev,
2329                                     rx_ring->cq_size,
2330                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2331                 rx_ring->cq_base = NULL;
2332         }
2333 }
2334
2335 /* Allocate queues and buffers for this completions queue based
2336  * on the values in the parameter structure. */
2337 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2338                                  struct rx_ring *rx_ring)
2339 {
2340
2341         /*
2342          * Allocate the completion queue for this rx_ring.
2343          */
2344         rx_ring->cq_base =
2345             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2346                                  &rx_ring->cq_base_dma);
2347
2348         if (rx_ring->cq_base == NULL) {
2349                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2350                 return -ENOMEM;
2351         }
2352
2353         if (rx_ring->sbq_len) {
2354                 /*
2355                  * Allocate small buffer queue.
2356                  */
2357                 rx_ring->sbq_base =
2358                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2359                                          &rx_ring->sbq_base_dma);
2360
2361                 if (rx_ring->sbq_base == NULL) {
2362                         QPRINTK(qdev, IFUP, ERR,
2363                                 "Small buffer queue allocation failed.\n");
2364                         goto err_mem;
2365                 }
2366
2367                 /*
2368                  * Allocate small buffer queue control blocks.
2369                  */
2370                 rx_ring->sbq =
2371                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2372                             GFP_KERNEL);
2373                 if (rx_ring->sbq == NULL) {
2374                         QPRINTK(qdev, IFUP, ERR,
2375                                 "Small buffer queue control block allocation failed.\n");
2376                         goto err_mem;
2377                 }
2378
2379                 ql_init_sbq_ring(qdev, rx_ring);
2380         }
2381
2382         if (rx_ring->lbq_len) {
2383                 /*
2384                  * Allocate large buffer queue.
2385                  */
2386                 rx_ring->lbq_base =
2387                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2388                                          &rx_ring->lbq_base_dma);
2389
2390                 if (rx_ring->lbq_base == NULL) {
2391                         QPRINTK(qdev, IFUP, ERR,
2392                                 "Large buffer queue allocation failed.\n");
2393                         goto err_mem;
2394                 }
2395                 /*
2396                  * Allocate large buffer queue control blocks.
2397                  */
2398                 rx_ring->lbq =
2399                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2400                             GFP_KERNEL);
2401                 if (rx_ring->lbq == NULL) {
2402                         QPRINTK(qdev, IFUP, ERR,
2403                                 "Large buffer queue control block allocation failed.\n");
2404                         goto err_mem;
2405                 }
2406
2407                 ql_init_lbq_ring(qdev, rx_ring);
2408         }
2409
2410         return 0;
2411
2412 err_mem:
2413         ql_free_rx_resources(qdev, rx_ring);
2414         return -ENOMEM;
2415 }
2416
2417 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2418 {
2419         struct tx_ring *tx_ring;
2420         struct tx_ring_desc *tx_ring_desc;
2421         int i, j;
2422
2423         /*
2424          * Loop through all queues and free
2425          * any resources.
2426          */
2427         for (j = 0; j < qdev->tx_ring_count; j++) {
2428                 tx_ring = &qdev->tx_ring[j];
2429                 for (i = 0; i < tx_ring->wq_len; i++) {
2430                         tx_ring_desc = &tx_ring->q[i];
2431                         if (tx_ring_desc && tx_ring_desc->skb) {
2432                                 QPRINTK(qdev, IFDOWN, ERR,
2433                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2434                                         tx_ring_desc->skb, j,
2435                                         tx_ring_desc->index);
2436                                 ql_unmap_send(qdev, tx_ring_desc,
2437                                               tx_ring_desc->map_cnt);
2438                                 dev_kfree_skb(tx_ring_desc->skb);
2439                                 tx_ring_desc->skb = NULL;
2440                         }
2441                 }
2442         }
2443 }
2444
2445 static void ql_free_mem_resources(struct ql_adapter *qdev)
2446 {
2447         int i;
2448
2449         for (i = 0; i < qdev->tx_ring_count; i++)
2450                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2451         for (i = 0; i < qdev->rx_ring_count; i++)
2452                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2453         ql_free_shadow_space(qdev);
2454 }
2455
2456 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2457 {
2458         int i;
2459
2460         /* Allocate space for our shadow registers and such. */
2461         if (ql_alloc_shadow_space(qdev))
2462                 return -ENOMEM;
2463
2464         for (i = 0; i < qdev->rx_ring_count; i++) {
2465                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2466                         QPRINTK(qdev, IFUP, ERR,
2467                                 "RX resource allocation failed.\n");
2468                         goto err_mem;
2469                 }
2470         }
2471         /* Allocate tx queue resources */
2472         for (i = 0; i < qdev->tx_ring_count; i++) {
2473                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2474                         QPRINTK(qdev, IFUP, ERR,
2475                                 "TX resource allocation failed.\n");
2476                         goto err_mem;
2477                 }
2478         }
2479         return 0;
2480
2481 err_mem:
2482         ql_free_mem_resources(qdev);
2483         return -ENOMEM;
2484 }
2485
2486 /* Set up the rx ring control block and pass it to the chip.
2487  * The control block is defined as
2488  * "Completion Queue Initialization Control Block", or cqicb.
2489  */
2490 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2491 {
2492         struct cqicb *cqicb = &rx_ring->cqicb;
2493         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2494             (rx_ring->cq_id * sizeof(u64) * 4);
2495         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2496             (rx_ring->cq_id * sizeof(u64) * 4);
2497         void __iomem *doorbell_area =
2498             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2499         int err = 0;
2500         u16 bq_len;
2501
2502         /* Set up the shadow registers for this ring. */
2503         rx_ring->prod_idx_sh_reg = shadow_reg;
2504         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2505         shadow_reg += sizeof(u64);
2506         shadow_reg_dma += sizeof(u64);
2507         rx_ring->lbq_base_indirect = shadow_reg;
2508         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2509         shadow_reg += sizeof(u64);
2510         shadow_reg_dma += sizeof(u64);
2511         rx_ring->sbq_base_indirect = shadow_reg;
2512         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2513
2514         /* PCI doorbell mem area + 0x00 for consumer index register */
2515         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2516         rx_ring->cnsmr_idx = 0;
2517         rx_ring->curr_entry = rx_ring->cq_base;
2518
2519         /* PCI doorbell mem area + 0x04 for valid register */
2520         rx_ring->valid_db_reg = doorbell_area + 0x04;
2521
2522         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2523         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2524
2525         /* PCI doorbell mem area + 0x1c */
2526         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2527
2528         memset((void *)cqicb, 0, sizeof(struct cqicb));
2529         cqicb->msix_vect = rx_ring->irq;
2530
2531         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2532         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2533
2534         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2535
2536         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2537
2538         /*
2539          * Set up the control block load flags.
2540          */
2541         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2542             FLAGS_LV |          /* Load MSI-X vector */
2543             FLAGS_LI;           /* Load irq delay values */
2544         if (rx_ring->lbq_len) {
2545                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2546                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2547                 cqicb->lbq_addr =
2548                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2549                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2550                         (u16) rx_ring->lbq_buf_size;
2551                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2552                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2553                         (u16) rx_ring->lbq_len;
2554                 cqicb->lbq_len = cpu_to_le16(bq_len);
2555                 rx_ring->lbq_prod_idx = 0;
2556                 rx_ring->lbq_curr_idx = 0;
2557                 rx_ring->lbq_clean_idx = 0;
2558                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2559         }
2560         if (rx_ring->sbq_len) {
2561                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2562                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2563                 cqicb->sbq_addr =
2564                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2565                 cqicb->sbq_buf_size =
2566                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2567                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2568                         (u16) rx_ring->sbq_len;
2569                 cqicb->sbq_len = cpu_to_le16(bq_len);
2570                 rx_ring->sbq_prod_idx = 0;
2571                 rx_ring->sbq_curr_idx = 0;
2572                 rx_ring->sbq_clean_idx = 0;
2573                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2574         }
2575         switch (rx_ring->type) {
2576         case TX_Q:
2577                 /* If there's only one interrupt, then we use
2578                  * worker threads to process the outbound
2579                  * completion handling rx_rings. We do this so
2580                  * they can be run on multiple CPUs. There is
2581                  * room to play with this more where we would only
2582                  * run in a worker if there are more than x number
2583                  * of outbound completions on the queue and more
2584                  * than one queue active.  Some threshold that
2585                  * would indicate a benefit in spite of the cost
2586                  * of a context switch.
2587                  * If there's more than one interrupt, then the
2588                  * outbound completions are processed in the ISR.
2589                  */
2590                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2591                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2592                 else {
2593                         /* With all debug warnings on we see a WARN_ON message
2594                          * when we free the skb in the interrupt context.
2595                          */
2596                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2597                 }
2598                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2599                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2600                 break;
2601         case DEFAULT_Q:
2602                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2603                 cqicb->irq_delay = 0;
2604                 cqicb->pkt_delay = 0;
2605                 break;
2606         case RX_Q:
2607                 /* Inbound completion handling rx_rings run in
2608                  * separate NAPI contexts.
2609                  */
2610                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2611                                64);
2612                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2613                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2614                 break;
2615         default:
2616                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2617                         rx_ring->type);
2618         }
2619         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2620         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2621                            CFG_LCQ, rx_ring->cq_id);
2622         if (err) {
2623                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2624                 return err;
2625         }
2626         return err;
2627 }
2628
2629 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2630 {
2631         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2632         void __iomem *doorbell_area =
2633             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2634         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2635             (tx_ring->wq_id * sizeof(u64));
2636         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2637             (tx_ring->wq_id * sizeof(u64));
2638         int err = 0;
2639
2640         /*
2641          * Assign doorbell registers for this tx_ring.
2642          */
2643         /* TX PCI doorbell mem area for tx producer index */
2644         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2645         tx_ring->prod_idx = 0;
2646         /* TX PCI doorbell mem area + 0x04 */
2647         tx_ring->valid_db_reg = doorbell_area + 0x04;
2648
2649         /*
2650          * Assign shadow registers for this tx_ring.
2651          */
2652         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2653         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2654
2655         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2656         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2657                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2658         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2659         wqicb->rid = 0;
2660         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2661
2662         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2663
2664         ql_init_tx_ring(qdev, tx_ring);
2665
2666         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2667                            (u16) tx_ring->wq_id);
2668         if (err) {
2669                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2670                 return err;
2671         }
2672         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2673         return err;
2674 }
2675
2676 static void ql_disable_msix(struct ql_adapter *qdev)
2677 {
2678         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2679                 pci_disable_msix(qdev->pdev);
2680                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2681                 kfree(qdev->msi_x_entry);
2682                 qdev->msi_x_entry = NULL;
2683         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2684                 pci_disable_msi(qdev->pdev);
2685                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2686         }
2687 }
2688
2689 static void ql_enable_msix(struct ql_adapter *qdev)
2690 {
2691         int i;
2692
2693         qdev->intr_count = 1;
2694         /* Get the MSIX vectors. */
2695         if (irq_type == MSIX_IRQ) {
2696                 /* Try to alloc space for the msix struct,
2697                  * if it fails then go to MSI/legacy.
2698                  */
2699                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2700                                             sizeof(struct msix_entry),
2701                                             GFP_KERNEL);
2702                 if (!qdev->msi_x_entry) {
2703                         irq_type = MSI_IRQ;
2704                         goto msi;
2705                 }
2706
2707                 for (i = 0; i < qdev->rx_ring_count; i++)
2708                         qdev->msi_x_entry[i].entry = i;
2709
2710                 if (!pci_enable_msix
2711                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2712                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2713                         qdev->intr_count = qdev->rx_ring_count;
2714                         QPRINTK(qdev, IFUP, DEBUG,
2715                                 "MSI-X Enabled, got %d vectors.\n",
2716                                 qdev->intr_count);
2717                         return;
2718                 } else {
2719                         kfree(qdev->msi_x_entry);
2720                         qdev->msi_x_entry = NULL;
2721                         QPRINTK(qdev, IFUP, WARNING,
2722                                 "MSI-X Enable failed, trying MSI.\n");
2723                         irq_type = MSI_IRQ;
2724                 }
2725         }
2726 msi:
2727         if (irq_type == MSI_IRQ) {
2728                 if (!pci_enable_msi(qdev->pdev)) {
2729                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2730                         QPRINTK(qdev, IFUP, INFO,
2731                                 "Running with MSI interrupts.\n");
2732                         return;
2733                 }
2734         }
2735         irq_type = LEG_IRQ;
2736         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2737 }
2738
2739 /*
2740  * Here we build the intr_context structures based on
2741  * our rx_ring count and intr vector count.
2742  * The intr_context structure is used to hook each vector
2743  * to possibly different handlers.
2744  */
2745 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2746 {
2747         int i = 0;
2748         struct intr_context *intr_context = &qdev->intr_context[0];
2749
2750         ql_enable_msix(qdev);
2751
2752         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2753                 /* Each rx_ring has it's
2754                  * own intr_context since we have separate
2755                  * vectors for each queue.
2756                  * This only true when MSI-X is enabled.
2757                  */
2758                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2759                         qdev->rx_ring[i].irq = i;
2760                         intr_context->intr = i;
2761                         intr_context->qdev = qdev;
2762                         /*
2763                          * We set up each vectors enable/disable/read bits so
2764                          * there's no bit/mask calculations in the critical path.
2765                          */
2766                         intr_context->intr_en_mask =
2767                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2768                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2769                             | i;
2770                         intr_context->intr_dis_mask =
2771                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2772                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2773                             INTR_EN_IHD | i;
2774                         intr_context->intr_read_mask =
2775                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2776                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2777                             i;
2778
2779                         if (i == 0) {
2780                                 /*
2781                                  * Default queue handles bcast/mcast plus
2782                                  * async events.  Needs buffers.
2783                                  */
2784                                 intr_context->handler = qlge_isr;
2785                                 sprintf(intr_context->name, "%s-default-queue",
2786                                         qdev->ndev->name);
2787                         } else if (i < qdev->rss_ring_first_cq_id) {
2788                                 /*
2789                                  * Outbound queue is for outbound completions only.
2790                                  */
2791                                 intr_context->handler = qlge_msix_tx_isr;
2792                                 sprintf(intr_context->name, "%s-tx-%d",
2793                                         qdev->ndev->name, i);
2794                         } else {
2795                                 /*
2796                                  * Inbound queues handle unicast frames only.
2797                                  */
2798                                 intr_context->handler = qlge_msix_rx_isr;
2799                                 sprintf(intr_context->name, "%s-rx-%d",
2800                                         qdev->ndev->name, i);
2801                         }
2802                 }
2803         } else {
2804                 /*
2805                  * All rx_rings use the same intr_context since
2806                  * there is only one vector.
2807                  */
2808                 intr_context->intr = 0;
2809                 intr_context->qdev = qdev;
2810                 /*
2811                  * We set up each vectors enable/disable/read bits so
2812                  * there's no bit/mask calculations in the critical path.
2813                  */
2814                 intr_context->intr_en_mask =
2815                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2816                 intr_context->intr_dis_mask =
2817                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2818                     INTR_EN_TYPE_DISABLE;
2819                 intr_context->intr_read_mask =
2820                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2821                 /*
2822                  * Single interrupt means one handler for all rings.
2823                  */
2824                 intr_context->handler = qlge_isr;
2825                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2826                 for (i = 0; i < qdev->rx_ring_count; i++)
2827                         qdev->rx_ring[i].irq = 0;
2828         }
2829 }
2830
2831 static void ql_free_irq(struct ql_adapter *qdev)
2832 {
2833         int i;
2834         struct intr_context *intr_context = &qdev->intr_context[0];
2835
2836         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2837                 if (intr_context->hooked) {
2838                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2839                                 free_irq(qdev->msi_x_entry[i].vector,
2840                                          &qdev->rx_ring[i]);
2841                                 QPRINTK(qdev, IFDOWN, DEBUG,
2842                                         "freeing msix interrupt %d.\n", i);
2843                         } else {
2844                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2845                                 QPRINTK(qdev, IFDOWN, DEBUG,
2846                                         "freeing msi interrupt %d.\n", i);
2847                         }
2848                 }
2849         }
2850         ql_disable_msix(qdev);
2851 }
2852
2853 static int ql_request_irq(struct ql_adapter *qdev)
2854 {
2855         int i;
2856         int status = 0;
2857         struct pci_dev *pdev = qdev->pdev;
2858         struct intr_context *intr_context = &qdev->intr_context[0];
2859
2860         ql_resolve_queues_to_irqs(qdev);
2861
2862         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2863                 atomic_set(&intr_context->irq_cnt, 0);
2864                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2865                         status = request_irq(qdev->msi_x_entry[i].vector,
2866                                              intr_context->handler,
2867                                              0,
2868                                              intr_context->name,
2869                                              &qdev->rx_ring[i]);
2870                         if (status) {
2871                                 QPRINTK(qdev, IFUP, ERR,
2872                                         "Failed request for MSIX interrupt %d.\n",
2873                                         i);
2874                                 goto err_irq;
2875                         } else {
2876                                 QPRINTK(qdev, IFUP, DEBUG,
2877                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2878                                         i,
2879                                         qdev->rx_ring[i].type ==
2880                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2881                                         qdev->rx_ring[i].type ==
2882                                         TX_Q ? "TX_Q" : "",
2883                                         qdev->rx_ring[i].type ==
2884                                         RX_Q ? "RX_Q" : "", intr_context->name);
2885                         }
2886                 } else {
2887                         QPRINTK(qdev, IFUP, DEBUG,
2888                                 "trying msi or legacy interrupts.\n");
2889                         QPRINTK(qdev, IFUP, DEBUG,
2890                                 "%s: irq = %d.\n", __func__, pdev->irq);
2891                         QPRINTK(qdev, IFUP, DEBUG,
2892                                 "%s: context->name = %s.\n", __func__,
2893                                intr_context->name);
2894                         QPRINTK(qdev, IFUP, DEBUG,
2895                                 "%s: dev_id = 0x%p.\n", __func__,
2896                                &qdev->rx_ring[0]);
2897                         status =
2898                             request_irq(pdev->irq, qlge_isr,
2899                                         test_bit(QL_MSI_ENABLED,
2900                                                  &qdev->
2901                                                  flags) ? 0 : IRQF_SHARED,
2902                                         intr_context->name, &qdev->rx_ring[0]);
2903                         if (status)
2904                                 goto err_irq;
2905
2906                         QPRINTK(qdev, IFUP, ERR,
2907                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2908                                 i,
2909                                 qdev->rx_ring[0].type ==
2910                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2911                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2912                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2913                                 intr_context->name);
2914                 }
2915                 intr_context->hooked = 1;
2916         }
2917         return status;
2918 err_irq:
2919         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2920         ql_free_irq(qdev);
2921         return status;
2922 }
2923
2924 static int ql_start_rss(struct ql_adapter *qdev)
2925 {
2926         struct ricb *ricb = &qdev->ricb;
2927         int status = 0;
2928         int i;
2929         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2930
2931         memset((void *)ricb, 0, sizeof(ricb));
2932
2933         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2934         ricb->flags =
2935             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2936              RSS_RT6);
2937         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2938
2939         /*
2940          * Fill out the Indirection Table.
2941          */
2942         for (i = 0; i < 256; i++)
2943                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2944
2945         /*
2946          * Random values for the IPv6 and IPv4 Hash Keys.
2947          */
2948         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2949         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2950
2951         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2952
2953         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2954         if (status) {
2955                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2956                 return status;
2957         }
2958         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2959         return status;
2960 }
2961
2962 /* Initialize the frame-to-queue routing. */
2963 static int ql_route_initialize(struct ql_adapter *qdev)
2964 {
2965         int status = 0;
2966         int i;
2967
2968         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2969         if (status)
2970                 return status;
2971
2972         /* Clear all the entries in the routing table. */
2973         for (i = 0; i < 16; i++) {
2974                 status = ql_set_routing_reg(qdev, i, 0, 0);
2975                 if (status) {
2976                         QPRINTK(qdev, IFUP, ERR,
2977                                 "Failed to init routing register for CAM packets.\n");
2978                         goto exit;
2979                 }
2980         }
2981
2982         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2983         if (status) {
2984                 QPRINTK(qdev, IFUP, ERR,
2985                         "Failed to init routing register for error packets.\n");
2986                 goto exit;
2987         }
2988         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2989         if (status) {
2990                 QPRINTK(qdev, IFUP, ERR,
2991                         "Failed to init routing register for broadcast packets.\n");
2992                 goto exit;
2993         }
2994         /* If we have more than one inbound queue, then turn on RSS in the
2995          * routing block.
2996          */
2997         if (qdev->rss_ring_count > 1) {
2998                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2999                                         RT_IDX_RSS_MATCH, 1);
3000                 if (status) {
3001                         QPRINTK(qdev, IFUP, ERR,
3002                                 "Failed to init routing register for MATCH RSS packets.\n");
3003                         goto exit;
3004                 }
3005         }
3006
3007         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3008                                     RT_IDX_CAM_HIT, 1);
3009         if (status)
3010                 QPRINTK(qdev, IFUP, ERR,
3011                         "Failed to init routing register for CAM packets.\n");
3012 exit:
3013         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3014         return status;
3015 }
3016
3017 int ql_cam_route_initialize(struct ql_adapter *qdev)
3018 {
3019         int status;
3020
3021         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3022         if (status)
3023                 return status;
3024         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3025                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3026         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3027         if (status) {
3028                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3029                 return status;
3030         }
3031
3032         status = ql_route_initialize(qdev);
3033         if (status)
3034                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3035
3036         return status;
3037 }
3038
3039 static int ql_adapter_initialize(struct ql_adapter *qdev)
3040 {
3041         u32 value, mask;
3042         int i;
3043         int status = 0;
3044
3045         /*
3046          * Set up the System register to halt on errors.
3047          */
3048         value = SYS_EFE | SYS_FAE;
3049         mask = value << 16;
3050         ql_write32(qdev, SYS, mask | value);
3051
3052         /* Set the default queue. */
3053         value = NIC_RCV_CFG_DFQ;
3054         mask = NIC_RCV_CFG_DFQ_MASK;
3055         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3056
3057         /* Set the MPI interrupt to enabled. */
3058         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3059
3060         /* Enable the function, set pagesize, enable error checking. */
3061         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3062             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3063
3064         /* Set/clear header splitting. */
3065         mask = FSC_VM_PAGESIZE_MASK |
3066             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3067         ql_write32(qdev, FSC, mask | value);
3068
3069         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3070                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3071
3072         /* Start up the rx queues. */
3073         for (i = 0; i < qdev->rx_ring_count; i++) {
3074                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3075                 if (status) {
3076                         QPRINTK(qdev, IFUP, ERR,
3077                                 "Failed to start rx ring[%d].\n", i);
3078                         return status;
3079                 }
3080         }
3081
3082         /* If there is more than one inbound completion queue
3083          * then download a RICB to configure RSS.
3084          */
3085         if (qdev->rss_ring_count > 1) {
3086                 status = ql_start_rss(qdev);
3087                 if (status) {
3088                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3089                         return status;
3090                 }
3091         }
3092
3093         /* Start up the tx queues. */
3094         for (i = 0; i < qdev->tx_ring_count; i++) {
3095                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3096                 if (status) {
3097                         QPRINTK(qdev, IFUP, ERR,
3098                                 "Failed to start tx ring[%d].\n", i);
3099                         return status;
3100                 }
3101         }
3102
3103         /* Initialize the port and set the max framesize. */
3104         status = qdev->nic_ops->port_initialize(qdev);
3105        if (status) {
3106               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3107               return status;
3108        }
3109
3110         /* Set up the MAC address and frame routing filter. */
3111         status = ql_cam_route_initialize(qdev);
3112         if (status) {
3113                 QPRINTK(qdev, IFUP, ERR,
3114                                 "Failed to init CAM/Routing tables.\n");
3115                 return status;
3116         }
3117
3118         /* Start NAPI for the RSS queues. */
3119         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3120                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3121                         i);
3122                 napi_enable(&qdev->rx_ring[i].napi);
3123         }
3124
3125         return status;
3126 }
3127
3128 /* Issue soft reset to chip. */
3129 static int ql_adapter_reset(struct ql_adapter *qdev)
3130 {
3131         u32 value;
3132         int max_wait_time;
3133         int status = 0;
3134         int resetCnt = 0;
3135
3136 #define MAX_RESET_CNT   1
3137 issueReset:
3138         resetCnt++;
3139         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3140         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3141         /* Wait for reset to complete. */
3142         max_wait_time = 3;
3143         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3144                 max_wait_time);
3145         do {
3146                 value = ql_read32(qdev, RST_FO);
3147                 if ((value & RST_FO_FR) == 0)
3148                         break;
3149
3150                 ssleep(1);
3151         } while ((--max_wait_time));
3152         if (value & RST_FO_FR) {
3153                 QPRINTK(qdev, IFDOWN, ERR,
3154                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3155                 if (resetCnt < MAX_RESET_CNT)
3156                         goto issueReset;
3157         }
3158         if (max_wait_time == 0) {
3159                 status = -ETIMEDOUT;
3160                 QPRINTK(qdev, IFDOWN, ERR,
3161                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3162         }
3163
3164         return status;
3165 }
3166
3167 static void ql_display_dev_info(struct net_device *ndev)
3168 {
3169         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3170
3171         QPRINTK(qdev, PROBE, INFO,
3172                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3173                 "XG Roll = %d, XG Rev = %d.\n",
3174                 qdev->func,
3175                 qdev->chip_rev_id & 0x0000000f,
3176                 qdev->chip_rev_id >> 4 & 0x0000000f,
3177                 qdev->chip_rev_id >> 8 & 0x0000000f,
3178                 qdev->chip_rev_id >> 12 & 0x0000000f);
3179         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3180 }
3181
3182 static int ql_adapter_down(struct ql_adapter *qdev)
3183 {
3184         struct net_device *ndev = qdev->ndev;
3185         int i, status = 0;
3186         struct rx_ring *rx_ring;
3187
3188         netif_stop_queue(ndev);
3189         netif_carrier_off(ndev);
3190
3191         /* Don't kill the reset worker thread if we
3192          * are in the process of recovery.
3193          */
3194         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3195                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3196         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3197         cancel_delayed_work_sync(&qdev->mpi_work);
3198         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3199         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3200
3201         /* The default queue at index 0 is always processed in
3202          * a workqueue.
3203          */
3204         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3205
3206         /* The rest of the rx_rings are processed in
3207          * a workqueue only if it's a single interrupt
3208          * environment (MSI/Legacy).
3209          */
3210         for (i = 1; i < qdev->rx_ring_count; i++) {
3211                 rx_ring = &qdev->rx_ring[i];
3212                 /* Only the RSS rings use NAPI on multi irq
3213                  * environment.  Outbound completion processing
3214                  * is done in interrupt context.
3215                  */
3216                 if (i >= qdev->rss_ring_first_cq_id) {
3217                         napi_disable(&rx_ring->napi);
3218                 } else {
3219                         cancel_delayed_work_sync(&rx_ring->rx_work);
3220                 }
3221         }
3222
3223         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3224
3225         ql_disable_interrupts(qdev);
3226
3227         ql_tx_ring_clean(qdev);
3228
3229         ql_free_rx_buffers(qdev);
3230         spin_lock(&qdev->hw_lock);
3231         status = ql_adapter_reset(qdev);
3232         if (status)
3233                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3234                         qdev->func);
3235         spin_unlock(&qdev->hw_lock);
3236         return status;
3237 }
3238
3239 static int ql_adapter_up(struct ql_adapter *qdev)
3240 {
3241         int err = 0;
3242
3243         spin_lock(&qdev->hw_lock);
3244         err = ql_adapter_initialize(qdev);
3245         if (err) {
3246                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3247                 spin_unlock(&qdev->hw_lock);
3248                 goto err_init;
3249         }
3250         spin_unlock(&qdev->hw_lock);
3251         set_bit(QL_ADAPTER_UP, &qdev->flags);
3252         ql_alloc_rx_buffers(qdev);
3253         ql_enable_interrupts(qdev);
3254         ql_enable_all_completion_interrupts(qdev);
3255         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3256                 netif_carrier_on(qdev->ndev);
3257                 netif_start_queue(qdev->ndev);
3258         }
3259
3260         return 0;
3261 err_init:
3262         ql_adapter_reset(qdev);
3263         return err;
3264 }
3265
3266 static int ql_cycle_adapter(struct ql_adapter *qdev)
3267 {
3268         int status;
3269
3270         status = ql_adapter_down(qdev);
3271         if (status)
3272                 goto error;
3273
3274         status = ql_adapter_up(qdev);
3275         if (status)
3276                 goto error;
3277
3278         return status;
3279 error:
3280         QPRINTK(qdev, IFUP, ALERT,
3281                 "Driver up/down cycle failed, closing device\n");
3282         rtnl_lock();
3283         dev_close(qdev->ndev);
3284         rtnl_unlock();
3285         return status;
3286 }
3287
3288 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3289 {
3290         ql_free_mem_resources(qdev);
3291         ql_free_irq(qdev);
3292 }
3293
3294 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3295 {
3296         int status = 0;
3297
3298         if (ql_alloc_mem_resources(qdev)) {
3299                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3300                 return -ENOMEM;
3301         }
3302         status = ql_request_irq(qdev);
3303         if (status)
3304                 goto err_irq;
3305         return status;
3306 err_irq:
3307         ql_free_mem_resources(qdev);
3308         return status;
3309 }
3310
3311 static int qlge_close(struct net_device *ndev)
3312 {
3313         struct ql_adapter *qdev = netdev_priv(ndev);
3314
3315         /*
3316          * Wait for device to recover from a reset.
3317          * (Rarely happens, but possible.)
3318          */
3319         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3320                 msleep(1);
3321         ql_adapter_down(qdev);
3322         ql_release_adapter_resources(qdev);
3323         return 0;
3324 }
3325
3326 static int ql_configure_rings(struct ql_adapter *qdev)
3327 {
3328         int i;
3329         struct rx_ring *rx_ring;
3330         struct tx_ring *tx_ring;
3331         int cpu_cnt = num_online_cpus();
3332
3333         /*
3334          * For each processor present we allocate one
3335          * rx_ring for outbound completions, and one
3336          * rx_ring for inbound completions.  Plus there is
3337          * always the one default queue.  For the CPU
3338          * counts we end up with the following rx_rings:
3339          * rx_ring count =
3340          *  one default queue +
3341          *  (CPU count * outbound completion rx_ring) +
3342          *  (CPU count * inbound (RSS) completion rx_ring)
3343          * To keep it simple we limit the total number of
3344          * queues to < 32, so we truncate CPU to 8.
3345          * This limitation can be removed when requested.
3346          */
3347
3348         if (cpu_cnt > MAX_CPUS)
3349                 cpu_cnt = MAX_CPUS;
3350
3351         /*
3352          * rx_ring[0] is always the default queue.
3353          */
3354         /* Allocate outbound completion ring for each CPU. */
3355         qdev->tx_ring_count = cpu_cnt;
3356         /* Allocate inbound completion (RSS) ring for each CPU. */
3357         qdev->rss_ring_count = cpu_cnt;
3358         /* cq_id for the first inbound ring handler. */
3359         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3360         /*
3361          * qdev->rx_ring_count:
3362          * Total number of rx_rings.  This includes the one
3363          * default queue, a number of outbound completion
3364          * handler rx_rings, and the number of inbound
3365          * completion handler rx_rings.
3366          */
3367         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3368
3369         for (i = 0; i < qdev->tx_ring_count; i++) {
3370                 tx_ring = &qdev->tx_ring[i];
3371                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3372                 tx_ring->qdev = qdev;
3373                 tx_ring->wq_id = i;
3374                 tx_ring->wq_len = qdev->tx_ring_size;
3375                 tx_ring->wq_size =
3376                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3377
3378                 /*
3379                  * The completion queue ID for the tx rings start
3380                  * immediately after the default Q ID, which is zero.
3381                  */
3382                 tx_ring->cq_id = i + 1;
3383         }
3384
3385         for (i = 0; i < qdev->rx_ring_count; i++) {
3386                 rx_ring = &qdev->rx_ring[i];
3387                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3388                 rx_ring->qdev = qdev;
3389                 rx_ring->cq_id = i;
3390                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3391                 if (i == 0) {   /* Default queue at index 0. */
3392                         /*
3393                          * Default queue handles bcast/mcast plus
3394                          * async events.  Needs buffers.
3395                          */
3396                         rx_ring->cq_len = qdev->rx_ring_size;
3397                         rx_ring->cq_size =
3398                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3399                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3400                         rx_ring->lbq_size =
3401                             rx_ring->lbq_len * sizeof(__le64);
3402                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3403                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3404                         rx_ring->sbq_size =
3405                             rx_ring->sbq_len * sizeof(__le64);
3406                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3407                         rx_ring->type = DEFAULT_Q;
3408                 } else if (i < qdev->rss_ring_first_cq_id) {
3409                         /*
3410                          * Outbound queue handles outbound completions only.
3411                          */
3412                         /* outbound cq is same size as tx_ring it services. */
3413                         rx_ring->cq_len = qdev->tx_ring_size;
3414                         rx_ring->cq_size =
3415                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3416                         rx_ring->lbq_len = 0;
3417                         rx_ring->lbq_size = 0;
3418                         rx_ring->lbq_buf_size = 0;
3419                         rx_ring->sbq_len = 0;
3420                         rx_ring->sbq_size = 0;
3421                         rx_ring->sbq_buf_size = 0;
3422                         rx_ring->type = TX_Q;
3423                 } else {        /* Inbound completions (RSS) queues */
3424                         /*
3425                          * Inbound queues handle unicast frames only.
3426                          */
3427                         rx_ring->cq_len = qdev->rx_ring_size;
3428                         rx_ring->cq_size =
3429                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3430                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3431                         rx_ring->lbq_size =
3432                             rx_ring->lbq_len * sizeof(__le64);
3433                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3434                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3435                         rx_ring->sbq_size =
3436                             rx_ring->sbq_len * sizeof(__le64);
3437                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3438                         rx_ring->type = RX_Q;
3439                 }
3440         }
3441         return 0;
3442 }
3443
3444 static int qlge_open(struct net_device *ndev)
3445 {
3446         int err = 0;
3447         struct ql_adapter *qdev = netdev_priv(ndev);
3448
3449         err = ql_configure_rings(qdev);
3450         if (err)
3451                 return err;
3452
3453         err = ql_get_adapter_resources(qdev);
3454         if (err)
3455                 goto error_up;
3456
3457         err = ql_adapter_up(qdev);
3458         if (err)
3459                 goto error_up;
3460
3461         return err;
3462
3463 error_up:
3464         ql_release_adapter_resources(qdev);
3465         return err;
3466 }
3467
3468 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3469 {
3470         struct ql_adapter *qdev = netdev_priv(ndev);
3471
3472         if (ndev->mtu == 1500 && new_mtu == 9000) {
3473                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3474                 queue_delayed_work(qdev->workqueue,
3475                                 &qdev->mpi_port_cfg_work, 0);
3476         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3477                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3478         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3479                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3480                 return 0;
3481         } else
3482                 return -EINVAL;
3483         ndev->mtu = new_mtu;
3484         return 0;
3485 }
3486
3487 static struct net_device_stats *qlge_get_stats(struct net_device
3488                                                *ndev)
3489 {
3490         struct ql_adapter *qdev = netdev_priv(ndev);
3491         return &qdev->stats;
3492 }
3493
3494 static void qlge_set_multicast_list(struct net_device *ndev)
3495 {
3496         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3497         struct dev_mc_list *mc_ptr;
3498         int i, status;
3499
3500         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3501         if (status)
3502                 return;
3503         spin_lock(&qdev->hw_lock);
3504         /*
3505          * Set or clear promiscuous mode if a
3506          * transition is taking place.
3507          */
3508         if (ndev->flags & IFF_PROMISC) {
3509                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3510                         if (ql_set_routing_reg
3511                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3512                                 QPRINTK(qdev, HW, ERR,
3513                                         "Failed to set promiscous mode.\n");
3514                         } else {
3515                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3516                         }
3517                 }
3518         } else {
3519                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3520                         if (ql_set_routing_reg
3521                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3522                                 QPRINTK(qdev, HW, ERR,
3523                                         "Failed to clear promiscous mode.\n");
3524                         } else {
3525                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3526                         }
3527                 }
3528         }
3529
3530         /*
3531          * Set or clear all multicast mode if a
3532          * transition is taking place.
3533          */
3534         if ((ndev->flags & IFF_ALLMULTI) ||
3535             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3536                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3537                         if (ql_set_routing_reg
3538                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3539                                 QPRINTK(qdev, HW, ERR,
3540                                         "Failed to set all-multi mode.\n");
3541                         } else {
3542                                 set_bit(QL_ALLMULTI, &qdev->flags);
3543                         }
3544                 }
3545         } else {
3546                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3547                         if (ql_set_routing_reg
3548                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3549                                 QPRINTK(qdev, HW, ERR,
3550                                         "Failed to clear all-multi mode.\n");
3551                         } else {
3552                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3553                         }
3554                 }
3555         }
3556
3557         if (ndev->mc_count) {
3558                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3559                 if (status)
3560                         goto exit;
3561                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3562                      i++, mc_ptr = mc_ptr->next)
3563                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3564                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3565                                 QPRINTK(qdev, HW, ERR,
3566                                         "Failed to loadmulticast address.\n");
3567                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3568                                 goto exit;
3569                         }
3570                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3571                 if (ql_set_routing_reg
3572                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3573                         QPRINTK(qdev, HW, ERR,
3574                                 "Failed to set multicast match mode.\n");
3575                 } else {
3576                         set_bit(QL_ALLMULTI, &qdev->flags);
3577                 }
3578         }
3579 exit:
3580         spin_unlock(&qdev->hw_lock);
3581         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3582 }
3583
3584 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3585 {
3586         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3587         struct sockaddr *addr = p;
3588         int status;
3589
3590         if (netif_running(ndev))
3591                 return -EBUSY;
3592
3593         if (!is_valid_ether_addr(addr->sa_data))
3594                 return -EADDRNOTAVAIL;
3595         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3596
3597         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3598         if (status)
3599                 return status;
3600         spin_lock(&qdev->hw_lock);
3601         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3602                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3603         spin_unlock(&qdev->hw_lock);
3604         if (status)
3605                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3606         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3607         return status;
3608 }
3609
3610 static void qlge_tx_timeout(struct net_device *ndev)
3611 {
3612         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3613         ql_queue_asic_error(qdev);
3614 }
3615
3616 static void ql_asic_reset_work(struct work_struct *work)
3617 {
3618         struct ql_adapter *qdev =
3619             container_of(work, struct ql_adapter, asic_reset_work.work);
3620         ql_cycle_adapter(qdev);
3621 }
3622
3623 static struct nic_operations qla8012_nic_ops = {
3624         .get_flash              = ql_get_8012_flash_params,
3625         .port_initialize        = ql_8012_port_initialize,
3626 };
3627
3628 static struct nic_operations qla8000_nic_ops = {
3629         .get_flash              = ql_get_8000_flash_params,
3630         .port_initialize        = ql_8000_port_initialize,
3631 };
3632
3633
3634 static void ql_get_board_info(struct ql_adapter *qdev)
3635 {
3636         qdev->func =
3637             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3638         if (qdev->func) {
3639                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3640                 qdev->port_link_up = STS_PL1;
3641                 qdev->port_init = STS_PI1;
3642                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3643                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3644         } else {
3645                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3646                 qdev->port_link_up = STS_PL0;
3647                 qdev->port_init = STS_PI0;
3648                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3649                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3650         }
3651         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3652         qdev->device_id = qdev->pdev->device;
3653         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3654                 qdev->nic_ops = &qla8012_nic_ops;
3655         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3656                 qdev->nic_ops = &qla8000_nic_ops;
3657 }
3658
3659 static void ql_release_all(struct pci_dev *pdev)
3660 {
3661         struct net_device *ndev = pci_get_drvdata(pdev);
3662         struct ql_adapter *qdev = netdev_priv(ndev);
3663
3664         if (qdev->workqueue) {
3665                 destroy_workqueue(qdev->workqueue);
3666                 qdev->workqueue = NULL;
3667         }
3668         if (qdev->q_workqueue) {
3669                 destroy_workqueue(qdev->q_workqueue);
3670                 qdev->q_workqueue = NULL;
3671         }
3672         if (qdev->reg_base)
3673                 iounmap(qdev->reg_base);
3674         if (qdev->doorbell_area)
3675                 iounmap(qdev->doorbell_area);
3676         pci_release_regions(pdev);
3677         pci_set_drvdata(pdev, NULL);
3678 }
3679
3680 static int __devinit ql_init_device(struct pci_dev *pdev,
3681                                     struct net_device *ndev, int cards_found)
3682 {
3683         struct ql_adapter *qdev = netdev_priv(ndev);
3684         int pos, err = 0;
3685         u16 val16;
3686
3687         memset((void *)qdev, 0, sizeof(qdev));
3688         err = pci_enable_device(pdev);
3689         if (err) {
3690                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3691                 return err;
3692         }
3693
3694         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3695         if (pos <= 0) {
3696                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3697                         "aborting.\n");
3698                 goto err_out;
3699         } else {
3700                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3701                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3702                 val16 |= (PCI_EXP_DEVCTL_CERE |
3703                           PCI_EXP_DEVCTL_NFERE |
3704                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3705                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3706         }
3707
3708         err = pci_request_regions(pdev, DRV_NAME);
3709         if (err) {
3710                 dev_err(&pdev->dev, "PCI region request failed.\n");
3711                 goto err_out;
3712         }
3713
3714         pci_set_master(pdev);
3715         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3716                 set_bit(QL_DMA64, &qdev->flags);
3717                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3718         } else {
3719                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3720                 if (!err)
3721                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3722         }
3723
3724         if (err) {
3725                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3726                 goto err_out;
3727         }
3728
3729         pci_set_drvdata(pdev, ndev);
3730         qdev->reg_base =
3731             ioremap_nocache(pci_resource_start(pdev, 1),
3732                             pci_resource_len(pdev, 1));
3733         if (!qdev->reg_base) {
3734                 dev_err(&pdev->dev, "Register mapping failed.\n");
3735                 err = -ENOMEM;
3736                 goto err_out;
3737         }
3738
3739         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3740         qdev->doorbell_area =
3741             ioremap_nocache(pci_resource_start(pdev, 3),
3742                             pci_resource_len(pdev, 3));
3743         if (!qdev->doorbell_area) {
3744                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3745                 err = -ENOMEM;
3746                 goto err_out;
3747         }
3748
3749         qdev->ndev = ndev;
3750         qdev->pdev = pdev;
3751         ql_get_board_info(qdev);
3752         qdev->msg_enable = netif_msg_init(debug, default_msg);
3753         spin_lock_init(&qdev->hw_lock);
3754         spin_lock_init(&qdev->stats_lock);
3755
3756         /* make sure the EEPROM is good */
3757         err = qdev->nic_ops->get_flash(qdev);
3758         if (err) {
3759                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3760                 goto err_out;
3761         }
3762
3763         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3764
3765         /* Set up the default ring sizes. */
3766         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3767         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3768
3769         /* Set up the coalescing parameters. */
3770         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3771         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3772         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3773         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3774
3775         /*
3776          * Set up the operating parameters.
3777          */
3778         qdev->rx_csum = 1;
3779
3780         qdev->q_workqueue = create_workqueue(ndev->name);
3781         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3782         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3783         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3784         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3785         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3786         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3787         mutex_init(&qdev->mpi_mutex);
3788         init_completion(&qdev->ide_completion);
3789
3790         if (!cards_found) {
3791                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3792                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3793                          DRV_NAME, DRV_VERSION);
3794         }
3795         return 0;
3796 err_out:
3797         ql_release_all(pdev);
3798         pci_disable_device(pdev);
3799         return err;
3800 }
3801
3802
3803 static const struct net_device_ops qlge_netdev_ops = {
3804         .ndo_open               = qlge_open,
3805         .ndo_stop               = qlge_close,
3806         .ndo_start_xmit         = qlge_send,
3807         .ndo_change_mtu         = qlge_change_mtu,
3808         .ndo_get_stats          = qlge_get_stats,
3809         .ndo_set_multicast_list = qlge_set_multicast_list,
3810         .ndo_set_mac_address    = qlge_set_mac_address,
3811         .ndo_validate_addr      = eth_validate_addr,
3812         .ndo_tx_timeout         = qlge_tx_timeout,
3813         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3814         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3815         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3816 };
3817
3818 static int __devinit qlge_probe(struct pci_dev *pdev,
3819                                 const struct pci_device_id *pci_entry)
3820 {
3821         struct net_device *ndev = NULL;
3822         struct ql_adapter *qdev = NULL;
3823         static int cards_found = 0;
3824         int err = 0;
3825
3826         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3827         if (!ndev)
3828                 return -ENOMEM;
3829
3830         err = ql_init_device(pdev, ndev, cards_found);
3831         if (err < 0) {
3832                 free_netdev(ndev);
3833                 return err;
3834         }
3835
3836         qdev = netdev_priv(ndev);
3837         SET_NETDEV_DEV(ndev, &pdev->dev);
3838         ndev->features = (0
3839                           | NETIF_F_IP_CSUM
3840                           | NETIF_F_SG
3841                           | NETIF_F_TSO
3842                           | NETIF_F_TSO6
3843                           | NETIF_F_TSO_ECN
3844                           | NETIF_F_HW_VLAN_TX
3845                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3846
3847         if (test_bit(QL_DMA64, &qdev->flags))
3848                 ndev->features |= NETIF_F_HIGHDMA;
3849
3850         /*
3851          * Set up net_device structure.
3852          */
3853         ndev->tx_queue_len = qdev->tx_ring_size;
3854         ndev->irq = pdev->irq;
3855
3856         ndev->netdev_ops = &qlge_netdev_ops;
3857         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3858         ndev->watchdog_timeo = 10 * HZ;
3859
3860         err = register_netdev(ndev);
3861         if (err) {
3862                 dev_err(&pdev->dev, "net device registration failed.\n");
3863                 ql_release_all(pdev);
3864                 pci_disable_device(pdev);
3865                 return err;
3866         }
3867         netif_carrier_off(ndev);
3868         netif_stop_queue(ndev);
3869         ql_display_dev_info(ndev);
3870         cards_found++;
3871         return 0;
3872 }
3873
3874 static void __devexit qlge_remove(struct pci_dev *pdev)
3875 {
3876         struct net_device *ndev = pci_get_drvdata(pdev);
3877         unregister_netdev(ndev);
3878         ql_release_all(pdev);
3879         pci_disable_device(pdev);
3880         free_netdev(ndev);
3881 }
3882
3883 /*
3884  * This callback is called by the PCI subsystem whenever
3885  * a PCI bus error is detected.
3886  */
3887 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3888                                                enum pci_channel_state state)
3889 {
3890         struct net_device *ndev = pci_get_drvdata(pdev);
3891         struct ql_adapter *qdev = netdev_priv(ndev);
3892
3893         if (netif_running(ndev))
3894                 ql_adapter_down(qdev);
3895
3896         pci_disable_device(pdev);
3897
3898         /* Request a slot reset. */
3899         return PCI_ERS_RESULT_NEED_RESET;
3900 }
3901
3902 /*
3903  * This callback is called after the PCI buss has been reset.
3904  * Basically, this tries to restart the card from scratch.
3905  * This is a shortened version of the device probe/discovery code,
3906  * it resembles the first-half of the () routine.
3907  */
3908 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3909 {
3910         struct net_device *ndev = pci_get_drvdata(pdev);
3911         struct ql_adapter *qdev = netdev_priv(ndev);
3912
3913         if (pci_enable_device(pdev)) {
3914                 QPRINTK(qdev, IFUP, ERR,
3915                         "Cannot re-enable PCI device after reset.\n");
3916                 return PCI_ERS_RESULT_DISCONNECT;
3917         }
3918
3919         pci_set_master(pdev);
3920
3921         netif_carrier_off(ndev);
3922         netif_stop_queue(ndev);
3923         ql_adapter_reset(qdev);
3924
3925         /* Make sure the EEPROM is good */
3926         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3927
3928         if (!is_valid_ether_addr(ndev->perm_addr)) {
3929                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3930                 return PCI_ERS_RESULT_DISCONNECT;
3931         }
3932
3933         return PCI_ERS_RESULT_RECOVERED;
3934 }
3935
3936 static void qlge_io_resume(struct pci_dev *pdev)
3937 {
3938         struct net_device *ndev = pci_get_drvdata(pdev);
3939         struct ql_adapter *qdev = netdev_priv(ndev);
3940
3941         pci_set_master(pdev);
3942
3943         if (netif_running(ndev)) {
3944                 if (ql_adapter_up(qdev)) {
3945                         QPRINTK(qdev, IFUP, ERR,
3946                                 "Device initialization failed after reset.\n");
3947                         return;
3948                 }
3949         }
3950
3951         netif_device_attach(ndev);
3952 }
3953
3954 static struct pci_error_handlers qlge_err_handler = {
3955         .error_detected = qlge_io_error_detected,
3956         .slot_reset = qlge_io_slot_reset,
3957         .resume = qlge_io_resume,
3958 };
3959
3960 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3961 {
3962         struct net_device *ndev = pci_get_drvdata(pdev);
3963         struct ql_adapter *qdev = netdev_priv(ndev);
3964         int err, i;
3965
3966         netif_device_detach(ndev);
3967
3968         if (netif_running(ndev)) {
3969                 err = ql_adapter_down(qdev);
3970                 if (!err)
3971                         return err;
3972         }
3973
3974         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3975                 netif_napi_del(&qdev->rx_ring[i].napi);
3976
3977         err = pci_save_state(pdev);
3978         if (err)
3979                 return err;
3980
3981         pci_disable_device(pdev);
3982
3983         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3984
3985         return 0;
3986 }
3987
3988 #ifdef CONFIG_PM
3989 static int qlge_resume(struct pci_dev *pdev)
3990 {
3991         struct net_device *ndev = pci_get_drvdata(pdev);
3992         struct ql_adapter *qdev = netdev_priv(ndev);
3993         int err;
3994
3995         pci_set_power_state(pdev, PCI_D0);
3996         pci_restore_state(pdev);
3997         err = pci_enable_device(pdev);
3998         if (err) {
3999                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4000                 return err;
4001         }
4002         pci_set_master(pdev);
4003
4004         pci_enable_wake(pdev, PCI_D3hot, 0);
4005         pci_enable_wake(pdev, PCI_D3cold, 0);
4006
4007         if (netif_running(ndev)) {
4008                 err = ql_adapter_up(qdev);
4009                 if (err)
4010                         return err;
4011         }
4012
4013         netif_device_attach(ndev);
4014
4015         return 0;
4016 }
4017 #endif /* CONFIG_PM */
4018
4019 static void qlge_shutdown(struct pci_dev *pdev)
4020 {
4021         qlge_suspend(pdev, PMSG_SUSPEND);
4022 }
4023
4024 static struct pci_driver qlge_driver = {
4025         .name = DRV_NAME,
4026         .id_table = qlge_pci_tbl,
4027         .probe = qlge_probe,
4028         .remove = __devexit_p(qlge_remove),
4029 #ifdef CONFIG_PM
4030         .suspend = qlge_suspend,
4031         .resume = qlge_resume,
4032 #endif
4033         .shutdown = qlge_shutdown,
4034         .err_handler = &qlge_err_handler
4035 };
4036
4037 static int __init qlge_init_module(void)
4038 {
4039         return pci_register_driver(&qlge_driver);
4040 }
4041
4042 static void __exit qlge_exit(void)
4043 {
4044         pci_unregister_driver(&qlge_driver);
4045 }
4046
4047 module_init(qlge_init_module);
4048 module_exit(qlge_exit);