IB/ipath: Change HT CRC message to indicate how to resolve problem
[linux-2.6] / drivers / infiniband / hw / ipath / ipath_iba6110.c
1 /*
2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33
34 /*
35  * This file contains all of the code that is specific to the InfiniPath
36  * HT chip.
37  */
38
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41
42 #include "ipath_kernel.h"
43 #include "ipath_registers.h"
44
45 /*
46  * This lists the InfiniPath registers, in the actual chip layout.
47  * This structure should never be directly accessed.
48  *
49  * The names are in InterCap form because they're taken straight from
50  * the chip specification.  Since they're only used in this file, they
51  * don't pollute the rest of the source.
52 */
53
54 struct _infinipath_do_not_use_kernel_regs {
55         unsigned long long Revision;
56         unsigned long long Control;
57         unsigned long long PageAlign;
58         unsigned long long PortCnt;
59         unsigned long long DebugPortSelect;
60         unsigned long long DebugPort;
61         unsigned long long SendRegBase;
62         unsigned long long UserRegBase;
63         unsigned long long CounterRegBase;
64         unsigned long long Scratch;
65         unsigned long long ReservedMisc1;
66         unsigned long long InterruptConfig;
67         unsigned long long IntBlocked;
68         unsigned long long IntMask;
69         unsigned long long IntStatus;
70         unsigned long long IntClear;
71         unsigned long long ErrorMask;
72         unsigned long long ErrorStatus;
73         unsigned long long ErrorClear;
74         unsigned long long HwErrMask;
75         unsigned long long HwErrStatus;
76         unsigned long long HwErrClear;
77         unsigned long long HwDiagCtrl;
78         unsigned long long MDIO;
79         unsigned long long IBCStatus;
80         unsigned long long IBCCtrl;
81         unsigned long long ExtStatus;
82         unsigned long long ExtCtrl;
83         unsigned long long GPIOOut;
84         unsigned long long GPIOMask;
85         unsigned long long GPIOStatus;
86         unsigned long long GPIOClear;
87         unsigned long long RcvCtrl;
88         unsigned long long RcvBTHQP;
89         unsigned long long RcvHdrSize;
90         unsigned long long RcvHdrCnt;
91         unsigned long long RcvHdrEntSize;
92         unsigned long long RcvTIDBase;
93         unsigned long long RcvTIDCnt;
94         unsigned long long RcvEgrBase;
95         unsigned long long RcvEgrCnt;
96         unsigned long long RcvBufBase;
97         unsigned long long RcvBufSize;
98         unsigned long long RxIntMemBase;
99         unsigned long long RxIntMemSize;
100         unsigned long long RcvPartitionKey;
101         unsigned long long ReservedRcv[10];
102         unsigned long long SendCtrl;
103         unsigned long long SendPIOBufBase;
104         unsigned long long SendPIOSize;
105         unsigned long long SendPIOBufCnt;
106         unsigned long long SendPIOAvailAddr;
107         unsigned long long TxIntMemBase;
108         unsigned long long TxIntMemSize;
109         unsigned long long ReservedSend[9];
110         unsigned long long SendBufferError;
111         unsigned long long SendBufferErrorCONT1;
112         unsigned long long SendBufferErrorCONT2;
113         unsigned long long SendBufferErrorCONT3;
114         unsigned long long ReservedSBE[4];
115         unsigned long long RcvHdrAddr0;
116         unsigned long long RcvHdrAddr1;
117         unsigned long long RcvHdrAddr2;
118         unsigned long long RcvHdrAddr3;
119         unsigned long long RcvHdrAddr4;
120         unsigned long long RcvHdrAddr5;
121         unsigned long long RcvHdrAddr6;
122         unsigned long long RcvHdrAddr7;
123         unsigned long long RcvHdrAddr8;
124         unsigned long long ReservedRHA[7];
125         unsigned long long RcvHdrTailAddr0;
126         unsigned long long RcvHdrTailAddr1;
127         unsigned long long RcvHdrTailAddr2;
128         unsigned long long RcvHdrTailAddr3;
129         unsigned long long RcvHdrTailAddr4;
130         unsigned long long RcvHdrTailAddr5;
131         unsigned long long RcvHdrTailAddr6;
132         unsigned long long RcvHdrTailAddr7;
133         unsigned long long RcvHdrTailAddr8;
134         unsigned long long ReservedRHTA[7];
135         unsigned long long Sync;        /* Software only */
136         unsigned long long Dump;        /* Software only */
137         unsigned long long SimVer;      /* Software only */
138         unsigned long long ReservedSW[5];
139         unsigned long long SerdesConfig0;
140         unsigned long long SerdesConfig1;
141         unsigned long long SerdesStatus;
142         unsigned long long XGXSConfig;
143         unsigned long long ReservedSW2[4];
144 };
145
146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
147     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
148 #define IPATH_CREG_OFFSET(field) (offsetof( \
149     struct infinipath_counters, field) / sizeof(u64))
150
151 static const struct ipath_kregs ipath_ht_kregs = {
152         .kr_control = IPATH_KREG_OFFSET(Control),
153         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
154         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
155         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
156         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
157         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
158         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
159         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
160         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
161         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
162         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
163         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
164         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
165         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
166         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
167         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
168         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
169         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
170         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
171         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
172         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
173         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
174         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
175         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
176         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
177         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
178         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
179         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
180         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
181         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
182         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
183         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
184         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
185         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
186         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
187         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
188         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
189         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
190         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
191         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
192         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
193         .kr_revision = IPATH_KREG_OFFSET(Revision),
194         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
195         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
196         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
197         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
198         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
199         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
200         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
201         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
202         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
203         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
204         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
205         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
206         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
207         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
208         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
209         /*
210          * These should not be used directly via ipath_read_kreg64(),
211          * use them with ipath_read_kreg64_port(),
212          */
213         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
214         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
215 };
216
217 static const struct ipath_cregs ipath_ht_cregs = {
218         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
219         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
220         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
221         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
222         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
223         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
224         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
225         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
226         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
227         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
228         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
229         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
230         /* calc from Reg_CounterRegBase + offset */
231         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
232         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
233         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
234         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
235         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
236         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
237         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
238         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
239         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
240         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
241         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
242         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
243         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
244         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
245         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
246         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
247         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
248         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
249         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
250         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
251         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
252 };
253
254 /* kr_intstatus, kr_intclear, kr_intmask bits */
255 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
256 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
257
258 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
259 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
260 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
261 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
262 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
263 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
264 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
265 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
266 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
267 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
268 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
269 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
270 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
271 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
272 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
273 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
274 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
275 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
276 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
277 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
278 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
279
280 /* kr_extstatus bits */
281 #define INFINIPATH_EXTS_FREQSEL 0x2
282 #define INFINIPATH_EXTS_SERDESSEL 0x4
283 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
284 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
285
286 /*
287  * masks and bits that are different in different chips, or present only
288  * in one
289  */
290 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
291     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
292 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
293     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
294
295 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
296     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
297 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
298     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
299 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
300     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
301 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
302     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
303
304 #define _IPATH_GPIO_SDA_NUM 1
305 #define _IPATH_GPIO_SCL_NUM 0
306
307 #define IPATH_GPIO_SDA \
308         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
309 #define IPATH_GPIO_SCL \
310         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
311
312 /* keep the code below somewhat more readonable; not used elsewhere */
313 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
314                                 infinipath_hwe_htclnkabyte1crcerr)
315 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
316                                 infinipath_hwe_htclnkbbyte1crcerr)
317 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
318                                 infinipath_hwe_htclnkbbyte0crcerr)
319 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
320                                 infinipath_hwe_htclnkbbyte1crcerr)
321
322 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
323                           char *msg, size_t msgl)
324 {
325         char bitsmsg[64];
326         ipath_err_t crcbits = hwerrs &
327                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
328         /* don't check if 8bit HT */
329         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
330                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
331         /* don't check if 8bit HT */
332         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
333                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
334         /*
335          * we'll want to ignore link errors on link that is
336          * not in use, if any.  For now, complain about both
337          */
338         if (crcbits) {
339                 u16 ctrl0, ctrl1;
340                 snprintf(bitsmsg, sizeof bitsmsg,
341                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
342                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
343                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
344                                     ? "1 (B)" : "0+1 (A+B)"),
345                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
346                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
347                             "0+1"), (unsigned long long) crcbits);
348                 strlcat(msg, bitsmsg, msgl);
349
350                 /*
351                  * print extra info for debugging.  slave/primary
352                  * config word 4, 8 (link control 0, 1)
353                  */
354
355                 if (pci_read_config_word(dd->pcidev,
356                                          dd->ipath_ht_slave_off + 0x4,
357                                          &ctrl0))
358                         dev_info(&dd->pcidev->dev, "Couldn't read "
359                                  "linkctrl0 of slave/primary "
360                                  "config block\n");
361                 else if (!(ctrl0 & 1 << 6))
362                         /* not if EOC bit set */
363                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
364                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
365                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
366                                   "");
367                 if (pci_read_config_word(dd->pcidev,
368                                          dd->ipath_ht_slave_off + 0x8,
369                                          &ctrl1))
370                         dev_info(&dd->pcidev->dev, "Couldn't read "
371                                  "linkctrl1 of slave/primary "
372                                  "config block\n");
373                 else if (!(ctrl1 & 1 << 6))
374                         /* not if EOC bit set */
375                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
376                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
377                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
378                                   "");
379
380                 /* disable until driver reloaded */
381                 dd->ipath_hwerrmask &= ~crcbits;
382                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
383                                  dd->ipath_hwerrmask);
384                 ipath_dbg("HT crc errs: %s\n", msg);
385         } else
386                 ipath_dbg("ignoring HT crc errors 0x%llx, "
387                           "not in use\n", (unsigned long long)
388                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
389                                      _IPATH_HTLINK1_CRCBITS)));
390 }
391
392 /* 6110 specific hardware errors... */
393 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
394         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
395         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
396         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
397         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
398         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
399         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
400         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
401         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
402 };
403
404 /**
405  * ipath_ht_handle_hwerrors - display hardware errors.
406  * @dd: the infinipath device
407  * @msg: the output buffer
408  * @msgl: the size of the output buffer
409  *
410  * Use same msg buffer as regular errors to avoid excessive stack
411  * use.  Most hardware errors are catastrophic, but for right now,
412  * we'll print them and continue.  We reuse the same message buffer as
413  * ipath_handle_errors() to avoid excessive stack usage.
414  */
415 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
416                                      size_t msgl)
417 {
418         ipath_err_t hwerrs;
419         u32 bits, ctrl;
420         int isfatal = 0;
421         char bitsmsg[64];
422
423         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
424
425         if (!hwerrs) {
426                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
427                 /*
428                  * better than printing cofusing messages
429                  * This seems to be related to clearing the crc error, or
430                  * the pll error during init.
431                  */
432                 goto bail;
433         } else if (hwerrs == -1LL) {
434                 ipath_dev_err(dd, "Read of hardware error status failed "
435                               "(all bits set); ignoring\n");
436                 goto bail;
437         }
438         ipath_stats.sps_hwerrs++;
439
440         /* Always clear the error status register, except MEMBISTFAIL,
441          * regardless of whether we continue or stop using the chip.
442          * We want that set so we know it failed, even across driver reload.
443          * We'll still ignore it in the hwerrmask.  We do this partly for
444          * diagnostics, but also for support */
445         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
446                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
447
448         hwerrs &= dd->ipath_hwerrmask;
449
450         /*
451          * make sure we get this much out, unless told to be quiet,
452          * or it's occurred within the last 5 seconds
453          */
454         if ((hwerrs & ~dd->ipath_lasthwerror) ||
455             (ipath_debug & __IPATH_VERBDBG))
456                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
457                          "(cleared)\n", (unsigned long long) hwerrs);
458         dd->ipath_lasthwerror |= hwerrs;
459
460         if (hwerrs & ~dd->ipath_hwe_bitsextant)
461                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
462                               "%llx set\n", (unsigned long long)
463                               (hwerrs & ~dd->ipath_hwe_bitsextant));
464
465         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
466         if (ctrl & INFINIPATH_C_FREEZEMODE) {
467                 if (hwerrs) {
468                         /*
469                          * if any set that we aren't ignoring; only
470                          * make the complaint once, in case it's stuck
471                          * or recurring, and we get here multiple
472                          * times.
473                          */
474                         if (dd->ipath_flags & IPATH_INITTED) {
475                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
476                                               "mode), no longer usable, SN %.16s\n",
477                                                   dd->ipath_serial);
478                                 isfatal = 1;
479                         }
480                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
481                         /* mark as having had error */
482                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
483                         /*
484                          * mark as not usable, at a minimum until driver
485                          * is reloaded, probably until reboot, since no
486                          * other reset is possible.
487                          */
488                         dd->ipath_flags &= ~IPATH_INITTED;
489                 } else {
490                         ipath_dbg("Clearing freezemode on ignored hardware "
491                                   "error\n");
492                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
493                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
494                                          ctrl);
495                 }
496         }
497
498         *msg = '\0';
499
500         /*
501          * may someday want to decode into which bits are which
502          * functional area for parity errors, etc.
503          */
504         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
505                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
506                 bits = (u32) ((hwerrs >>
507                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
508                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
509                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
510                          bits);
511                 strlcat(msg, bitsmsg, msgl);
512         }
513
514         ipath_format_hwerrors(hwerrs,
515                               ipath_6110_hwerror_msgs,
516                               sizeof(ipath_6110_hwerror_msgs) /
517                               sizeof(ipath_6110_hwerror_msgs[0]),
518                               msg, msgl);
519
520         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
521                 hwerr_crcbits(dd, hwerrs, msg, msgl);
522
523         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
524                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
525                         msgl);
526                 /* ignore from now on, so disable until driver reloaded */
527                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
528                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
529                                  dd->ipath_hwerrmask);
530         }
531 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
532                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
533                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
534                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
535                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
536                          INFINIPATH_HWE_HTAPLL_RFSLIP)
537
538         if (hwerrs & _IPATH_PLL_FAIL) {
539                 snprintf(bitsmsg, sizeof bitsmsg,
540                          "[PLL failed (%llx), InfiniPath hardware unusable]",
541                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
542                 strlcat(msg, bitsmsg, msgl);
543                 /* ignore from now on, so disable until driver reloaded */
544                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
545                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
546                                  dd->ipath_hwerrmask);
547         }
548
549         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
550                 /*
551                  * If it occurs, it is left masked since the eternal
552                  * interface is unused
553                  */
554                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
555                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
556                                  dd->ipath_hwerrmask);
557         }
558
559         ipath_dev_err(dd, "%s hardware error\n", msg);
560         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
561                 /*
562                  * for status file; if no trailing brace is copied,
563                  * we'll know it was truncated.
564                  */
565                 snprintf(dd->ipath_freezemsg,
566                          dd->ipath_freezelen, "{%s}", msg);
567
568 bail:;
569 }
570
571 /**
572  * ipath_ht_boardname - fill in the board name
573  * @dd: the infinipath device
574  * @name: the output buffer
575  * @namelen: the size of the output buffer
576  *
577  * fill in the board name, based on the board revision register
578  */
579 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
580                               size_t namelen)
581 {
582         char *n = NULL;
583         u8 boardrev = dd->ipath_boardrev;
584         int ret;
585
586         switch (boardrev) {
587         case 4:         /* Ponderosa is one of the bringup boards */
588                 n = "Ponderosa";
589                 break;
590         case 5:
591                 /*
592                  * original production board; two production levels, with
593                  * different serial number ranges.   See ipath_ht_early_init() for
594                  * case where we enable IPATH_GPIO_INTR for later serial # range.
595                  */
596                 n = "InfiniPath_QHT7040";
597                 break;
598         case 6:
599                 n = "OEM_Board_3";
600                 break;
601         case 7:
602                 /* small form factor production board */
603                 n = "InfiniPath_QHT7140";
604                 break;
605         case 8:
606                 n = "LS/X-1";
607                 break;
608         case 9:         /* Comstock bringup test board */
609                 n = "Comstock";
610                 break;
611         case 10:
612                 n = "OEM_Board_2";
613                 break;
614         case 11:
615                 n = "InfiniPath_HT-470"; /* obsoleted */
616                 break;
617         case 12:
618                 n = "OEM_Board_4";
619                 break;
620         default:                /* don't know, just print the number */
621                 ipath_dev_err(dd, "Don't yet know about board "
622                               "with ID %u\n", boardrev);
623                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
624                          boardrev);
625                 break;
626         }
627         if (n)
628                 snprintf(name, namelen, "%s", n);
629
630         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || dd->ipath_minrev > 3)) {
631                 /*
632                  * This version of the driver only supports Rev 3.2 and 3.3
633                  */
634                 ipath_dev_err(dd,
635                               "Unsupported InfiniPath hardware revision %u.%u!\n",
636                               dd->ipath_majrev, dd->ipath_minrev);
637                 ret = 1;
638                 goto bail;
639         }
640         /*
641          * pkt/word counters are 32 bit, and therefore wrap fast enough
642          * that we snapshot them from a timer, and maintain 64 bit shadow
643          * copies
644          */
645         dd->ipath_flags |= IPATH_32BITCOUNTERS;
646         if (dd->ipath_htspeed != 800)
647                 ipath_dev_err(dd,
648                               "Incorrectly configured for HT @ %uMHz\n",
649                               dd->ipath_htspeed);
650         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
651             dd->ipath_boardrev == 6)
652                 dd->ipath_flags |= IPATH_GPIO_INTR;
653         else
654                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
655         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
656                 u64 val;
657                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
658                 if (val & INFINIPATH_EXTS_SERDESSEL) {
659                         /*
660                          * hardware disabled
661                          *
662                          * This means that the chip is hardware disabled,
663                          * and will not be able to bring up the link,
664                          * in any case.  We special case this and abort
665                          * early, to avoid later messages.  We also set
666                          * the DISABLED status bit
667                          */
668                         ipath_dbg("Unit %u is hardware-disabled\n",
669                                   dd->ipath_unit);
670                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
671                         /* this value is handled differently */
672                         ret = 2;
673                         goto bail;
674                 }
675         }
676         ret = 0;
677
678 bail:
679         return ret;
680 }
681
682 static void ipath_check_htlink(struct ipath_devdata *dd)
683 {
684         u8 linkerr, link_off, i;
685
686         for (i = 0; i < 2; i++) {
687                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
688                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
689                         dev_info(&dd->pcidev->dev, "Couldn't read "
690                                  "linkerror%d of HT slave/primary block\n",
691                                  i);
692                 else if (linkerr & 0xf0) {
693                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
694                                    "clearing\n", linkerr >> 4, i);
695                         /*
696                          * writing the linkerr bits that are set should
697                          * clear them
698                          */
699                         if (pci_write_config_byte(dd->pcidev, link_off,
700                                                   linkerr))
701                                 ipath_dbg("Failed write to clear HT "
702                                           "linkerror%d\n", i);
703                         if (pci_read_config_byte(dd->pcidev, link_off,
704                                                  &linkerr))
705                                 dev_info(&dd->pcidev->dev,
706                                          "Couldn't reread linkerror%d of "
707                                          "HT slave/primary block\n", i);
708                         else if (linkerr & 0xf0)
709                                 dev_info(&dd->pcidev->dev,
710                                          "HT linkerror%d bits 0x%x "
711                                          "couldn't be cleared\n",
712                                          i, linkerr >> 4);
713                 }
714         }
715 }
716
717 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
718 {
719         ipath_dbg("No reset possible for this InfiniPath hardware\n");
720         return 0;
721 }
722
723 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
724 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
725
726 /*
727  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
728  * errors.  We only bother to do this at load time, because it's OK if
729  * it happened before we were loaded (first time after boot/reset),
730  * but any time after that, it's fatal anyway.  Also need to not check
731  * for for upper byte errors if we are in 8 bit mode, so figure out
732  * our width.  For now, at least, also complain if it's 8 bit.
733  */
734 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
735                              int pos, u8 cap_type)
736 {
737         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
738         u16 linkctrl = 0;
739         int i;
740
741         dd->ipath_ht_slave_off = pos;
742         /* command word, master_host bit */
743         /* master host || slave */
744         if ((cap_type >> 2) & 1)
745                 link_a_b_off = 4;
746         else
747                 link_a_b_off = 0;
748         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
749                    link_a_b_off ? 1 : 0,
750                    link_a_b_off ? 'B' : 'A');
751
752         link_a_b_off += pos;
753
754         /*
755          * check both link control registers; clear both HT CRC sets if
756          * necessary.
757          */
758         for (i = 0; i < 2; i++) {
759                 link_off = pos + i * 4 + 0x4;
760                 if (pci_read_config_word(pdev, link_off, &linkctrl))
761                         ipath_dev_err(dd, "Couldn't read HT link control%d "
762                                       "register\n", i);
763                 else if (linkctrl & (0xf << 8)) {
764                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
765                                    "bits %x\n", i, linkctrl & (0xf << 8));
766                         /*
767                          * now write them back to clear the error.
768                          */
769                         pci_write_config_byte(pdev, link_off,
770                                               linkctrl & (0xf << 8));
771                 }
772         }
773
774         /*
775          * As with HT CRC bits, same for protocol errors that might occur
776          * during boot.
777          */
778         for (i = 0; i < 2; i++) {
779                 link_off = pos + i * 4 + 0xd;
780                 if (pci_read_config_byte(pdev, link_off, &linkerr))
781                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
782                                  "of HT slave/primary block\n", i);
783                 else if (linkerr & 0xf0) {
784                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
785                                    "clearing\n", linkerr >> 4, i);
786                         /*
787                          * writing the linkerr bits that are set will clear
788                          * them
789                          */
790                         if (pci_write_config_byte
791                             (pdev, link_off, linkerr))
792                                 ipath_dbg("Failed write to clear HT "
793                                           "linkerror%d\n", i);
794                         if (pci_read_config_byte(pdev, link_off, &linkerr))
795                                 dev_info(&pdev->dev, "Couldn't reread "
796                                          "linkerror%d of HT slave/primary "
797                                          "block\n", i);
798                         else if (linkerr & 0xf0)
799                                 dev_info(&pdev->dev, "HT linkerror%d bits "
800                                          "0x%x couldn't be cleared\n",
801                                          i, linkerr >> 4);
802                 }
803         }
804
805         /*
806          * this is just for our link to the host, not devices connected
807          * through tunnel.
808          */
809
810         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
811                 ipath_dev_err(dd, "Couldn't read HT link width "
812                               "config register\n");
813         else {
814                 u32 width;
815                 switch (linkwidth & 7) {
816                 case 5:
817                         width = 4;
818                         break;
819                 case 4:
820                         width = 2;
821                         break;
822                 case 3:
823                         width = 32;
824                         break;
825                 case 1:
826                         width = 16;
827                         break;
828                 case 0:
829                 default:        /* if wrong, assume 8 bit */
830                         width = 8;
831                         break;
832                 }
833
834                 dd->ipath_htwidth = width;
835
836                 if (linkwidth != 0x11) {
837                         ipath_dev_err(dd, "Not configured for 16 bit HT "
838                                       "(%x)\n", linkwidth);
839                         if (!(linkwidth & 0xf)) {
840                                 ipath_dbg("Will ignore HT lane1 errors\n");
841                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
842                         }
843                 }
844         }
845
846         /*
847          * this is just for our link to the host, not devices connected
848          * through tunnel.
849          */
850         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
851                 ipath_dev_err(dd, "Couldn't read HT link frequency "
852                               "config register\n");
853         else {
854                 u32 speed;
855                 switch (linkwidth & 0xf) {
856                 case 6:
857                         speed = 1000;
858                         break;
859                 case 5:
860                         speed = 800;
861                         break;
862                 case 4:
863                         speed = 600;
864                         break;
865                 case 3:
866                         speed = 500;
867                         break;
868                 case 2:
869                         speed = 400;
870                         break;
871                 case 1:
872                         speed = 300;
873                         break;
874                 default:
875                         /*
876                          * assume reserved and vendor-specific are 200...
877                          */
878                 case 0:
879                         speed = 200;
880                         break;
881                 }
882                 dd->ipath_htspeed = speed;
883         }
884 }
885
886 static int set_int_handler(struct ipath_devdata *dd, struct pci_dev *pdev,
887                             int pos)
888 {
889         u32 int_handler_addr_lower;
890         u32 int_handler_addr_upper;
891         u64 ihandler;
892         u32 intvec;
893
894         /* use indirection register to get the intr handler */
895         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x10);
896         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_lower);
897         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x11);
898         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_upper);
899
900         ihandler = (u64) int_handler_addr_lower |
901                 ((u64) int_handler_addr_upper << 32);
902
903         /*
904          * kernels with CONFIG_PCI_MSI set the vector in the irq field of
905          * struct pci_device, so we use that to program the internal
906          * interrupt register (not config space) with that value. The BIOS
907          * must still have done the basic MSI setup.
908          */
909         intvec = pdev->irq;
910         /*
911          * clear any vector bits there; normally not set but we'll overload
912          * this for some debug purposes (setting the HTC debug register
913          * value from software, rather than GPIOs), so it might be set on a
914          * driver reload.
915          */
916         ihandler &= ~0xff0000;
917         /* x86 vector goes in intrinfo[23:16] */
918         ihandler |= intvec << 16;
919         ipath_cdbg(VERBOSE, "ihandler lower %x, upper %x, intvec %x, "
920                    "interruptconfig %llx\n", int_handler_addr_lower,
921                    int_handler_addr_upper, intvec,
922                    (unsigned long long) ihandler);
923
924         /* can't program yet, so save for interrupt setup */
925         dd->ipath_intconfig = ihandler;
926         /* keep going, so we find link control stuff also */
927
928         return ihandler != 0;
929 }
930
931 /**
932  * ipath_setup_ht_config - setup the interruptconfig register
933  * @dd: the infinipath device
934  * @pdev: the PCI device
935  *
936  * setup the interruptconfig register from the HT config info.
937  * Also clear CRC errors in HT linkcontrol, if necessary.
938  * This is done only for the real hardware.  It is done before
939  * chip address space is initted, so can't touch infinipath registers
940  */
941 static int ipath_setup_ht_config(struct ipath_devdata *dd,
942                                  struct pci_dev *pdev)
943 {
944         int pos, ret = 0;
945         int ihandler = 0;
946
947         /*
948          * Read the capability info to find the interrupt info, and also
949          * handle clearing CRC errors in linkctrl register if necessary.  We
950          * do this early, before we ever enable errors or hardware errors,
951          * mostly to avoid causing the chip to enter freeze mode.
952          */
953         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
954         if (!pos) {
955                 ipath_dev_err(dd, "Couldn't find HyperTransport "
956                               "capability; no interrupts\n");
957                 ret = -ENODEV;
958                 goto bail;
959         }
960         do {
961                 u8 cap_type;
962
963                 /* the HT capability type byte is 3 bytes after the
964                  * capability byte.
965                  */
966                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
967                         dev_info(&pdev->dev, "Couldn't read config "
968                                  "command @ %d\n", pos);
969                         continue;
970                 }
971                 if (!(cap_type & 0xE0))
972                         slave_or_pri_blk(dd, pdev, pos, cap_type);
973                 else if (cap_type == HT_INTR_DISC_CONFIG)
974                         ihandler = set_int_handler(dd, pdev, pos);
975         } while ((pos = pci_find_next_capability(pdev, pos,
976                                                  PCI_CAP_ID_HT)));
977
978         if (!ihandler) {
979                 ipath_dev_err(dd, "Couldn't find interrupt handler in "
980                               "config space\n");
981                 ret = -ENODEV;
982         }
983
984 bail:
985         return ret;
986 }
987
988 /**
989  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
990  * @dd: the infinipath device
991  *
992  * Called during driver unload.
993  * This is currently a nop for the HT chip, not for all chips
994  */
995 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
996 {
997 }
998
999 /**
1000  * ipath_setup_ht_setextled - set the state of the two external LEDs
1001  * @dd: the infinipath device
1002  * @lst: the L state
1003  * @ltst: the LT state
1004  *
1005  * Set the state of the two external LEDs, to indicate physical and
1006  * logical state of IB link.   For this chip (at least with recommended
1007  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1008  * (logical state)
1009  *
1010  * Note:  We try to match the Mellanox HCA LED behavior as best
1011  * we can.  Green indicates physical link state is OK (something is
1012  * plugged in, and we can train).
1013  * Amber indicates the link is logically up (ACTIVE).
1014  * Mellanox further blinks the amber LED to indicate data packet
1015  * activity, but we have no hardware support for that, so it would
1016  * require waking up every 10-20 msecs and checking the counters
1017  * on the chip, and then turning the LED off if appropriate.  That's
1018  * visible overhead, so not something we will do.
1019  *
1020  */
1021 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1022                                      u64 lst, u64 ltst)
1023 {
1024         u64 extctl;
1025
1026         /* the diags use the LED to indicate diag info, so we leave
1027          * the external LED alone when the diags are running */
1028         if (ipath_diag_inuse)
1029                 return;
1030
1031         /*
1032          * start by setting both LED control bits to off, then turn
1033          * on the appropriate bit(s).
1034          */
1035         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1036                 /*
1037                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1038                  * is inverted,  because it is normally used to indicate
1039                  * a hardware fault at reset, if there were errors
1040                  */
1041                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1042                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1043                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1044                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1045                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1046                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1047         }
1048         else {
1049                 extctl = dd->ipath_extctrl &
1050                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1051                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1052                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1053                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1054                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1055                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1056         }
1057         dd->ipath_extctrl = extctl;
1058         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1059 }
1060
1061 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1062 {
1063         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1064         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1065         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1066         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1067
1068         dd->ipath_i_bitsextant =
1069                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1070                 (INFINIPATH_I_RCVAVAIL_MASK <<
1071                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1072                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1073                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1074
1075         dd->ipath_e_bitsextant =
1076                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1077                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1078                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1079                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1080                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1081                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1082                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1083                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1084                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1085                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1086                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1087                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1088                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1089                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1090                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1091                 INFINIPATH_E_HARDWARE;
1092
1093         dd->ipath_hwe_bitsextant =
1094                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1095                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1096                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1097                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1098                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1099                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1100                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1101                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1102                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1103                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1104                 INFINIPATH_HWE_HTCMISCERR4 |
1105                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1106                 INFINIPATH_HWE_HTCMISCERR7 |
1107                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1108                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1109                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1110                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1111                 INFINIPATH_HWE_MEMBISTFAILED |
1112                 INFINIPATH_HWE_COREPLL_FBSLIP |
1113                 INFINIPATH_HWE_COREPLL_RFSLIP |
1114                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1115                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1116                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1117                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1118                 INFINIPATH_HWE_SERDESPLLFAILED |
1119                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1120                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1121
1122         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1123         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1124 }
1125
1126 /**
1127  * ipath_ht_init_hwerrors - enable hardware errors
1128  * @dd: the infinipath device
1129  *
1130  * now that we have finished initializing everything that might reasonably
1131  * cause a hardware error, and cleared those errors bits as they occur,
1132  * we can enable hardware errors in the mask (potentially enabling
1133  * freeze mode), and enable hardware errors as errors (along with
1134  * everything else) in errormask
1135  */
1136 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1137 {
1138         ipath_err_t val;
1139         u64 extsval;
1140
1141         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1142
1143         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1144                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1145
1146         ipath_check_htlink(dd);
1147
1148         /* barring bugs, all hwerrors become interrupts, which can */
1149         val = -1LL;
1150         /* don't look at crc lane1 if 8 bit */
1151         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1152                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1153         /* don't look at crc lane1 if 8 bit */
1154         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1155                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1156
1157         /*
1158          * disable RXDSYNCMEMPARITY because external serdes is unused,
1159          * and therefore the logic will never be used or initialized,
1160          * and uninitialized state will normally result in this error
1161          * being asserted.  Similarly for the external serdess pll
1162          * lock signal.
1163          */
1164         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1165                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1166
1167         /*
1168          * Disable MISCERR4 because of an inversion in the HT core
1169          * logic checking for errors that cause this bit to be set.
1170          * The errata can also cause the protocol error bit to be set
1171          * in the HT config space linkerror register(s).
1172          */
1173         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1174
1175         /*
1176          * PLL ignored because MDIO interface has a logic problem
1177          * for reads, on Comstock and Ponderosa.  BRINGUP
1178          */
1179         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1180                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1181         dd->ipath_hwerrmask = val;
1182 }
1183
1184 /**
1185  * ipath_ht_bringup_serdes - bring up the serdes
1186  * @dd: the infinipath device
1187  */
1188 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1189 {
1190         u64 val, config1;
1191         int ret = 0, change = 0;
1192
1193         ipath_dbg("Trying to bringup serdes\n");
1194
1195         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1196             INFINIPATH_HWE_SERDESPLLFAILED)
1197         {
1198                 ipath_dbg("At start, serdes PLL failed bit set in "
1199                           "hwerrstatus, clearing and continuing\n");
1200                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1201                                  INFINIPATH_HWE_SERDESPLLFAILED);
1202         }
1203
1204         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1205         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1206
1207         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1208                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1209                    (unsigned long long) val, (unsigned long long) config1,
1210                    (unsigned long long)
1211                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1212                    (unsigned long long)
1213                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1214
1215         /* force reset on */
1216         val |= INFINIPATH_SERDC0_RESET_PLL
1217                 /* | INFINIPATH_SERDC0_RESET_MASK */
1218                 ;
1219         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1220         udelay(15);             /* need pll reset set at least for a bit */
1221
1222         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1223                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1224                 /* set lane resets, and tx idle, during pll reset */
1225                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1226                         INFINIPATH_SERDC0_TXIDLE;
1227                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1228                            "%llx)\n", (unsigned long long) val2);
1229                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1230                                  val2);
1231                 /*
1232                  * be sure chip saw it
1233                  */
1234                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1235                 /*
1236                  * need pll reset clear at least 11 usec before lane
1237                  * resets cleared; give it a few more
1238                  */
1239                 udelay(15);
1240                 val = val2;     /* for check below */
1241         }
1242
1243         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1244                    INFINIPATH_SERDC0_RESET_MASK |
1245                    INFINIPATH_SERDC0_TXIDLE)) {
1246                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1247                          INFINIPATH_SERDC0_RESET_MASK |
1248                          INFINIPATH_SERDC0_TXIDLE);
1249                 /* clear them */
1250                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1251                                  val);
1252         }
1253
1254         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1255         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1256              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1257                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1258                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1259                 /*
1260                  * we use address 3
1261                  */
1262                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1263                 change = 1;
1264         }
1265         if (val & INFINIPATH_XGXS_RESET) {
1266                 /* normally true after boot */
1267                 val &= ~INFINIPATH_XGXS_RESET;
1268                 change = 1;
1269         }
1270         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1271              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1272                 /* need to compensate for Tx inversion in partner */
1273                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1274                          INFINIPATH_XGXS_RX_POL_SHIFT);
1275                 val |= dd->ipath_rx_pol_inv <<
1276                         INFINIPATH_XGXS_RX_POL_SHIFT;
1277                 change = 1;
1278         }
1279         if (change)
1280                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1281
1282         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1283
1284         /* clear current and de-emphasis bits */
1285         config1 &= ~0x0ffffffff00ULL;
1286         /* set current to 20ma */
1287         config1 |= 0x00000000000ULL;
1288         /* set de-emphasis to -5.68dB */
1289         config1 |= 0x0cccc000000ULL;
1290         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1291
1292         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1293                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1294                    (unsigned long long) val, (unsigned long long) config1,
1295                    (unsigned long long)
1296                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1297                    (unsigned long long)
1298                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1299
1300         if (!ipath_waitfor_mdio_cmdready(dd)) {
1301                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1302                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1303                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1304                                                 0));
1305                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1306                                            IPATH_MDIO_DATAVALID, &val))
1307                         ipath_dbg("Never got MDIO data for XGXS status "
1308                                   "read\n");
1309                 else
1310                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1311                                    "'bank' 31 %x\n", (u32) val);
1312         } else
1313                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1314
1315         return ret;             /* for now, say we always succeeded */
1316 }
1317
1318 /**
1319  * ipath_ht_quiet_serdes - set serdes to txidle
1320  * @dd: the infinipath device
1321  * driver is being unloaded
1322  */
1323 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1324 {
1325         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1326
1327         val |= INFINIPATH_SERDC0_TXIDLE;
1328         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1329                   (unsigned long long) val);
1330         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1331 }
1332
1333 static int ipath_ht_intconfig(struct ipath_devdata *dd)
1334 {
1335         int ret;
1336
1337         if (!dd->ipath_intconfig) {
1338                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
1339                               "interrupt address\n");
1340                 ret = 1;
1341                 goto bail;
1342         }
1343
1344         ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
1345                          dd->ipath_intconfig);  /* interrupt address */
1346         ret = 0;
1347
1348 bail:
1349         return ret;
1350 }
1351
1352 /**
1353  * ipath_pe_put_tid - write a TID in chip
1354  * @dd: the infinipath device
1355  * @tidptr: pointer to the expected TID (in chip) to udpate
1356  * @tidtype: 0 for eager, 1 for expected
1357  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1358  *
1359  * This exists as a separate routine to allow for special locking etc.
1360  * It's used for both the full cleanup on exit, as well as the normal
1361  * setup and teardown.
1362  */
1363 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1364                              u64 __iomem *tidptr, u32 type,
1365                              unsigned long pa)
1366 {
1367         if (pa != dd->ipath_tidinvalid) {
1368                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1369                         dev_info(&dd->pcidev->dev,
1370                                  "physaddr %lx has more than "
1371                                  "40 bits, using only 40!!!\n", pa);
1372                         pa &= INFINIPATH_RT_ADDR_MASK;
1373                 }
1374                 if (type == 0)
1375                         pa |= dd->ipath_tidtemplate;
1376                 else {
1377                         /* in words (fixed, full page).  */
1378                         u64 lenvalid = PAGE_SIZE >> 2;
1379                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1380                         pa |= lenvalid | INFINIPATH_RT_VALID;
1381                 }
1382         }
1383         if (dd->ipath_kregbase)
1384                 writeq(pa, tidptr);
1385 }
1386
1387 /**
1388  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1389  * @dd: the infinipath device
1390  * @port: the port
1391  *
1392  * Used from ipath_close(), and at chip initialization.
1393  */
1394 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1395 {
1396         u64 __iomem *tidbase;
1397         int i;
1398
1399         if (!dd->ipath_kregbase)
1400                 return;
1401
1402         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1403
1404         /*
1405          * need to invalidate all of the expected TID entries for this
1406          * port, so we don't have valid entries that might somehow get
1407          * used (early in next use of this port, or through some bug)
1408          */
1409         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1410                                    dd->ipath_rcvtidbase +
1411                                    port * dd->ipath_rcvtidcnt *
1412                                    sizeof(*tidbase));
1413         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1414                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1415
1416         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1417                                    dd->ipath_rcvegrbase +
1418                                    port * dd->ipath_rcvegrcnt *
1419                                    sizeof(*tidbase));
1420
1421         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1422                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1423 }
1424
1425 /**
1426  * ipath_ht_tidtemplate - setup constants for TID updates
1427  * @dd: the infinipath device
1428  *
1429  * We setup stuff that we use a lot, to avoid calculating each time
1430  */
1431 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1432 {
1433         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1434         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1435         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1436
1437         /*
1438          * work around chip errata bug 7358, by marking invalid tids
1439          * as having max length
1440          */
1441         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1442                 INFINIPATH_RT_BUFSIZE_SHIFT;
1443 }
1444
1445 static int ipath_ht_early_init(struct ipath_devdata *dd)
1446 {
1447         u32 __iomem *piobuf;
1448         u32 pioincr, val32, egrsize;
1449         int i;
1450
1451         /*
1452          * one cache line; long IB headers will spill over into received
1453          * buffer
1454          */
1455         dd->ipath_rcvhdrentsize = 16;
1456         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1457
1458         /*
1459          * For HT, we allocate a somewhat overly large eager buffer,
1460          * such that we can guarantee that we can receive the largest
1461          * packet that we can send out.  To truly support a 4KB MTU,
1462          * we need to bump this to a large value.  To date, other than
1463          * testing, we have never encountered an HCA that can really
1464          * send 4KB MTU packets, so we do not handle that (we'll get
1465          * errors interrupts if we ever see one).
1466          */
1467         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1468         egrsize = dd->ipath_rcvegrbufsize;
1469
1470         /*
1471          * the min() check here is currently a nop, but it may not
1472          * always be, depending on just how we do ipath_rcvegrbufsize
1473          */
1474         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1475                                  dd->ipath_rcvegrbufsize);
1476         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1477         ipath_ht_tidtemplate(dd);
1478
1479         /*
1480          * zero all the TID entries at startup.  We do this for sanity,
1481          * in case of a previous driver crash of some kind, and also
1482          * because the chip powers up with these memories in an unknown
1483          * state.  Use portcnt, not cfgports, since this is for the
1484          * full chip, not for current (possibly different) configuration
1485          * value.
1486          * Chip Errata bug 6447
1487          */
1488         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1489                 ipath_ht_clear_tids(dd, val32);
1490
1491         /*
1492          * write the pbc of each buffer, to be sure it's initialized, then
1493          * cancel all the buffers, and also abort any packets that might
1494          * have been in flight for some reason (the latter is for driver
1495          * unload/reload, but isn't a bad idea at first init).  PIO send
1496          * isn't enabled at this point, so there is no danger of sending
1497          * these out on the wire.
1498          * Chip Errata bug 6610
1499          */
1500         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1501                                   dd->ipath_piobufbase);
1502         pioincr = dd->ipath_palign / sizeof(*piobuf);
1503         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1504                 /*
1505                  * reasonable word count, just to init pbc
1506                  */
1507                 writel(16, piobuf);
1508                 piobuf += pioincr;
1509         }
1510         /*
1511          * self-clearing
1512          */
1513         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1514                          INFINIPATH_S_ABORT);
1515
1516         ipath_get_eeprom_info(dd);
1517         if(dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1518                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1519                 /*
1520                  * Later production QHT7040 has same changes as QHT7140, so
1521                  * can use GPIO interrupts.  They have serial #'s starting
1522                  * with 128, rather than 112.
1523                  */
1524                 dd->ipath_flags |= IPATH_GPIO_INTR;
1525                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1526         }
1527         return 0;
1528 }
1529
1530 /**
1531  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1532  * @dd: the infinipath device
1533  * @kbase: ipath_base_info pointer
1534  *
1535  * We set the PCIE flag because the lower bandwidth on PCIe vs
1536  * HyperTransport can affect some user packet algorithims.
1537  */
1538 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1539 {
1540         struct ipath_base_info *kinfo = kbase;
1541
1542         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1543                 IPATH_RUNTIME_RCVHDR_COPY;
1544
1545         return 0;
1546 }
1547
1548 /**
1549  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1550  * @dd: the infinipath device
1551  *
1552  * This is global, and is called directly at init to set up the
1553  * chip-specific function pointers for later use.
1554  */
1555 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1556 {
1557         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1558         dd->ipath_f_bus = ipath_setup_ht_config;
1559         dd->ipath_f_reset = ipath_setup_ht_reset;
1560         dd->ipath_f_get_boardname = ipath_ht_boardname;
1561         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1562         dd->ipath_f_early_init = ipath_ht_early_init;
1563         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1564         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1565         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1566         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1567         dd->ipath_f_put_tid = ipath_ht_put_tid;
1568         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1569         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1570         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1571
1572         /*
1573          * initialize chip-specific variables
1574          */
1575         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1576
1577         /*
1578          * setup the register offsets, since they are different for each
1579          * chip
1580          */
1581         dd->ipath_kregs = &ipath_ht_kregs;
1582         dd->ipath_cregs = &ipath_ht_cregs;
1583
1584         /*
1585          * do very early init that is needed before ipath_f_bus is
1586          * called
1587          */
1588         ipath_init_ht_variables(dd);
1589 }