2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
44 #include <asm/stacktrace.h>
46 extern asmlinkage void handle_int(void);
47 extern asmlinkage void handle_tlbm(void);
48 extern asmlinkage void handle_tlbl(void);
49 extern asmlinkage void handle_tlbs(void);
50 extern asmlinkage void handle_adel(void);
51 extern asmlinkage void handle_ades(void);
52 extern asmlinkage void handle_ibe(void);
53 extern asmlinkage void handle_dbe(void);
54 extern asmlinkage void handle_sys(void);
55 extern asmlinkage void handle_bp(void);
56 extern asmlinkage void handle_ri(void);
57 extern asmlinkage void handle_cpu(void);
58 extern asmlinkage void handle_ov(void);
59 extern asmlinkage void handle_tr(void);
60 extern asmlinkage void handle_fpe(void);
61 extern asmlinkage void handle_mdmx(void);
62 extern asmlinkage void handle_watch(void);
63 extern asmlinkage void handle_mt(void);
64 extern asmlinkage void handle_dsp(void);
65 extern asmlinkage void handle_mcheck(void);
66 extern asmlinkage void handle_reserved(void);
68 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
69 struct mips_fpu_struct *ctx, int has_fpu);
71 void (*board_be_init)(void);
72 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
73 void (*board_nmi_handler_setup)(void);
74 void (*board_ejtag_handler_setup)(void);
75 void (*board_bind_eic_interrupt)(int irq, int regset);
78 static void show_raw_backtrace(unsigned long reg29)
80 unsigned long *sp = (unsigned long *)reg29;
83 printk("Call Trace:");
84 #ifdef CONFIG_KALLSYMS
87 while (!kstack_end(sp)) {
89 if (__kernel_text_address(addr))
95 #ifdef CONFIG_KALLSYMS
97 static int __init set_raw_show_trace(char *str)
102 __setup("raw_show_trace", set_raw_show_trace);
105 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
107 unsigned long sp = regs->regs[29];
108 unsigned long ra = regs->regs[31];
109 unsigned long pc = regs->cp0_epc;
111 if (raw_show_trace || !__kernel_text_address(pc)) {
112 show_raw_backtrace(sp);
115 printk("Call Trace:\n");
118 pc = unwind_stack(task, &sp, pc, &ra);
124 * This routine abuses get_user()/put_user() to reference pointers
125 * with at least a bit of error checking ...
127 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
129 const int field = 2 * sizeof(unsigned long);
132 unsigned long *sp = (unsigned long *)regs->regs[29];
136 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
137 if (i && ((i % (64 / field)) == 0))
144 if (__get_user(stackdata, sp++)) {
145 printk(" (Bad stack address)");
149 printk(" %0*lx", field, stackdata);
153 show_backtrace(task, regs);
156 void show_stack(struct task_struct *task, unsigned long *sp)
160 regs.regs[29] = (unsigned long)sp;
164 if (task && task != current) {
165 regs.regs[29] = task->thread.reg29;
167 regs.cp0_epc = task->thread.reg31;
169 prepare_frametrace(®s);
172 show_stacktrace(task, ®s);
176 * The architecture-independent dump_stack generator
178 void dump_stack(void)
182 prepare_frametrace(®s);
183 show_backtrace(current, ®s);
186 EXPORT_SYMBOL(dump_stack);
188 void show_code(unsigned int *pc)
194 for(i = -3 ; i < 6 ; i++) {
196 if (__get_user(insn, pc + i)) {
197 printk(" (Bad address in epc)\n");
200 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
204 void show_regs(struct pt_regs *regs)
206 const int field = 2 * sizeof(unsigned long);
207 unsigned int cause = regs->cp0_cause;
210 printk("Cpu %d\n", smp_processor_id());
213 * Saved main processor registers
215 for (i = 0; i < 32; ) {
219 printk(" %0*lx", field, 0UL);
220 else if (i == 26 || i == 27)
221 printk(" %*s", field, "");
223 printk(" %0*lx", field, regs->regs[i]);
230 printk("Hi : %0*lx\n", field, regs->hi);
231 printk("Lo : %0*lx\n", field, regs->lo);
234 * Saved cp0 registers
236 printk("epc : %0*lx ", field, regs->cp0_epc);
237 print_symbol("%s ", regs->cp0_epc);
238 printk(" %s\n", print_tainted());
239 printk("ra : %0*lx ", field, regs->regs[31]);
240 print_symbol("%s\n", regs->regs[31]);
242 printk("Status: %08x ", (uint32_t) regs->cp0_status);
244 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
245 if (regs->cp0_status & ST0_KUO)
247 if (regs->cp0_status & ST0_IEO)
249 if (regs->cp0_status & ST0_KUP)
251 if (regs->cp0_status & ST0_IEP)
253 if (regs->cp0_status & ST0_KUC)
255 if (regs->cp0_status & ST0_IEC)
258 if (regs->cp0_status & ST0_KX)
260 if (regs->cp0_status & ST0_SX)
262 if (regs->cp0_status & ST0_UX)
264 switch (regs->cp0_status & ST0_KSU) {
269 printk("SUPERVISOR ");
278 if (regs->cp0_status & ST0_ERL)
280 if (regs->cp0_status & ST0_EXL)
282 if (regs->cp0_status & ST0_IE)
287 printk("Cause : %08x\n", cause);
289 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
290 if (1 <= cause && cause <= 5)
291 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
293 printk("PrId : %08x\n", read_c0_prid());
296 void show_registers(struct pt_regs *regs)
300 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
301 current->comm, current->pid, current_thread_info(), current);
302 show_stacktrace(current, regs);
303 show_code((unsigned int *) regs->cp0_epc);
307 static DEFINE_SPINLOCK(die_lock);
309 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
311 static int die_counter;
312 #ifdef CONFIG_MIPS_MT_SMTC
313 unsigned long dvpret = dvpe();
314 #endif /* CONFIG_MIPS_MT_SMTC */
317 spin_lock_irq(&die_lock);
319 #ifdef CONFIG_MIPS_MT_SMTC
320 mips_mt_regdump(dvpret);
321 #endif /* CONFIG_MIPS_MT_SMTC */
322 printk("%s[#%d]:\n", str, ++die_counter);
323 show_registers(regs);
324 spin_unlock_irq(&die_lock);
327 panic("Fatal exception in interrupt");
330 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
332 panic("Fatal exception");
338 extern const struct exception_table_entry __start___dbe_table[];
339 extern const struct exception_table_entry __stop___dbe_table[];
341 void __declare_dbe_table(void)
343 __asm__ __volatile__(
344 ".section\t__dbe_table,\"a\"\n\t"
349 /* Given an address, look for it in the exception tables. */
350 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
352 const struct exception_table_entry *e;
354 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
356 e = search_module_dbetables(addr);
360 asmlinkage void do_be(struct pt_regs *regs)
362 const int field = 2 * sizeof(unsigned long);
363 const struct exception_table_entry *fixup = NULL;
364 int data = regs->cp0_cause & 4;
365 int action = MIPS_BE_FATAL;
367 /* XXX For now. Fixme, this searches the wrong table ... */
368 if (data && !user_mode(regs))
369 fixup = search_dbe_tables(exception_epc(regs));
372 action = MIPS_BE_FIXUP;
374 if (board_be_handler)
375 action = board_be_handler(regs, fixup != 0);
378 case MIPS_BE_DISCARD:
382 regs->cp0_epc = fixup->nextinsn;
391 * Assume it would be too dangerous to continue ...
393 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
394 data ? "Data" : "Instruction",
395 field, regs->cp0_epc, field, regs->regs[31]);
396 die_if_kernel("Oops", regs);
397 force_sig(SIGBUS, current);
400 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
402 unsigned int __user *epc;
404 epc = (unsigned int __user *) regs->cp0_epc +
405 ((regs->cp0_cause & CAUSEF_BD) != 0);
406 if (!get_user(*opcode, epc))
409 force_sig(SIGSEGV, current);
417 #define OPCODE 0xfc000000
418 #define BASE 0x03e00000
419 #define RT 0x001f0000
420 #define OFFSET 0x0000ffff
421 #define LL 0xc0000000
422 #define SC 0xe0000000
423 #define SPEC3 0x7c000000
424 #define RD 0x0000f800
425 #define FUNC 0x0000003f
426 #define RDHWR 0x0000003b
429 * The ll_bit is cleared by r*_switch.S
432 unsigned long ll_bit;
434 static struct task_struct *ll_task = NULL;
436 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
438 unsigned long value, __user *vaddr;
443 * analyse the ll instruction that just caused a ri exception
444 * and put the referenced address to addr.
447 /* sign extend offset */
448 offset = opcode & OFFSET;
452 vaddr = (unsigned long __user *)
453 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
455 if ((unsigned long)vaddr & 3) {
459 if (get_user(value, vaddr)) {
466 if (ll_task == NULL || ll_task == current) {
475 compute_return_epc(regs);
477 regs->regs[(opcode & RT) >> 16] = value;
482 force_sig(signal, current);
485 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
487 unsigned long __user *vaddr;
493 * analyse the sc instruction that just caused a ri exception
494 * and put the referenced address to addr.
497 /* sign extend offset */
498 offset = opcode & OFFSET;
502 vaddr = (unsigned long __user *)
503 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
504 reg = (opcode & RT) >> 16;
506 if ((unsigned long)vaddr & 3) {
513 if (ll_bit == 0 || ll_task != current) {
514 compute_return_epc(regs);
522 if (put_user(regs->regs[reg], vaddr)) {
527 compute_return_epc(regs);
533 force_sig(signal, current);
537 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
538 * opcodes are supposed to result in coprocessor unusable exceptions if
539 * executed on ll/sc-less processors. That's the theory. In practice a
540 * few processors such as NEC's VR4100 throw reserved instruction exceptions
541 * instead, so we're doing the emulation thing in both exception handlers.
543 static inline int simulate_llsc(struct pt_regs *regs)
547 if (unlikely(get_insn_opcode(regs, &opcode)))
550 if ((opcode & OPCODE) == LL) {
551 simulate_ll(regs, opcode);
554 if ((opcode & OPCODE) == SC) {
555 simulate_sc(regs, opcode);
559 return -EFAULT; /* Strange things going on ... */
563 * Simulate trapping 'rdhwr' instructions to provide user accessible
564 * registers not implemented in hardware. The only current use of this
565 * is the thread area pointer.
567 static inline int simulate_rdhwr(struct pt_regs *regs)
569 struct thread_info *ti = task_thread_info(current);
572 if (unlikely(get_insn_opcode(regs, &opcode)))
575 if (unlikely(compute_return_epc(regs)))
578 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
579 int rd = (opcode & RD) >> 11;
580 int rt = (opcode & RT) >> 16;
583 regs->regs[rt] = ti->tp_value;
594 asmlinkage void do_ov(struct pt_regs *regs)
598 die_if_kernel("Integer overflow", regs);
600 info.si_code = FPE_INTOVF;
601 info.si_signo = SIGFPE;
603 info.si_addr = (void __user *) regs->cp0_epc;
604 force_sig_info(SIGFPE, &info, current);
608 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
610 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
612 die_if_kernel("FP exception in kernel code", regs);
614 if (fcr31 & FPU_CSR_UNI_X) {
619 #ifdef CONFIG_PREEMPT
620 if (!is_fpu_owner()) {
621 /* We might lose fpu before disabling preempt... */
623 BUG_ON(!used_math());
628 * Unimplemented operation exception. If we've got the full
629 * software emulator on-board, let's use it...
631 * Force FPU to dump state into task/thread context. We're
632 * moving a lot of data here for what is probably a single
633 * instruction, but the alternative is to pre-decode the FP
634 * register operands before invoking the emulator, which seems
635 * a bit extreme for what should be an infrequent event.
638 /* Ensure 'resume' not overwrite saved fp context again. */
643 /* Run the emulator */
644 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1);
648 own_fpu(); /* Using the FPU again. */
650 * We can't allow the emulated instruction to leave any of
651 * the cause bit set in $fcr31.
653 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
655 /* Restore the hardware register state */
660 /* If something went wrong, signal */
662 force_sig(sig, current);
667 force_sig(SIGFPE, current);
670 asmlinkage void do_bp(struct pt_regs *regs)
672 unsigned int opcode, bcode;
675 die_if_kernel("Break instruction in kernel code", regs);
677 if (get_insn_opcode(regs, &opcode))
681 * There is the ancient bug in the MIPS assemblers that the break
682 * code starts left to bit 16 instead to bit 6 in the opcode.
683 * Gas is bug-compatible, but not always, grrr...
684 * We handle both cases with a simple heuristics. --macro
686 bcode = ((opcode >> 6) & ((1 << 20) - 1));
687 if (bcode < (1 << 10))
691 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
692 * insns, even for break codes that indicate arithmetic failures.
694 * But should we continue the brokenness??? --macro
697 case BRK_OVERFLOW << 10:
698 case BRK_DIVZERO << 10:
699 if (bcode == (BRK_DIVZERO << 10))
700 info.si_code = FPE_INTDIV;
702 info.si_code = FPE_INTOVF;
703 info.si_signo = SIGFPE;
705 info.si_addr = (void __user *) regs->cp0_epc;
706 force_sig_info(SIGFPE, &info, current);
709 force_sig(SIGTRAP, current);
713 asmlinkage void do_tr(struct pt_regs *regs)
715 unsigned int opcode, tcode = 0;
718 die_if_kernel("Trap instruction in kernel code", regs);
720 if (get_insn_opcode(regs, &opcode))
723 /* Immediate versions don't provide a code. */
724 if (!(opcode & OPCODE))
725 tcode = ((opcode >> 6) & ((1 << 10) - 1));
728 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
729 * insns, even for trap codes that indicate arithmetic failures.
731 * But should we continue the brokenness??? --macro
736 if (tcode == BRK_DIVZERO)
737 info.si_code = FPE_INTDIV;
739 info.si_code = FPE_INTOVF;
740 info.si_signo = SIGFPE;
742 info.si_addr = (void __user *) regs->cp0_epc;
743 force_sig_info(SIGFPE, &info, current);
746 force_sig(SIGTRAP, current);
750 asmlinkage void do_ri(struct pt_regs *regs)
752 die_if_kernel("Reserved instruction in kernel code", regs);
755 if (!simulate_llsc(regs))
758 if (!simulate_rdhwr(regs))
761 force_sig(SIGILL, current);
764 asmlinkage void do_cpu(struct pt_regs *regs)
768 die_if_kernel("do_cpu invoked from kernel context!", regs);
770 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
775 if (!simulate_llsc(regs))
778 if (!simulate_rdhwr(regs))
787 if (used_math()) { /* Using the FPU again. */
789 } else { /* First time FPU user. */
799 sig = fpu_emulator_cop1Handler(regs,
800 ¤t->thread.fpu, 0);
802 force_sig(sig, current);
803 #ifdef CONFIG_MIPS_MT_FPAFF
806 * MIPS MT processors may have fewer FPU contexts
807 * than CPU threads. If we've emulated more than
808 * some threshold number of instructions, force
809 * migration to a "CPU" that has FP support.
811 if(mt_fpemul_threshold > 0
812 && ((current->thread.emulated_fp++
813 > mt_fpemul_threshold))) {
815 * If there's no FPU present, or if the
816 * application has already restricted
817 * the allowed set to exclude any CPUs
818 * with FPUs, we'll skip the procedure.
820 if (cpus_intersects(current->cpus_allowed,
825 current->thread.user_cpus_allowed,
827 set_cpus_allowed(current, tmask);
828 current->thread.mflags |= MF_FPUBOUND;
832 #endif /* CONFIG_MIPS_MT_FPAFF */
839 die_if_kernel("do_cpu invoked from kernel context!", regs);
843 force_sig(SIGILL, current);
846 asmlinkage void do_mdmx(struct pt_regs *regs)
848 force_sig(SIGILL, current);
851 asmlinkage void do_watch(struct pt_regs *regs)
854 * We use the watch exception where available to detect stack
859 panic("Caught WATCH exception - probably caused by stack overflow.");
862 asmlinkage void do_mcheck(struct pt_regs *regs)
864 const int field = 2 * sizeof(unsigned long);
865 int multi_match = regs->cp0_status & ST0_TS;
870 printk("Index : %0x\n", read_c0_index());
871 printk("Pagemask: %0x\n", read_c0_pagemask());
872 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
873 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
874 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
879 show_code((unsigned int *) regs->cp0_epc);
882 * Some chips may have other causes of machine check (e.g. SB1
885 panic("Caught Machine Check exception - %scaused by multiple "
886 "matching entries in the TLB.",
887 (multi_match) ? "" : "not ");
890 asmlinkage void do_mt(struct pt_regs *regs)
894 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
895 >> VPECONTROL_EXCPT_SHIFT;
898 printk(KERN_DEBUG "Thread Underflow\n");
901 printk(KERN_DEBUG "Thread Overflow\n");
904 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
907 printk(KERN_DEBUG "Gating Storage Exception\n");
910 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
913 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
916 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
920 die_if_kernel("MIPS MT Thread exception in kernel", regs);
922 force_sig(SIGILL, current);
926 asmlinkage void do_dsp(struct pt_regs *regs)
929 panic("Unexpected DSP exception\n");
931 force_sig(SIGILL, current);
934 asmlinkage void do_reserved(struct pt_regs *regs)
937 * Game over - no way to handle this if it ever occurs. Most probably
938 * caused by a new unknown cpu type or after another deadly
939 * hard/software error.
942 panic("Caught reserved exception %ld - should not happen.",
943 (regs->cp0_cause & 0x7f) >> 2);
946 asmlinkage void do_default_vi(struct pt_regs *regs)
949 panic("Caught unexpected vectored interrupt.");
953 * Some MIPS CPUs can enable/disable for cache parity detection, but do
956 static inline void parity_protection_init(void)
958 switch (current_cpu_data.cputype) {
962 write_c0_ecc(0x80000000);
963 back_to_back_c0_hazard();
964 /* Set the PE bit (bit 31) in the c0_errctl register. */
965 printk(KERN_INFO "Cache parity protection %sabled\n",
966 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
970 /* Clear the DE bit (bit 16) in the c0_status register. */
971 printk(KERN_INFO "Enable cache parity protection for "
972 "MIPS 20KC/25KF CPUs.\n");
973 clear_c0_status(ST0_DE);
980 asmlinkage void cache_parity_error(void)
982 const int field = 2 * sizeof(unsigned long);
983 unsigned int reg_val;
985 /* For the moment, report the problem and hang. */
986 printk("Cache error exception:\n");
987 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
988 reg_val = read_c0_cacheerr();
989 printk("c0_cacheerr == %08x\n", reg_val);
991 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
992 reg_val & (1<<30) ? "secondary" : "primary",
993 reg_val & (1<<31) ? "data" : "insn");
994 printk("Error bits: %s%s%s%s%s%s%s\n",
995 reg_val & (1<<29) ? "ED " : "",
996 reg_val & (1<<28) ? "ET " : "",
997 reg_val & (1<<26) ? "EE " : "",
998 reg_val & (1<<25) ? "EB " : "",
999 reg_val & (1<<24) ? "EI " : "",
1000 reg_val & (1<<23) ? "E1 " : "",
1001 reg_val & (1<<22) ? "E0 " : "");
1002 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1004 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1005 if (reg_val & (1<<22))
1006 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1008 if (reg_val & (1<<23))
1009 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1012 panic("Can't handle the cache error!");
1016 * SDBBP EJTAG debug exception handler.
1017 * We skip the instruction and return to the next instruction.
1019 void ejtag_exception_handler(struct pt_regs *regs)
1021 const int field = 2 * sizeof(unsigned long);
1022 unsigned long depc, old_epc;
1025 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1026 depc = read_c0_depc();
1027 debug = read_c0_debug();
1028 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1029 if (debug & 0x80000000) {
1031 * In branch delay slot.
1032 * We cheat a little bit here and use EPC to calculate the
1033 * debug return address (DEPC). EPC is restored after the
1036 old_epc = regs->cp0_epc;
1037 regs->cp0_epc = depc;
1038 __compute_return_epc(regs);
1039 depc = regs->cp0_epc;
1040 regs->cp0_epc = old_epc;
1043 write_c0_depc(depc);
1046 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1047 write_c0_debug(debug | 0x100);
1052 * NMI exception handler.
1054 void nmi_exception_handler(struct pt_regs *regs)
1056 #ifdef CONFIG_MIPS_MT_SMTC
1057 unsigned long dvpret = dvpe();
1059 printk("NMI taken!!!!\n");
1060 mips_mt_regdump(dvpret);
1063 printk("NMI taken!!!!\n");
1064 #endif /* CONFIG_MIPS_MT_SMTC */
1069 #define VECTORSPACING 0x100 /* for EI/VI mode */
1071 unsigned long ebase;
1072 unsigned long exception_handlers[32];
1073 unsigned long vi_handlers[64];
1076 * As a side effect of the way this is implemented we're limited
1077 * to interrupt handlers in the address range from
1078 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1080 void *set_except_vector(int n, void *addr)
1082 unsigned long handler = (unsigned long) addr;
1083 unsigned long old_handler = exception_handlers[n];
1085 exception_handlers[n] = handler;
1086 if (n == 0 && cpu_has_divec) {
1087 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1088 (0x03ffffff & (handler >> 2));
1089 flush_icache_range(ebase + 0x200, ebase + 0x204);
1091 return (void *)old_handler;
1094 #ifdef CONFIG_CPU_MIPSR2_SRS
1096 * MIPSR2 shadow register set allocation
1100 static struct shadow_registers {
1102 * Number of shadow register sets supported
1104 unsigned long sr_supported;
1106 * Bitmap of allocated shadow registers
1108 unsigned long sr_allocated;
1111 static void mips_srs_init(void)
1113 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1114 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1115 shadow_registers.sr_supported);
1116 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1119 int mips_srs_max(void)
1121 return shadow_registers.sr_supported;
1124 int mips_srs_alloc(void)
1126 struct shadow_registers *sr = &shadow_registers;
1130 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1131 if (set >= sr->sr_supported)
1134 if (test_and_set_bit(set, &sr->sr_allocated))
1140 void mips_srs_free(int set)
1142 struct shadow_registers *sr = &shadow_registers;
1144 clear_bit(set, &sr->sr_allocated);
1147 static void *set_vi_srs_handler(int n, void *addr, int srs)
1149 unsigned long handler;
1150 unsigned long old_handler = vi_handlers[n];
1154 if (!cpu_has_veic && !cpu_has_vint)
1158 handler = (unsigned long) do_default_vi;
1161 handler = (unsigned long) addr;
1162 vi_handlers[n] = (unsigned long) addr;
1164 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1166 if (srs >= mips_srs_max())
1167 panic("Shadow register set %d not supported", srs);
1170 if (board_bind_eic_interrupt)
1171 board_bind_eic_interrupt (n, srs);
1172 } else if (cpu_has_vint) {
1173 /* SRSMap is only defined if shadow sets are implemented */
1174 if (mips_srs_max() > 1)
1175 change_c0_srsmap (0xf << n*4, srs << n*4);
1180 * If no shadow set is selected then use the default handler
1181 * that does normal register saving and a standard interrupt exit
1184 extern char except_vec_vi, except_vec_vi_lui;
1185 extern char except_vec_vi_ori, except_vec_vi_end;
1186 #ifdef CONFIG_MIPS_MT_SMTC
1188 * We need to provide the SMTC vectored interrupt handler
1189 * not only with the address of the handler, but with the
1190 * Status.IM bit to be masked before going there.
1192 extern char except_vec_vi_mori;
1193 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1194 #endif /* CONFIG_MIPS_MT_SMTC */
1195 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1196 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1197 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1199 if (handler_len > VECTORSPACING) {
1201 * Sigh... panicing won't help as the console
1202 * is probably not configured :(
1204 panic ("VECTORSPACING too small");
1207 memcpy (b, &except_vec_vi, handler_len);
1208 #ifdef CONFIG_MIPS_MT_SMTC
1210 printk("Vector index %d exceeds SMTC maximum\n", n);
1211 w = (u32 *)(b + mori_offset);
1212 *w = (*w & 0xffff0000) | (0x100 << n);
1213 #endif /* CONFIG_MIPS_MT_SMTC */
1214 w = (u32 *)(b + lui_offset);
1215 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1216 w = (u32 *)(b + ori_offset);
1217 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1218 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1222 * In other cases jump directly to the interrupt handler
1224 * It is the handlers responsibility to save registers if required
1225 * (eg hi/lo) and return from the exception using "eret"
1228 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1230 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1233 return (void *)old_handler;
1236 void *set_vi_handler(int n, void *addr)
1238 return set_vi_srs_handler(n, addr, 0);
1243 static inline void mips_srs_init(void)
1247 #endif /* CONFIG_CPU_MIPSR2_SRS */
1250 * This is used by native signal handling
1252 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1253 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1255 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1256 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1258 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1259 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1262 static int smp_save_fp_context(struct sigcontext *sc)
1265 ? _save_fp_context(sc)
1266 : fpu_emulator_save_context(sc);
1269 static int smp_restore_fp_context(struct sigcontext *sc)
1272 ? _restore_fp_context(sc)
1273 : fpu_emulator_restore_context(sc);
1277 static inline void signal_init(void)
1280 /* For now just do the cpu_has_fpu check when the functions are invoked */
1281 save_fp_context = smp_save_fp_context;
1282 restore_fp_context = smp_restore_fp_context;
1285 save_fp_context = _save_fp_context;
1286 restore_fp_context = _restore_fp_context;
1288 save_fp_context = fpu_emulator_save_context;
1289 restore_fp_context = fpu_emulator_restore_context;
1294 #ifdef CONFIG_MIPS32_COMPAT
1297 * This is used by 32-bit signal stuff on the 64-bit kernel
1299 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1300 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1302 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1303 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1305 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1306 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1308 static inline void signal32_init(void)
1311 save_fp_context32 = _save_fp_context32;
1312 restore_fp_context32 = _restore_fp_context32;
1314 save_fp_context32 = fpu_emulator_save_context32;
1315 restore_fp_context32 = fpu_emulator_restore_context32;
1320 extern void cpu_cache_init(void);
1321 extern void tlb_init(void);
1322 extern void flush_tlb_handlers(void);
1324 void __init per_cpu_trap_init(void)
1326 unsigned int cpu = smp_processor_id();
1327 unsigned int status_set = ST0_CU0;
1328 #ifdef CONFIG_MIPS_MT_SMTC
1329 int secondaryTC = 0;
1330 int bootTC = (cpu == 0);
1333 * Only do per_cpu_trap_init() for first TC of Each VPE.
1334 * Note that this hack assumes that the SMTC init code
1335 * assigns TCs consecutively and in ascending order.
1338 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1339 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1341 #endif /* CONFIG_MIPS_MT_SMTC */
1344 * Disable coprocessors and select 32-bit or 64-bit addressing
1345 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1346 * flag that some firmware may have left set and the TS bit (for
1347 * IP27). Set XX for ISA IV code to work.
1350 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1352 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1353 status_set |= ST0_XX;
1354 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1358 set_c0_status(ST0_MX);
1360 #ifdef CONFIG_CPU_MIPSR2
1361 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1364 #ifdef CONFIG_MIPS_MT_SMTC
1366 #endif /* CONFIG_MIPS_MT_SMTC */
1369 * Interrupt handling.
1371 if (cpu_has_veic || cpu_has_vint) {
1372 write_c0_ebase (ebase);
1373 /* Setting vector spacing enables EI/VI mode */
1374 change_c0_intctl (0x3e0, VECTORSPACING);
1376 if (cpu_has_divec) {
1377 if (cpu_has_mipsmt) {
1378 unsigned int vpflags = dvpe();
1379 set_c0_cause(CAUSEF_IV);
1382 set_c0_cause(CAUSEF_IV);
1384 #ifdef CONFIG_MIPS_MT_SMTC
1386 #endif /* CONFIG_MIPS_MT_SMTC */
1388 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1389 TLBMISS_HANDLER_SETUP();
1391 atomic_inc(&init_mm.mm_count);
1392 current->active_mm = &init_mm;
1393 BUG_ON(current->mm);
1394 enter_lazy_tlb(&init_mm, current);
1396 #ifdef CONFIG_MIPS_MT_SMTC
1398 #endif /* CONFIG_MIPS_MT_SMTC */
1401 #ifdef CONFIG_MIPS_MT_SMTC
1403 #endif /* CONFIG_MIPS_MT_SMTC */
1406 /* Install CPU exception handler */
1407 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1409 memcpy((void *)(ebase + offset), addr, size);
1410 flush_icache_range(ebase + offset, ebase + offset + size);
1413 /* Install uncached CPU exception handler */
1414 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1417 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1420 unsigned long uncached_ebase = TO_UNCAC(ebase);
1423 memcpy((void *)(uncached_ebase + offset), addr, size);
1426 void __init trap_init(void)
1428 extern char except_vec3_generic, except_vec3_r4000;
1429 extern char except_vec4;
1432 if (cpu_has_veic || cpu_has_vint)
1433 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1439 per_cpu_trap_init();
1442 * Copy the generic exception handlers to their final destination.
1443 * This will be overriden later as suitable for a particular
1446 set_handler(0x180, &except_vec3_generic, 0x80);
1449 * Setup default vectors
1451 for (i = 0; i <= 31; i++)
1452 set_except_vector(i, handle_reserved);
1455 * Copy the EJTAG debug exception vector handler code to it's final
1458 if (cpu_has_ejtag && board_ejtag_handler_setup)
1459 board_ejtag_handler_setup ();
1462 * Only some CPUs have the watch exceptions.
1465 set_except_vector(23, handle_watch);
1468 * Initialise interrupt handlers
1470 if (cpu_has_veic || cpu_has_vint) {
1471 int nvec = cpu_has_veic ? 64 : 8;
1472 for (i = 0; i < nvec; i++)
1473 set_vi_handler(i, NULL);
1475 else if (cpu_has_divec)
1476 set_handler(0x200, &except_vec4, 0x8);
1479 * Some CPUs can enable/disable for cache parity detection, but does
1480 * it different ways.
1482 parity_protection_init();
1485 * The Data Bus Errors / Instruction Bus Errors are signaled
1486 * by external hardware. Therefore these two exceptions
1487 * may have board specific handlers.
1492 set_except_vector(0, handle_int);
1493 set_except_vector(1, handle_tlbm);
1494 set_except_vector(2, handle_tlbl);
1495 set_except_vector(3, handle_tlbs);
1497 set_except_vector(4, handle_adel);
1498 set_except_vector(5, handle_ades);
1500 set_except_vector(6, handle_ibe);
1501 set_except_vector(7, handle_dbe);
1503 set_except_vector(8, handle_sys);
1504 set_except_vector(9, handle_bp);
1505 set_except_vector(10, handle_ri);
1506 set_except_vector(11, handle_cpu);
1507 set_except_vector(12, handle_ov);
1508 set_except_vector(13, handle_tr);
1510 if (current_cpu_data.cputype == CPU_R6000 ||
1511 current_cpu_data.cputype == CPU_R6000A) {
1513 * The R6000 is the only R-series CPU that features a machine
1514 * check exception (similar to the R4000 cache error) and
1515 * unaligned ldc1/sdc1 exception. The handlers have not been
1516 * written yet. Well, anyway there is no R6000 machine on the
1517 * current list of targets for Linux/MIPS.
1518 * (Duh, crap, there is someone with a triple R6k machine)
1520 //set_except_vector(14, handle_mc);
1521 //set_except_vector(15, handle_ndc);
1525 if (board_nmi_handler_setup)
1526 board_nmi_handler_setup();
1528 if (cpu_has_fpu && !cpu_has_nofpuex)
1529 set_except_vector(15, handle_fpe);
1531 set_except_vector(22, handle_mdmx);
1534 set_except_vector(24, handle_mcheck);
1537 set_except_vector(25, handle_mt);
1540 set_except_vector(26, handle_dsp);
1543 /* Special exception: R4[04]00 uses also the divec space. */
1544 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1545 else if (cpu_has_4kex)
1546 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1548 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1551 #ifdef CONFIG_MIPS32_COMPAT
1555 flush_icache_range(ebase, ebase + 0x400);
1556 flush_tlb_handlers();