2 * Interrupt handling for INTC2-based IRQ.
4 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
5 * Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
10 * These are the "new Hitachi style" interrupts, as present on the
11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
16 #include <asm/system.h>
19 static void disable_intc2_irq(unsigned int irq)
21 struct intc2_data *p = get_irq_chip_data(irq);
22 ctrl_outl(1 << p->msk_shift,
23 INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);
26 static void enable_intc2_irq(unsigned int irq)
28 struct intc2_data *p = get_irq_chip_data(irq);
29 ctrl_outl(1 << p->msk_shift,
30 INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);
33 static struct irq_chip intc2_irq_chip = {
35 .mask = disable_intc2_irq,
36 .unmask = enable_intc2_irq,
37 .mask_ack = disable_intc2_irq,
41 * Setup an INTC2 style interrupt.
42 * NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
43 * allowing the use of the numbers straight out of the datasheet.
45 * PIO1 which is INTPRI00[19,16] and INTMSK00[13]
48 * make_intc2_irq(84, 0, 16, 0, 13);
50 void make_intc2_irq(struct intc2_data *p)
55 disable_irq_nosync(p->irq);
57 /* Set the priority level */
58 local_irq_save(flags);
60 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
61 ipr &= ~(0xf << p->ipr_shift);
62 ipr |= p->priority << p->ipr_shift;
63 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
65 local_irq_restore(flags);
67 set_irq_chip_and_handler(p->irq, &intc2_irq_chip, handle_level_irq);
68 set_irq_chip_data(p->irq, p);
70 enable_intc2_irq(p->irq);
73 static struct intc2_data intc2_irq_table[] = {
74 #if defined(CONFIG_CPU_SUBTYPE_ST40)
75 {64, 0, 0, 0, 0, 13}, /* PCI serr */
76 {65, 0, 4, 0, 1, 13}, /* PCI err */
77 {66, 0, 4, 0, 2, 13}, /* PCI ad */
78 {67, 0, 4, 0, 3, 13}, /* PCI pwd down */
79 {72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
80 {73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
81 {74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
82 {75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
83 {76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
84 {78, 0, 8, 0, 11, 13}, /* DMAC ERR */
85 {80, 0, 12, 0, 12, 13}, /* PIO0 */
86 {84, 0, 16, 0, 13, 13}, /* PIO1 */
87 {88, 0, 20, 0, 14, 13}, /* PIO2 */
88 {112, 4, 0, 4, 0, 13}, /* Mailbox */
89 #ifdef CONFIG_CPU_SUBTYPE_ST40GX1
90 {116, 4, 4, 4, 4, 13}, /* SSC0 */
91 {120, 4, 8, 4, 8, 13}, /* IR Blaster */
92 {124, 4, 12, 4, 12, 13}, /* USB host */
93 {128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
94 {132, 4, 20, 4, 20, 13}, /* UART0 */
95 {134, 4, 20, 4, 22, 13}, /* UART2 */
96 {136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
97 {140, 4, 28, 4, 28, 13}, /* EMPI */
98 {144, 8, 0, 8, 0, 13}, /* MAFE */
99 {148, 8, 4, 8, 4, 13}, /* PWM */
100 {152, 8, 8, 8, 8, 13}, /* SSC1 */
101 {156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
102 {160, 8, 16, 8, 16, 13}, /* USB target */
103 {164, 8, 20, 8, 20, 13}, /* UART1 */
104 {168, 8, 24, 8, 24, 13}, /* Teletext */
105 {172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
106 {173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
107 {174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
109 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
111 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
113 /* INTPRIO0 | INTMSK0 */
114 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
115 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
116 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
117 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
118 /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
119 /* INTPRIO4 | INTMSK0 */
120 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
121 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
122 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
123 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
124 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
125 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
126 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
127 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
128 /* INTPRIO8 | INTMSK0 */
129 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
130 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
131 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
132 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
133 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
134 {65, 8, 24, 0, 16, 3}, /* LCDC */
136 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
137 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
138 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
140 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
141 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
142 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
143 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
144 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
145 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
146 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
147 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
149 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
150 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
151 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
152 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
153 {84, 8, 0, 4, 19, 3}, /* HSPII */
154 /* INTPRIOC | INTMSK4 */
155 /* 85-87 unused/reserved */
156 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
157 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
158 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
159 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
160 {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
161 /* 93-107 reserved/undocumented */
162 {108,12, 4, 4, 1, 3}, /* ADC */
163 {109,12, 0, 4, 0, 3}, /* CMTI */
164 /* 110-111 reserved/unused */
165 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
166 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
167 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
168 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
169 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
170 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
171 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
172 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
173 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
175 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
176 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
177 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
178 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
180 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
181 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
182 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
183 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
184 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
188 void __init init_IRQ_intc2(void)
192 for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++)
193 make_intc2_irq(intc2_irq_table + i);