git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78
  79         /* Call PHY identify routine to get the phy type */
  80         ixgbe_identify_phy_generic(hw);
  81
  82         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
  83         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
  84         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
  85         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
  86         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
  87         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
  88
  89         return 0;
  90 }
  91
  92 /**
  93  *  ixgbe_init_phy_ops_82598 - PHY/SFP specific init
  94  *  @hw: pointer to hardware structure
  95  *
  96  *  Initialize any function pointers that were not able to be
  97  *  set during get_invariants because the PHY/SFP type was
  98  *  not known.  Perform the SFP init if necessary.
  99  *
 100  **/
 101 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
 102 {
 103         struct ixgbe_mac_info *mac = &hw->mac;
 104         struct ixgbe_phy_info *phy = &hw->phy;
 105         s32 ret_val = 0;
 106         u16 list_offset, data_offset;
 107
 108         /* Identify the PHY */
 109         phy->ops.identify(hw);
 110
 111         /* Overwrite the link function pointers if copper PHY */
 112         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 113                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 114                 mac->ops.setup_link_speed =
 115                                      &ixgbe_setup_copper_link_speed_82598;
 116                 mac->ops.get_link_capabilities =
 117                                   &ixgbe_get_copper_link_capabilities_82598;
 118         }
 119
 120         switch (hw->phy.type) {
 121         case ixgbe_phy_tn:
 122                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 123                 phy->ops.get_firmware_version =
 124                              &ixgbe_get_phy_firmware_version_tnx;
 125                 break;
 126         case ixgbe_phy_nl:
 127                 phy->ops.reset = &ixgbe_reset_phy_nl;
 128
 129                 /* Call SFP+ identify routine to get the SFP+ module type */
 130                 ret_val = phy->ops.identify_sfp(hw);
 131                 if (ret_val != 0)
 132                         goto out;
 133                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 134                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 135                         goto out;
 136                 }
 137
 138                 /* Check to see if SFP+ module is supported */
 139                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 140                                                             &list_offset,
 141                                                             &data_offset);
 142                 if (ret_val != 0) {
 143                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 144                         goto out;
 145                 }
 146                 break;
 147         default:
 148                 break;
 149         }
 150
 151 out:
 152         return ret_val;
 153 }
 154
 155 /**
 156  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 157  *  @hw: pointer to hardware structure
 158  *  @speed: pointer to link speed
 159  *  @autoneg: boolean auto-negotiation value
 160  *
 161  *  Determines the link capabilities by reading the AUTOC register.
 162  **/
 163 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 164                                              ixgbe_link_speed *speed,
 165                                              bool *autoneg)
 166 {
 167         s32 status = 0;
 168         u32 autoc = 0;
 169
 170         /*
 171          * Determine link capabilities based on the stored value of AUTOC,
 172          * which represents EEPROM defaults.  If AUTOC value has not been
 173          * stored, use the current register value.
 174          */
 175         if (hw->mac.orig_link_settings_stored)
 176                 autoc = hw->mac.orig_autoc;
 177         else
 178                 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 179
 180         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 181         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 182                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 183                 *autoneg = false;
 184                 break;
 185
 186         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 187                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 188                 *autoneg = false;
 189                 break;
 190
 191         case IXGBE_AUTOC_LMS_1G_AN:
 192                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 193                 *autoneg = true;
 194                 break;
 195
 196         case IXGBE_AUTOC_LMS_KX4_AN:
 197         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 198                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 199                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 200                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 201                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 202                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 203                 *autoneg = true;
 204                 break;
 205
 206         default:
 207                 status = IXGBE_ERR_LINK_SETUP;
 208                 break;
 209         }
 210
 211         return status;
 212 }
 213
 214 /**
 215  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 216  *  @hw: pointer to hardware structure
 217  *  @speed: pointer to link speed
 218  *  @autoneg: boolean auto-negotiation value
 219  *
 220  *  Determines the link capabilities by reading the AUTOC register.
 221  **/
 222 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 223                                                     ixgbe_link_speed *speed,
 224                                                     bool *autoneg)
 225 {
 226         s32 status = IXGBE_ERR_LINK_SETUP;
 227         u16 speed_ability;
 228
 229         *speed = 0;
 230         *autoneg = true;
 231
 232         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 233                                       &speed_ability);
 234
 235         if (status == 0) {
 236                 if (speed_ability & MDIO_SPEED_10G)
 237                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 238                 if (speed_ability & MDIO_PMA_SPEED_1000)
 239                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 240         }
 241
 242         return status;
 243 }
 244
 245 /**
 246  *  ixgbe_get_media_type_82598 - Determines media type
 247  *  @hw: pointer to hardware structure
 248  *
 249  *  Returns the media type (fiber, copper, backplane)
 250  **/
 251 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 252 {
 253         enum ixgbe_media_type media_type;
 254
 255         /* Media type for I82598 is based on device ID */
 256         switch (hw->device_id) {
 257         case IXGBE_DEV_ID_82598:
 258         case IXGBE_DEV_ID_82598_BX:
 259                 media_type = ixgbe_media_type_backplane;
 260                 break;
 261         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 262         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 263         case IXGBE_DEV_ID_82598EB_CX4:
 264         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 265         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 266         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 267         case IXGBE_DEV_ID_82598EB_XF_LR:
 268         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 269                 media_type = ixgbe_media_type_fiber;
 270                 break;
 271         case IXGBE_DEV_ID_82598AT:
 272                 media_type = ixgbe_media_type_copper;
 273                 break;
 274         default:
 275                 media_type = ixgbe_media_type_unknown;
 276                 break;
 277         }
 278
 279         return media_type;
 280 }
 281
 282 /**
 283  *  ixgbe_fc_enable_82598 - Enable flow control
 284  *  @hw: pointer to hardware structure
 285  *  @packetbuf_num: packet buffer number (0-7)
 286  *
 287  *  Enable flow control according to the current settings.
 288  **/
 289 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 290 {
 291         s32 ret_val = 0;
 292         u32 fctrl_reg;
 293         u32 rmcs_reg;
 294         u32 reg;
 295
 296         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 297         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 298
 299         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 300         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 301
 302         /*
 303          * The possible values of fc.current_mode are:
 304          * 0: Flow control is completely disabled
 305          * 1: Rx flow control is enabled (we can receive pause frames,
 306          *    but not send pause frames).
 307          * 2:  Tx flow control is enabled (we can send pause frames but
 308          *     we do not support receiving pause frames).
 309          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 310          * other: Invalid.
 311          */
 312         switch (hw->fc.current_mode) {
 313         case ixgbe_fc_none:
 314                 /* Flow control completely disabled by software override. */
 315                 break;
 316         case ixgbe_fc_rx_pause:
 317                 /*
 318                  * Rx Flow control is enabled and Tx Flow control is
 319                  * disabled by software override. Since there really
 320                  * isn't a way to advertise that we are capable of RX
 321                  * Pause ONLY, we will advertise that we support both
 322                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 323                  * disable the adapter's ability to send PAUSE frames.
 324                  */
 325                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 326                 break;
 327         case ixgbe_fc_tx_pause:
 328                 /*
 329                  * Tx Flow control is enabled, and Rx Flow control is
 330                  * disabled by software override.
 331                  */
 332                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 333                 break;
 334         case ixgbe_fc_full:
 335                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 336                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 337                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 338                 break;
 339         default:
 340                 hw_dbg(hw, "Flow control param set incorrectly\n");
 341                 ret_val = -IXGBE_ERR_CONFIG;
 342                 goto out;
 343                 break;
 344         }
 345
 346         /* Enable 802.3x based flow control settings. */
 347         fctrl_reg |= IXGBE_FCTRL_DPF;
 348         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 349         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 350
 351         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 352         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 353                 if (hw->fc.send_xon) {
 354                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 355                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 356                 } else {
 357                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 358                                         hw->fc.low_water);
 359                 }
 360
 361                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 362                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 363         }
 364
 365         /* Configure pause time (2 TCs per register) */
 366         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
 367         if ((packetbuf_num & 1) == 0)
 368                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 369         else
 370                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 371         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 372
 373         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 374
 375 out:
 376         return ret_val;
 377 }
 378
 379 /**
 380  *  ixgbe_setup_fc_82598 - Configure flow control settings
 381  *  @hw: pointer to hardware structure
 382  *  @packetbuf_num: packet buffer number (0-7)
 383  *
 384  *  Configures the flow control settings based on SW configuration.  This
 385  *  function is used for 802.3x flow control configuration only.
 386  **/
 387 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 388 {
 389         s32 ret_val = 0;
 390         ixgbe_link_speed speed;
 391         bool link_up;
 392
 393         /* Validate the packetbuf configuration */
 394         if (packetbuf_num < 0 || packetbuf_num > 7) {
 395                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 396                           " 0-7\n", packetbuf_num);
 397                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 398                 goto out;
 399         }
 400
 401         /*
 402          * Validate the water mark configuration.  Zero water marks are invalid
 403          * because it causes the controller to just blast out fc packets.
 404          */
 405         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 406                 if (hw->fc.requested_mode != ixgbe_fc_none) {
 407                         hw_dbg(hw, "Invalid water mark configuration\n");
 408                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 409                         goto out;
 410                 }
 411         }
 412
 413         /*
 414          * Validate the requested mode.  Strict IEEE mode does not allow
 415          * ixgbe_fc_rx_pause because it will cause testing anomalies.
 416          */
 417         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 418                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 419                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 420                 goto out;
 421         }
 422
 423         /*
 424          * 10gig parts do not have a word in the EEPROM to determine the
 425          * default flow control setting, so we explicitly set it to full.
 426          */
 427         if (hw->fc.requested_mode == ixgbe_fc_default)
 428                 hw->fc.requested_mode = ixgbe_fc_full;
 429
 430         /*
 431          * Save off the requested flow control mode for use later.  Depending
 432          * on the link partner's capabilities, we may or may not use this mode.
 433          */
 434
 435         hw->fc.current_mode = hw->fc.requested_mode;
 436
 437         /* Decide whether to use autoneg or not. */
 438         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 439         if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
 440             (speed == IXGBE_LINK_SPEED_1GB_FULL))
 441                 ret_val = ixgbe_fc_autoneg(hw);
 442
 443         if (ret_val)
 444                 goto out;
 445
 446         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
 447
 448 out:
 449         return ret_val;
 450 }
 451
 452 /**
 453  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 454  *  @hw: pointer to hardware structure
 455  *
 456  *  Configures link settings based on values in the ixgbe_hw struct.
 457  *  Restarts the link.  Performs autonegotiation if needed.
 458  **/
 459 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 460 {
 461         u32 autoc_reg;
 462         u32 links_reg;
 463         u32 i;
 464         s32 status = 0;
 465
 466         /* Restart link */
 467         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 468         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 469         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 470
 471         /* Only poll for autoneg to complete if specified to do so */
 472         if (hw->phy.autoneg_wait_to_complete) {
 473                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 474                      IXGBE_AUTOC_LMS_KX4_AN ||
 475                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 476                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 477                         links_reg = 0; /* Just in case Autoneg time = 0 */
 478                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 479                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 480                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 481                                         break;
 482                                 msleep(100);
 483                         }
 484                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 485                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 486                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 487                         }
 488                 }
 489         }
 490
 491         /*
 492          * We want to save off the original Flow Control configuration just in
 493          * case we get disconnected and then reconnected into a different hub
 494          * or switch with different Flow Control capabilities.
 495          */
 496         ixgbe_setup_fc_82598(hw, 0);
 497
 498         /* Add delay to filter out noises during initial link setup */
 499         msleep(50);
 500
 501         return status;
 502 }
 503
 504 /**
 505  *  ixgbe_check_mac_link_82598 - Get link/speed status
 506  *  @hw: pointer to hardware structure
 507  *  @speed: pointer to link speed
 508  *  @link_up: true is link is up, false otherwise
 509  *  @link_up_wait_to_complete: bool used to wait for link up or not
 510  *
 511  *  Reads the links register to determine if link is up and the current speed
 512  **/
 513 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 514                                       ixgbe_link_speed *speed, bool *link_up,
 515                                       bool link_up_wait_to_complete)
 516 {
 517         u32 links_reg;
 518         u32 i;
 519         u16 link_reg, adapt_comp_reg;
 520
 521         /*
 522          * SERDES PHY requires us to read link status from register 0xC79F.
 523          * Bit 0 set indicates link is up/ready; clear indicates link down.
 524          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 525          * clear indicates active; set indicates inactive.
 526          */
 527         if (hw->phy.type == ixgbe_phy_nl) {
 528                 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
 529                 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
 530                 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
 531                                      &adapt_comp_reg);
 532                 if (link_up_wait_to_complete) {
 533                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 534                                 if ((link_reg & 1) &&
 535                                     ((adapt_comp_reg & 1) == 0)) {
 536                                         *link_up = true;
 537                                         break;
 538                                 } else {
 539                                         *link_up = false;
 540                                 }
 541                                 msleep(100);
 542                                 hw->phy.ops.read_reg(hw, 0xC79F,
 543                                                      MDIO_MMD_PMAPMD,
 544                                                      &link_reg);
 545                                 hw->phy.ops.read_reg(hw, 0xC00C,
 546                                                      MDIO_MMD_PMAPMD,
 547                                                      &adapt_comp_reg);
 548                         }
 549                 } else {
 550                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 551                                 *link_up = true;
 552                         else
 553                                 *link_up = false;
 554                 }
 555
 556                 if (*link_up == false)
 557                         goto out;
 558         }
 559
 560         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 561         if (link_up_wait_to_complete) {
 562                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 563                         if (links_reg & IXGBE_LINKS_UP) {
 564                                 *link_up = true;
 565                                 break;
 566                         } else {
 567                                 *link_up = false;
 568                         }
 569                         msleep(100);
 570                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 571                 }
 572         } else {
 573                 if (links_reg & IXGBE_LINKS_UP)
 574                         *link_up = true;
 575                 else
 576                         *link_up = false;
 577         }
 578
 579         if (links_reg & IXGBE_LINKS_SPEED)
 580                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 581         else
 582                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 583
 584 out:
 585         return 0;
 586 }
 587
 588
 589 /**
 590  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 591  *  @hw: pointer to hardware structure
 592  *  @speed: new link speed
 593  *  @autoneg: true if auto-negotiation enabled
 594  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 595  *
 596  *  Set the link speed in the AUTOC register and restarts link.
 597  **/
 598 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 599                                            ixgbe_link_speed speed, bool autoneg,
 600                                            bool autoneg_wait_to_complete)
 601 {
 602         s32              status            = 0;
 603         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 604         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 605         u32              autoc             = curr_autoc;
 606         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 607
 608         /* Check to see if speed passed in is supported. */
 609         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 610         speed &= link_capabilities;
 611
 612         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 613                 status = IXGBE_ERR_LINK_SETUP;
 614
 615         /* Set KX4/KX support according to speed requested */
 616         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 617                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 618                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 619                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 620                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 621                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 622                         autoc |= IXGBE_AUTOC_KX_SUPP;
 623                 if (autoc != curr_autoc)
 624                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 625         }
 626
 627         if (status == 0) {
 628                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 629
 630                 /*
 631                  * Setup and restart the link based on the new values in
 632                  * ixgbe_hw This will write the AUTOC register based on the new
 633                  * stored values
 634                  */
 635                 status = ixgbe_setup_mac_link_82598(hw);
 636         }
 637
 638         return status;
 639 }
 640
 641
 642 /**
 643  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 644  *  @hw: pointer to hardware structure
 645  *
 646  *  Configures link settings based on values in the ixgbe_hw struct.
 647  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 648  *  phy and wait for autonegotiate to finish.  Then synchronize the
 649  *  MAC and PHY.
 650  **/
 651 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 652 {
 653         s32 status;
 654
 655         /* Restart autonegotiation on PHY */
 656         status = hw->phy.ops.setup_link(hw);
 657
 658         /* Set up MAC */
 659         ixgbe_setup_mac_link_82598(hw);
 660
 661         return status;
 662 }
 663
 664 /**
 665  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 666  *  @hw: pointer to hardware structure
 667  *  @speed: new link speed
 668  *  @autoneg: true if autonegotiation enabled
 669  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 670  *
 671  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 672  **/
 673 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 674                                                ixgbe_link_speed speed,
 675                                                bool autoneg,
 676                                                bool autoneg_wait_to_complete)
 677 {
 678         s32 status;
 679
 680         /* Setup the PHY according to input speed */
 681         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 682                                               autoneg_wait_to_complete);
 683
 684         /* Set up MAC */
 685         ixgbe_setup_mac_link_82598(hw);
 686
 687         return status;
 688 }
 689
 690 /**
 691  *  ixgbe_reset_hw_82598 - Performs hardware reset
 692  *  @hw: pointer to hardware structure
 693  *
 694  *  Resets the hardware by resetting the transmit and receive units, masks and
 695  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 696  *  reset.
 697  **/
 698 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 699 {
 700         s32 status = 0;
 701         u32 ctrl;
 702         u32 gheccr;
 703         u32 i;
 704         u32 autoc;
 705         u8  analog_val;
 706
 707         /* Call adapter stop to disable tx/rx and clear interrupts */
 708         hw->mac.ops.stop_adapter(hw);
 709
 710         /*
 711          * Power up the Atlas Tx lanes if they are currently powered down.
 712          * Atlas Tx lanes are powered down for MAC loopback tests, but
 713          * they are not automatically restored on reset.
 714          */
 715         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 716         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 717                 /* Enable Tx Atlas so packets can be transmitted again */
 718                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 719                                              &analog_val);
 720                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 721                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 722                                               analog_val);
 723
 724                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 725                                              &analog_val);
 726                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 727                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 728                                               analog_val);
 729
 730                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 731                                              &analog_val);
 732                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 733                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 734                                               analog_val);
 735
 736                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 737                                              &analog_val);
 738                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 739                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 740                                               analog_val);
 741         }
 742
 743         /* Reset PHY */
 744         if (hw->phy.reset_disable == false) {
 745                 /* PHY ops must be identified and initialized prior to reset */
 746
 747                 /* Init PHY and function pointers, perform SFP setup */
 748                 status = hw->phy.ops.init(hw);
 749                 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 750                         goto reset_hw_out;
 751
 752                 hw->phy.ops.reset(hw);
 753         }
 754
 755         /*
 756          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 757          * access and verify no pending requests before reset
 758          */
 759         status = ixgbe_disable_pcie_master(hw);
 760         if (status != 0) {
 761                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 762                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 763         }
 764
 765         /*
 766          * Issue global reset to the MAC.  This needs to be a SW reset.
 767          * If link reset is used, it might reset the MAC when mng is using it
 768          */
 769         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 770         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 771         IXGBE_WRITE_FLUSH(hw);
 772
 773         /* Poll for reset bit to self-clear indicating reset is complete */
 774         for (i = 0; i < 10; i++) {
 775                 udelay(1);
 776                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 777                 if (!(ctrl & IXGBE_CTRL_RST))
 778                         break;
 779         }
 780         if (ctrl & IXGBE_CTRL_RST) {
 781                 status = IXGBE_ERR_RESET_FAILED;
 782                 hw_dbg(hw, "Reset polling failed to complete.\n");
 783         }
 784
 785         msleep(50);
 786
 787         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 788         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 789         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 790
 791         /*
 792          * Store the original AUTOC value if it has not been
 793          * stored off yet.  Otherwise restore the stored original
 794          * AUTOC value since the reset operation sets back to deaults.
 795          */
 796         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 797         if (hw->mac.orig_link_settings_stored == false) {
 798                 hw->mac.orig_autoc = autoc;
 799                 hw->mac.orig_link_settings_stored = true;
 800         } else if (autoc != hw->mac.orig_autoc) {
 801                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 802         }
 803
 804         /* Store the permanent mac address */
 805         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 806
 807 reset_hw_out:
 808         return status;
 809 }
 810
 811 /**
 812  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 813  *  @hw: pointer to hardware struct
 814  *  @rar: receive address register index to associate with a VMDq index
 815  *  @vmdq: VMDq set index
 816  **/
 817 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 818 {
 819         u32 rar_high;
 820
 821         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 822         rar_high &= ~IXGBE_RAH_VIND_MASK;
 823         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 824         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 825         return 0;
 826 }
 827
 828 /**
 829  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 830  *  @hw: pointer to hardware struct
 831  *  @rar: receive address register index to associate with a VMDq index
 832  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 833  **/
 834 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 835 {
 836         u32 rar_high;
 837         u32 rar_entries = hw->mac.num_rar_entries;
 838
 839         if (rar < rar_entries) {
 840                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 841                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 842                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 843                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 844                 }
 845         } else {
 846                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 847         }
 848
 849         return 0;
 850 }
 851
 852 /**
 853  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 854  *  @hw: pointer to hardware structure
 855  *  @vlan: VLAN id to write to VLAN filter
 856  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 857  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 858  *
 859  *  Turn on/off specified VLAN in the VLAN filter table.
 860  **/
 861 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 862                                 bool vlan_on)
 863 {
 864         u32 regindex;
 865         u32 bitindex;
 866         u32 bits;
 867         u32 vftabyte;
 868
 869         if (vlan > 4095)
 870                 return IXGBE_ERR_PARAM;
 871
 872         /* Determine 32-bit word position in array */
 873         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 874
 875         /* Determine the location of the (VMD) queue index */
 876         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 877         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 878
 879         /* Set the nibble for VMD queue index */
 880         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 881         bits &= (~(0x0F << bitindex));
 882         bits |= (vind << bitindex);
 883         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 884
 885         /* Determine the location of the bit for this VLAN id */
 886         bitindex = vlan & 0x1F;   /* lower five bits */
 887
 888         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 889         if (vlan_on)
 890                 /* Turn on this VLAN id */
 891                 bits |= (1 << bitindex);
 892         else
 893                 /* Turn off this VLAN id */
 894                 bits &= ~(1 << bitindex);
 895         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 896
 897         return 0;
 898 }
 899
 900 /**
 901  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 902  *  @hw: pointer to hardware structure
 903  *
 904  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 905  **/
 906 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 907 {
 908         u32 offset;
 909         u32 vlanbyte;
 910
 911         for (offset = 0; offset < hw->mac.vft_size; offset++)
 912                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 913
 914         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 915                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 916                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 917                                         0);
 918
 919         return 0;
 920 }
 921
 922 /**
 923  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 924  *  @hw: pointer to hardware structure
 925  *  @reg: analog register to read
 926  *  @val: read value
 927  *
 928  *  Performs read operation to Atlas analog register specified.
 929  **/
 930 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 931 {
 932         u32  atlas_ctl;
 933
 934         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 935                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 936         IXGBE_WRITE_FLUSH(hw);
 937         udelay(10);
 938         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 939         *val = (u8)atlas_ctl;
 940
 941         return 0;
 942 }
 943
 944 /**
 945  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 946  *  @hw: pointer to hardware structure
 947  *  @reg: atlas register to write
 948  *  @val: value to write
 949  *
 950  *  Performs write operation to Atlas analog register specified.
 951  **/
 952 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 953 {
 954         u32  atlas_ctl;
 955
 956         atlas_ctl = (reg << 8) | val;
 957         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 958         IXGBE_WRITE_FLUSH(hw);
 959         udelay(10);
 960
 961         return 0;
 962 }
 963
 964 /**
 965  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 966  *  over I2C interface through an intermediate phy.
 967  *  @hw: pointer to hardware structure
 968  *  @byte_offset: EEPROM byte offset to read
 969  *  @eeprom_data: value read
 970  *
 971  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 972  **/
 973 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 974                                        u8 *eeprom_data)
 975 {
 976         s32 status = 0;
 977         u16 sfp_addr = 0;
 978         u16 sfp_data = 0;
 979         u16 sfp_stat = 0;
 980         u32 i;
 981
 982         if (hw->phy.type == ixgbe_phy_nl) {
 983                 /*
 984                  * phy SDA/SCL registers are at addresses 0xC30A to
 985                  * 0xC30D.  These registers are used to talk to the SFP+
 986                  * module's EEPROM through the SDA/SCL (I2C) interface.
 987                  */
 988                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
 989                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
 990                 hw->phy.ops.write_reg(hw,
 991                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
 992                                       MDIO_MMD_PMAPMD,
 993                                       sfp_addr);
 994
 995                 /* Poll status */
 996                 for (i = 0; i < 100; i++) {
 997                         hw->phy.ops.read_reg(hw,
 998                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
 999                                              MDIO_MMD_PMAPMD,
1000                                              &sfp_stat);
1001                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1002                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1003                                 break;
1004                         msleep(10);
1005                 }
1006
1007                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1008                         hw_dbg(hw, "EEPROM read did not pass.\n");
1009                         status = IXGBE_ERR_SFP_NOT_PRESENT;
1010                         goto out;
1011                 }
1012
1013                 /* Read data */
1014                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1015                                      MDIO_MMD_PMAPMD, &sfp_data);
1016
1017                 *eeprom_data = (u8)(sfp_data >> 8);
1018         } else {
1019                 status = IXGBE_ERR_PHY;
1020                 goto out;
1021         }
1022
1023 out:
1024         return status;
1025 }
1026
1027 /**
1028  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1029  *  @hw: pointer to hardware structure
1030  *
1031  *  Determines physical layer capabilities of the current configuration.
1032  **/
1033 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1034 {
1035         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1036         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1037         u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1038         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1039         u16 ext_ability = 0;
1040
1041         hw->phy.ops.identify(hw);
1042
1043         /* Copper PHY must be checked before AUTOC LMS to determine correct
1044          * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1045         if (hw->phy.type == ixgbe_phy_tn ||
1046             hw->phy.type == ixgbe_phy_cu_unknown) {
1047                 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1048                                      &ext_ability);
1049                 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1050                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1051                 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1052                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1053                 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1054                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1055                 goto out;
1056         }
1057
1058         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1059         case IXGBE_AUTOC_LMS_1G_AN:
1060         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1061                 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1062                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1063                 else
1064                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1065                 break;
1066         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1067                 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1068                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1069                 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1070                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1071                 else /* XAUI */
1072                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1073                 break;
1074         case IXGBE_AUTOC_LMS_KX4_AN:
1075         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1076                 if (autoc & IXGBE_AUTOC_KX_SUPP)
1077                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1078                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1079                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1080                 break;
1081         default:
1082                 break;
1083         }
1084
1085         if (hw->phy.type == ixgbe_phy_nl) {
1086                 hw->phy.ops.identify_sfp(hw);
1087
1088                 switch (hw->phy.sfp_type) {
1089                 case ixgbe_sfp_type_da_cu:
1090                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1091                         break;
1092                 case ixgbe_sfp_type_sr:
1093                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1094                         break;
1095                 case ixgbe_sfp_type_lr:
1096                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1097                         break;
1098                 default:
1099                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1100                         break;
1101                 }
1102         }
1103
1104         switch (hw->device_id) {
1105         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1106                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1107                 break;
1108         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1109         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1110         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1111                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1112                 break;
1113         case IXGBE_DEV_ID_82598EB_XF_LR:
1114                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1115                 break;
1116         default:
1117                 break;
1118         }
1119
1120 out:
1121         return physical_layer;
1122 }
1123
1124 static struct ixgbe_mac_operations mac_ops_82598 = {
1125         .init_hw                = &ixgbe_init_hw_generic,
1126         .reset_hw               = &ixgbe_reset_hw_82598,
1127         .start_hw               = &ixgbe_start_hw_generic,
1128         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1129         .get_media_type         = &ixgbe_get_media_type_82598,
1130         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1131         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1132         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1133         .stop_adapter           = &ixgbe_stop_adapter_generic,
1134         .get_bus_info           = &ixgbe_get_bus_info_generic,
1135         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1136         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1137         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1138         .setup_link             = &ixgbe_setup_mac_link_82598,
1139         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1140         .check_link             = &ixgbe_check_mac_link_82598,
1141         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1142         .led_on                 = &ixgbe_led_on_generic,
1143         .led_off                = &ixgbe_led_off_generic,
1144         .blink_led_start        = &ixgbe_blink_led_start_generic,
1145         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
1146         .set_rar                = &ixgbe_set_rar_generic,
1147         .clear_rar              = &ixgbe_clear_rar_generic,
1148         .set_vmdq               = &ixgbe_set_vmdq_82598,
1149         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1150         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1151         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1152         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1153         .enable_mc              = &ixgbe_enable_mc_generic,
1154         .disable_mc             = &ixgbe_disable_mc_generic,
1155         .clear_vfta             = &ixgbe_clear_vfta_82598,
1156         .set_vfta               = &ixgbe_set_vfta_82598,
1157         .setup_fc               = &ixgbe_setup_fc_82598,
1158 };
1159
1160 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1161         .init_params            = &ixgbe_init_eeprom_params_generic,
1162         .read                   = &ixgbe_read_eeprom_generic,
1163         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1164         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1165 };
1166
1167 static struct ixgbe_phy_operations phy_ops_82598 = {
1168         .identify               = &ixgbe_identify_phy_generic,
1169         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1170         .init                   = &ixgbe_init_phy_ops_82598,
1171         .reset                  = &ixgbe_reset_phy_generic,
1172         .read_reg               = &ixgbe_read_phy_reg_generic,
1173         .write_reg              = &ixgbe_write_phy_reg_generic,
1174         .setup_link             = &ixgbe_setup_phy_link_generic,
1175         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1176         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1177 };
1178
1179 struct ixgbe_info ixgbe_82598_info = {
1180         .mac                    = ixgbe_mac_82598EB,
1181         .get_invariants         = &ixgbe_get_invariants_82598,
1182         .mac_ops                = &mac_ops_82598,
1183         .eeprom_ops             = &eeprom_ops_82598,
1184         .phy_ops                = &phy_ops_82598,
1185 };
1186