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   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright (c) 2004,2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C240 NAND driver
   8  *
   9  * Changelog:
  10  *      21-Sep-2004  BJD  Initial version
  11  *      23-Sep-2004  BJD  Mulitple device support
  12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
  13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
  14  *      18-Feb-2005  BJD  Fix sparse errors
  15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
  16  *      02-May-2005  BJD  Fixed s3c2440 support
  17  *      02-May-2005  BJD  Reduced hwcontrol decode
  18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
  19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
  20  *      20-Oct-2005  BJD  Fix timing calculation bug
  21  *      14-Jan-2006  BJD  Allow clock to be stopped when idle
  22  *
  23  * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
  24  *
  25  * This program is free software; you can redistribute it and/or modify
  26  * it under the terms of the GNU General Public License as published by
  27  * the Free Software Foundation; either version 2 of the License, or
  28  * (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  38 */
  39
  40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  41 #define DEBUG
  42 #endif
  43
  44 #include <linux/module.h>
  45 #include <linux/types.h>
  46 #include <linux/init.h>
  47 #include <linux/kernel.h>
  48 #include <linux/string.h>
  49 #include <linux/ioport.h>
  50 #include <linux/platform_device.h>
  51 #include <linux/delay.h>
  52 #include <linux/err.h>
  53 #include <linux/slab.h>
  54 #include <linux/clk.h>
  55
  56 #include <linux/mtd/mtd.h>
  57 #include <linux/mtd/nand.h>
  58 #include <linux/mtd/nand_ecc.h>
  59 #include <linux/mtd/partitions.h>
  60
  61 #include <asm/io.h>
  62
  63 #include <asm/arch/regs-nand.h>
  64 #include <asm/arch/nand.h>
  65
  66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  67 static int hardware_ecc = 1;
  68 #else
  69 static int hardware_ecc = 0;
  70 #endif
  71
  72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
  73 static int clock_stop = 1;
  74 #else
  75 static const int clock_stop = 0;
  76 #endif
  77
  78
  79 /* new oob placement block for use with hardware ecc generation
  80  */
  81
  82 static struct nand_ecclayout nand_hw_eccoob = {
  83         .eccbytes = 3,
  84         .eccpos = {0, 1, 2},
  85         .oobfree = {{8, 8}}
  86 };
  87
  88 /* controller and mtd information */
  89
  90 struct s3c2410_nand_info;
  91
  92 struct s3c2410_nand_mtd {
  93         struct mtd_info                 mtd;
  94         struct nand_chip                chip;
  95         struct s3c2410_nand_set         *set;
  96         struct s3c2410_nand_info        *info;
  97         int                             scan_res;
  98 };
  99
 100 enum s3c_cpu_type {
 101         TYPE_S3C2410,
 102         TYPE_S3C2412,
 103         TYPE_S3C2440,
 104 };
 105
 106 /* overview of the s3c2410 nand state */
 107
 108 struct s3c2410_nand_info {
 109         /* mtd info */
 110         struct nand_hw_control          controller;
 111         struct s3c2410_nand_mtd         *mtds;
 112         struct s3c2410_platform_nand    *platform;
 113
 114         /* device info */
 115         struct device                   *device;
 116         struct resource                 *area;
 117         struct clk                      *clk;
 118         void __iomem                    *regs;
 119         void __iomem                    *sel_reg;
 120         int                             sel_bit;
 121         int                             mtd_count;
 122
 123         enum s3c_cpu_type               cpu_type;
 124 };
 125
 126 /* conversion functions */
 127
 128 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 129 {
 130         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 131 }
 132
 133 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 134 {
 135         return s3c2410_nand_mtd_toours(mtd)->info;
 136 }
 137
 138 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 139 {
 140         return platform_get_drvdata(dev);
 141 }
 142
 143 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 144 {
 145         return dev->dev.platform_data;
 146 }
 147
 148 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
 149 {
 150         return clock_stop;
 151 }
 152
 153 /* timing calculations */
 154
 155 #define NS_IN_KHZ 1000000
 156
 157 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 158 {
 159         int result;
 160
 161         result = (wanted * clk) / NS_IN_KHZ;
 162         result++;
 163
 164         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 165
 166         if (result > max) {
 167                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
 168                 return -1;
 169         }
 170
 171         if (result < 1)
 172                 result = 1;
 173
 174         return result;
 175 }
 176
 177 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 178
 179 /* controller setup */
 180
 181 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
 182                                struct platform_device *pdev)
 183 {
 184         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 185         unsigned long clkrate = clk_get_rate(info->clk);
 186         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 187         int tacls, twrph0, twrph1;
 188         unsigned long cfg = 0;
 189
 190         /* calculate the timing information for the controller */
 191
 192         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 193
 194         if (plat != NULL) {
 195                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 196                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 197                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 198         } else {
 199                 /* default timings */
 200                 tacls = tacls_max;
 201                 twrph0 = 8;
 202                 twrph1 = 8;
 203         }
 204
 205         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 206                 dev_err(info->device, "cannot get suitable timings\n");
 207                 return -EINVAL;
 208         }
 209
 210         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 211                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
 212
 213         switch (info->cpu_type) {
 214         case TYPE_S3C2410:
 215                 cfg = S3C2410_NFCONF_EN;
 216                 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 217                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 218                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 219                 break;
 220
 221         case TYPE_S3C2440:
 222         case TYPE_S3C2412:
 223                 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
 224                 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 225                 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 226
 227                 /* enable the controller and de-assert nFCE */
 228
 229                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 230         }
 231
 232         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 233
 234         writel(cfg, info->regs + S3C2410_NFCONF);
 235         return 0;
 236 }
 237
 238 /* select chip */
 239
 240 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 241 {
 242         struct s3c2410_nand_info *info;
 243         struct s3c2410_nand_mtd *nmtd;
 244         struct nand_chip *this = mtd->priv;
 245         unsigned long cur;
 246
 247         nmtd = this->priv;
 248         info = nmtd->info;
 249
 250         if (chip != -1 && allow_clk_stop(info))
 251                 clk_enable(info->clk);
 252
 253         cur = readl(info->sel_reg);
 254
 255         if (chip == -1) {
 256                 cur |= info->sel_bit;
 257         } else {
 258                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 259                         dev_err(info->device, "invalid chip %d\n", chip);
 260                         return;
 261                 }
 262
 263                 if (info->platform != NULL) {
 264                         if (info->platform->select_chip != NULL)
 265                                 (info->platform->select_chip) (nmtd->set, chip);
 266                 }
 267
 268                 cur &= ~info->sel_bit;
 269         }
 270
 271         writel(cur, info->sel_reg);
 272
 273         if (chip == -1 && allow_clk_stop(info))
 274                 clk_disable(info->clk);
 275 }
 276
 277 /* s3c2410_nand_hwcontrol
 278  *
 279  * Issue command and address cycles to the chip
 280 */
 281
 282 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 283                                    unsigned int ctrl)
 284 {
 285         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 286
 287         if (cmd == NAND_CMD_NONE)
 288                 return;
 289
 290         if (ctrl & NAND_CLE)
 291                 writeb(cmd, info->regs + S3C2410_NFCMD);
 292         else
 293                 writeb(cmd, info->regs + S3C2410_NFADDR);
 294 }
 295
 296 /* command and control functions */
 297
 298 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 299                                    unsigned int ctrl)
 300 {
 301         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 302
 303         if (cmd == NAND_CMD_NONE)
 304                 return;
 305
 306         if (ctrl & NAND_CLE)
 307                 writeb(cmd, info->regs + S3C2440_NFCMD);
 308         else
 309                 writeb(cmd, info->regs + S3C2440_NFADDR);
 310 }
 311
 312 /* s3c2410_nand_devready()
 313  *
 314  * returns 0 if the nand is busy, 1 if it is ready
 315 */
 316
 317 static int s3c2410_nand_devready(struct mtd_info *mtd)
 318 {
 319         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 320         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 321 }
 322
 323 static int s3c2440_nand_devready(struct mtd_info *mtd)
 324 {
 325         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 326         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 327 }
 328
 329 static int s3c2412_nand_devready(struct mtd_info *mtd)
 330 {
 331         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 332         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 333 }
 334
 335 /* ECC handling functions */
 336
 337 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 338                                      u_char *read_ecc, u_char *calc_ecc)
 339 {
 340         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 341         unsigned int diff0, diff1, diff2;
 342         unsigned int bit, byte;
 343
 344         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 345
 346         diff0 = read_ecc[0] ^ calc_ecc[0];
 347         diff1 = read_ecc[1] ^ calc_ecc[1];
 348         diff2 = read_ecc[2] ^ calc_ecc[2];
 349
 350         pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
 351                  __func__,
 352                  read_ecc[0], read_ecc[1], read_ecc[2],
 353                  calc_ecc[0], calc_ecc[1], calc_ecc[2],
 354                  diff0, diff1, diff2);
 355
 356         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 357                 return 0;               /* ECC is ok */
 358
 359         /* Can we correct this ECC (ie, one row and column change).
 360          * Note, this is similar to the 256 error code on smartmedia */
 361
 362         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 363             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 364             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 365                 /* calculate the bit position of the error */
 366
 367                 bit  = (diff2 >> 2) & 1;
 368                 bit |= (diff2 >> 3) & 2;
 369                 bit |= (diff2 >> 4) & 4;
 370
 371                 /* calculate the byte position of the error */
 372
 373                 byte  = (diff1 << 1) & 0x80;
 374                 byte |= (diff1 << 2) & 0x40;
 375                 byte |= (diff1 << 3) & 0x20;
 376                 byte |= (diff1 << 4) & 0x10;
 377
 378                 byte |= (diff0 >> 3) & 0x08;
 379                 byte |= (diff0 >> 2) & 0x04;
 380                 byte |= (diff0 >> 1) & 0x02;
 381                 byte |= (diff0 >> 0) & 0x01;
 382
 383                 byte |= (diff2 << 8) & 0x100;
 384
 385                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 386                         bit, byte);
 387
 388                 dat[byte] ^= (1 << bit);
 389                 return 1;
 390         }
 391
 392         /* if there is only one bit difference in the ECC, then
 393          * one of only a row or column parity has changed, which
 394          * means the error is most probably in the ECC itself */
 395
 396         diff0 |= (diff1 << 8);
 397         diff0 |= (diff2 << 16);
 398
 399         if ((diff0 & ~(1<<fls(diff0))) == 0)
 400                 return 1;
 401
 402         return 0;
 403 }
 404
 405 /* ECC functions
 406  *
 407  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 408  * generator block to ECC the data as it passes through]
 409 */
 410
 411 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 412 {
 413         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 414         unsigned long ctrl;
 415
 416         ctrl = readl(info->regs + S3C2410_NFCONF);
 417         ctrl |= S3C2410_NFCONF_INITECC;
 418         writel(ctrl, info->regs + S3C2410_NFCONF);
 419 }
 420
 421 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 422 {
 423         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 424         unsigned long ctrl;
 425
 426         ctrl = readl(info->regs + S3C2440_NFCONT);
 427         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
 428 }
 429
 430 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 431 {
 432         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 433         unsigned long ctrl;
 434
 435         ctrl = readl(info->regs + S3C2440_NFCONT);
 436         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 437 }
 438
 439 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 440 {
 441         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 442
 443         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 444         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 445         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 446
 447         pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
 448                  ecc_code[0], ecc_code[1], ecc_code[2]);
 449
 450         return 0;
 451 }
 452
 453 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 454 {
 455         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 456         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 457
 458         ecc_code[0] = ecc;
 459         ecc_code[1] = ecc >> 8;
 460         ecc_code[2] = ecc >> 16;
 461
 462         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
 463
 464         return 0;
 465 }
 466
 467 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 468 {
 469         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 470         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 471
 472         ecc_code[0] = ecc;
 473         ecc_code[1] = ecc >> 8;
 474         ecc_code[2] = ecc >> 16;
 475
 476         pr_debug("%s: returning ecc %06lx\n", __func__, ecc);
 477
 478         return 0;
 479 }
 480
 481 /* over-ride the standard functions for a little more speed. We can
 482  * use read/write block to move the data buffers to/from the controller
 483 */
 484
 485 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 486 {
 487         struct nand_chip *this = mtd->priv;
 488         readsb(this->IO_ADDR_R, buf, len);
 489 }
 490
 491 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 492 {
 493         struct nand_chip *this = mtd->priv;
 494         writesb(this->IO_ADDR_W, buf, len);
 495 }
 496
 497 /* device management functions */
 498
 499 static int s3c2410_nand_remove(struct platform_device *pdev)
 500 {
 501         struct s3c2410_nand_info *info = to_nand_info(pdev);
 502
 503         platform_set_drvdata(pdev, NULL);
 504
 505         if (info == NULL)
 506                 return 0;
 507
 508         /* first thing we need to do is release all our mtds
 509          * and their partitions, then go through freeing the
 510          * resources used
 511          */
 512
 513         if (info->mtds != NULL) {
 514                 struct s3c2410_nand_mtd *ptr = info->mtds;
 515                 int mtdno;
 516
 517                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 518                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 519                         nand_release(&ptr->mtd);
 520                 }
 521
 522                 kfree(info->mtds);
 523         }
 524
 525         /* free the common resources */
 526
 527         if (info->clk != NULL && !IS_ERR(info->clk)) {
 528                 if (!allow_clk_stop(info))
 529                         clk_disable(info->clk);
 530                 clk_put(info->clk);
 531         }
 532
 533         if (info->regs != NULL) {
 534                 iounmap(info->regs);
 535                 info->regs = NULL;
 536         }
 537
 538         if (info->area != NULL) {
 539                 release_resource(info->area);
 540                 kfree(info->area);
 541                 info->area = NULL;
 542         }
 543
 544         kfree(info);
 545
 546         return 0;
 547 }
 548
 549 #ifdef CONFIG_MTD_PARTITIONS
 550 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 551                                       struct s3c2410_nand_mtd *mtd,
 552                                       struct s3c2410_nand_set *set)
 553 {
 554         if (set == NULL)
 555                 return add_mtd_device(&mtd->mtd);
 556
 557         if (set->nr_partitions > 0 && set->partitions != NULL) {
 558                 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
 559         }
 560
 561         return add_mtd_device(&mtd->mtd);
 562 }
 563 #else
 564 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 565                                       struct s3c2410_nand_mtd *mtd,
 566                                       struct s3c2410_nand_set *set)
 567 {
 568         return add_mtd_device(&mtd->mtd);
 569 }
 570 #endif
 571
 572 /* s3c2410_nand_init_chip
 573  *
 574  * init a single instance of an chip
 575 */
 576
 577 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 578                                    struct s3c2410_nand_mtd *nmtd,
 579                                    struct s3c2410_nand_set *set)
 580 {
 581         struct nand_chip *chip = &nmtd->chip;
 582         void __iomem *regs = info->regs;
 583
 584         chip->write_buf    = s3c2410_nand_write_buf;
 585         chip->read_buf     = s3c2410_nand_read_buf;
 586         chip->select_chip  = s3c2410_nand_select_chip;
 587         chip->chip_delay   = 50;
 588         chip->priv         = nmtd;
 589         chip->options      = 0;
 590         chip->controller   = &info->controller;
 591
 592         switch (info->cpu_type) {
 593         case TYPE_S3C2410:
 594                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
 595                 info->sel_reg   = regs + S3C2410_NFCONF;
 596                 info->sel_bit   = S3C2410_NFCONF_nFCE;
 597                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
 598                 chip->dev_ready = s3c2410_nand_devready;
 599                 break;
 600
 601         case TYPE_S3C2440:
 602                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 603                 info->sel_reg   = regs + S3C2440_NFCONT;
 604                 info->sel_bit   = S3C2440_NFCONT_nFCE;
 605                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 606                 chip->dev_ready = s3c2440_nand_devready;
 607                 break;
 608
 609         case TYPE_S3C2412:
 610                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 611                 info->sel_reg   = regs + S3C2440_NFCONT;
 612                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
 613                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 614                 chip->dev_ready = s3c2412_nand_devready;
 615
 616                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 617                         dev_info(info->device, "System booted from NAND\n");
 618
 619                 break;
 620         }
 621
 622         chip->IO_ADDR_R = chip->IO_ADDR_W;
 623
 624         nmtd->info         = info;
 625         nmtd->mtd.priv     = chip;
 626         nmtd->mtd.owner    = THIS_MODULE;
 627         nmtd->set          = set;
 628
 629         if (hardware_ecc) {
 630                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 631                 chip->ecc.correct   = s3c2410_nand_correct_data;
 632                 chip->ecc.mode      = NAND_ECC_HW;
 633                 chip->ecc.size      = 512;
 634                 chip->ecc.bytes     = 3;
 635                 chip->ecc.layout    = &nand_hw_eccoob;
 636
 637                 switch (info->cpu_type) {
 638                 case TYPE_S3C2410:
 639                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
 640                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 641                         break;
 642
 643                 case TYPE_S3C2412:
 644                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 645                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 646                         break;
 647
 648                 case TYPE_S3C2440:
 649                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 650                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 651                         break;
 652
 653                 }
 654         } else {
 655                 chip->ecc.mode      = NAND_ECC_SOFT;
 656         }
 657 }
 658
 659 /* s3c2410_nand_probe
 660  *
 661  * called by device layer when it finds a device matching
 662  * one our driver can handled. This code checks to see if
 663  * it can allocate all necessary resources then calls the
 664  * nand layer to look for devices
 665 */
 666
 667 static int s3c24xx_nand_probe(struct platform_device *pdev,
 668                               enum s3c_cpu_type cpu_type)
 669 {
 670         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 671         struct s3c2410_nand_info *info;
 672         struct s3c2410_nand_mtd *nmtd;
 673         struct s3c2410_nand_set *sets;
 674         struct resource *res;
 675         int err = 0;
 676         int size;
 677         int nr_sets;
 678         int setno;
 679
 680         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 681
 682         info = kmalloc(sizeof(*info), GFP_KERNEL);
 683         if (info == NULL) {
 684                 dev_err(&pdev->dev, "no memory for flash info\n");
 685                 err = -ENOMEM;
 686                 goto exit_error;
 687         }
 688
 689         memzero(info, sizeof(*info));
 690         platform_set_drvdata(pdev, info);
 691
 692         spin_lock_init(&info->controller.lock);
 693         init_waitqueue_head(&info->controller.wq);
 694
 695         /* get the clock source and enable it */
 696
 697         info->clk = clk_get(&pdev->dev, "nand");
 698         if (IS_ERR(info->clk)) {
 699                 dev_err(&pdev->dev, "failed to get clock");
 700                 err = -ENOENT;
 701                 goto exit_error;
 702         }
 703
 704         clk_enable(info->clk);
 705
 706         /* allocate and map the resource */
 707
 708         /* currently we assume we have the one resource */
 709         res  = pdev->resource;
 710         size = res->end - res->start + 1;
 711
 712         info->area = request_mem_region(res->start, size, pdev->name);
 713
 714         if (info->area == NULL) {
 715                 dev_err(&pdev->dev, "cannot reserve register region\n");
 716                 err = -ENOENT;
 717                 goto exit_error;
 718         }
 719
 720         info->device     = &pdev->dev;
 721         info->platform   = plat;
 722         info->regs       = ioremap(res->start, size);
 723         info->cpu_type   = cpu_type;
 724
 725         if (info->regs == NULL) {
 726                 dev_err(&pdev->dev, "cannot reserve register region\n");
 727                 err = -EIO;
 728                 goto exit_error;
 729         }
 730
 731         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 732
 733         /* initialise the hardware */
 734
 735         err = s3c2410_nand_inithw(info, pdev);
 736         if (err != 0)
 737                 goto exit_error;
 738
 739         sets = (plat != NULL) ? plat->sets : NULL;
 740         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
 741
 742         info->mtd_count = nr_sets;
 743
 744         /* allocate our information */
 745
 746         size = nr_sets * sizeof(*info->mtds);
 747         info->mtds = kmalloc(size, GFP_KERNEL);
 748         if (info->mtds == NULL) {
 749                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
 750                 err = -ENOMEM;
 751                 goto exit_error;
 752         }
 753
 754         memzero(info->mtds, size);
 755
 756         /* initialise all possible chips */
 757
 758         nmtd = info->mtds;
 759
 760         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
 761                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
 762
 763                 s3c2410_nand_init_chip(info, nmtd, sets);
 764
 765                 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
 766
 767                 if (nmtd->scan_res == 0) {
 768                         s3c2410_nand_add_partition(info, nmtd, sets);
 769                 }
 770
 771                 if (sets != NULL)
 772                         sets++;
 773         }
 774
 775         if (allow_clk_stop(info)) {
 776                 dev_info(&pdev->dev, "clock idle support enabled\n");
 777                 clk_disable(info->clk);
 778         }
 779
 780         pr_debug("initialised ok\n");
 781         return 0;
 782
 783  exit_error:
 784         s3c2410_nand_remove(pdev);
 785
 786         if (err == 0)
 787                 err = -EINVAL;
 788         return err;
 789 }
 790
 791 /* PM Support */
 792 #ifdef CONFIG_PM
 793
 794 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 795 {
 796         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
 797
 798         if (info) {
 799                 if (!allow_clk_stop(info))
 800                         clk_disable(info->clk);
 801         }
 802
 803         return 0;
 804 }
 805
 806 static int s3c24xx_nand_resume(struct platform_device *dev)
 807 {
 808         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
 809
 810         if (info) {
 811                 clk_enable(info->clk);
 812                 s3c2410_nand_inithw(info, dev);
 813
 814                 if (allow_clk_stop(info))
 815                         clk_disable(info->clk);
 816         }
 817
 818         return 0;
 819 }
 820
 821 #else
 822 #define s3c24xx_nand_suspend NULL
 823 #define s3c24xx_nand_resume NULL
 824 #endif
 825
 826 /* driver device registration */
 827
 828 static int s3c2410_nand_probe(struct platform_device *dev)
 829 {
 830         return s3c24xx_nand_probe(dev, TYPE_S3C2410);
 831 }
 832
 833 static int s3c2440_nand_probe(struct platform_device *dev)
 834 {
 835         return s3c24xx_nand_probe(dev, TYPE_S3C2440);
 836 }
 837
 838 static int s3c2412_nand_probe(struct platform_device *dev)
 839 {
 840         return s3c24xx_nand_probe(dev, TYPE_S3C2412);
 841 }
 842
 843 static struct platform_driver s3c2410_nand_driver = {
 844         .probe          = s3c2410_nand_probe,
 845         .remove         = s3c2410_nand_remove,
 846         .suspend        = s3c24xx_nand_suspend,
 847         .resume         = s3c24xx_nand_resume,
 848         .driver         = {
 849                 .name   = "s3c2410-nand",
 850                 .owner  = THIS_MODULE,
 851         },
 852 };
 853
 854 static struct platform_driver s3c2440_nand_driver = {
 855         .probe          = s3c2440_nand_probe,
 856         .remove         = s3c2410_nand_remove,
 857         .suspend        = s3c24xx_nand_suspend,
 858         .resume         = s3c24xx_nand_resume,
 859         .driver         = {
 860                 .name   = "s3c2440-nand",
 861                 .owner  = THIS_MODULE,
 862         },
 863 };
 864
 865 static struct platform_driver s3c2412_nand_driver = {
 866         .probe          = s3c2412_nand_probe,
 867         .remove         = s3c2410_nand_remove,
 868         .suspend        = s3c24xx_nand_suspend,
 869         .resume         = s3c24xx_nand_resume,
 870         .driver         = {
 871                 .name   = "s3c2412-nand",
 872                 .owner  = THIS_MODULE,
 873         },
 874 };
 875
 876 static int __init s3c2410_nand_init(void)
 877 {
 878         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
 879
 880         platform_driver_register(&s3c2412_nand_driver);
 881         platform_driver_register(&s3c2440_nand_driver);
 882         return platform_driver_register(&s3c2410_nand_driver);
 883 }
 884
 885 static void __exit s3c2410_nand_exit(void)
 886 {
 887         platform_driver_unregister(&s3c2412_nand_driver);
 888         platform_driver_unregister(&s3c2440_nand_driver);
 889         platform_driver_unregister(&s3c2410_nand_driver);
 890 }
 891
 892 module_init(s3c2410_nand_init);
 893 module_exit(s3c2410_nand_exit);
 894
 895 MODULE_LICENSE("GPL");
 896 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 897 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");