2 * MPC85xx Device descriptions
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/serial_8250.h>
18 #include <linux/fsl_devices.h>
19 #include <asm/mpc85xx.h>
21 #include <asm/ppc_sys.h>
23 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
24 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
26 struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
36 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
37 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
38 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41 static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
42 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
43 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
44 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
45 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
46 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
50 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
51 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
52 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
53 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
54 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
57 static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
58 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
59 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
60 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
61 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
62 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
65 static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
66 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
67 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
68 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
69 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
70 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
73 static struct gianfar_platform_data mpc85xx_fec_pdata = {
77 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
78 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
81 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
82 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
85 static struct plat_serial8250_port serial_platform_data[] = {
88 .irq = MPC85xx_IRQ_DUART,
90 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
94 .irq = MPC85xx_IRQ_DUART,
96 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
101 struct platform_device ppc_sys_platform_devices[] = {
103 .name = "fsl-gianfar",
105 .dev.platform_data = &mpc85xx_tsec1_pdata,
107 .resource = (struct resource[]) {
109 .start = MPC85xx_ENET1_OFFSET,
110 .end = MPC85xx_ENET1_OFFSET +
111 MPC85xx_ENET1_SIZE - 1,
112 .flags = IORESOURCE_MEM,
116 .start = MPC85xx_IRQ_TSEC1_TX,
117 .end = MPC85xx_IRQ_TSEC1_TX,
118 .flags = IORESOURCE_IRQ,
122 .start = MPC85xx_IRQ_TSEC1_RX,
123 .end = MPC85xx_IRQ_TSEC1_RX,
124 .flags = IORESOURCE_IRQ,
128 .start = MPC85xx_IRQ_TSEC1_ERROR,
129 .end = MPC85xx_IRQ_TSEC1_ERROR,
130 .flags = IORESOURCE_IRQ,
135 .name = "fsl-gianfar",
137 .dev.platform_data = &mpc85xx_tsec2_pdata,
139 .resource = (struct resource[]) {
141 .start = MPC85xx_ENET2_OFFSET,
142 .end = MPC85xx_ENET2_OFFSET +
143 MPC85xx_ENET2_SIZE - 1,
144 .flags = IORESOURCE_MEM,
148 .start = MPC85xx_IRQ_TSEC2_TX,
149 .end = MPC85xx_IRQ_TSEC2_TX,
150 .flags = IORESOURCE_IRQ,
154 .start = MPC85xx_IRQ_TSEC2_RX,
155 .end = MPC85xx_IRQ_TSEC2_RX,
156 .flags = IORESOURCE_IRQ,
160 .start = MPC85xx_IRQ_TSEC2_ERROR,
161 .end = MPC85xx_IRQ_TSEC2_ERROR,
162 .flags = IORESOURCE_IRQ,
167 .name = "fsl-gianfar",
169 .dev.platform_data = &mpc85xx_fec_pdata,
171 .resource = (struct resource[]) {
173 .start = MPC85xx_ENET3_OFFSET,
174 .end = MPC85xx_ENET3_OFFSET +
175 MPC85xx_ENET3_SIZE - 1,
176 .flags = IORESOURCE_MEM,
180 .start = MPC85xx_IRQ_FEC,
181 .end = MPC85xx_IRQ_FEC,
182 .flags = IORESOURCE_IRQ,
189 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
191 .resource = (struct resource[]) {
193 .start = MPC85xx_IIC1_OFFSET,
194 .end = MPC85xx_IIC1_OFFSET +
195 MPC85xx_IIC1_SIZE - 1,
196 .flags = IORESOURCE_MEM,
199 .start = MPC85xx_IRQ_IIC1,
200 .end = MPC85xx_IRQ_IIC1,
201 .flags = IORESOURCE_IRQ,
209 .resource = (struct resource[]) {
211 .start = MPC85xx_DMA0_OFFSET,
212 .end = MPC85xx_DMA0_OFFSET +
213 MPC85xx_DMA0_SIZE - 1,
214 .flags = IORESOURCE_MEM,
217 .start = MPC85xx_IRQ_DMA0,
218 .end = MPC85xx_IRQ_DMA0,
219 .flags = IORESOURCE_IRQ,
227 .resource = (struct resource[]) {
229 .start = MPC85xx_DMA1_OFFSET,
230 .end = MPC85xx_DMA1_OFFSET +
231 MPC85xx_DMA1_SIZE - 1,
232 .flags = IORESOURCE_MEM,
235 .start = MPC85xx_IRQ_DMA1,
236 .end = MPC85xx_IRQ_DMA1,
237 .flags = IORESOURCE_IRQ,
245 .resource = (struct resource[]) {
247 .start = MPC85xx_DMA2_OFFSET,
248 .end = MPC85xx_DMA2_OFFSET +
249 MPC85xx_DMA2_SIZE - 1,
250 .flags = IORESOURCE_MEM,
253 .start = MPC85xx_IRQ_DMA2,
254 .end = MPC85xx_IRQ_DMA2,
255 .flags = IORESOURCE_IRQ,
263 .resource = (struct resource[]) {
265 .start = MPC85xx_DMA3_OFFSET,
266 .end = MPC85xx_DMA3_OFFSET +
267 MPC85xx_DMA3_SIZE - 1,
268 .flags = IORESOURCE_MEM,
271 .start = MPC85xx_IRQ_DMA3,
272 .end = MPC85xx_IRQ_DMA3,
273 .flags = IORESOURCE_IRQ,
278 .name = "serial8250",
279 .id = PLAT8250_DEV_PLATFORM,
280 .dev.platform_data = serial_platform_data,
282 [MPC85xx_PERFMON] = {
283 .name = "fsl-perfmon",
286 .resource = (struct resource[]) {
288 .start = MPC85xx_PERFMON_OFFSET,
289 .end = MPC85xx_PERFMON_OFFSET +
290 MPC85xx_PERFMON_SIZE - 1,
291 .flags = IORESOURCE_MEM,
294 .start = MPC85xx_IRQ_PERFMON,
295 .end = MPC85xx_IRQ_PERFMON,
296 .flags = IORESOURCE_IRQ,
304 .resource = (struct resource[]) {
306 .start = MPC85xx_SEC2_OFFSET,
307 .end = MPC85xx_SEC2_OFFSET +
308 MPC85xx_SEC2_SIZE - 1,
309 .flags = IORESOURCE_MEM,
312 .start = MPC85xx_IRQ_SEC2,
313 .end = MPC85xx_IRQ_SEC2,
314 .flags = IORESOURCE_IRQ,
318 [MPC85xx_CPM_FCC1] = {
319 .name = "fsl-cpm-fcc",
322 .resource = (struct resource[]) {
326 .flags = IORESOURCE_MEM,
331 .flags = IORESOURCE_MEM,
334 .start = SIU_INT_FCC1,
336 .flags = IORESOURCE_IRQ,
340 [MPC85xx_CPM_FCC2] = {
341 .name = "fsl-cpm-fcc",
344 .resource = (struct resource[]) {
348 .flags = IORESOURCE_MEM,
353 .flags = IORESOURCE_MEM,
356 .start = SIU_INT_FCC2,
358 .flags = IORESOURCE_IRQ,
362 [MPC85xx_CPM_FCC3] = {
363 .name = "fsl-cpm-fcc",
366 .resource = (struct resource[]) {
370 .flags = IORESOURCE_MEM,
375 .flags = IORESOURCE_MEM,
378 .start = SIU_INT_FCC3,
380 .flags = IORESOURCE_IRQ,
384 [MPC85xx_CPM_I2C] = {
385 .name = "fsl-cpm-i2c",
388 .resource = (struct resource[]) {
392 .flags = IORESOURCE_MEM,
395 .start = SIU_INT_I2C,
397 .flags = IORESOURCE_IRQ,
401 [MPC85xx_CPM_SCC1] = {
402 .name = "fsl-cpm-scc",
405 .resource = (struct resource[]) {
409 .flags = IORESOURCE_MEM,
412 .start = SIU_INT_SCC1,
414 .flags = IORESOURCE_IRQ,
418 [MPC85xx_CPM_SCC2] = {
419 .name = "fsl-cpm-scc",
422 .resource = (struct resource[]) {
426 .flags = IORESOURCE_MEM,
429 .start = SIU_INT_SCC2,
431 .flags = IORESOURCE_IRQ,
435 [MPC85xx_CPM_SCC3] = {
436 .name = "fsl-cpm-scc",
439 .resource = (struct resource[]) {
443 .flags = IORESOURCE_MEM,
446 .start = SIU_INT_SCC3,
448 .flags = IORESOURCE_IRQ,
452 [MPC85xx_CPM_SCC4] = {
453 .name = "fsl-cpm-scc",
456 .resource = (struct resource[]) {
460 .flags = IORESOURCE_MEM,
463 .start = SIU_INT_SCC4,
465 .flags = IORESOURCE_IRQ,
469 [MPC85xx_CPM_SPI] = {
470 .name = "fsl-cpm-spi",
473 .resource = (struct resource[]) {
477 .flags = IORESOURCE_MEM,
480 .start = SIU_INT_SPI,
482 .flags = IORESOURCE_IRQ,
486 [MPC85xx_CPM_MCC1] = {
487 .name = "fsl-cpm-mcc",
490 .resource = (struct resource[]) {
494 .flags = IORESOURCE_MEM,
497 .start = SIU_INT_MCC1,
499 .flags = IORESOURCE_IRQ,
503 [MPC85xx_CPM_MCC2] = {
504 .name = "fsl-cpm-mcc",
507 .resource = (struct resource[]) {
511 .flags = IORESOURCE_MEM,
514 .start = SIU_INT_MCC2,
516 .flags = IORESOURCE_IRQ,
520 [MPC85xx_CPM_SMC1] = {
521 .name = "fsl-cpm-smc",
524 .resource = (struct resource[]) {
528 .flags = IORESOURCE_MEM,
531 .start = SIU_INT_SMC1,
533 .flags = IORESOURCE_IRQ,
537 [MPC85xx_CPM_SMC2] = {
538 .name = "fsl-cpm-smc",
541 .resource = (struct resource[]) {
545 .flags = IORESOURCE_MEM,
548 .start = SIU_INT_SMC2,
550 .flags = IORESOURCE_IRQ,
554 [MPC85xx_CPM_USB] = {
555 .name = "fsl-cpm-usb",
558 .resource = (struct resource[]) {
562 .flags = IORESOURCE_MEM,
565 .start = SIU_INT_USB,
567 .flags = IORESOURCE_IRQ,
572 .name = "fsl-gianfar",
574 .dev.platform_data = &mpc85xx_etsec1_pdata,
576 .resource = (struct resource[]) {
578 .start = MPC85xx_ENET1_OFFSET,
579 .end = MPC85xx_ENET1_OFFSET +
580 MPC85xx_ENET1_SIZE - 1,
581 .flags = IORESOURCE_MEM,
585 .start = MPC85xx_IRQ_TSEC1_TX,
586 .end = MPC85xx_IRQ_TSEC1_TX,
587 .flags = IORESOURCE_IRQ,
591 .start = MPC85xx_IRQ_TSEC1_RX,
592 .end = MPC85xx_IRQ_TSEC1_RX,
593 .flags = IORESOURCE_IRQ,
597 .start = MPC85xx_IRQ_TSEC1_ERROR,
598 .end = MPC85xx_IRQ_TSEC1_ERROR,
599 .flags = IORESOURCE_IRQ,
604 .name = "fsl-gianfar",
606 .dev.platform_data = &mpc85xx_etsec2_pdata,
608 .resource = (struct resource[]) {
610 .start = MPC85xx_ENET2_OFFSET,
611 .end = MPC85xx_ENET2_OFFSET +
612 MPC85xx_ENET2_SIZE - 1,
613 .flags = IORESOURCE_MEM,
617 .start = MPC85xx_IRQ_TSEC2_TX,
618 .end = MPC85xx_IRQ_TSEC2_TX,
619 .flags = IORESOURCE_IRQ,
623 .start = MPC85xx_IRQ_TSEC2_RX,
624 .end = MPC85xx_IRQ_TSEC2_RX,
625 .flags = IORESOURCE_IRQ,
629 .start = MPC85xx_IRQ_TSEC2_ERROR,
630 .end = MPC85xx_IRQ_TSEC2_ERROR,
631 .flags = IORESOURCE_IRQ,
636 .name = "fsl-gianfar",
638 .dev.platform_data = &mpc85xx_etsec3_pdata,
640 .resource = (struct resource[]) {
642 .start = MPC85xx_ENET3_OFFSET,
643 .end = MPC85xx_ENET3_OFFSET +
644 MPC85xx_ENET3_SIZE - 1,
645 .flags = IORESOURCE_MEM,
649 .start = MPC85xx_IRQ_TSEC3_TX,
650 .end = MPC85xx_IRQ_TSEC3_TX,
651 .flags = IORESOURCE_IRQ,
655 .start = MPC85xx_IRQ_TSEC3_RX,
656 .end = MPC85xx_IRQ_TSEC3_RX,
657 .flags = IORESOURCE_IRQ,
661 .start = MPC85xx_IRQ_TSEC3_ERROR,
662 .end = MPC85xx_IRQ_TSEC3_ERROR,
663 .flags = IORESOURCE_IRQ,
668 .name = "fsl-gianfar",
670 .dev.platform_data = &mpc85xx_etsec4_pdata,
672 .resource = (struct resource[]) {
676 .flags = IORESOURCE_MEM,
680 .start = MPC85xx_IRQ_TSEC4_TX,
681 .end = MPC85xx_IRQ_TSEC4_TX,
682 .flags = IORESOURCE_IRQ,
686 .start = MPC85xx_IRQ_TSEC4_RX,
687 .end = MPC85xx_IRQ_TSEC4_RX,
688 .flags = IORESOURCE_IRQ,
692 .start = MPC85xx_IRQ_TSEC4_ERROR,
693 .end = MPC85xx_IRQ_TSEC4_ERROR,
694 .flags = IORESOURCE_IRQ,
701 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
703 .resource = (struct resource[]) {
707 .flags = IORESOURCE_MEM,
710 .start = MPC85xx_IRQ_IIC1,
711 .end = MPC85xx_IRQ_IIC1,
712 .flags = IORESOURCE_IRQ,
717 .name = "fsl-gianfar_mdio",
719 .dev.platform_data = &mpc85xx_mdio_pdata,
721 .resource = (struct resource[]) {
725 .flags = IORESOURCE_MEM,
731 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
733 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
737 static int __init mach_mpc85xx_init(void)
739 ppc_sys_device_fixup = mach_mpc85xx_fixup;
743 postcore_initcall(mach_mpc85xx_init);