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   1 /*******************************************************************************
   2 *
   3 *      "cs4281.c" --  Cirrus Logic-Crystal CS4281 linux audio driver.
   4 *
   5 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   6 *            -- adapted from drivers by Thomas Sailer,
   7 *            -- but don't bug him; Problems should go to:
   8 *            -- tom woller (twoller@crystal.cirrus.com) or
   9 *               (audio@crystal.cirrus.com).
  10 *
  11 *      This program is free software; you can redistribute it and/or modify
  12 *      it under the terms of the GNU General Public License as published by
  13 *      the Free Software Foundation; either version 2 of the License, or
  14 *      (at your option) any later version.
  15 *
  16 *      This program is distributed in the hope that it will be useful,
  17 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *      GNU General Public License for more details.
  20 *
  21 *      You should have received a copy of the GNU General Public License
  22 *      along with this program; if not, write to the Free Software
  23 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 * Module command line parameters:
  26 *   none
  27 *
  28 *  Supported devices:
  29 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  30 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  31 *  /dev/midi   simple MIDI UART interface, no ioctl
  32 *
  33 * Modification History
  34 * 08/20/00 trw - silence and no stopping DAC until release
  35 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  36 * 09/18/00 trw - added 16bit only record with conversion
  37 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  38 *                capture/playback rates)
  39 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  40 *                libOSSm.so)
  41 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  42 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  43 * 11/10/00 bkz - added __devinit to cs4281_hw_init()
  44 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  45 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  46 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  47 * 12/08/00 trw - added PM support.
  48 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  49 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  50 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  51 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  52 *                defaultorder-100 as power of 2 for the buffer size. example:
  53 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  54 *
  55 *******************************************************************************/
  56
  57 /* uncomment the following line to disable building PM support into the driver */
  58 //#define NOT_CS4281_PM 1
  59
  60 #include <linux/list.h>
  61 #include <linux/module.h>
  62 #include <linux/string.h>
  63 #include <linux/ioport.h>
  64 #include <linux/sched.h>
  65 #include <linux/delay.h>
  66 #include <linux/sound.h>
  67 #include <linux/slab.h>
  68 #include <linux/soundcard.h>
  69 #include <linux/pci.h>
  70 #include <linux/bitops.h>
  71 #include <linux/init.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/poll.h>
  74 #include <linux/fs.h>
  75 #include <linux/wait.h>
  76
  77 #include <asm/current.h>
  78 #include <asm/io.h>
  79 #include <asm/dma.h>
  80 #include <asm/page.h>
  81 #include <asm/uaccess.h>
  82
  83 //#include "cs_dm.h"
  84 #include "cs4281_hwdefs.h"
  85 #include "cs4281pm.h"
  86
  87 struct cs4281_state;
  88
  89 static void stop_dac(struct cs4281_state *s);
  90 static void stop_adc(struct cs4281_state *s);
  91 static void start_dac(struct cs4281_state *s);
  92 static void start_adc(struct cs4281_state *s);
  93 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  94
  95 // ---------------------------------------------------------------------
  96
  97 #ifndef PCI_VENDOR_ID_CIRRUS
  98 #define PCI_VENDOR_ID_CIRRUS          0x1013
  99 #endif
 100 #ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
 101 #define PCI_DEVICE_ID_CRYSTAL_CS4281  0x6005
 102 #endif
 103
 104 #define CS4281_MAGIC  ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
 105 #define CS4281_CFLR_DEFAULT     0x00000001  /* CFLR must be in AC97 link mode */
 106
 107 // buffer order determines the size of the dma buffer for the driver.
 108 // under Linux, a smaller buffer allows more responsiveness from many of the
 109 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 110 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 111 // rather than 64k as some of the games work more responsively.
 112 // log base 2( buff sz = 32k).
 113 static unsigned long defaultorder = 3;
 114 module_param(defaultorder, ulong, 0);
 115
 116 //
 117 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 118 //
 119 #define CSDEBUG 1
 120 #if CSDEBUG
 121 #define CSDEBUG_INTERFACE 1
 122 #else
 123 #undef CSDEBUG_INTERFACE
 124 #endif
 125 //
 126 // cs_debugmask areas
 127 //
 128 #define CS_INIT         0x00000001      // initialization and probe functions
 129 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 130 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 131 #define CS_FUNCTION     0x00000008      // enter/leave functions
 132 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 133 #define CS_WAVE_READ    0x00000020      // read information for wave
 134 #define CS_MIDI_WRITE   0x00000040      // write information for midi
 135 #define CS_MIDI_READ    0x00000080      // read information for midi
 136 #define CS_MPU401_WRITE 0x00000100      // write information for mpu401
 137 #define CS_MPU401_READ  0x00000200      // read information for mpu401
 138 #define CS_OPEN         0x00000400      // all open functions in the driver
 139 #define CS_RELEASE      0x00000800      // all release functions in the driver
 140 #define CS_PARMS        0x00001000      // functional and operational parameters
 141 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 142 #define CS_PM           0x00004000      // power management
 143 #define CS_TMP          0x10000000      // tmp debug mask bit
 144
 145 #define CS_IOCTL_CMD_SUSPEND    0x1     // suspend
 146 #define CS_IOCTL_CMD_RESUME     0x2     // resume
 147 //
 148 // CSDEBUG is usual mode is set to 1, then use the
 149 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 150 // Debug level of 1 has been defined to be kernel errors and info
 151 // that should be printed on any released driver.
 152 //
 153 #if CSDEBUG
 154 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 155 #else
 156 #define CS_DBGOUT(mask,level,x)
 157 #endif
 158
 159 #if CSDEBUG
 160 static unsigned long cs_debuglevel = 1; // levels range from 1-9
 161 static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
 162 module_param(cs_debuglevel, ulong, 0);
 163 module_param(cs_debugmask, ulong, 0);
 164 #endif
 165 #define CS_TRUE         1
 166 #define CS_FALSE        0
 167
 168 // MIDI buffer sizes
 169 #define MIDIINBUF  500
 170 #define MIDIOUTBUF 500
 171
 172 #define FMODE_MIDI_SHIFT 3
 173 #define FMODE_MIDI_READ  (FMODE_READ << FMODE_MIDI_SHIFT)
 174 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
 175
 176 #define CS4281_MAJOR_VERSION    1
 177 #define CS4281_MINOR_VERSION    13
 178 #ifdef __ia64__
 179 #define CS4281_ARCH             64      //architecture key
 180 #else
 181 #define CS4281_ARCH             32      //architecture key
 182 #endif
 183
 184 #define CS_TYPE_ADC 0
 185 #define CS_TYPE_DAC 1
 186
 187
 188 static const char invalid_magic[] =
 189     KERN_CRIT "cs4281: invalid magic value\n";
 190
 191 #define VALIDATE_STATE(s)                         \
 192 ({                                                \
 193         if (!(s) || (s)->magic != CS4281_MAGIC) { \
 194                 printk(invalid_magic);            \
 195                 return -ENXIO;                    \
 196         }                                         \
 197 })
 198
 199 //LIST_HEAD(cs4281_devs);
 200 static struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs };
 201
 202 struct cs4281_state;
 203
 204 #include "cs4281_wrapper-24.c"
 205
 206 struct cs4281_state {
 207         // magic
 208         unsigned int magic;
 209
 210         // we keep the cards in a linked list
 211         struct cs4281_state *next;
 212
 213         // pcidev is needed to turn off the DDMA controller at driver shutdown
 214         struct pci_dev *pcidev;
 215         struct list_head list;
 216
 217         // soundcore stuff
 218         int dev_audio;
 219         int dev_mixer;
 220         int dev_midi;
 221
 222         // hardware resources
 223         unsigned int pBA0phys, pBA1phys;
 224         char __iomem *pBA0;
 225         char __iomem *pBA1;
 226         unsigned int irq;
 227
 228         // mixer registers
 229         struct {
 230                 unsigned short vol[10];
 231                 unsigned int recsrc;
 232                 unsigned int modcnt;
 233                 unsigned short micpreamp;
 234         } mix;
 235
 236         // wave stuff
 237         struct properties {
 238                 unsigned fmt;
 239                 unsigned fmt_original;  // original requested format
 240                 unsigned channels;
 241                 unsigned rate;
 242                 unsigned char clkdiv;
 243         } prop_dac, prop_adc;
 244         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 245         void *tmpbuff;          // tmp buffer for sample conversions
 246         unsigned ena;
 247         spinlock_t lock;
 248         struct semaphore open_sem;
 249         struct semaphore open_sem_adc;
 250         struct semaphore open_sem_dac;
 251         mode_t open_mode;
 252         wait_queue_head_t open_wait;
 253         wait_queue_head_t open_wait_adc;
 254         wait_queue_head_t open_wait_dac;
 255
 256         dma_addr_t dmaaddr_tmpbuff;
 257         unsigned buforder_tmpbuff;      // Log base 2 of 'rawbuf' size in bytes..
 258         struct dmabuf {
 259                 void *rawbuf;   // Physical address of
 260                 dma_addr_t dmaaddr;
 261                 unsigned buforder;      // Log base 2 of 'rawbuf' size in bytes..
 262                 unsigned numfrag;       // # of 'fragments' in the buffer.
 263                 unsigned fragshift;     // Log base 2 of fragment size.
 264                 unsigned hwptr, swptr;
 265                 unsigned total_bytes;   // # bytes process since open.
 266                 unsigned blocks;        // last returned blocks value GETOPTR
 267                 unsigned wakeup;        // interrupt occurred on block
 268                 int count;
 269                 unsigned underrun;      // underrun flag
 270                 unsigned error; // over/underrun
 271                 wait_queue_head_t wait;
 272                 // redundant, but makes calculations easier
 273                 unsigned fragsize;      // 2**fragshift..
 274                 unsigned dmasize;       // 2**buforder.
 275                 unsigned fragsamples;
 276                 // OSS stuff
 277                 unsigned mapped:1;      // Buffer mapped in cs4281_mmap()?
 278                 unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 279                 unsigned endcleared:1;
 280                 unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 281                 unsigned ossfragshift;
 282                 int ossmaxfrags;
 283                 unsigned subdivision;
 284         } dma_dac, dma_adc;
 285
 286         // midi stuff
 287         struct {
 288                 unsigned ird, iwr, icnt;
 289                 unsigned ord, owr, ocnt;
 290                 wait_queue_head_t iwait;
 291                 wait_queue_head_t owait;
 292                 struct timer_list timer;
 293                 unsigned char ibuf[MIDIINBUF];
 294                 unsigned char obuf[MIDIOUTBUF];
 295         } midi;
 296
 297         struct cs4281_pm pm;
 298         struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES];
 299 };
 300
 301 #include <linux/pm_legacy.h>
 302 #include "cs4281pm-24.c"
 303
 304 #if CSDEBUG
 305
 306 // DEBUG ROUTINES
 307
 308 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 309 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 310 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 311 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 312
 313 #define SOUND_MIXER_CS_APM              _SIOWR('M',124, int)
 314
 315
 316 static void cs_printioctl(unsigned int x)
 317 {
 318         unsigned int i;
 319         unsigned char vidx;
 320         // Index of mixtable1[] member is Device ID
 321         // and must be <= SOUND_MIXER_NRDEVICES.
 322         // Value of array member is index into s->mix.vol[]
 323         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 324                 [SOUND_MIXER_PCM] = 1,  // voice
 325                 [SOUND_MIXER_LINE1] = 2,        // AUX
 326                 [SOUND_MIXER_CD] = 3,   // CD
 327                 [SOUND_MIXER_LINE] = 4, // Line
 328                 [SOUND_MIXER_SYNTH] = 5,        // FM
 329                 [SOUND_MIXER_MIC] = 6,  // Mic
 330                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 331                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 332                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 333         };
 334
 335         switch (x) {
 336         case SOUND_MIXER_CS_GETDBGMASK:
 337                 CS_DBGOUT(CS_IOCTL, 4,
 338                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 339                 break;
 340         case SOUND_MIXER_CS_GETDBGLEVEL:
 341                 CS_DBGOUT(CS_IOCTL, 4,
 342                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 343                 break;
 344         case SOUND_MIXER_CS_SETDBGMASK:
 345                 CS_DBGOUT(CS_IOCTL, 4,
 346                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 347                 break;
 348         case SOUND_MIXER_CS_SETDBGLEVEL:
 349                 CS_DBGOUT(CS_IOCTL, 4,
 350                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 351                 break;
 352         case OSS_GETVERSION:
 353                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 354                 break;
 355         case SNDCTL_DSP_SYNC:
 356                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 357                 break;
 358         case SNDCTL_DSP_SETDUPLEX:
 359                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 360                 break;
 361         case SNDCTL_DSP_GETCAPS:
 362                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 363                 break;
 364         case SNDCTL_DSP_RESET:
 365                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 366                 break;
 367         case SNDCTL_DSP_SPEED:
 368                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 369                 break;
 370         case SNDCTL_DSP_STEREO:
 371                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 372                 break;
 373         case SNDCTL_DSP_CHANNELS:
 374                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 375                 break;
 376         case SNDCTL_DSP_GETFMTS:
 377                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 378                 break;
 379         case SNDCTL_DSP_SETFMT:
 380                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 381                 break;
 382         case SNDCTL_DSP_POST:
 383                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 384                 break;
 385         case SNDCTL_DSP_GETTRIGGER:
 386                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 387                 break;
 388         case SNDCTL_DSP_SETTRIGGER:
 389                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 390                 break;
 391         case SNDCTL_DSP_GETOSPACE:
 392                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 393                 break;
 394         case SNDCTL_DSP_GETISPACE:
 395                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 396                 break;
 397         case SNDCTL_DSP_NONBLOCK:
 398                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 399                 break;
 400         case SNDCTL_DSP_GETODELAY:
 401                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 402                 break;
 403         case SNDCTL_DSP_GETIPTR:
 404                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 405                 break;
 406         case SNDCTL_DSP_GETOPTR:
 407                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 408                 break;
 409         case SNDCTL_DSP_GETBLKSIZE:
 410                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 411                 break;
 412         case SNDCTL_DSP_SETFRAGMENT:
 413                 CS_DBGOUT(CS_IOCTL, 4,
 414                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 415                 break;
 416         case SNDCTL_DSP_SUBDIVIDE:
 417                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 418                 break;
 419         case SOUND_PCM_READ_RATE:
 420                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 421                 break;
 422         case SOUND_PCM_READ_CHANNELS:
 423                 CS_DBGOUT(CS_IOCTL, 4,
 424                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 425                 break;
 426         case SOUND_PCM_READ_BITS:
 427                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 428                 break;
 429         case SOUND_PCM_WRITE_FILTER:
 430                 CS_DBGOUT(CS_IOCTL, 4,
 431                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 432                 break;
 433         case SNDCTL_DSP_SETSYNCRO:
 434                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 435                 break;
 436         case SOUND_PCM_READ_FILTER:
 437                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 438                 break;
 439         case SOUND_MIXER_PRIVATE1:
 440                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 441                 break;
 442         case SOUND_MIXER_PRIVATE2:
 443                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 444                 break;
 445         case SOUND_MIXER_PRIVATE3:
 446                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 447                 break;
 448         case SOUND_MIXER_PRIVATE4:
 449                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 450                 break;
 451         case SOUND_MIXER_PRIVATE5:
 452                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 453                 break;
 454         case SOUND_MIXER_INFO:
 455                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 456                 break;
 457         case SOUND_OLD_MIXER_INFO:
 458                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 459                 break;
 460
 461         default:
 462                 switch (_IOC_NR(x)) {
 463                 case SOUND_MIXER_VOLUME:
 464                         CS_DBGOUT(CS_IOCTL, 4,
 465                                   printk("SOUND_MIXER_VOLUME:\n"));
 466                         break;
 467                 case SOUND_MIXER_SPEAKER:
 468                         CS_DBGOUT(CS_IOCTL, 4,
 469                                   printk("SOUND_MIXER_SPEAKER:\n"));
 470                         break;
 471                 case SOUND_MIXER_RECLEV:
 472                         CS_DBGOUT(CS_IOCTL, 4,
 473                                   printk("SOUND_MIXER_RECLEV:\n"));
 474                         break;
 475                 case SOUND_MIXER_MIC:
 476                         CS_DBGOUT(CS_IOCTL, 4,
 477                                   printk("SOUND_MIXER_MIC:\n"));
 478                         break;
 479                 case SOUND_MIXER_SYNTH:
 480                         CS_DBGOUT(CS_IOCTL, 4,
 481                                   printk("SOUND_MIXER_SYNTH:\n"));
 482                         break;
 483                 case SOUND_MIXER_RECSRC:
 484                         CS_DBGOUT(CS_IOCTL, 4,
 485                                   printk("SOUND_MIXER_RECSRC:\n"));
 486                         break;
 487                 case SOUND_MIXER_DEVMASK:
 488                         CS_DBGOUT(CS_IOCTL, 4,
 489                                   printk("SOUND_MIXER_DEVMASK:\n"));
 490                         break;
 491                 case SOUND_MIXER_RECMASK:
 492                         CS_DBGOUT(CS_IOCTL, 4,
 493                                   printk("SOUND_MIXER_RECMASK:\n"));
 494                         break;
 495                 case SOUND_MIXER_STEREODEVS:
 496                         CS_DBGOUT(CS_IOCTL, 4,
 497                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 498                         break;
 499                 case SOUND_MIXER_CAPS:
 500                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 501                         break;
 502                 default:
 503                         i = _IOC_NR(x);
 504                         if (i >= SOUND_MIXER_NRDEVICES
 505                             || !(vidx = mixtable1[i])) {
 506                                 CS_DBGOUT(CS_IOCTL, 4, printk
 507                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 508                                                 x, i));
 509                         } else {
 510                                 CS_DBGOUT(CS_IOCTL, 4, printk
 511                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 512                                                 x, i));
 513                         }
 514                         break;
 515                 }
 516         }
 517 }
 518 #endif
 519 static int prog_dmabuf_adc(struct cs4281_state *s);
 520 static void prog_codec(struct cs4281_state *s, unsigned type);
 521
 522 // ---------------------------------------------------------------------
 523 //
 524 //              Hardware Interfaces For the CS4281
 525 //
 526
 527
 528 //******************************************************************************
 529 // "delayus()-- Delay for the specified # of microseconds.
 530 //******************************************************************************
 531 static void delayus(struct cs4281_state *s, u32 delay)
 532 {
 533         u32 j;
 534         if ((delay > 9999) && (s->pm.flags & CS4281_PM_IDLE)) {
 535                 j = (delay * HZ) / 1000000;     /* calculate delay in jiffies  */
 536                 if (j < 1)
 537                         j = 1;  /* minimum one jiffy. */
 538                 current->state = TASK_UNINTERRUPTIBLE;
 539                 schedule_timeout(j);
 540         } else
 541                 udelay(delay);
 542         return;
 543 }
 544
 545
 546 //******************************************************************************
 547 // "cs4281_read_ac97" -- Reads a word from the specified location in the
 548 //               CS4281's address space(based on the BA0 register).
 549 //
 550 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 551 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
 552 //                                            0h for reads.
 553 // 3. Write ACCTL = Control Register = 460h for initiating the write
 554 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 555 // 5. if DCV not cleared, break and return error
 556 // 6. Read ACSTS = Status Register = 464h, check VSTS bit
 557 //****************************************************************************
 558 static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
 559                             u32 * value)
 560 {
 561         u32 count, status;
 562
 563         // Make sure that there is not data sitting
 564         // around from a previous uncompleted access.
 565         // ACSDA = Status Data Register = 47Ch
 566         status = readl(card->pBA0 + BA0_ACSDA);
 567
 568         // Setup the AC97 control registers on the CS4281 to send the
 569         // appropriate command to the AC97 to perform the read.
 570         // ACCAD = Command Address Register = 46Ch
 571         // ACCDA = Command Data Register = 470h
 572         // ACCTL = Control Register = 460h
 573         // bit DCV - will clear when process completed
 574         // bit CRW - Read command
 575         // bit VFRM - valid frame enabled
 576         // bit ESYN - ASYNC generation enabled
 577
 578         // Get the actual AC97 register from the offset
 579         writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
 580         writel(0, card->pBA0 + BA0_ACCDA);
 581         writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
 582                card->pBA0 + BA0_ACCTL);
 583
 584         // Wait for the read to occur.
 585         for (count = 0; count < 10; count++) {
 586                 // First, we want to wait for a short time.
 587                 udelay(25);
 588
 589                 // Now, check to see if the read has completed.
 590                 // ACCTL = 460h, DCV should be reset by now and 460h = 17h
 591                 if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
 592                         break;
 593         }
 594
 595         // Make sure the read completed.
 596         if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
 597                 return 1;
 598
 599         // Wait for the valid status bit to go active.
 600         for (count = 0; count < 10; count++) {
 601                 // Read the AC97 status register.
 602                 // ACSTS = Status Register = 464h
 603                 status = readl(card->pBA0 + BA0_ACSTS);
 604
 605                 // See if we have valid status.
 606                 // VSTS - Valid Status
 607                 if (status & ACSTS_VSTS)
 608                         break;
 609                 // Wait for a short while.
 610                 udelay(25);
 611         }
 612
 613         // Make sure we got valid status.
 614         if (!(status & ACSTS_VSTS))
 615                 return 1;
 616
 617         // Read the data returned from the AC97 register.
 618         // ACSDA = Status Data Register = 474h
 619         *value = readl(card->pBA0 + BA0_ACSDA);
 620
 621         // Success.
 622         return (0);
 623 }
 624
 625
 626 //****************************************************************************
 627 //
 628 // "cs4281_write_ac97()"-- writes a word to the specified location in the
 629 // CS461x's address space (based on the part's base address zero register).
 630 //
 631 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 632 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
 633 // 3. Write ACCTL = Control Register = 460h for initiating the write
 634 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 635 // 5. if DCV not cleared, break and return error
 636 //
 637 //****************************************************************************
 638 static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
 639                              u32 value)
 640 {
 641         u32 count, status=0;
 642
 643         CS_DBGOUT(CS_FUNCTION, 2,
 644                   printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n"));
 645
 646         // Setup the AC97 control registers on the CS4281 to send the
 647         // appropriate command to the AC97 to perform the read.
 648         // ACCAD = Command Address Register = 46Ch
 649         // ACCDA = Command Data Register = 470h
 650         // ACCTL = Control Register = 460h
 651         // set DCV - will clear when process completed
 652         // reset CRW - Write command
 653         // set VFRM - valid frame enabled
 654         // set ESYN - ASYNC generation enabled
 655         // set RSTN - ARST# inactive, AC97 codec not reset
 656
 657         // Get the actual AC97 register from the offset
 658
 659         writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
 660         writel(value, card->pBA0 + BA0_ACCDA);
 661         writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
 662                card->pBA0 + BA0_ACCTL);
 663
 664         // Wait for the write to occur.
 665         for (count = 0; count < 100; count++) {
 666                 // First, we want to wait for a short time.
 667                 udelay(25);
 668                 // Now, check to see if the write has completed.
 669                 // ACCTL = 460h, DCV should be reset by now and 460h = 07h
 670                 status = readl(card->pBA0 + BA0_ACCTL);
 671                 if (!(status & ACCTL_DCV))
 672                         break;
 673         }
 674
 675         // Make sure the write completed.
 676         if (status & ACCTL_DCV) {
 677                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
 678                         "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n"));
 679                 return 1;
 680         }
 681         CS_DBGOUT(CS_FUNCTION, 2,
 682                   printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n"));
 683         // Success.
 684         return 0;
 685 }
 686
 687
 688 //******************************************************************************
 689 // "Init4281()" -- Bring up the part.
 690 //******************************************************************************
 691 static __devinit int cs4281_hw_init(struct cs4281_state *card)
 692 {
 693         u32 ac97_slotid;
 694         u32 temp1, temp2;
 695
 696         CS_DBGOUT(CS_FUNCTION, 2,
 697                   printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n"));
 698 #ifndef NOT_CS4281_PM
 699         if(!card)
 700                 return 1;
 701 #endif
 702         temp2 = readl(card->pBA0 + BA0_CFLR);
 703         CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO
 704                 "cs4281: cs4281_hw_init() CFLR 0x%x\n", temp2));
 705         if(temp2 != CS4281_CFLR_DEFAULT)
 706         {
 707                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
 708                         "cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%x\n",
 709                                 temp2,CS4281_CFLR_DEFAULT));
 710                 writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR);
 711                 temp2 = readl(card->pBA0 + BA0_CFLR);
 712                 if(temp2 != CS4281_CFLR_DEFAULT)
 713                 {
 714                         CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
 715                                 "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR\n"));
 716                         return 1;
 717                 }
 718         }
 719
 720         //***************************************7
 721         //  Set up the Sound System Configuration
 722         //***************************************
 723
 724         // Set the 'Configuration Write Protect' register
 725         // to 4281h.  Allows vendor-defined configuration
 726         // space between 0e4h and 0ffh to be written.
 727
 728         writel(0x4281, card->pBA0 + BA0_CWPR);  // (3e0h)
 729
 730         // (0), Blast the clock control register to zero so that the
 731         // PLL starts out in a known state, and blast the master serial
 732         // port control register to zero so that the serial ports also
 733         // start out in a known state.
 734
 735         writel(0, card->pBA0 + BA0_CLKCR1);     // (400h)
 736         writel(0, card->pBA0 + BA0_SERMC);      // (420h)
 737
 738
 739         // (1), Make ESYN go to zero to turn off
 740         // the Sync pulse on the AC97 link.
 741
 742         writel(0, card->pBA0 + BA0_ACCTL);
 743         udelay(50);
 744
 745
 746         // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
 747         // the AC97 spec) and then drive it high.  This is done for non
 748         // AC97 modes since there might be logic external to the CS461x
 749         // that uses the ARST# line for a reset.
 750
 751         writel(0, card->pBA0 + BA0_SPMC);       // (3ech)
 752         udelay(100);
 753         writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
 754         delayus(card,50000);            // Wait 50 ms for ABITCLK to become stable.
 755
 756         // (3) Turn on the Sound System Clocks.
 757         writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1);   // (400h)
 758         delayus(card,50000);            // Wait for the PLL to stabilize.
 759         // Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
 760         writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
 761
 762         // (4) Power on everything for now..
 763         writel(0x7E, card->pBA0 + BA0_SSPM);    // (740h)
 764
 765         // (5) Wait for clock stabilization.
 766         for (temp1 = 0; temp1 < 1000; temp1++) {
 767                 udelay(1000);
 768                 if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
 769                         break;
 770         }
 771         if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
 772                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
 773                         "cs4281: DLLRDY failed!\n"));
 774                 return -EIO;
 775         }
 776         // (6) Enable ASYNC generation.
 777         writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL);     // (460h)
 778
 779         // Now wait 'for a short while' to allow the  AC97
 780         // part to start generating bit clock. (so we don't
 781         // Try to start the PLL without an input clock.)
 782         delayus(card,50000);
 783
 784         // Set the serial port timing configuration, so that the
 785         // clock control circuit gets its clock from the right place.
 786         writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
 787
 788         // (7) Wait for the codec ready signal from the AC97 codec.
 789
 790         for (temp1 = 0; temp1 < 1000; temp1++) {
 791                 // Delay a mil to let things settle out and
 792                 // to prevent retrying the read too quickly.
 793                 udelay(1000);
 794                 if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready,  (464h)
 795                         break;  //   exit the 'for' loop.
 796         }
 797         if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY))      // If never came ready,
 798         {
 799                 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
 800                          "cs4281: ACSTS never came ready!\n"));
 801                 return -EIO;    //   exit initialization.
 802         }
 803         // (8) Assert the 'valid frame' signal so we can
 804         // begin sending commands to the AC97 codec.
 805         writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL);        // (460h)
 806
 807         // (9), Wait until CODEC calibration is finished.
 808         // Print an error message if it doesn't.
 809         for (temp1 = 0; temp1 < 1000; temp1++) {
 810                 delayus(card,10000);
 811                 // Read the AC97 Powerdown Control/Status Register.
 812                 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
 813                 if ((temp2 & 0x0000000F) == 0x0000000F)
 814                         break;
 815         }
 816         if ((temp2 & 0x0000000F) != 0x0000000F) {
 817                 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
 818                         "cs4281: Codec failed to calibrate.  Status = %.8x.\n",
 819                                 temp2));
 820                 return -EIO;
 821         }
 822         // (10), Set the serial port timing configuration, so that the
 823         // clock control circuit gets its clock from the right place.
 824         writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
 825
 826
 827         // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
 828         // that the codec is pumping ADC data across the AC link.
 829         for (temp1 = 0; temp1 < 1000; temp1++) {
 830                 // Delay a mil to let things settle out and
 831                 // to prevent retrying the read too quickly.
 832                 delayus(card,1000);     //(test)
 833
 834                 // Read the input slot valid register;  See
 835                 // if input slots 3 and 4 are valid yet.
 836                 if (
 837                     (readl(card->pBA0 + BA0_ACISV) &
 838                      (ACISV_ISV3 | ACISV_ISV4)) ==
 839                     (ACISV_ISV3 | ACISV_ISV4)) break;   // Exit the 'for' if slots are valid.
 840         }
 841         // If we never got valid data, exit initialization.
 842         if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
 843             != (ACISV_ISV3 | ACISV_ISV4)) {
 844                 CS_DBGOUT(CS_FUNCTION, 2,
 845                           printk(KERN_ERR
 846                                  "cs4281: Never got valid data!\n"));
 847                 return -EIO;    // If no valid data, exit initialization.
 848         }
 849         // (12), Start digital data transfer of audio data to the codec.
 850         writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV);        // (468h)
 851
 852
 853         //**************************************
 854         // Unmute the Master and Alternate
 855         // (headphone) volumes.  Set to max.
 856         //**************************************
 857         cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
 858         cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
 859
 860         //******************************************
 861         // Power on the DAC(AddDACUser()from main())
 862         //******************************************
 863         cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 864         cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
 865
 866         // Wait until we sample a DAC ready state.
 867         for (temp2 = 0; temp2 < 32; temp2++) {
 868                 // Let's wait a mil to let things settle.
 869                 delayus(card,1000);
 870                 // Read the current state of the power control reg.
 871                 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 872                 // If the DAC ready state bit is set, stop waiting.
 873                 if (temp1 & 0x2)
 874                         break;
 875         }
 876
 877         //******************************************
 878         // Power on the ADC(AddADCUser()from main())
 879         //******************************************
 880         cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 881         cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
 882
 883         // Wait until we sample ADC ready state.
 884         for (temp2 = 0; temp2 < 32; temp2++) {
 885                 // Let's wait a mil to let things settle.
 886                 delayus(card,1000);
 887                 // Read the current state of the power control reg.
 888                 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 889                 // If the ADC ready state bit is set, stop waiting.
 890                 if (temp1 & 0x1)
 891                         break;
 892         }
 893         // Set up 4281 Register contents that
 894         // don't change for boot duration.
 895
 896         // For playback, we map AC97 slot 3 and 4(Left
 897         // & Right PCM playback) to DMA Channel 0.
 898         // Set the fifo to be 15 bytes at offset zero.
 899
 900         ac97_slotid = 0x01000f00;       // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
 901         // FCR0.LS[4:0]=0(=>slot3, left PCM playback).
 902         // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
 903         writel(ac97_slotid, card->pBA0 + BA0_FCR0);     // (180h)
 904         writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0);  // Turn on FIFO Enable.
 905
 906         // For capture, we map AC97 slot 10 and 11(Left
 907         // and Right PCM Record) to DMA Channel 1.
 908         // Set the fifo to be 15 bytes at offset sixteen.
 909         ac97_slotid = 0x0B0A0f10;       // FCR1.RS[4:0]=11(=>slot11, right PCM record).
 910         // FCR1.LS[4:0]=10(=>slot10, left PCM record).
 911         // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
 912         writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1);  // (184h)
 913         writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1);  // Turn on FIFO Enable.
 914
 915         // Map the Playback SRC to the same AC97 slots(3 & 4--
 916         // --Playback left & right)as DMA channel 0.
 917         // Map the record SRC to the same AC97 slots(10 & 11--
 918         // -- Record left & right) as DMA channel 1.
 919
 920         ac97_slotid = 0x0b0a0100;       // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
 921         // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
 922         // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
 923         // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
 924         writel(ac97_slotid, card->pBA0 + BA0_SRCSA);    // (75ch)
 925
 926         // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
 927         // Count Interrupt Enable' in DMA Control Registers 0 & 1.
 928         // Set 'MSK' flag to 1 to keep the DMA engines paused.
 929         temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK);    // (00030001h)
 930         writel(temp1, card->pBA0 + BA0_DCR0);   // (154h
 931         writel(temp1, card->pBA0 + BA0_DCR1);   // (15ch)
 932
 933         // Set 'Auto-Initialize Control' to 'enabled'; For playback,
 934         // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
 935         // for record, set Transfer Type Control to 'write transfer'.
 936         // All other bits set to zero;  Some will be changed @ transfer start.
 937         temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ);  // (20000018h)
 938         writel(temp1, card->pBA0 + BA0_DMR0);   // (150h)
 939         temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
 940         writel(temp1, card->pBA0 + BA0_DMR1);   // (158h)
 941
 942         // Enable DMA interrupts generally, and
 943         // DMA0 & DMA1 interrupts specifically.
 944         temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
 945         writel(temp1, card->pBA0 + BA0_HIMR);
 946
 947         CS_DBGOUT(CS_FUNCTION, 2,
 948                   printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n"));
 949         return 0;
 950 }
 951
 952 #ifndef NOT_CS4281_PM
 953 static void printpm(struct cs4281_state *s)
 954 {
 955         CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
 956         CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%x\n",
 957                 (unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue));
 958         CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%x\n",
 959                 s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue));
 960         CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%x\n",
 961                 s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue));
 962         CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%x\n",
 963                 s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue));
 964         CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%x\n",
 965                 s->pm.u32SSCR,s->pm.u32SRCSA));
 966         CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%x\n",
 967                 s->pm.u32DacASR,s->pm.u32AdcASR));
 968         CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%x\n",
 969                 s->pm.u32DacSR,s->pm.u32AdcSR));
 970         CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%x\n",
 971                 s->pm.u32MIDCR_Save));
 972
 973 }
 974 static void printpipe(struct cs4281_pipeline *pl)
 975 {
 976
 977         CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
 978         CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%x\n",
 979                 (unsigned)pl->flags,pl->number));
 980         CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%x\n",
 981                 pl->u32DBAnValue,pl->u32DBCnValue));
 982         CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%x\n",
 983                 pl->u32DMRnValue,pl->u32DCRnValue));
 984         CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%x\n",
 985                 pl->u32DBAnAddress,pl->u32DBCnAddress));
 986         CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%x\n",
 987                 pl->u32DCCnAddress,pl->u32DCCnAddress));
 988         CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%x\n",
 989                 pl->u32DMRnAddress,pl->u32DCRnAddress));
 990         CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%x\n",
 991                 pl->u32HDSRnAddress,pl->u32DBAn_Save));
 992         CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%x\n",
 993                 pl->u32DBCn_Save,pl->u32DMRn_Save));
 994         CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%x\n",
 995                 pl->u32DCRn_Save,pl->u32DCCn_Save));
 996         CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%x\n",
 997                 pl->u32DCAn_Save));
 998         CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%x\n",
 999                 pl->u32FCRn_Save,pl->u32FSICn_Save));
1000         CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%x\n",
1001                 pl->u32FCRnValue,pl->u32FSICnValue));
1002         CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%x\n",
1003                 pl->u32FCRnAddress,pl->u32FSICnAddress));
1004         CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%x\n",
1005                 pl->u32FPDRnValue,pl->u32FPDRnAddress));
1006 }
1007 static void printpipelines(struct cs4281_state *s)
1008 {
1009         int i;
1010         for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
1011         {
1012                 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1013                 {
1014                         printpipe(&s->pl[i]);
1015                 }
1016         }
1017 }
1018 /****************************************************************************
1019 *
1020 *  Suspend - save the ac97 regs, mute the outputs and power down the part.
1021 *
1022 ****************************************************************************/
1023 static void cs4281_ac97_suspend(struct cs4281_state *s)
1024 {
1025         int Count,i;
1026
1027         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+\n"));
1028 /*
1029 * change the state, save the current hwptr, then stop the dac/adc
1030 */
1031         s->pm.flags &= ~CS4281_PM_IDLE;
1032         s->pm.flags |= CS4281_PM_SUSPENDING;
1033         s->pm.u32hwptr_playback = readl(s->pBA0 + BA0_DCA0);
1034         s->pm.u32hwptr_capture = readl(s->pBA0 + BA0_DCA1);
1035         stop_dac(s);
1036         stop_adc(s);
1037
1038         for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1039                         && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1040                 Count += 2, i++)
1041         {
1042                 cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]);
1043         }
1044 /*
1045 * Save the ac97 volume registers as well as the current powerdown state.
1046 * Now, mute the all the outputs (master, headphone, and mono), as well
1047 * as the PCM volume, in preparation for powering down the entire part.
1048 */
1049         cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume);
1050         cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume);
1051         cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono);
1052         cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume);
1053
1054         cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000);
1055         cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000);
1056         cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000);
1057         cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000);
1058
1059         cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown);
1060         cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose);
1061
1062 /*
1063 * And power down everything on the AC97 codec.
1064 */
1065         cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00);
1066         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-\n"));
1067 }
1068
1069 /****************************************************************************
1070 *
1071 *  Resume - power up the part and restore its registers..
1072 *
1073 ****************************************************************************/
1074 static void cs4281_ac97_resume(struct cs4281_state *s)
1075 {
1076         int Count,i;
1077
1078         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+\n"));
1079
1080 /* do not save the power state registers at this time
1081     //
1082     // If we saved away the power control registers, write them into the
1083     // shadows so those saved values get restored instead of the current
1084     // shadowed value.
1085     //
1086     if( bPowerStateSaved )
1087     {
1088         PokeShadow( 0x26, ulSaveReg0x26 );
1089         bPowerStateSaved = FALSE;
1090     }
1091 */
1092
1093 //
1094 // First, we restore the state of the general purpose register.  This
1095 // contains the mic select (mic1 or mic2) and if we restore this after
1096 // we restore the mic volume/boost state and mic2 was selected at
1097 // suspend time, we will end up with a brief period of time where mic1
1098 // is selected with the volume/boost settings for mic2, causing
1099 // acoustic feedback.  So we restore the general purpose register
1100 // first, thereby getting the correct mic selected before we restore
1101 // the mic volume/boost.
1102 //
1103         cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose);
1104
1105 //
1106 // Now, while the outputs are still muted, restore the state of power
1107 // on the AC97 part.
1108 //
1109         cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown);
1110
1111 /*
1112 * Restore just the first set of registers, from register number
1113 * 0x02 to the register number that ulHighestRegToRestore specifies.
1114 */
1115         for(    Count = 0x2, i=0;
1116                 (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1117                         && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1118                 Count += 2, i++)
1119         {
1120                 cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]);
1121         }
1122         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-\n"));
1123 }
1124
1125 /* do not save the power state registers at this time
1126 ****************************************************************************
1127 *
1128 *  SavePowerState - Save the power registers away.
1129 *
1130 ****************************************************************************
1131 void
1132 HWAC97codec::SavePowerState(void)
1133 {
1134     ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()\r\n");
1135
1136     ulSaveReg0x26 = PeekShadow(0x26);
1137
1138     //
1139     // Note that we have saved registers that need to be restored during a
1140     // resume instead of ulAC97Regs[].
1141     //
1142     bPowerStateSaved = TRUE;
1143
1144 } // SavePowerState
1145 */
1146
1147 static void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1148 {
1149  /*
1150  * We need to save the contents of the BASIC FIFO Registers.
1151  */
1152         pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress);
1153         pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress);
1154 }
1155 static void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1156 {
1157  /*
1158  * We need to restore the contents of the BASIC FIFO Registers.
1159  */
1160         writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress);
1161         writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress);
1162 }
1163 static void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1164 {
1165         //
1166         // We need to save the contents of the BASIC DMA Registers.
1167         //
1168         pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress);
1169         pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress);
1170         pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress);
1171         pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress);
1172         pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress);
1173         pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress);
1174 }
1175 static void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1176 {
1177         //
1178         // We need to save the contents of the BASIC DMA Registers.
1179         //
1180         writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress);
1181         writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress);
1182         writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress);
1183         writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress);
1184         writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress);
1185         writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress);
1186 }
1187
1188 static int cs4281_suspend(struct cs4281_state *s)
1189 {
1190         int i;
1191         u32 u32CLKCR1;
1192         struct cs4281_pm *pm = &s->pm;
1193         CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1194                 printk("cs4281: cs4281_suspend()+ flags=%d\n",
1195                         (unsigned)s->pm.flags));
1196 /*
1197 * check the current state, only suspend if IDLE
1198 */
1199         if(!(s->pm.flags & CS4281_PM_IDLE))
1200         {
1201                 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1202                         printk("cs4281: cs4281_suspend() unable to suspend, not IDLE\n"));
1203                 return 1;
1204         }
1205         s->pm.flags &= ~CS4281_PM_IDLE;
1206         s->pm.flags |= CS4281_PM_SUSPENDING;
1207
1208 //
1209 // Gershwin CLKRUN - Set CKRA
1210 //
1211         u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1212
1213         pm->u32CLKCR1_SAVE = u32CLKCR1;
1214         if(!(u32CLKCR1 & 0x00010000 ) )
1215                 writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1216
1217 //
1218 // First, turn on the clocks (yikes) to the devices, so that they will
1219 // respond when we try to save their state.
1220 //
1221         if(!(u32CLKCR1 & CLKCR1_SWCE))
1222         {
1223                 writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1);
1224         }
1225
1226         //
1227         // Save the power state
1228         //
1229         pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM);
1230
1231         //
1232         // Disable interrupts.
1233         //
1234         writel(HICR_CHGM, s->pBA0 + BA0_HICR);
1235
1236         //
1237         // Save the PCM Playback Left and Right Volume Control.
1238         //
1239         pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC);
1240         pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC);
1241
1242         //
1243         // Save the FM Synthesis Left and Right Volume Control.
1244         //
1245         pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC);
1246         pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC);
1247
1248         //
1249         // Save the GPIOR value.
1250         //
1251         pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR);
1252
1253         //
1254         // Save the JSCTL value.
1255         //
1256         pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR);
1257
1258         //
1259         // Save Sound System Control Register
1260         //
1261         pm->u32SSCR = readl(s->pBA0 + BA0_SSCR);
1262
1263         //
1264         // Save SRC Slot Assinment register
1265         //
1266         pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA);
1267
1268         //
1269         // Save sample rate
1270         //
1271         pm->u32DacASR = readl(s->pBA0 + BA0_PASR);
1272         pm->u32AdcASR = readl(s->pBA0 + BA0_CASR);
1273         pm->u32DacSR = readl(s->pBA0 + BA0_DACSR);
1274         pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR);
1275
1276         //
1277         // Loop through all of the PipeLines
1278         //
1279         for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1280         {
1281                 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1282                 {
1283                 //
1284                 // Ask the DMAengines and FIFOs to Suspend.
1285                 //
1286                         cs4281_SuspendDMAengine(s,&s->pl[i]);
1287                         cs4281_SuspendFIFO(s,&s->pl[i]);
1288                 }
1289         }
1290         //
1291         // We need to save the contents of the Midi Control Register.
1292         //
1293         pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR);
1294 /*
1295 * save off the AC97 part information
1296 */
1297         cs4281_ac97_suspend(s);
1298
1299         //
1300         // Turn off the serial ports.
1301         //
1302         writel(0, s->pBA0 + BA0_SERMC);
1303
1304         //
1305         // Power off FM, Joystick, AC link,
1306         //
1307         writel(0, s->pBA0 + BA0_SSPM);
1308
1309         //
1310         // DLL off.
1311         //
1312         writel(0, s->pBA0 + BA0_CLKCR1);
1313
1314         //
1315         // AC link off.
1316         //
1317         writel(0, s->pBA0 + BA0_SPMC);
1318
1319         //
1320         // Put the chip into D3(hot) state.
1321         //
1322         // PokeBA0(BA0_PMCS, 0x00000003);
1323
1324         //
1325         // Gershwin CLKRUN - Clear CKRA
1326         //
1327         u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1328         writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1);
1329
1330 #ifdef CSDEBUG
1331         printpm(s);
1332         printpipelines(s);
1333 #endif
1334
1335         s->pm.flags &= ~CS4281_PM_SUSPENDING;
1336         s->pm.flags |= CS4281_PM_SUSPENDED;
1337
1338         CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1339                 printk("cs4281: cs4281_suspend()- flags=%d\n",
1340                         (unsigned)s->pm.flags));
1341         return 0;
1342 }
1343
1344 static int cs4281_resume(struct cs4281_state *s)
1345 {
1346         int i;
1347         unsigned temp1;
1348         u32 u32CLKCR1;
1349         struct cs4281_pm *pm = &s->pm;
1350         CS_DBGOUT(CS_PM | CS_FUNCTION, 4,
1351                 printk( "cs4281: cs4281_resume()+ flags=%d\n",
1352                         (unsigned)s->pm.flags));
1353         if(!(s->pm.flags & CS4281_PM_SUSPENDED))
1354         {
1355                 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1356                         printk("cs4281: cs4281_resume() unable to resume, not SUSPENDED\n"));
1357                 return 1;
1358         }
1359         s->pm.flags &= ~CS4281_PM_SUSPENDED;
1360         s->pm.flags |= CS4281_PM_RESUMING;
1361
1362 //
1363 // Gershwin CLKRUN - Set CKRA
1364 //
1365         u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1366         writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1367
1368         //
1369         // set the power state.
1370         //
1371         //old PokeBA0(BA0_PMCS, 0);
1372
1373         //
1374         // Program the clock circuit and serial ports.
1375         //
1376         temp1 = cs4281_hw_init(s);
1377         if (temp1) {
1378                 CS_DBGOUT(CS_ERROR | CS_INIT, 1,
1379                     printk(KERN_ERR
1380                         "cs4281: resume cs4281_hw_init() error.\n"));
1381                 return -1;
1382         }
1383
1384         //
1385         // restore the Power state
1386         //
1387         writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM);
1388
1389         //
1390         // Set post SRC mix setting (FM or ALT48K)
1391         //
1392         writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM);
1393
1394         //
1395         // Loop through all of the PipeLines
1396         //
1397         for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1398         {
1399                 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1400                 {
1401                 //
1402                 // Ask the DMAengines and FIFOs to Resume.
1403                 //
1404                         cs4281_ResumeDMAengine(s,&s->pl[i]);
1405                         cs4281_ResumeFIFO(s,&s->pl[i]);
1406                 }
1407         }
1408         //
1409         // We need to restore the contents of the Midi Control Register.
1410         //
1411         writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR);
1412
1413         cs4281_ac97_resume(s);
1414         //
1415         // Restore the PCM Playback Left and Right Volume Control.
1416         //
1417         writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC);
1418         writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC);
1419
1420         //
1421         // Restore the FM Synthesis Left and Right Volume Control.
1422         //
1423         writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC);
1424         writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC);
1425
1426         //
1427         // Restore the JSCTL value.
1428         //
1429         writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL);
1430
1431         //
1432         // Restore the GPIOR register value.
1433         //
1434         writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR);
1435
1436         //
1437         // Restore Sound System Control Register
1438         //
1439         writel(pm->u32SSCR, s->pBA0 + BA0_SSCR);
1440
1441         //
1442         // Restore SRC Slot Assignment register
1443         //
1444         writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA);
1445
1446         //
1447         // Restore sample rate
1448         //
1449         writel(pm->u32DacASR, s->pBA0 + BA0_PASR);
1450         writel(pm->u32AdcASR, s->pBA0 + BA0_CASR);
1451         writel(pm->u32DacSR, s->pBA0 + BA0_DACSR);
1452         writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR);
1453
1454         //
1455         // Restore CFL1/2 registers we saved to compensate for OEM bugs.
1456         //
1457         //      PokeBA0(BA0_CFLR, ulConfig);
1458
1459         //
1460         // Gershwin CLKRUN - Clear CKRA
1461         //
1462         writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1);
1463
1464         //
1465         // Enable interrupts on the part.
1466         //
1467         writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
1468
1469 #ifdef CSDEBUG
1470         printpm(s);
1471         printpipelines(s);
1472 #endif
1473 /*
1474 * change the state, restore the current hwptrs, then stop the dac/adc
1475 */
1476         s->pm.flags |= CS4281_PM_IDLE;
1477         s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED
1478                         | CS4281_PM_RESUMING | CS4281_PM_RESUMED);
1479
1480         writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0);
1481         writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1);
1482         start_dac(s);
1483         start_adc(s);
1484
1485         CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%d\n",
1486                 (unsigned)s->pm.flags));
1487         return 0;
1488 }
1489
1490 #endif
1491
1492 //******************************************************************************
1493 // "cs4281_play_rate()" --
1494 //******************************************************************************
1495 static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
1496 {
1497         u32 DACSRvalue = 1;
1498
1499         // Based on the sample rate, program the DACSR register.
1500         if (playrate == 8000)
1501                 DACSRvalue = 5;
1502         if (playrate == 11025)
1503                 DACSRvalue = 4;
1504         else if (playrate == 22050)
1505                 DACSRvalue = 2;
1506         else if (playrate == 44100)
1507                 DACSRvalue = 1;
1508         else if ((playrate <= 48000) && (playrate >= 6023))
1509                 DACSRvalue = 24576000 / (playrate * 16);
1510         else if (playrate < 6023)
1511                 // Not allowed by open.
1512                 return;
1513         else if (playrate > 48000)
1514                 // Not allowed by open.
1515                 return;
1516         CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
1517                 "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n",
1518                         DACSRvalue, playrate));
1519         //  Write the 'sample rate select code'
1520         //  to the 'DAC Sample Rate' register.
1521         writel(DACSRvalue, card->pBA0 + BA0_DACSR);     // (744h)
1522 }
1523
1524 //******************************************************************************
1525 // "cs4281_record_rate()" -- Initialize the record sample rate converter.
1526 //******************************************************************************
1527 static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
1528 {
1529         u32 ADCSRvalue = 1;
1530
1531         //
1532         // Based on the sample rate, program the ADCSR register
1533         //
1534         if (outrate == 8000)
1535                 ADCSRvalue = 5;
1536         if (outrate == 11025)
1537                 ADCSRvalue = 4;
1538         else if (outrate == 22050)
1539                 ADCSRvalue = 2;
1540         else if (outrate == 44100)
1541                 ADCSRvalue = 1;
1542         else if ((outrate <= 48000) && (outrate >= 6023))
1543                 ADCSRvalue = 24576000 / (outrate * 16);
1544         else if (outrate < 6023) {
1545                 // Not allowed by open.
1546                 return;
1547         } else if (outrate > 48000) {
1548                 // Not allowed by open.
1549                 return;
1550         }
1551         CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
1552                 "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n",
1553                         ADCSRvalue, outrate));
1554         //  Write the 'sample rate select code
1555         //  to the 'ADC Sample Rate' register.
1556         writel(ADCSRvalue, card->pBA0 + BA0_ADCSR);     // (748h)
1557 }
1558
1559
1560
1561 static void stop_dac(struct cs4281_state *s)
1562 {
1563         unsigned long flags;
1564         unsigned temp1;
1565
1566         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():\n"));
1567         spin_lock_irqsave(&s->lock, flags);
1568         s->ena &= ~FMODE_WRITE;
1569         temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
1570         writel(temp1, s->pBA0 + BA0_DCR0);
1571
1572         spin_unlock_irqrestore(&s->lock, flags);
1573 }
1574
1575
1576 static void start_dac(struct cs4281_state *s)
1577 {
1578         unsigned long flags;
1579         unsigned temp1;
1580
1581         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+\n"));
1582         spin_lock_irqsave(&s->lock, flags);
1583         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
1584                                         (s->dma_dac.count > 0
1585                                         && s->dma_dac.ready))
1586 #ifndef NOT_CS4281_PM
1587         && (s->pm.flags & CS4281_PM_IDLE))
1588 #else
1589 )
1590 #endif
1591  {
1592                 s->ena |= FMODE_WRITE;
1593                 temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK;  // Clear DMA0 channel mask.
1594                 writel(temp1, s->pBA0 + BA0_DCR0);      // Start DMA'ing.
1595                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts.
1596
1597                 writel(7, s->pBA0 + BA0_PPRVC);
1598                 writel(7, s->pBA0 + BA0_PPLVC);
1599                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
1600                         "cs4281: start_dac(): writel 0x%x start dma\n", temp1));
1601
1602         }
1603         spin_unlock_irqrestore(&s->lock, flags);
1604         CS_DBGOUT(CS_FUNCTION, 3,
1605                   printk(KERN_INFO "cs4281: start_dac()-\n"));
1606 }
1607
1608
1609 static void stop_adc(struct cs4281_state *s)
1610 {
1611         unsigned long flags;
1612         unsigned temp1;
1613
1614         CS_DBGOUT(CS_FUNCTION, 3,
1615                   printk(KERN_INFO "cs4281: stop_adc()+\n"));
1616
1617         spin_lock_irqsave(&s->lock, flags);
1618         s->ena &= ~FMODE_READ;
1619
1620         if (s->conversion == 1) {
1621                 s->conversion = 0;
1622                 s->prop_adc.fmt = s->prop_adc.fmt_original;
1623         }
1624         temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
1625         writel(temp1, s->pBA0 + BA0_DCR1);
1626         spin_unlock_irqrestore(&s->lock, flags);
1627         CS_DBGOUT(CS_FUNCTION, 3,
1628                   printk(KERN_INFO "cs4281: stop_adc()-\n"));
1629 }
1630
1631
1632 static void start_adc(struct cs4281_state *s)
1633 {
1634         unsigned long flags;
1635         unsigned temp1;
1636
1637         CS_DBGOUT(CS_FUNCTION, 2,
1638                   printk(KERN_INFO "cs4281: start_adc()+\n"));
1639
1640         if (!(s->ena & FMODE_READ) &&
1641             (s->dma_adc.mapped || s->dma_adc.count <=
1642              (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
1643             && s->dma_adc.ready
1644 #ifndef NOT_CS4281_PM
1645         && (s->pm.flags & CS4281_PM_IDLE))
1646 #else
1647 )
1648 #endif
1649         {
1650                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
1651                         //
1652                         // now only use 16 bit capture, due to truncation issue
1653                         // in the chip, noticable distortion occurs.
1654                         // allocate buffer and then convert from 16 bit to
1655                         // 8 bit for the user buffer.
1656                         //
1657                         s->prop_adc.fmt_original = s->prop_adc.fmt;
1658                         if (s->prop_adc.fmt & AFMT_S8) {
1659                                 s->prop_adc.fmt &= ~AFMT_S8;
1660                                 s->prop_adc.fmt |= AFMT_S16_LE;
1661                         }
1662                         if (s->prop_adc.fmt & AFMT_U8) {
1663                                 s->prop_adc.fmt &= ~AFMT_U8;
1664                                 s->prop_adc.fmt |= AFMT_U16_LE;
1665                         }
1666                         //
1667                         // prog_dmabuf_adc performs a stop_adc() but that is
1668                         // ok since we really haven't started the DMA yet.
1669                         //
1670                         prog_codec(s, CS_TYPE_ADC);
1671
1672                         if (prog_dmabuf_adc(s) != 0) {
1673                                 CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
1674                                          "cs4281: start_adc(): error in prog_dmabuf_adc\n"));
1675                         }
1676                         s->conversion = 1;
1677                 }
1678                 spin_lock_irqsave(&s->lock, flags);
1679                 s->ena |= FMODE_READ;
1680                 temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK;  // Clear DMA1 channel mask bit.
1681                 writel(temp1, s->pBA0 + BA0_DCR1);      // Start recording
1682                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts.
1683                 spin_unlock_irqrestore(&s->lock, flags);
1684
1685                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
1686                          "cs4281: start_adc(): writel 0x%x \n", temp1));
1687         }
1688         CS_DBGOUT(CS_FUNCTION, 2,
1689                   printk(KERN_INFO "cs4281: start_adc()-\n"));
1690
1691 }
1692
1693
1694 // ---------------------------------------------------------------------
1695
1696 #define DMABUF_MINORDER 1       // ==> min buffer size = 8K.
1697
1698
1699 static void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1700 {
1701         struct page *map, *mapend;
1702
1703         if (db->rawbuf) {
1704                 // Undo prog_dmabuf()'s marking the pages as reserved
1705                 mapend =
1706                     virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -
1707                                  1);
1708                 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1709                         ClearPageReserved(map);
1710                 free_dmabuf(s, db);
1711         }
1712         if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1713                 // Undo prog_dmabuf()'s marking the pages as reserved
1714                 mapend =
1715                     virt_to_page(s->tmpbuff +
1716                                  (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1717                 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1718                         ClearPageReserved(map);
1719                 free_dmabuf2(s, db);
1720         }
1721         s->tmpbuff = NULL;
1722         db->rawbuf = NULL;
1723         db->mapped = db->ready = 0;
1724 }
1725
1726 static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1727 {
1728         int order;
1729         unsigned bytespersec, temp1;
1730         unsigned bufs, sample_shift = 0;
1731         struct page *map, *mapend;
1732         unsigned long df;
1733
1734         CS_DBGOUT(CS_FUNCTION, 2,
1735                   printk(KERN_INFO "cs4281: prog_dmabuf()+\n"));
1736         db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
1737             db->endcleared = db->blocks = db->wakeup = db->underrun = 0;
1738 /*
1739 * check for order within limits, but do not overwrite value, check
1740 * later for a fractional defaultorder (i.e. 100+).
1741 */
1742         if((defaultorder > 0) && (defaultorder < 12))
1743                 df = defaultorder;
1744         else
1745                 df = 1;
1746
1747         if (!db->rawbuf) {
1748                 db->ready = db->mapped = 0;
1749                 for (order = df; order >= DMABUF_MINORDER; order--)
1750                         if ( (db->rawbuf = (void *) pci_alloc_consistent(
1751                                 s->pcidev, PAGE_SIZE << order, &db-> dmaaddr)))
1752                                     break;
1753                 if (!db->rawbuf) {
1754                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1755                                 "cs4281: prog_dmabuf(): unable to allocate rawbuf\n"));
1756                         return -ENOMEM;
1757                 }
1758                 db->buforder = order;
1759                 // Now mark the pages as reserved; otherwise the
1760                 // remap_pfn_range() in cs4281_mmap doesn't work.
1761                 // 1. get index to last page in mem_map array for rawbuf.
1762                 mapend = virt_to_page(db->rawbuf +
1763                         (PAGE_SIZE << db->buforder) - 1);
1764
1765                 // 2. mark each physical page in range as 'reserved'.
1766                 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1767                         SetPageReserved(map);
1768         }
1769         if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1770                 for (order = df; order >= DMABUF_MINORDER;
1771                      order--)
1772                         if ( (s->tmpbuff = (void *) pci_alloc_consistent(
1773                                         s->pcidev, PAGE_SIZE << order,
1774                                         &s->dmaaddr_tmpbuff)))
1775                                     break;
1776                 if (!s->tmpbuff) {
1777                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1778                                 "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n"));
1779                         return -ENOMEM;
1780                 }
1781                 s->buforder_tmpbuff = order;
1782                 // Now mark the pages as reserved; otherwise the
1783                 // remap_pfn_range() in cs4281_mmap doesn't work.
1784                 // 1. get index to last page in mem_map array for rawbuf.
1785                 mapend = virt_to_page(s->tmpbuff +
1786                                 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1787
1788                 // 2. mark each physical page in range as 'reserved'.
1789                 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1790                         SetPageReserved(map);
1791         }
1792         if (db->type == CS_TYPE_DAC) {
1793                 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1794                         sample_shift++;
1795                 if (s->prop_dac.channels > 1)
1796                         sample_shift++;
1797                 bytespersec = s->prop_dac.rate << sample_shift;
1798         } else                  // CS_TYPE_ADC
1799         {
1800                 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1801                         sample_shift++;
1802                 if (s->prop_adc.channels > 1)
1803                         sample_shift++;
1804                 bytespersec = s->prop_adc.rate << sample_shift;
1805         }
1806         bufs = PAGE_SIZE << db->buforder;
1807
1808 /*
1809 * added fractional "defaultorder" inputs. if >100 then use
1810 * defaultorder-100 as power of 2 for the buffer size. example:
1811 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
1812 */
1813         if(defaultorder >= 100)
1814         {
1815                 bufs = 1 << (defaultorder-100);
1816         }
1817
1818 #define INTERRUPT_RATE_MS       100     // Interrupt rate in milliseconds.
1819         db->numfrag = 2;
1820 /*
1821 * Nominal frag size(bytes/interrupt)
1822 */
1823         temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS);
1824         db->fragshift = 8;      // Min 256 bytes.
1825         while (1 << db->fragshift < temp1)      // Calc power of 2 frag size.
1826                 db->fragshift += 1;
1827         db->fragsize = 1 << db->fragshift;
1828         db->dmasize = db->fragsize * 2;
1829         db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1830
1831 // If the calculated size is larger than the allocated
1832 //  buffer, divide the allocated buffer into 2 fragments.
1833         if (db->dmasize > bufs) {
1834
1835                 db->numfrag = 2;        // Two fragments.
1836                 db->fragsize = bufs >> 1;       // Each 1/2 the alloc'ed buffer.
1837                 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1838                 db->dmasize = bufs;     // Use all the alloc'ed buffer.
1839
1840                 db->fragshift = 0;      // Calculate 'fragshift'.
1841                 temp1 = db->fragsize;   // update_ptr() uses it
1842                 while ((temp1 >>= 1) > 1)       // to calc 'total-bytes'
1843                         db->fragshift += 1;     // returned in DSP_GETI/OPTR.
1844         }
1845         CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO
1846                 "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n",
1847                         db->numfrag, db->fragsize, db->fragsamples,
1848                         db->fragshift, bufs,
1849                         (db->type == CS_TYPE_DAC) ? s->prop_dac.fmt :
1850                                 s->prop_adc.fmt,
1851                         (db->type == CS_TYPE_DAC) ? s->prop_dac.channels :
1852                                 s->prop_adc.channels));
1853         CS_DBGOUT(CS_FUNCTION, 2,
1854                   printk(KERN_INFO "cs4281: prog_dmabuf()-\n"));
1855         return 0;
1856 }
1857
1858
1859 static int prog_dmabuf_adc(struct cs4281_state *s)
1860 {
1861         unsigned long va;
1862         unsigned count;
1863         int c;
1864         stop_adc(s);
1865         s->dma_adc.type = CS_TYPE_ADC;
1866         if ((c = prog_dmabuf(s, &s->dma_adc)))
1867                 return c;
1868
1869         if (s->dma_adc.rawbuf) {
1870                 memset(s->dma_adc.rawbuf,
1871                        (s->prop_adc.
1872                         fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1873                        s->dma_adc.dmasize);
1874         }
1875         if (s->tmpbuff) {
1876                 memset(s->tmpbuff,
1877                        (s->prop_adc.
1878                         fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1879                        PAGE_SIZE << s->buforder_tmpbuff);
1880         }
1881
1882         va = virt_to_bus(s->dma_adc.rawbuf);
1883
1884         count = s->dma_adc.dmasize;
1885
1886         if (s->prop_adc.
1887             fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1888                     count /= 2; // 16-bit.
1889
1890         if (s->prop_adc.channels > 1)
1891                 count /= 2;     // Assume stereo.
1892
1893         CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
1894                 "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n",
1895                         count, (unsigned) va));
1896
1897         writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
1898         writel(count - 1, s->pBA0 + BA0_DBC1);  // Set count.
1899         s->dma_adc.ready = 1;
1900         return 0;
1901 }
1902
1903
1904 static int prog_dmabuf_dac(struct cs4281_state *s)
1905 {
1906         unsigned long va;
1907         unsigned count;
1908         int c;
1909         stop_dac(s);
1910         s->dma_dac.type = CS_TYPE_DAC;
1911         if ((c = prog_dmabuf(s, &s->dma_dac)))
1912                 return c;
1913         memset(s->dma_dac.rawbuf,
1914                (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1915                s->dma_dac.dmasize);
1916
1917         va = virt_to_bus(s->dma_dac.rawbuf);
1918
1919         count = s->dma_dac.dmasize;
1920         if (s->prop_dac.
1921             fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1922                     count /= 2; // 16-bit.
1923
1924         if (s->prop_dac.channels > 1)
1925                 count /= 2;     // Assume stereo.
1926
1927         writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
1928         writel(count - 1, s->pBA0 + BA0_DBC0);  // Set count.
1929
1930         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
1931                 "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n",
1932                         count, (unsigned) va));
1933
1934         s->dma_dac.ready = 1;
1935         return 0;
1936 }
1937
1938
1939 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
1940                           unsigned len, unsigned char c)
1941 {
1942         if (bptr + len > bsize) {
1943                 unsigned x = bsize - bptr;
1944                 memset(((char *) buf) + bptr, c, x);
1945                 bptr = 0;
1946                 len -= x;
1947         }
1948         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1949                 "cs4281: clear_advance(): memset %d at %p for %d size \n",
1950                         (unsigned)c, ((char *) buf) + bptr, len));
1951         memset(((char *) buf) + bptr, c, len);
1952 }
1953
1954
1955
1956 // call with spinlock held!
1957 static void cs4281_update_ptr(struct cs4281_state *s, int intflag)
1958 {
1959         int diff;
1960         unsigned hwptr, va;
1961
1962         // update ADC pointer
1963         if (s->ena & FMODE_READ) {
1964                 hwptr = readl(s->pBA0 + BA0_DCA1);      // Read capture DMA address.
1965                 va = virt_to_bus(s->dma_adc.rawbuf);
1966                 hwptr -= (unsigned) va;
1967                 diff =
1968                     (s->dma_adc.dmasize + hwptr -
1969                      s->dma_adc.hwptr) % s->dma_adc.dmasize;
1970                 s->dma_adc.hwptr = hwptr;
1971                 s->dma_adc.total_bytes += diff;
1972                 s->dma_adc.count += diff;
1973                 if (s->dma_adc.count > s->dma_adc.dmasize)
1974                         s->dma_adc.count = s->dma_adc.dmasize;
1975                 if (s->dma_adc.mapped) {
1976                         if (s->dma_adc.count >=
1977                             (signed) s->dma_adc.fragsize) wake_up(&s->
1978                                                                   dma_adc.
1979                                                                   wait);
1980                 } else {
1981                         if (s->dma_adc.count > 0)
1982                                 wake_up(&s->dma_adc.wait);
1983                 }
1984                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1985                         "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n",
1986                                 s, s->dma_adc.hwptr, s->dma_adc.total_bytes, s->dma_adc.count));
1987         }
1988         // update DAC pointer
1989         //
1990         // check for end of buffer, means that we are going to wait for another interrupt
1991         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1992         //
1993         if (s->ena & FMODE_WRITE) {
1994                 hwptr = readl(s->pBA0 + BA0_DCA0);      // Read play DMA address.
1995                 va = virt_to_bus(s->dma_dac.rawbuf);
1996                 hwptr -= (unsigned) va;
1997                 diff = (s->dma_dac.dmasize + hwptr -
1998                      s->dma_dac.hwptr) % s->dma_dac.dmasize;
1999                 s->dma_dac.hwptr = hwptr;
2000                 s->dma_dac.total_bytes += diff;
2001                 if (s->dma_dac.mapped) {
2002                         s->dma_dac.count += diff;
2003                         if (s->dma_dac.count >= s->dma_dac.fragsize) {
2004                                 s->dma_dac.wakeup = 1;
2005                                 wake_up(&s->dma_dac.wait);
2006                                 if (s->dma_dac.count > s->dma_dac.dmasize)
2007                                         s->dma_dac.count &=
2008                                             s->dma_dac.dmasize - 1;
2009                         }
2010                 } else {
2011                         s->dma_dac.count -= diff;
2012                         if (s->dma_dac.count <= 0) {
2013                                 //
2014                                 // fill with silence, and do not shut down the DAC.
2015                                 // Continue to play silence until the _release.
2016                                 //
2017                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
2018                                         "cs4281: cs4281_update_ptr(): memset %d at %p for %d size \n",
2019                                                 (unsigned)(s->prop_dac.fmt &
2020                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
2021                                                 s->dma_dac.rawbuf, s->dma_dac.dmasize));
2022                                 memset(s->dma_dac.rawbuf,
2023                                        (s->prop_dac.
2024                                         fmt & (AFMT_U8 | AFMT_U16_LE)) ?
2025                                        0x80 : 0, s->dma_dac.dmasize);
2026                                 if (s->dma_dac.count < 0) {
2027                                         s->dma_dac.underrun = 1;
2028                                         s->dma_dac.count = 0;
2029                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
2030                                          "cs4281: cs4281_update_ptr(): underrun\n"));
2031                                 }
2032                         } else if (s->dma_dac.count <=
2033                                    (signed) s->dma_dac.fragsize
2034                                    && !s->dma_dac.endcleared) {
2035                                 clear_advance(s->dma_dac.rawbuf,
2036                                               s->dma_dac.dmasize,
2037                                               s->dma_dac.swptr,
2038                                               s->dma_dac.fragsize,
2039                                               (s->prop_dac.
2040                                                fmt & (AFMT_U8 |
2041                                                       AFMT_U16_LE)) ? 0x80
2042                                               : 0);
2043                                 s->dma_dac.endcleared = 1;
2044                         }
2045                         if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) ||
2046                                 intflag)
2047                         {
2048                                 wake_up(&s->dma_dac.wait);
2049                         }
2050                 }
2051                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
2052                         "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n",
2053                                 s, s->dma_dac.hwptr, s->dma_dac.total_bytes, s->dma_dac.count));
2054         }
2055 }
2056
2057
2058 // ---------------------------------------------------------------------
2059
2060 static void prog_codec(struct cs4281_state *s, unsigned type)
2061 {
2062         unsigned long flags;
2063         unsigned temp1, format;
2064
2065         CS_DBGOUT(CS_FUNCTION, 2,
2066                   printk(KERN_INFO "cs4281: prog_codec()+ \n"));
2067
2068         spin_lock_irqsave(&s->lock, flags);
2069         if (type == CS_TYPE_ADC) {
2070                 temp1 = readl(s->pBA0 + BA0_DCR1);
2071                 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1);   // Stop capture DMA, if active.
2072
2073                 // program sampling rates
2074                 // Note, for CS4281, capture & play rates can be set independently.
2075                 cs4281_record_rate(s, s->prop_adc.rate);
2076
2077                 // program ADC parameters
2078                 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
2079                 if (s->prop_adc.
2080                     fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) {    // 16-bit
2081                         if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE))      // Big-endian?
2082                                 format |= DMRn_BEND;
2083                         if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2084                                 format |= DMRn_USIGN;   // Unsigned.
2085                 } else
2086                         format |= DMRn_SIZE8 | DMRn_USIGN;      // 8-bit, unsigned
2087                 if (s->prop_adc.channels < 2)
2088                         format |= DMRn_MONO;
2089
2090                 writel(format, s->pBA0 + BA0_DMR1);
2091
2092                 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2093                         "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n",
2094                                 (format & DMRn_SIZE8) ? "8" : "16",
2095                                 (format & DMRn_USIGN) ?  "Unsigned" : "Signed",
2096                                 (format & DMRn_MONO) ? "Mono" : "Stereo",
2097                                 s->prop_adc.rate, format));
2098
2099                 s->ena &= ~FMODE_READ;  // not capturing data yet
2100         }
2101
2102
2103         if (type == CS_TYPE_DAC) {
2104                 temp1 = readl(s->pBA0 + BA0_DCR0);
2105                 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0);   // Stop play DMA, if active.
2106
2107                 // program sampling rates
2108                 // Note, for CS4281, capture & play rates can be set independently.
2109                 cs4281_play_rate(s, s->prop_dac.rate);
2110
2111                 // program DAC parameters
2112                 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
2113                 if (s->prop_dac.
2114                     fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) {    // 16-bit
2115                         if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
2116                                 format |= DMRn_BEND;    // Big Endian.
2117                         if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2118                                 format |= DMRn_USIGN;   // Unsigned.
2119                 } else
2120                         format |= DMRn_SIZE8 | DMRn_USIGN;      // 8-bit, unsigned
2121
2122                 if (s->prop_dac.channels < 2)
2123                         format |= DMRn_MONO;
2124
2125                 writel(format, s->pBA0 + BA0_DMR0);
2126
2127
2128                 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2129                         "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n",
2130                                 (format & DMRn_SIZE8) ? "8" : "16",
2131                                 (format & DMRn_USIGN) ?  "Unsigned" : "Signed",
2132                                 (format & DMRn_MONO) ? "Mono" : "Stereo",
2133                                 s->prop_dac.rate, format));
2134
2135                 s->ena &= ~FMODE_WRITE; // not capturing data yet
2136
2137         }
2138         spin_unlock_irqrestore(&s->lock, flags);
2139         CS_DBGOUT(CS_FUNCTION, 2,
2140                   printk(KERN_INFO "cs4281: prog_codec()- \n"));
2141 }
2142
2143
2144 static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
2145                        unsigned long arg)
2146 {
2147         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
2148         // Value of array member is recording source Device ID Mask.
2149         static const unsigned int mixer_src[8] = {
2150                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
2151                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
2152         };
2153         void __user *argp = (void __user *)arg;
2154
2155         // Index of mixtable1[] member is Device ID
2156         // and must be <= SOUND_MIXER_NRDEVICES.
2157         // Value of array member is index into s->mix.vol[]
2158         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
2159                 [SOUND_MIXER_PCM] = 1,  // voice
2160                 [SOUND_MIXER_LINE1] = 2,        // AUX
2161                 [SOUND_MIXER_CD] = 3,   // CD
2162                 [SOUND_MIXER_LINE] = 4, // Line
2163                 [SOUND_MIXER_SYNTH] = 5,        // FM
2164                 [SOUND_MIXER_MIC] = 6,  // Mic
2165                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
2166                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
2167                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
2168         };
2169
2170
2171         static const unsigned mixreg[] = {
2172                 BA0_AC97_PCM_OUT_VOLUME,
2173                 BA0_AC97_AUX_VOLUME,
2174                 BA0_AC97_CD_VOLUME,
2175                 BA0_AC97_LINE_IN_VOLUME
2176         };
2177         unsigned char l, r, rl, rr, vidx;
2178         unsigned char attentbl[11] =
2179             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
2180         unsigned temp1;
2181         int i, val;
2182
2183         VALIDATE_STATE(s);
2184         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
2185                  "cs4281: mixer_ioctl(): s=%p cmd=0x%.8x\n", s, cmd));
2186 #if CSDEBUG
2187         cs_printioctl(cmd);
2188 #endif
2189 #if CSDEBUG_INTERFACE
2190
2191         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
2192             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
2193             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
2194             (cmd == SOUND_MIXER_CS_SETDBGLEVEL) ||
2195             (cmd == SOUND_MIXER_CS_APM))
2196         {
2197                 switch (cmd) {
2198
2199                 case SOUND_MIXER_CS_GETDBGMASK:
2200                         return put_user(cs_debugmask,
2201                                         (unsigned long __user *) argp);
2202
2203                 case SOUND_MIXER_CS_GETDBGLEVEL:
2204                         return put_user(cs_debuglevel,
2205                                         (unsigned long __user *) argp);
2206
2207                 case SOUND_MIXER_CS_SETDBGMASK:
2208                         if (get_user(val, (unsigned long __user *) argp))
2209                                 return -EFAULT;
2210                         cs_debugmask = val;
2211                         return 0;
2212
2213                 case SOUND_MIXER_CS_SETDBGLEVEL:
2214                         if (get_user(val, (unsigned long __user *) argp))
2215                                 return -EFAULT;
2216                         cs_debuglevel = val;
2217                         return 0;
2218 #ifndef NOT_CS4281_PM
2219                 case SOUND_MIXER_CS_APM:
2220                         if (get_user(val, (unsigned long __user *) argp))
2221                                 return -EFAULT;
2222                         if(val == CS_IOCTL_CMD_SUSPEND)
2223                                 cs4281_suspend(s);
2224                         else if(val == CS_IOCTL_CMD_RESUME)
2225                                 cs4281_resume(s);
2226                         else
2227                         {
2228                                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2229                                     "cs4281: mixer_ioctl(): invalid APM cmd (%d)\n",
2230                                         val));
2231                         }
2232                         return 0;
2233 #endif
2234                 default:
2235                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2236                                 "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n"));
2237                         return 0;
2238                 }
2239         }
2240 #endif
2241
2242         if (cmd == SOUND_MIXER_PRIVATE1) {
2243                 // enable/disable/query mixer preamp
2244                 if (get_user(val, (int __user *) argp))
2245                         return -EFAULT;
2246                 if (val != -1) {
2247                         cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2248                         temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
2249                         cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2250                 }
2251                 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2252                 val = (temp1 & 0x40) ? 1 : 0;
2253                 return put_user(val, (int __user *) argp);
2254         }
2255         if (cmd == SOUND_MIXER_PRIVATE2) {
2256                 // enable/disable/query spatializer
2257                 if (get_user(val, (int __user *)argp))
2258                         return -EFAULT;
2259                 if (val != -1) {
2260                         temp1 = (val & 0x3f) >> 2;
2261                         cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
2262                         cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2263                                          &temp1);
2264                         cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2265                                           temp1 | 0x2000);
2266                 }
2267                 cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
2268                 return put_user((temp1 << 2) | 3, (int __user *)argp);
2269         }
2270         if (cmd == SOUND_MIXER_INFO) {
2271                 mixer_info info;
2272                 strlcpy(info.id, "CS4281", sizeof(info.id));
2273                 strlcpy(info.name, "Crystal CS4281", sizeof(info.name));
2274                 info.modify_counter = s->mix.modcnt;
2275                 if (copy_to_user(argp, &info, sizeof(info)))
2276                         return -EFAULT;
2277                 return 0;
2278         }
2279         if (cmd == SOUND_OLD_MIXER_INFO) {
2280                 _old_mixer_info info;
2281                 strlcpy(info.id, "CS4281", sizeof(info.id));
2282                 strlcpy(info.name, "Crystal CS4281", sizeof(info.name));
2283                 if (copy_to_user(argp, &info, sizeof(info)))
2284                         return -EFAULT;
2285                 return 0;
2286         }
2287         if (cmd == OSS_GETVERSION)
2288                 return put_user(SOUND_VERSION, (int __user *) argp);
2289
2290         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
2291                 return -EINVAL;
2292
2293         // If ioctl has only the SIOC_READ bit(bit 31)
2294         // on, process the only-read commands.
2295         if (_SIOC_DIR(cmd) == _SIOC_READ) {
2296                 switch (_IOC_NR(cmd)) {
2297                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
2298                         cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT, &temp1);
2299                         return put_user(mixer_src[temp1&7], (int __user *)argp);
2300
2301                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
2302                         return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2303                                         SOUND_MASK_CD | SOUND_MASK_LINE |
2304                                         SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2305                                         SOUND_MASK_VOLUME |
2306                                         SOUND_MASK_RECLEV |
2307                                         SOUND_MASK_SPEAKER, (int __user *)argp);
2308
2309                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
2310                         return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC |
2311                                         SOUND_MASK_CD | SOUND_MASK_VOLUME |
2312                                         SOUND_MASK_LINE1, (int __user *) argp);
2313
2314                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
2315                         return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2316                                         SOUND_MASK_CD | SOUND_MASK_LINE |
2317                                         SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2318                                         SOUND_MASK_VOLUME |
2319                                         SOUND_MASK_RECLEV, (int __user *)argp);
2320
2321                 case SOUND_MIXER_CAPS:
2322                         return put_user(SOUND_CAP_EXCL_INPUT, (int __user *)argp);
2323
2324                 default:
2325                         i = _IOC_NR(cmd);
2326                         if (i >= SOUND_MIXER_NRDEVICES
2327                             || !(vidx = mixtable1[i]))
2328                                 return -EINVAL;
2329                         return put_user(s->mix.vol[vidx - 1], (int __user *)argp);
2330                 }
2331         }
2332         // If ioctl doesn't have both the SIOC_READ and
2333         // the SIOC_WRITE bit set, return invalid.
2334         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
2335                 return -EINVAL;
2336
2337         // Increment the count of volume writes.
2338         s->mix.modcnt++;
2339
2340         // Isolate the command; it must be a write.
2341         switch (_IOC_NR(cmd)) {
2342
2343         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
2344                 if (get_user(val, (int __user *)argp))
2345                         return -EFAULT;
2346                 i = hweight32(val);     // i = # bits on in val.
2347                 if (i != 1)     // One & only 1 bit must be on.
2348                         return 0;
2349                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
2350                         if (val == mixer_src[i]) {
2351                                 temp1 = (i << 8) | i;
2352                                 cs4281_write_ac97(s,
2353                                                   BA0_AC97_RECORD_SELECT,
2354                                                   temp1);
2355                                 return 0;
2356                         }
2357                 }
2358                 return 0;
2359
2360         case SOUND_MIXER_VOLUME:
2361                 if (get_user(val, (int __user *)argp))
2362                         return -EFAULT;
2363                 l = val & 0xff;
2364                 if (l > 100)
2365                         l = 100;        // Max soundcard.h vol is 100.
2366                 if (l < 6) {
2367                         rl = 63;
2368                         l = 0;
2369                 } else
2370                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
2371
2372                 r = (val >> 8) & 0xff;
2373                 if (r > 100)
2374                         r = 100;        // Max right volume is 100, too
2375                 if (r < 6) {
2376                         rr = 63;
2377                         r = 0;
2378                 } else
2379                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
2380
2381                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
2382                         temp1 = 0x8000; //  turn on the mute bit.
2383                 else
2384                         temp1 = 0;
2385
2386                 temp1 |= (rl << 8) | rr;
2387
2388                 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
2389                 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
2390
2391 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2392                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
2393 #else
2394                 s->mix.vol[8] = val;
2395 #endif
2396                 return put_user(s->mix.vol[8], (int __user *)argp);
2397
2398         case SOUND_MIXER_SPEAKER:
2399                 if (get_user(val, (int __user *)argp))
2400                         return -EFAULT;
2401                 l = val & 0xff;
2402                 if (l > 100)
2403                         l = 100;
2404                 if (l < 3) {
2405                         rl = 0;
2406                         l = 0;
2407                 } else {
2408                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
2409                         l = (rl * 13 + 5) / 2;
2410                 }
2411
2412                 if (rl < 3) {
2413                         temp1 = 0x8000;
2414                         rl = 0;
2415                 } else
2416                         temp1 = 0;
2417                 rl = 15 - rl;   // Convert volume to attenuation.
2418                 temp1 |= rl << 1;
2419                 cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
2420
2421 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2422                 s->mix.vol[6] = l << 8;
2423 #else
2424                 s->mix.vol[6] = val;
2425 #endif
2426                 return put_user(s->mix.vol[6], (int __user *)argp);
2427
2428         case SOUND_MIXER_RECLEV:
2429                 if (get_user(val, (int __user *)argp))
2430                         return -EFAULT;
2431                 l = val & 0xff;
2432                 if (l > 100)
2433                         l = 100;
2434                 r = (val >> 8) & 0xff;
2435                 if (r > 100)
2436                         r = 100;
2437                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
2438                 rr = (r * 2 - 5) / 13;
2439                 if (rl < 3 && rr < 3)
2440                         temp1 = 0x8000;
2441                 else
2442                         temp1 = 0;
2443
2444                 temp1 = temp1 | (rl << 8) | rr;
2445                 cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1);
2446
2447 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2448                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
2449 #else
2450                 s->mix.vol[7] = val;
2451 #endif
2452                 return put_user(s->mix.vol[7], (int __user *)argp);
2453
2454         case SOUND_MIXER_MIC:
2455                 if (get_user(val, (int __user *)argp))
2456                         return -EFAULT;
2457                 l = val & 0xff;
2458                 if (l > 100)
2459                         l = 100;
2460                 if (l < 1) {
2461                         l = 0;
2462                         rl = 0;
2463                 } else {
2464                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
2465                         l = (rl * 16 + 4) / 5;
2466                 }
2467                 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2468                 temp1 &= 0x40;  // Isolate 20db gain bit.
2469                 if (rl < 3) {
2470                         temp1 |= 0x8000;
2471                         rl = 0;
2472                 }
2473                 rl = 31 - rl;   // Convert volume to attenuation.
2474                 temp1 |= rl;
2475                 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2476
2477 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2478                 s->mix.vol[5] = val << 8;
2479 #else
2480                 s->mix.vol[5] = val;
2481 #endif
2482                 return put_user(s->mix.vol[5], (int __user *)argp);
2483
2484
2485         case SOUND_MIXER_SYNTH:
2486                 if (get_user(val, (int __user *)argp))
2487                         return -EFAULT;
2488                 l = val & 0xff;
2489                 if (l > 100)
2490                         l = 100;
2491                 if (get_user(val, (int __user *)argp))
2492                         return -EFAULT;
2493                 r = (val >> 8) & 0xff;
2494                 if (r > 100)
2495                         r = 100;
2496                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
2497                 rr = (r * 2 - 11) / 3;
2498                 if (rl < 3)     // If l is low, turn on
2499                         temp1 = 0x0080; //  the mute bit.
2500                 else
2501                         temp1 = 0;
2502
2503                 rl = 63 - rl;   // Convert vol to attenuation.
2504                 writel(temp1 | rl, s->pBA0 + BA0_FMLVC);
2505                 if (rr < 3)     //  If rr is low, turn on
2506                         temp1 = 0x0080; //   the mute bit.
2507                 else
2508                         temp1 = 0;
2509                 rr = 63 - rr;   // Convert vol to attenuation.
2510                 writel(temp1 | rr, s->pBA0 + BA0_FMRVC);
2511
2512 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2513                 s->mix.vol[4] = (r << 8) | l;
2514 #else
2515                 s->mix.vol[4] = val;
2516 #endif
2517                 return put_user(s->mix.vol[4], (int __user *)argp);
2518
2519
2520         default:
2521                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2522                         "cs4281: mixer_ioctl(): default\n"));
2523
2524                 i = _IOC_NR(cmd);
2525                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
2526                         return -EINVAL;
2527                 if (get_user(val, (int __user *)argp))
2528                         return -EFAULT;
2529                 l = val & 0xff;
2530                 if (l > 100)
2531                         l = 100;
2532                 if (l < 1) {
2533                         l = 0;
2534                         rl = 31;
2535                 } else
2536                         rl = (attentbl[(l * 10) / 100]) >> 1;
2537
2538                 r = (val >> 8) & 0xff;
2539                 if (r > 100)
2540                         r = 100;
2541                 if (r < 1) {
2542                         r = 0;
2543                         rr = 31;
2544                 } else
2545                         rr = (attentbl[(r * 10) / 100]) >> 1;
2546                 if ((rl > 30) && (rr > 30))
2547                         temp1 = 0x8000;
2548                 else
2549                         temp1 = 0;
2550                 temp1 = temp1 | (rl << 8) | rr;
2551                 cs4281_write_ac97(s, mixreg[vidx - 1], temp1);
2552
2553 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2554                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
2555 #else
2556                 s->mix.vol[vidx - 1] = val;
2557 #endif
2558 #ifndef NOT_CS4281_PM
2559                 CS_DBGOUT(CS_PM, 9, printk(KERN_INFO
2560                         "write ac97 mixreg[%d]=0x%x mix.vol[]=0x%x\n",
2561                                 vidx-1,temp1,s->mix.vol[vidx-1]));
2562 #endif
2563                 return put_user(s->mix.vol[vidx - 1], (int __user *)argp);
2564         }
2565 }
2566
2567
2568 // ---------------------------------------------------------------------
2569
2570 static int cs4281_open_mixdev(struct inode *inode, struct file *file)
2571 {
2572         unsigned int minor = iminor(inode);
2573         struct cs4281_state *s=NULL;
2574         struct list_head *entry;
2575
2576         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2577                   printk(KERN_INFO "cs4281: cs4281_open_mixdev()+\n"));
2578
2579         list_for_each(entry, &cs4281_devs)
2580         {
2581                 s = list_entry(entry, struct cs4281_state, list);
2582                 if(s->dev_mixer == minor)
2583                         break;
2584         }
2585         if (!s)
2586         {
2587                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
2588                         printk(KERN_INFO "cs4281: cs4281_open_mixdev()- -ENODEV\n"));
2589                 return -ENODEV;
2590         }
2591         VALIDATE_STATE(s);
2592         file->private_data = s;
2593
2594         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2595                   printk(KERN_INFO "cs4281: cs4281_open_mixdev()- 0\n"));
2596
2597         return nonseekable_open(inode, file);
2598 }
2599
2600
2601 static int cs4281_release_mixdev(struct inode *inode, struct file *file)
2602 {
2603         struct cs4281_state *s =
2604             (struct cs4281_state *) file->private_data;
2605
2606         VALIDATE_STATE(s);
2607         return 0;
2608 }
2609
2610
2611 static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
2612                                unsigned int cmd, unsigned long arg)
2613 {
2614         return mixer_ioctl((struct cs4281_state *) file->private_data, cmd,
2615                            arg);
2616 }
2617
2618
2619 // ******************************************************************************************
2620 //   Mixer file operations struct.
2621 // ******************************************************************************************
2622 static /*const */ struct file_operations cs4281_mixer_fops = {
2623         .owner   = THIS_MODULE,
2624         .llseek  = no_llseek,
2625         .ioctl   = cs4281_ioctl_mixdev,
2626         .open    = cs4281_open_mixdev,
2627         .release = cs4281_release_mixdev,
2628 };
2629
2630 // ---------------------------------------------------------------------
2631
2632
2633 static int drain_adc(struct cs4281_state *s, int nonblock)
2634 {
2635         DECLARE_WAITQUEUE(wait, current);
2636         unsigned long flags;
2637         int count;
2638         unsigned tmo;
2639
2640         if (s->dma_adc.mapped)
2641                 return 0;
2642         add_wait_queue(&s->dma_adc.wait, &wait);
2643         for (;;) {
2644                 set_current_state(TASK_INTERRUPTIBLE);
2645                 spin_lock_irqsave(&s->lock, flags);
2646                 count = s->dma_adc.count;
2647                 CS_DBGOUT(CS_FUNCTION, 2,
2648                           printk(KERN_INFO "cs4281: drain_adc() %d\n", count));
2649                 spin_unlock_irqrestore(&s->lock, flags);
2650                 if (count <= 0) {
2651                         CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2652                                  "cs4281: drain_adc() count<0\n"));
2653                         break;
2654                 }
2655                 if (signal_pending(current))
2656                         break;
2657                 if (nonblock) {
2658                         remove_wait_queue(&s->dma_adc.wait, &wait);
2659                         current->state = TASK_RUNNING;
2660                         return -EBUSY;
2661                 }
2662                 tmo =
2663                     3 * HZ * (count +
2664                               s->dma_adc.fragsize) / 2 / s->prop_adc.rate;
2665                 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2666                         tmo >>= 1;
2667                 if (s->prop_adc.channels > 1)
2668                         tmo >>= 1;
2669                 if (!schedule_timeout(tmo + 1))
2670                         printk(KERN_DEBUG "cs4281: dma timed out??\n");
2671         }
2672         remove_wait_queue(&s->dma_adc.wait, &wait);
2673         current->state = TASK_RUNNING;
2674         if (signal_pending(current))
2675                 return -ERESTARTSYS;
2676         return 0;
2677 }
2678
2679 static int drain_dac(struct cs4281_state *s, int nonblock)
2680 {
2681         DECLARE_WAITQUEUE(wait, current);
2682         unsigned long flags;
2683         int count;
2684         unsigned tmo;
2685
2686         if (s->dma_dac.mapped)
2687                 return 0;
2688         add_wait_queue(&s->dma_dac.wait, &wait);
2689         for (;;) {
2690                 set_current_state(TASK_INTERRUPTIBLE);
2691                 spin_lock_irqsave(&s->lock, flags);
2692                 count = s->dma_dac.count;
2693                 spin_unlock_irqrestore(&s->lock, flags);
2694                 if (count <= 0)
2695                         break;
2696                 if (signal_pending(current))
2697                         break;
2698                 if (nonblock) {
2699                         remove_wait_queue(&s->dma_dac.wait, &wait);
2700                         current->state = TASK_RUNNING;
2701                         return -EBUSY;
2702                 }
2703                 tmo =
2704                     3 * HZ * (count +
2705                               s->dma_dac.fragsize) / 2 / s->prop_dac.rate;
2706                 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2707                         tmo >>= 1;
2708                 if (s->prop_dac.channels > 1)
2709                         tmo >>= 1;
2710                 if (!schedule_timeout(tmo + 1))
2711                         printk(KERN_DEBUG "cs4281: dma timed out??\n");
2712         }
2713         remove_wait_queue(&s->dma_dac.wait, &wait);
2714         current->state = TASK_RUNNING;
2715         if (signal_pending(current))
2716                 return -ERESTARTSYS;
2717         return 0;
2718 }
2719
2720 //****************************************************************************
2721 //
2722 // CopySamples copies 16-bit stereo samples from the source to the
2723 // destination, possibly converting down to either 8-bit or mono or both.
2724 // count specifies the number of output bytes to write.
2725 //
2726 //  Arguments:
2727 //
2728 //  dst             - Pointer to a destination buffer.
2729 //  src             - Pointer to a source buffer
2730 //  count           - The number of bytes to copy into the destination buffer.
2731 //  iChannels       - Stereo - 2
2732 //                    Mono   - 1
2733 //  fmt             - AFMT_xxx (soundcard.h formats)
2734 //
2735 // NOTES: only call this routine for conversion to 8bit from 16bit
2736 //
2737 //****************************************************************************
2738 static void CopySamples(char *dst, char *src, int count, int iChannels,
2739                         unsigned fmt)
2740 {
2741
2742         unsigned short *psSrc;
2743         long lAudioSample;
2744
2745         CS_DBGOUT(CS_FUNCTION, 2,
2746                   printk(KERN_INFO "cs4281: CopySamples()+ "));
2747         CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2748                  " dst=%p src=%p count=%d iChannels=%d fmt=0x%x\n",
2749                          dst, src, (unsigned) count, (unsigned) iChannels, (unsigned) fmt));
2750
2751         // Gershwin does format conversion in hardware so normally
2752         // we don't do any host based coversion. The data formatter
2753         // truncates 16 bit data to 8 bit and that causes some hiss.
2754         // We have already forced the HW to do 16 bit sampling and
2755         // 2 channel so that we can use software to round instead
2756         // of truncate
2757
2758         //
2759         // See if the data should be output as 8-bit unsigned stereo.
2760         // or if the data should be output at 8-bit unsigned mono.
2761         //
2762         if ( ((iChannels == 2) && (fmt & AFMT_U8)) ||
2763                 ((iChannels == 1) && (fmt & AFMT_U8)) ) {
2764                 //
2765                 // Convert each 16-bit unsigned stereo sample to 8-bit unsigned
2766                 // stereo using rounding.
2767                 //
2768                 psSrc = (unsigned short *) src;
2769                 count = count / 2;
2770                 while (count--) {
2771                         lAudioSample = (long) psSrc[count] + (long) 0x80;
2772                         if (lAudioSample > 0xffff) {
2773                                 lAudioSample = 0xffff;
2774                         }
2775                         dst[count] = (char) (lAudioSample >> 8);
2776                 }
2777         }
2778         //
2779         // check for 8-bit signed stereo.
2780         //
2781         else if ((iChannels == 2) && (fmt & AFMT_S8)) {
2782                 //
2783                 // Convert each 16-bit stereo sample to 8-bit stereo using rounding.
2784                 //
2785                 psSrc = (short *) src;
2786                 while (count--) {
2787                         lAudioSample =
2788                             (((long) psSrc[0] + (long) psSrc[1]) / 2);
2789                         psSrc += 2;
2790                         *dst++ = (char) ((short) lAudioSample >> 8);
2791                 }
2792         }
2793         //
2794         // Otherwise, the data should be output as 8-bit signed mono.
2795         //
2796         else if ((iChannels == 1) && (fmt & AFMT_S8)) {
2797                 //
2798                 // Convert each 16-bit signed mono sample to 8-bit signed mono
2799                 // using rounding.
2800                 //
2801                 psSrc = (short *) src;
2802                 count = count / 2;
2803                 while (count--) {
2804                         lAudioSample =
2805                             (((long) psSrc[0] + (long) psSrc[1]) / 2);
2806                         if (lAudioSample > 0x7fff) {
2807                                 lAudioSample = 0x7fff;
2808                         }
2809                         psSrc += 2;
2810                         *dst++ = (char) ((short) lAudioSample >> 8);
2811                 }
2812         }
2813 }
2814
2815 //
2816 // cs_copy_to_user()
2817 // replacement for the standard copy_to_user, to allow for a conversion from
2818 // 16 bit to 8 bit if the record conversion is active.  the cs4281 has some
2819 // issues with 8 bit capture, so the driver always captures data in 16 bit
2820 // and then if the user requested 8 bit, converts from 16 to 8 bit.
2821 //
2822 static unsigned cs_copy_to_user(struct cs4281_state *s, void __user *dest,
2823                                 unsigned *hwsrc, unsigned cnt,
2824                                 unsigned *copied)
2825 {
2826         void *src = hwsrc;      //default to the standard destination buffer addr
2827
2828         CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO
2829                 "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=%p\n",
2830                         s->prop_adc.fmt, s->prop_adc.fmt_original,
2831                         (unsigned) cnt, dest));
2832
2833         if (cnt > s->dma_adc.dmasize) {
2834                 cnt = s->dma_adc.dmasize;
2835         }
2836         if (!cnt) {
2837                 *copied = 0;
2838                 return 0;
2839         }
2840         if (s->conversion) {
2841                 if (!s->tmpbuff) {
2842                         *copied = cnt / 2;
2843                         return 0;
2844                 }
2845                 CopySamples(s->tmpbuff, (void *) hwsrc, cnt,
2846                             (unsigned) s->prop_adc.channels,
2847                             s->prop_adc.fmt_original);
2848                 src = s->tmpbuff;
2849                 cnt = cnt / 2;
2850         }
2851
2852         if (copy_to_user(dest, src, cnt)) {
2853                 *copied = 0;
2854                 return -EFAULT;
2855         }
2856         *copied = cnt;
2857         CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2858                 "cs4281: cs_copy_to_user()- copied bytes is %d \n", cnt));
2859         return 0;
2860 }
2861
2862 // ---------------------------------------------------------------------
2863
2864 static ssize_t cs4281_read(struct file *file, char __user *buffer, size_t count,
2865                            loff_t * ppos)
2866 {
2867         struct cs4281_state *s =
2868             (struct cs4281_state *) file->private_data;
2869         ssize_t ret;
2870         unsigned long flags;
2871         unsigned swptr;
2872         int cnt;
2873         unsigned copied = 0;
2874
2875         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2876                   printk(KERN_INFO "cs4281: cs4281_read()+ %Zu \n", count));
2877
2878         VALIDATE_STATE(s);
2879         if (s->dma_adc.mapped)
2880                 return -ENXIO;
2881         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
2882                 return ret;
2883         if (!access_ok(VERIFY_WRITE, buffer, count))
2884                 return -EFAULT;
2885         ret = 0;
2886 //
2887 // "count" is the amount of bytes to read (from app), is decremented each loop
2888 //      by the amount of bytes that have been returned to the user buffer.
2889 // "cnt" is the running total of each read from the buffer (changes each loop)
2890 // "buffer" points to the app's buffer
2891 // "ret" keeps a running total of the amount of bytes that have been copied
2892 //      to the user buffer.
2893 // "copied" is the total bytes copied into the user buffer for each loop.
2894 //
2895         while (count > 0) {
2896                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2897                         "_read() count>0 count=%Zu .count=%d .swptr=%d .hwptr=%d \n",
2898                                 count, s->dma_adc.count,
2899                                 s->dma_adc.swptr, s->dma_adc.hwptr));
2900                 spin_lock_irqsave(&s->lock, flags);
2901
2902                 // get the current copy point of the sw buffer
2903                 swptr = s->dma_adc.swptr;
2904
2905                 // cnt is the amount of unread bytes from the end of the
2906                 // hw buffer to the current sw pointer
2907                 cnt = s->dma_adc.dmasize - swptr;
2908
2909                 // dma_adc.count is the current total bytes that have not been read.
2910                 // if the amount of unread bytes from the current sw pointer to the
2911                 // end of the buffer is greater than the current total bytes that
2912                 // have not been read, then set the "cnt" (unread bytes) to the
2913                 // amount of unread bytes.
2914
2915                 if (s->dma_adc.count < cnt)
2916                         cnt = s->dma_adc.count;
2917                 spin_unlock_irqrestore(&s->lock, flags);
2918                 //
2919                 // if we are converting from 8/16 then we need to copy
2920                 // twice the number of 16 bit bytes then 8 bit bytes.
2921                 //
2922                 if (s->conversion) {
2923                         if (cnt > (count * 2))
2924                                 cnt = (count * 2);
2925                 } else {
2926                         if (cnt > count)
2927                                 cnt = count;
2928                 }
2929                 //
2930                 // "cnt" NOW is the smaller of the amount that will be read,
2931                 // and the amount that is requested in this read (or partial).
2932                 // if there are no bytes in the buffer to read, then start the
2933                 // ADC and wait for the interrupt handler to wake us up.
2934                 //
2935                 if (cnt <= 0) {
2936
2937                         // start up the dma engine and then continue back to the top of
2938                         // the loop when wake up occurs.
2939                         start_adc(s);
2940                         if (file->f_flags & O_NONBLOCK)
2941                                 return ret ? ret : -EAGAIN;
2942                         interruptible_sleep_on(&s->dma_adc.wait);
2943                         if (signal_pending(current))
2944                                 return ret ? ret : -ERESTARTSYS;
2945                         continue;
2946                 }
2947                 // there are bytes in the buffer to read.
2948                 // copy from the hw buffer over to the user buffer.
2949                 // user buffer is designated by "buffer"
2950                 // virtual address to copy from is rawbuf+swptr
2951                 // the "cnt" is the number of bytes to read.
2952
2953                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
2954                         "_read() copy_to cnt=%d count=%Zu ", cnt, count));
2955                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2956                          " .dmasize=%d .count=%d buffer=%p ret=%Zd\n",
2957                                  s->dma_adc.dmasize, s->dma_adc.count, buffer, ret));
2958
2959                 if (cs_copy_to_user
2960                     (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied))
2961                         return ret ? ret : -EFAULT;
2962                 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2963                 spin_lock_irqsave(&s->lock, flags);
2964                 s->dma_adc.swptr = swptr;
2965                 s->dma_adc.count -= cnt;
2966                 spin_unlock_irqrestore(&s->lock, flags);
2967                 count -= copied;
2968                 buffer += copied;
2969                 ret += copied;
2970                 start_adc(s);
2971         }
2972         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2973                   printk(KERN_INFO "cs4281: cs4281_read()- %Zd\n", ret));
2974         return ret;
2975 }
2976
2977
2978 static ssize_t cs4281_write(struct file *file, const char __user *buffer,
2979                             size_t count, loff_t * ppos)
2980 {
2981         struct cs4281_state *s =
2982             (struct cs4281_state *) file->private_data;
2983         ssize_t ret;
2984         unsigned long flags;
2985         unsigned swptr, hwptr, busaddr;
2986         int cnt;
2987
2988         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
2989                   printk(KERN_INFO "cs4281: cs4281_write()+ count=%Zu\n",
2990                          count));
2991         VALIDATE_STATE(s);
2992
2993         if (s->dma_dac.mapped)
2994                 return -ENXIO;
2995         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
2996                 return ret;
2997         if (!access_ok(VERIFY_READ, buffer, count))
2998                 return -EFAULT;
2999         ret = 0;
3000         while (count > 0) {
3001                 spin_lock_irqsave(&s->lock, flags);
3002                 if (s->dma_dac.count < 0) {
3003                         s->dma_dac.count = 0;
3004                         s->dma_dac.swptr = s->dma_dac.hwptr;
3005                 }
3006                 if (s->dma_dac.underrun) {
3007                         s->dma_dac.underrun = 0;
3008                         hwptr = readl(s->pBA0 + BA0_DCA0);
3009                         busaddr = virt_to_bus(s->dma_dac.rawbuf);
3010                         hwptr -= (unsigned) busaddr;
3011                         s->dma_dac.swptr = s->dma_dac.hwptr = hwptr;
3012                 }
3013                 swptr = s->dma_dac.swptr;
3014                 cnt = s->dma_dac.dmasize - swptr;
3015                 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
3016                         cnt = s->dma_dac.dmasize - s->dma_dac.count;
3017                 spin_unlock_irqrestore(&s->lock, flags);
3018                 if (cnt > count)
3019                         cnt = count;
3020                 if (cnt <= 0) {
3021                         start_dac(s);
3022                         if (file->f_flags & O_NONBLOCK)
3023                                 return ret ? ret : -EAGAIN;
3024                         interruptible_sleep_on(&s->dma_dac.wait);
3025                         if (signal_pending(current))
3026                                 return ret ? ret : -ERESTARTSYS;
3027                         continue;
3028                 }
3029                 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
3030                         return ret ? ret : -EFAULT;
3031                 swptr = (swptr + cnt) % s->dma_dac.dmasize;
3032                 spin_lock_irqsave(&s->lock, flags);
3033                 s->dma_dac.swptr = swptr;
3034                 s->dma_dac.count += cnt;
3035                 s->dma_dac.endcleared = 0;
3036                 spin_unlock_irqrestore(&s->lock, flags);
3037                 count -= cnt;
3038                 buffer += cnt;
3039                 ret += cnt;
3040                 start_dac(s);
3041         }
3042         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
3043                   printk(KERN_INFO "cs4281: cs4281_write()- %Zd\n", ret));
3044         return ret;
3045 }
3046
3047
3048 static unsigned int cs4281_poll(struct file *file,
3049                                 struct poll_table_struct *wait)
3050 {
3051         struct cs4281_state *s =
3052             (struct cs4281_state *) file->private_data;
3053         unsigned long flags;
3054         unsigned int mask = 0;
3055
3056         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3057                   printk(KERN_INFO "cs4281: cs4281_poll()+\n"));
3058         VALIDATE_STATE(s);
3059         if (file->f_mode & FMODE_WRITE) {
3060                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3061                           printk(KERN_INFO
3062                                  "cs4281: cs4281_poll() wait on FMODE_WRITE\n"));
3063                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3064                         return 0;
3065                 poll_wait(file, &s->dma_dac.wait, wait);
3066         }
3067         if (file->f_mode & FMODE_READ) {
3068                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3069                           printk(KERN_INFO
3070                                  "cs4281: cs4281_poll() wait on FMODE_READ\n"));
3071                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
3072                         return 0;
3073                 poll_wait(file, &s->dma_adc.wait, wait);
3074         }
3075         spin_lock_irqsave(&s->lock, flags);
3076         cs4281_update_ptr(s,CS_FALSE);
3077         if (file->f_mode & FMODE_WRITE) {
3078                 if (s->dma_dac.mapped) {
3079                         if (s->dma_dac.count >=
3080                             (signed) s->dma_dac.fragsize) {
3081                                 if (s->dma_dac.wakeup)
3082                                         mask |= POLLOUT | POLLWRNORM;
3083                                 else
3084                                         mask = 0;
3085                                 s->dma_dac.wakeup = 0;
3086                         }
3087                 } else {
3088                         if ((signed) (s->dma_dac.dmasize/2) >= s->dma_dac.count)
3089                                 mask |= POLLOUT | POLLWRNORM;
3090                 }
3091         } else if (file->f_mode & FMODE_READ) {
3092                 if (s->dma_adc.mapped) {
3093                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
3094                                 mask |= POLLIN | POLLRDNORM;
3095                 } else {
3096                         if (s->dma_adc.count > 0)
3097                                 mask |= POLLIN | POLLRDNORM;
3098                 }
3099         }
3100         spin_unlock_irqrestore(&s->lock, flags);
3101         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3102                   printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n",
3103                          mask));
3104         return mask;
3105 }
3106
3107
3108 static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
3109 {
3110         struct cs4281_state *s =
3111             (struct cs4281_state *) file->private_data;
3112         struct dmabuf *db;
3113         int ret;
3114         unsigned long size;
3115
3116         CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3117                   printk(KERN_INFO "cs4281: cs4281_mmap()+\n"));
3118
3119         VALIDATE_STATE(s);
3120         if (vma->vm_flags & VM_WRITE) {
3121                 if ((ret = prog_dmabuf_dac(s)) != 0)
3122                         return ret;
3123                 db = &s->dma_dac;
3124         } else if (vma->vm_flags & VM_READ) {
3125                 if ((ret = prog_dmabuf_adc(s)) != 0)
3126                         return ret;
3127                 db = &s->dma_adc;
3128         } else
3129                 return -EINVAL;
3130 //
3131 // only support PLAYBACK for now
3132 //
3133         db = &s->dma_dac;
3134
3135         if (cs4x_pgoff(vma) != 0)
3136                 return -EINVAL;
3137         size = vma->vm_end - vma->vm_start;
3138         if (size > (PAGE_SIZE << db->buforder))
3139                 return -EINVAL;
3140         if (remap_pfn_range(vma, vma->vm_start,
3141                                 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
3142                                 size, vma->vm_page_prot))
3143                 return -EAGAIN;
3144         db->mapped = 1;
3145
3146         CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3147                   printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n",
3148                          (unsigned) size));
3149
3150         return 0;
3151 }
3152
3153
3154 static int cs4281_ioctl(struct inode *inode, struct file *file,
3155                         unsigned int cmd, unsigned long arg)
3156 {
3157         struct cs4281_state *s =
3158             (struct cs4281_state *) file->private_data;
3159         unsigned long flags;
3160         audio_buf_info abinfo;
3161         count_info cinfo;
3162         int val, mapped, ret;
3163         int __user *p = (int __user *)arg;
3164
3165         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
3166                  "cs4281: cs4281_ioctl(): file=%p cmd=0x%.8x\n", file, cmd));
3167 #if CSDEBUG
3168         cs_printioctl(cmd);
3169 #endif
3170         VALIDATE_STATE(s);
3171         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
3172             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
3173         switch (cmd) {
3174         case OSS_GETVERSION:
3175                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3176                         "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n",
3177                                  SOUND_VERSION));
3178                 return put_user(SOUND_VERSION, p);
3179
3180         case SNDCTL_DSP_SYNC:
3181                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3182                          "cs4281: cs4281_ioctl(): DSP_SYNC\n"));
3183                 if (file->f_mode & FMODE_WRITE)
3184                         return drain_dac(s,
3185                                          0 /*file->f_flags & O_NONBLOCK */
3186                                          );
3187                 return 0;
3188
3189         case SNDCTL_DSP_SETDUPLEX:
3190                 return 0;
3191
3192         case SNDCTL_DSP_GETCAPS:
3193                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
3194                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
3195                                 p);
3196
3197         case SNDCTL_DSP_RESET:
3198                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3199                          "cs4281: cs4281_ioctl(): DSP_RESET\n"));
3200                 if (file->f_mode & FMODE_WRITE) {
3201                         stop_dac(s);
3202                         synchronize_irq(s->irq);
3203                         s->dma_dac.swptr = s->dma_dac.hwptr =
3204                             s->dma_dac.count = s->dma_dac.total_bytes =
3205                             s->dma_dac.blocks = s->dma_dac.wakeup = 0;
3206                         prog_codec(s, CS_TYPE_DAC);
3207                 }
3208                 if (file->f_mode & FMODE_READ) {
3209                         stop_adc(s);
3210                         synchronize_irq(s->irq);
3211                         s->dma_adc.swptr = s->dma_adc.hwptr =
3212                             s->dma_adc.count = s->dma_adc.total_bytes =
3213                             s->dma_adc.blocks = s->dma_dac.wakeup = 0;
3214                         prog_codec(s, CS_TYPE_ADC);
3215                 }
3216                 return 0;
3217
3218         case SNDCTL_DSP_SPEED:
3219                 if (get_user(val, p))
3220                         return -EFAULT;
3221                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3222                          "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n", val));
3223                 //
3224                 // support independent capture and playback channels
3225                 // assume that the file mode bit determines the
3226                 // direction of the data flow.
3227                 //
3228                 if (file->f_mode & FMODE_READ) {
3229                         if (val >= 0) {
3230                                 stop_adc(s);
3231                                 s->dma_adc.ready = 0;
3232                                 // program sampling rates
3233                                 if (val > 48000)
3234                                         val = 48000;
3235                                 if (val < 6300)
3236                                         val = 6300;
3237                                 s->prop_adc.rate = val;
3238                                 prog_codec(s, CS_TYPE_ADC);
3239                         }
3240                 }
3241                 if (file->f_mode & FMODE_WRITE) {
3242                         if (val >= 0) {
3243                                 stop_dac(s);
3244                                 s->dma_dac.ready = 0;
3245                                 // program sampling rates
3246                                 if (val > 48000)
3247                                         val = 48000;
3248                                 if (val < 6300)
3249                                         val = 6300;
3250                                 s->prop_dac.rate = val;
3251                                 prog_codec(s, CS_TYPE_DAC);
3252                         }
3253                 }
3254
3255                 if (file->f_mode & FMODE_WRITE)
3256                         val = s->prop_dac.rate;
3257                 else if (file->f_mode & FMODE_READ)
3258                         val = s->prop_adc.rate;
3259
3260                 return put_user(val, p);
3261
3262         case SNDCTL_DSP_STEREO:
3263                 if (get_user(val, p))
3264                         return -EFAULT;
3265                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3266                          "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n", val));
3267                 if (file->f_mode & FMODE_READ) {
3268                         stop_adc(s);
3269                         s->dma_adc.ready = 0;
3270                         s->prop_adc.channels = val ? 2 : 1;
3271                         prog_codec(s, CS_TYPE_ADC);
3272                 }
3273                 if (file->f_mode & FMODE_WRITE) {
3274                         stop_dac(s);
3275                         s->dma_dac.ready = 0;
3276                         s->prop_dac.channels = val ? 2 : 1;
3277                         prog_codec(s, CS_TYPE_DAC);
3278                 }
3279                 return 0;
3280
3281         case SNDCTL_DSP_CHANNELS:
3282                 if (get_user(val, p))
3283                         return -EFAULT;
3284                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3285                          "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n",
3286                                  val));
3287                 if (val != 0) {
3288                         if (file->f_mode & FMODE_READ) {
3289                                 stop_adc(s);
3290                                 s->dma_adc.ready = 0;
3291                                 if (val >= 2)
3292                                         s->prop_adc.channels = 2;
3293                                 else
3294                                         s->prop_adc.channels = 1;
3295                                 prog_codec(s, CS_TYPE_ADC);
3296                         }
3297                         if (file->f_mode & FMODE_WRITE) {
3298                                 stop_dac(s);
3299                                 s->dma_dac.ready = 0;
3300                                 if (val >= 2)
3301                                         s->prop_dac.channels = 2;
3302                                 else
3303                                         s->prop_dac.channels = 1;
3304                                 prog_codec(s, CS_TYPE_DAC);
3305                         }
3306                 }
3307
3308                 if (file->f_mode & FMODE_WRITE)
3309                         val = s->prop_dac.channels;
3310                 else if (file->f_mode & FMODE_READ)
3311                         val = s->prop_adc.channels;
3312
3313                 return put_user(val, p);
3314
3315         case SNDCTL_DSP_GETFMTS:        // Returns a mask
3316                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3317                         "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n",
3318                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3319                                  AFMT_U8));
3320                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3321                                 AFMT_U8, p);
3322
3323         case SNDCTL_DSP_SETFMT:
3324                 if (get_user(val, p))
3325                         return -EFAULT;
3326                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3327                          "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n",
3328                                  val));
3329                 if (val != AFMT_QUERY) {
3330                         if (file->f_mode & FMODE_READ) {
3331                                 stop_adc(s);
3332                                 s->dma_adc.ready = 0;
3333                                 if (val != AFMT_S16_LE
3334                                     && val != AFMT_U16_LE && val != AFMT_S8
3335                                     && val != AFMT_U8)
3336                                         val = AFMT_U8;
3337                                 s->prop_adc.fmt = val;
3338                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
3339                                 prog_codec(s, CS_TYPE_ADC);
3340                         }
3341                         if (file->f_mode & FMODE_WRITE) {
3342                                 stop_dac(s);
3343                                 s->dma_dac.ready = 0;
3344                                 if (val != AFMT_S16_LE
3345                                     && val != AFMT_U16_LE && val != AFMT_S8
3346                                     && val != AFMT_U8)
3347                                         val = AFMT_U8;
3348                                 s->prop_dac.fmt = val;
3349                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
3350                                 prog_codec(s, CS_TYPE_DAC);
3351                         }
3352                 } else {
3353                         if (file->f_mode & FMODE_WRITE)
3354                                 val = s->prop_dac.fmt_original;
3355                         else if (file->f_mode & FMODE_READ)
3356                                 val = s->prop_adc.fmt_original;
3357                 }
3358                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3359                   "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n",
3360                         val));
3361                 return put_user(val, p);
3362
3363         case SNDCTL_DSP_POST:
3364                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3365                          "cs4281: cs4281_ioctl(): DSP_POST\n"));
3366                 return 0;
3367
3368         case SNDCTL_DSP_GETTRIGGER:
3369                 val = 0;
3370                 if (file->f_mode & s->ena & FMODE_READ)
3371                         val |= PCM_ENABLE_INPUT;
3372                 if (file->f_mode & s->ena & FMODE_WRITE)
3373                         val |= PCM_ENABLE_OUTPUT;
3374                 return put_user(val, p);
3375
3376         case SNDCTL_DSP_SETTRIGGER:
3377                 if (get_user(val, p))
3378                         return -EFAULT;
3379                 if (file->f_mode & FMODE_READ) {
3380                         if (val & PCM_ENABLE_INPUT) {
3381                                 if (!s->dma_adc.ready
3382                                     && (ret = prog_dmabuf_adc(s)))
3383                                         return ret;
3384                                 start_adc(s);
3385                         } else
3386                                 stop_adc(s);
3387                 }
3388                 if (file->f_mode & FMODE_WRITE) {
3389                         if (val & PCM_ENABLE_OUTPUT) {
3390                                 if (!s->dma_dac.ready
3391                                     && (ret = prog_dmabuf_dac(s)))
3392                                         return ret;
3393                                 start_dac(s);
3394                         } else
3395                                 stop_dac(s);
3396                 }
3397                 return 0;
3398
3399         case SNDCTL_DSP_GETOSPACE:
3400                 if (!(file->f_mode & FMODE_WRITE))
3401                         return -EINVAL;
3402                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
3403                         return val;
3404                 spin_lock_irqsave(&s->lock, flags);
3405                 cs4281_update_ptr(s,CS_FALSE);
3406                 abinfo.fragsize = s->dma_dac.fragsize;
3407                 if (s->dma_dac.mapped)
3408                         abinfo.bytes = s->dma_dac.dmasize;
3409                 else
3410                         abinfo.bytes =
3411                             s->dma_dac.dmasize - s->dma_dac.count;
3412                 abinfo.fragstotal = s->dma_dac.numfrag;
3413                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
3414                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
3415                         "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
3416                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
3417                                 abinfo.fragments));
3418                 spin_unlock_irqrestore(&s->lock, flags);
3419                 return copy_to_user(p, &abinfo,
3420                                     sizeof(abinfo)) ? -EFAULT : 0;
3421
3422         case SNDCTL_DSP_GETISPACE:
3423                 if (!(file->f_mode & FMODE_READ))
3424                         return -EINVAL;
3425                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
3426                         return val;
3427                 spin_lock_irqsave(&s->lock, flags);
3428                 cs4281_update_ptr(s,CS_FALSE);
3429                 if (s->conversion) {
3430                         abinfo.fragsize = s->dma_adc.fragsize / 2;
3431                         abinfo.bytes = s->dma_adc.count / 2;
3432                         abinfo.fragstotal = s->dma_adc.numfrag;
3433                         abinfo.fragments =
3434                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
3435                 } else {
3436                         abinfo.fragsize = s->dma_adc.fragsize;
3437                         abinfo.bytes = s->dma_adc.count;
3438                         abinfo.fragstotal = s->dma_adc.numfrag;
3439                         abinfo.fragments =
3440                             abinfo.bytes >> s->dma_adc.fragshift;
3441                 }
3442                 spin_unlock_irqrestore(&s->lock, flags);
3443                 return copy_to_user(p, &abinfo,
3444                                     sizeof(abinfo)) ? -EFAULT : 0;
3445
3446         case SNDCTL_DSP_NONBLOCK:
3447                 file->f_flags |= O_NONBLOCK;
3448                 return 0;
3449
3450         case SNDCTL_DSP_GETODELAY:
3451                 if (!(file->f_mode & FMODE_WRITE))
3452                         return -EINVAL;
3453                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3454                         return 0;
3455                 spin_lock_irqsave(&s->lock, flags);
3456                 cs4281_update_ptr(s,CS_FALSE);
3457                 val = s->dma_dac.count;
3458                 spin_unlock_irqrestore(&s->lock, flags);
3459                 return put_user(val, p);
3460
3461         case SNDCTL_DSP_GETIPTR:
3462                 if (!(file->f_mode & FMODE_READ))
3463                         return -EINVAL;
3464                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
3465                         return 0;
3466                 spin_lock_irqsave(&s->lock, flags);
3467                 cs4281_update_ptr(s,CS_FALSE);
3468                 cinfo.bytes = s->dma_adc.total_bytes;
3469                 if (s->dma_adc.mapped) {
3470                         cinfo.blocks =
3471                             (cinfo.bytes >> s->dma_adc.fragshift) -
3472                             s->dma_adc.blocks;
3473                         s->dma_adc.blocks =
3474                             cinfo.bytes >> s->dma_adc.fragshift;
3475                 } else {
3476                         if (s->conversion) {
3477                                 cinfo.blocks =
3478                                     s->dma_adc.count /
3479                                     2 >> (s->dma_adc.fragshift - 1);
3480                         } else
3481                                 cinfo.blocks =
3482                                     s->dma_adc.count >> s->dma_adc.
3483                                     fragshift;
3484                 }
3485                 if (s->conversion)
3486                         cinfo.ptr = s->dma_adc.hwptr / 2;
3487                 else
3488                         cinfo.ptr = s->dma_adc.hwptr;
3489                 if (s->dma_adc.mapped)
3490                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
3491                 spin_unlock_irqrestore(&s->lock, flags);
3492                 if (copy_to_user(p, &cinfo, sizeof(cinfo)))
3493                         return -EFAULT;
3494                 return 0;
3495
3496         case SNDCTL_DSP_GETOPTR:
3497                 if (!(file->f_mode & FMODE_WRITE))
3498                         return -EINVAL;
3499                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3500                         return 0;
3501                 spin_lock_irqsave(&s->lock, flags);
3502                 cs4281_update_ptr(s,CS_FALSE);
3503                 cinfo.bytes = s->dma_dac.total_bytes;
3504                 if (s->dma_dac.mapped) {
3505                         cinfo.blocks =
3506                             (cinfo.bytes >> s->dma_dac.fragshift) -
3507                             s->dma_dac.blocks;
3508                         s->dma_dac.blocks =
3509                             cinfo.bytes >> s->dma_dac.fragshift;
3510                 } else {
3511                         cinfo.blocks =
3512                             s->dma_dac.count >> s->dma_dac.fragshift;
3513                 }
3514                 cinfo.ptr = s->dma_dac.hwptr;
3515                 if (s->dma_dac.mapped)
3516                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
3517                 spin_unlock_irqrestore(&s->lock, flags);
3518                 if (copy_to_user(p, &cinfo, sizeof(cinfo)))
3519                         return -EFAULT;
3520                 return 0;
3521
3522         case SNDCTL_DSP_GETBLKSIZE:
3523                 if (file->f_mode & FMODE_WRITE) {
3524                         if ((val = prog_dmabuf_dac(s)))
3525                                 return val;
3526                         return put_user(s->dma_dac.fragsize, p);
3527                 }
3528                 if ((val = prog_dmabuf_adc(s)))
3529                         return val;
3530                 if (s->conversion)
3531                         return put_user(s->dma_adc.fragsize / 2, p);
3532                 else
3533                         return put_user(s->dma_adc.fragsize, p);
3534
3535         case SNDCTL_DSP_SETFRAGMENT:
3536                 if (get_user(val, p))
3537                         return -EFAULT;
3538                 return 0;       // Say OK, but do nothing.
3539
3540         case SNDCTL_DSP_SUBDIVIDE:
3541                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
3542                     || (file->f_mode & FMODE_WRITE
3543                         && s->dma_dac.subdivision)) return -EINVAL;
3544                 if (get_user(val, p))
3545                         return -EFAULT;
3546                 if (val != 1 && val != 2 && val != 4)
3547                         return -EINVAL;
3548                 if (file->f_mode & FMODE_READ)
3549                         s->dma_adc.subdivision = val;
3550                 else if (file->f_mode & FMODE_WRITE)
3551                         s->dma_dac.subdivision = val;
3552                 return 0;
3553
3554         case SOUND_PCM_READ_RATE:
3555                 if (file->f_mode & FMODE_READ)
3556                         return put_user(s->prop_adc.rate, p);
3557                 else if (file->f_mode & FMODE_WRITE)
3558                         return put_user(s->prop_dac.rate, p);
3559
3560         case SOUND_PCM_READ_CHANNELS:
3561                 if (file->f_mode & FMODE_READ)
3562                         return put_user(s->prop_adc.channels, p);
3563                 else if (file->f_mode & FMODE_WRITE)
3564                         return put_user(s->prop_dac.channels, p);
3565
3566         case SOUND_PCM_READ_BITS:
3567                 if (file->f_mode & FMODE_READ)
3568                         return
3569                             put_user(
3570                                      (s->prop_adc.
3571                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3572                                      p);
3573                 else if (file->f_mode & FMODE_WRITE)
3574                         return
3575                             put_user(
3576                                      (s->prop_dac.
3577                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3578                                      p);
3579
3580         case SOUND_PCM_WRITE_FILTER:
3581         case SNDCTL_DSP_SETSYNCRO:
3582         case SOUND_PCM_READ_FILTER:
3583                 return -EINVAL;
3584         }
3585         return mixer_ioctl(s, cmd, arg);
3586 }
3587
3588
3589 static int cs4281_release(struct inode *inode, struct file *file)
3590 {
3591         struct cs4281_state *s =
3592             (struct cs4281_state *) file->private_data;
3593
3594         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
3595                  "cs4281: cs4281_release(): inode=%p file=%p f_mode=%d\n",
3596                          inode, file, file->f_mode));
3597
3598         VALIDATE_STATE(s);
3599
3600         if (file->f_mode & FMODE_WRITE) {
3601                 drain_dac(s, file->f_flags & O_NONBLOCK);
3602                 down(&s->open_sem_dac);
3603                 stop_dac(s);
3604                 dealloc_dmabuf(s, &s->dma_dac);
3605                 s->open_mode &= ~FMODE_WRITE;
3606                 up(&s->open_sem_dac);
3607                 wake_up(&s->open_wait_dac);
3608         }
3609         if (file->f_mode & FMODE_READ) {
3610                 drain_adc(s, file->f_flags & O_NONBLOCK);
3611                 down(&s->open_sem_adc);
3612                 stop_adc(s);
3613                 dealloc_dmabuf(s, &s->dma_adc);
3614                 s->open_mode &= ~FMODE_READ;
3615                 up(&s->open_sem_adc);
3616                 wake_up(&s->open_wait_adc);
3617         }
3618         return 0;
3619 }
3620
3621 static int cs4281_open(struct inode *inode, struct file *file)
3622 {
3623         unsigned int minor = iminor(inode);
3624         struct cs4281_state *s=NULL;
3625         struct list_head *entry;
3626
3627         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3628                 "cs4281: cs4281_open(): inode=%p file=%p f_mode=0x%x\n",
3629                         inode, file, file->f_mode));
3630
3631         list_for_each(entry, &cs4281_devs)
3632         {
3633                 s = list_entry(entry, struct cs4281_state, list);
3634
3635                 if (!((s->dev_audio ^ minor) & ~0xf))
3636                         break;
3637         }
3638         if (entry == &cs4281_devs)
3639                 return -ENODEV;
3640         if (!s) {
3641                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3642                         "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3643                 return -ENODEV;
3644         }
3645         VALIDATE_STATE(s);
3646         file->private_data = s;
3647
3648         // wait for device to become free
3649         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
3650                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
3651                          "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n"));
3652                 return -ENODEV;
3653         }
3654         if (file->f_mode & FMODE_WRITE) {
3655                 down(&s->open_sem_dac);
3656                 while (s->open_mode & FMODE_WRITE) {
3657                         if (file->f_flags & O_NONBLOCK) {
3658                                 up(&s->open_sem_dac);
3659                                 return -EBUSY;
3660                         }
3661                         up(&s->open_sem_dac);
3662                         interruptible_sleep_on(&s->open_wait_dac);
3663
3664                         if (signal_pending(current))
3665                                 return -ERESTARTSYS;
3666                         down(&s->open_sem_dac);
3667                 }
3668         }
3669         if (file->f_mode & FMODE_READ) {
3670                 down(&s->open_sem_adc);
3671                 while (s->open_mode & FMODE_READ) {
3672                         if (file->f_flags & O_NONBLOCK) {
3673                                 up(&s->open_sem_adc);
3674                                 return -EBUSY;
3675                         }
3676                         up(&s->open_sem_adc);
3677                         interruptible_sleep_on(&s->open_wait_adc);
3678
3679                         if (signal_pending(current))
3680                                 return -ERESTARTSYS;
3681                         down(&s->open_sem_adc);
3682                 }
3683         }
3684         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
3685         if (file->f_mode & FMODE_READ) {
3686                 s->prop_adc.fmt = AFMT_U8;
3687                 s->prop_adc.fmt_original = s->prop_adc.fmt;
3688                 s->prop_adc.channels = 1;
3689                 s->prop_adc.rate = 8000;
3690                 s->prop_adc.clkdiv = 96 | 0x80;
3691                 s->conversion = 0;
3692                 s->ena &= ~FMODE_READ;
3693                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
3694                     s->dma_adc.subdivision = 0;
3695                 up(&s->open_sem_adc);
3696
3697                 if (prog_dmabuf_adc(s)) {
3698                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3699                                 "cs4281: adc Program dmabufs failed.\n"));
3700                         cs4281_release(inode, file);
3701                         return -ENOMEM;
3702                 }
3703                 prog_codec(s, CS_TYPE_ADC);
3704         }
3705         if (file->f_mode & FMODE_WRITE) {
3706                 s->prop_dac.fmt = AFMT_U8;
3707                 s->prop_dac.fmt_original = s->prop_dac.fmt;
3708                 s->prop_dac.channels = 1;
3709                 s->prop_dac.rate = 8000;
3710                 s->prop_dac.clkdiv = 96 | 0x80;
3711                 s->conversion = 0;
3712                 s->ena &= ~FMODE_WRITE;
3713                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
3714                     s->dma_dac.subdivision = 0;
3715                 up(&s->open_sem_dac);
3716
3717                 if (prog_dmabuf_dac(s)) {
3718                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3719                                 "cs4281: dac Program dmabufs failed.\n"));
3720                         cs4281_release(inode, file);
3721                         return -ENOMEM;
3722                 }
3723                 prog_codec(s, CS_TYPE_DAC);
3724         }
3725         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3726                   printk(KERN_INFO "cs4281: cs4281_open()- 0\n"));
3727         return nonseekable_open(inode, file);
3728 }
3729
3730
3731 // ******************************************************************************************
3732 //   Wave (audio) file operations struct.
3733 // ******************************************************************************************
3734 static /*const */ struct file_operations cs4281_audio_fops = {
3735         .owner   = THIS_MODULE,
3736         .llseek  = no_llseek,
3737         .read    = cs4281_read,
3738         .write   = cs4281_write,
3739         .poll    = cs4281_poll,
3740         .ioctl   = cs4281_ioctl,
3741         .mmap    = cs4281_mmap,
3742         .open    = cs4281_open,
3743         .release = cs4281_release,
3744 };
3745
3746 // ---------------------------------------------------------------------
3747
3748 // hold spinlock for the following!
3749 static void cs4281_handle_midi(struct cs4281_state *s)
3750 {
3751         unsigned char ch;
3752         int wake;
3753         unsigned temp1;
3754
3755         wake = 0;
3756         while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) {
3757                 ch = readl(s->pBA0 + BA0_MIDRP);
3758                 if (s->midi.icnt < MIDIINBUF) {
3759                         s->midi.ibuf[s->midi.iwr] = ch;
3760                         s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
3761                         s->midi.icnt++;
3762                 }
3763                 wake = 1;
3764         }
3765         if (wake)
3766                 wake_up(&s->midi.iwait);
3767         wake = 0;
3768         while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
3769                 temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff;
3770                 writel(temp1, s->pBA0 + BA0_MIDWP);
3771                 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
3772                 s->midi.ocnt--;
3773                 if (s->midi.ocnt < MIDIOUTBUF - 16)
3774                         wake = 1;
3775         }
3776         if (wake)
3777                 wake_up(&s->midi.owait);
3778 }
3779
3780
3781
3782 static irqreturn_t cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3783 {
3784         struct cs4281_state *s = (struct cs4281_state *) dev_id;
3785         unsigned int temp1;
3786
3787         // fastpath out, to ease interrupt sharing
3788         temp1 = readl(s->pBA0 + BA0_HISR);      // Get Int Status reg.
3789
3790         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
3791                   "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n", temp1));
3792 /*
3793 * If not DMA or MIDI interrupt, then just return.
3794 */
3795         if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) {
3796                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
3797                 CS_DBGOUT(CS_INTERRUPT, 9, printk(KERN_INFO
3798                         "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n"));
3799                 return IRQ_NONE;
3800         }
3801
3802         if (temp1 & HISR_DMA0)  // If play interrupt,
3803                 readl(s->pBA0 + BA0_HDSR0);     //   clear the source.
3804
3805         if (temp1 & HISR_DMA1)  // Same for play.
3806                 readl(s->pBA0 + BA0_HDSR1);
3807         writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Local EOI
3808
3809         spin_lock(&s->lock);
3810         cs4281_update_ptr(s,CS_TRUE);
3811         cs4281_handle_midi(s);
3812         spin_unlock(&s->lock);
3813         return IRQ_HANDLED;
3814 }
3815
3816 // **************************************************************************
3817
3818 static void cs4281_midi_timer(unsigned long data)
3819 {
3820         struct cs4281_state *s = (struct cs4281_state *) data;
3821         unsigned long flags;
3822
3823         spin_lock_irqsave(&s->lock, flags);
3824         cs4281_handle_midi(s);
3825         spin_unlock_irqrestore(&s->lock, flags);
3826         s->midi.timer.expires = jiffies + 1;
3827         add_timer(&s->midi.timer);
3828 }
3829
3830
3831 // ---------------------------------------------------------------------
3832
3833 static ssize_t cs4281_midi_read(struct file *file, char __user *buffer,
3834                                 size_t count, loff_t * ppos)
3835 {
3836         struct cs4281_state *s =
3837             (struct cs4281_state *) file->private_data;
3838         ssize_t ret;
3839         unsigned long flags;
3840         unsigned ptr;
3841         int cnt;
3842
3843         VALIDATE_STATE(s);
3844         if (!access_ok(VERIFY_WRITE, buffer, count))
3845                 return -EFAULT;
3846         ret = 0;
3847         while (count > 0) {
3848                 spin_lock_irqsave(&s->lock, flags);
3849                 ptr = s->midi.ird;
3850                 cnt = MIDIINBUF - ptr;
3851                 if (s->midi.icnt < cnt)
3852                         cnt = s->midi.icnt;
3853                 spin_unlock_irqrestore(&s->lock, flags);
3854                 if (cnt > count)
3855                         cnt = count;
3856                 if (cnt <= 0) {
3857                         if (file->f_flags & O_NONBLOCK)
3858                                 return ret ? ret : -EAGAIN;
3859                         interruptible_sleep_on(&s->midi.iwait);
3860                         if (signal_pending(current))
3861                                 return ret ? ret : -ERESTARTSYS;
3862                         continue;
3863                 }
3864                 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
3865                         return ret ? ret : -EFAULT;
3866                 ptr = (ptr + cnt) % MIDIINBUF;
3867                 spin_lock_irqsave(&s->lock, flags);
3868                 s->midi.ird = ptr;
3869                 s->midi.icnt -= cnt;
3870                 spin_unlock_irqrestore(&s->lock, flags);
3871                 count -= cnt;
3872                 buffer += cnt;
3873                 ret += cnt;
3874         }
3875         return ret;
3876 }
3877
3878
3879 static ssize_t cs4281_midi_write(struct file *file, const char __user *buffer,
3880                                  size_t count, loff_t * ppos)
3881 {
3882         struct cs4281_state *s =
3883             (struct cs4281_state *) file->private_data;
3884         ssize_t ret;
3885         unsigned long flags;
3886         unsigned ptr;
3887         int cnt;
3888
3889         VALIDATE_STATE(s);
3890         if (!access_ok(VERIFY_READ, buffer, count))
3891                 return -EFAULT;
3892         ret = 0;
3893         while (count > 0) {
3894                 spin_lock_irqsave(&s->lock, flags);
3895                 ptr = s->midi.owr;
3896                 cnt = MIDIOUTBUF - ptr;
3897                 if (s->midi.ocnt + cnt > MIDIOUTBUF)
3898                         cnt = MIDIOUTBUF - s->midi.ocnt;
3899                 if (cnt <= 0)
3900                         cs4281_handle_midi(s);
3901                 spin_unlock_irqrestore(&s->lock, flags);
3902                 if (cnt > count)
3903                         cnt = count;
3904                 if (cnt <= 0) {
3905                         if (file->f_flags & O_NONBLOCK)
3906                                 return ret ? ret : -EAGAIN;
3907                         interruptible_sleep_on(&s->midi.owait);
3908                         if (signal_pending(current))
3909                                 return ret ? ret : -ERESTARTSYS;
3910                         continue;
3911                 }
3912                 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
3913                         return ret ? ret : -EFAULT;
3914                 ptr = (ptr + cnt) % MIDIOUTBUF;
3915                 spin_lock_irqsave(&s->lock, flags);
3916                 s->midi.owr = ptr;
3917                 s->midi.ocnt += cnt;
3918                 spin_unlock_irqrestore(&s->lock, flags);
3919                 count -= cnt;
3920                 buffer += cnt;
3921                 ret += cnt;
3922                 spin_lock_irqsave(&s->lock, flags);
3923                 cs4281_handle_midi(s);
3924                 spin_unlock_irqrestore(&s->lock, flags);
3925         }
3926         return ret;
3927 }
3928
3929
3930 static unsigned int cs4281_midi_poll(struct file *file,
3931                                      struct poll_table_struct *wait)
3932 {
3933         struct cs4281_state *s =
3934             (struct cs4281_state *) file->private_data;
3935         unsigned long flags;
3936         unsigned int mask = 0;
3937
3938         VALIDATE_STATE(s);
3939         if (file->f_flags & FMODE_WRITE)
3940                 poll_wait(file, &s->midi.owait, wait);
3941         if (file->f_flags & FMODE_READ)
3942                 poll_wait(file, &s->midi.iwait, wait);
3943         spin_lock_irqsave(&s->lock, flags);
3944         if (file->f_flags & FMODE_READ) {
3945                 if (s->midi.icnt > 0)
3946                         mask |= POLLIN | POLLRDNORM;
3947         }
3948         if (file->f_flags & FMODE_WRITE) {
3949                 if (s->midi.ocnt < MIDIOUTBUF)
3950                         mask |= POLLOUT | POLLWRNORM;
3951         }
3952         spin_unlock_irqrestore(&s->lock, flags);
3953         return mask;
3954 }
3955
3956
3957 static int cs4281_midi_open(struct inode *inode, struct file *file)
3958 {
3959         unsigned long flags, temp1;
3960         unsigned int minor = iminor(inode);
3961         struct cs4281_state *s=NULL;
3962         struct list_head *entry;
3963         list_for_each(entry, &cs4281_devs)
3964         {
3965                 s = list_entry(entry, struct cs4281_state, list);
3966
3967                 if (s->dev_midi == minor)
3968                         break;
3969         }
3970
3971         if (entry == &cs4281_devs)
3972                 return -ENODEV;
3973         if (!s)
3974         {
3975                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3976                         "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3977                 return -ENODEV;
3978         }
3979         VALIDATE_STATE(s);
3980         file->private_data = s;
3981         // wait for device to become free
3982         down(&s->open_sem);
3983         while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
3984                 if (file->f_flags & O_NONBLOCK) {
3985                         up(&s->open_sem);
3986                         return -EBUSY;
3987                 }
3988                 up(&s->open_sem);
3989                 interruptible_sleep_on(&s->open_wait);
3990                 if (signal_pending(current))
3991                         return -ERESTARTSYS;
3992                 down(&s->open_sem);
3993         }
3994         spin_lock_irqsave(&s->lock, flags);
3995         if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
3996                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
3997                 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
3998                 writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface.
3999                 writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode.
4000                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4001                 writel(0x0000000f, s->pBA0 + BA0_MIDCR);        // Enable transmit, record, ints.
4002                 temp1 = readl(s->pBA0 + BA0_HIMR);
4003                 writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition.
4004                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts
4005                 init_timer(&s->midi.timer);
4006                 s->midi.timer.expires = jiffies + 1;
4007                 s->midi.timer.data = (unsigned long) s;
4008                 s->midi.timer.function = cs4281_midi_timer;
4009                 add_timer(&s->midi.timer);
4010         }
4011         if (file->f_mode & FMODE_READ) {
4012                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4013         }
4014         if (file->f_mode & FMODE_WRITE) {
4015                 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4016         }
4017         spin_unlock_irqrestore(&s->lock, flags);
4018         s->open_mode |=
4019             (file->
4020              f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ |
4021                                             FMODE_MIDI_WRITE);
4022         up(&s->open_sem);
4023         return nonseekable_open(inode, file);
4024 }
4025
4026
4027 static int cs4281_midi_release(struct inode *inode, struct file *file)
4028 {
4029         struct cs4281_state *s =
4030             (struct cs4281_state *) file->private_data;
4031         DECLARE_WAITQUEUE(wait, current);
4032         unsigned long flags;
4033         unsigned count, tmo;
4034
4035         VALIDATE_STATE(s);
4036
4037         if (file->f_mode & FMODE_WRITE) {
4038                 add_wait_queue(&s->midi.owait, &wait);
4039                 for (;;) {
4040                         set_current_state(TASK_INTERRUPTIBLE);
4041                         spin_lock_irqsave(&s->lock, flags);
4042                         count = s->midi.ocnt;
4043                         spin_unlock_irqrestore(&s->lock, flags);
4044                         if (count <= 0)
4045                                 break;
4046                         if (signal_pending(current))
4047                                 break;
4048                         if (file->f_flags & O_NONBLOCK) {
4049                                 remove_wait_queue(&s->midi.owait, &wait);
4050                                 current->state = TASK_RUNNING;
4051                                 return -EBUSY;
4052                         }
4053                         tmo = (count * HZ) / 3100;
4054                         if (!schedule_timeout(tmo ? : 1) && tmo)
4055                                 printk(KERN_DEBUG
4056                                        "cs4281: midi timed out??\n");
4057                 }
4058                 remove_wait_queue(&s->midi.owait, &wait);
4059                 current->state = TASK_RUNNING;
4060         }
4061         down(&s->open_sem);
4062         s->open_mode &=
4063             (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ |
4064                                                      FMODE_MIDI_WRITE);
4065         spin_lock_irqsave(&s->lock, flags);
4066         if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4067                 writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts.
4068                 del_timer(&s->midi.timer);
4069         }
4070         spin_unlock_irqrestore(&s->lock, flags);
4071         up(&s->open_sem);
4072         wake_up(&s->open_wait);
4073         return 0;
4074 }
4075
4076 // ******************************************************************************************
4077 //   Midi file operations struct.
4078 // ******************************************************************************************
4079 static /*const */ struct file_operations cs4281_midi_fops = {
4080         .owner   = THIS_MODULE,
4081         .llseek  = no_llseek,
4082         .read    = cs4281_midi_read,
4083         .write   = cs4281_midi_write,
4084         .poll    = cs4281_midi_poll,
4085         .open    = cs4281_midi_open,
4086         .release = cs4281_midi_release,
4087 };
4088
4089
4090 // ---------------------------------------------------------------------
4091
4092 // maximum number of devices
4093 #define NR_DEVICE 8             // Only eight devices supported currently.
4094
4095 // ---------------------------------------------------------------------
4096
4097 static struct initvol {
4098         int mixch;
4099         int vol;
4100 } initvol[] __devinitdata = {
4101
4102         {
4103         SOUND_MIXER_WRITE_VOLUME, 0x4040}, {
4104         SOUND_MIXER_WRITE_PCM, 0x4040}, {
4105         SOUND_MIXER_WRITE_SYNTH, 0x4040}, {
4106         SOUND_MIXER_WRITE_CD, 0x4040}, {
4107         SOUND_MIXER_WRITE_LINE, 0x4040}, {
4108         SOUND_MIXER_WRITE_LINE1, 0x4040}, {
4109         SOUND_MIXER_WRITE_RECLEV, 0x0000}, {
4110         SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {
4111         SOUND_MIXER_WRITE_MIC, 0x0000}
4112 };
4113
4114
4115 #ifndef NOT_CS4281_PM
4116 static void __devinit cs4281_BuildFIFO(
4117         struct cs4281_pipeline *p,
4118         struct cs4281_state *s)
4119 {
4120         switch(p->number)
4121         {
4122                 case 0:  /* playback */
4123                 {
4124                         p->u32FCRnAddress  =  BA0_FCR0;
4125                         p->u32FSICnAddress = BA0_FSIC0;
4126                         p->u32FPDRnAddress = BA0_FPDR0;
4127                         break;
4128                 }
4129                 case 1:  /* capture */
4130                 {
4131                         p->u32FCRnAddress  =  BA0_FCR1;
4132                         p->u32FSICnAddress = BA0_FSIC1;
4133                         p->u32FPDRnAddress = BA0_FPDR1;
4134                         break;
4135                 }
4136
4137                 case 2:
4138                 {
4139                         p->u32FCRnAddress  =  BA0_FCR2;
4140                         p->u32FSICnAddress = BA0_FSIC2;
4141                         p->u32FPDRnAddress = BA0_FPDR2;
4142                         break;
4143                 }
4144                 case 3:
4145                 {
4146                         p->u32FCRnAddress  =  BA0_FCR3;
4147                         p->u32FSICnAddress = BA0_FSIC3;
4148                         p->u32FPDRnAddress = BA0_FPDR3;
4149                         break;
4150                 }
4151                 default:
4152                         break;
4153         }
4154         //
4155         // first read the hardware to initialize the member variables
4156         //
4157         p->u32FCRnValue = readl(s->pBA0 + p->u32FCRnAddress);
4158         p->u32FSICnValue = readl(s->pBA0 + p->u32FSICnAddress);
4159         p->u32FPDRnValue = readl(s->pBA0 + p->u32FPDRnAddress);
4160
4161 }
4162
4163 static void __devinit cs4281_BuildDMAengine(
4164         struct cs4281_pipeline *p,
4165         struct cs4281_state *s)
4166 {
4167 /*
4168 * initialize all the addresses of this pipeline dma info.
4169 */
4170         switch(p->number)
4171         {
4172                 case 0:  /* playback */
4173                 {
4174                         p->u32DBAnAddress = BA0_DBA0;
4175                         p->u32DCAnAddress = BA0_DCA0;
4176                         p->u32DBCnAddress = BA0_DBC0;
4177                         p->u32DCCnAddress = BA0_DCC0;
4178                         p->u32DMRnAddress = BA0_DMR0;
4179                         p->u32DCRnAddress = BA0_DCR0;
4180                         p->u32HDSRnAddress = BA0_HDSR0;
4181                         break;
4182                 }
4183
4184                 case 1: /* capture */
4185                 {
4186                         p->u32DBAnAddress = BA0_DBA1;
4187                         p->u32DCAnAddress = BA0_DCA1;
4188                         p->u32DBCnAddress = BA0_DBC1;
4189                         p->u32DCCnAddress = BA0_DCC1;
4190                         p->u32DMRnAddress = BA0_DMR1;
4191                         p->u32DCRnAddress = BA0_DCR1;
4192                         p->u32HDSRnAddress = BA0_HDSR1;
4193                         break;
4194                 }
4195
4196                 case 2:
4197                 {
4198                         p->u32DBAnAddress = BA0_DBA2;
4199                         p->u32DCAnAddress = BA0_DCA2;
4200                         p->u32DBCnAddress = BA0_DBC2;
4201                         p->u32DCCnAddress = BA0_DCC2;
4202                         p->u32DMRnAddress = BA0_DMR2;
4203                         p->u32DCRnAddress = BA0_DCR2;
4204                         p->u32HDSRnAddress = BA0_HDSR2;
4205                         break;
4206                 }
4207
4208                 case 3:
4209                 {
4210                         p->u32DBAnAddress = BA0_DBA3;
4211                         p->u32DCAnAddress = BA0_DCA3;
4212                         p->u32DBCnAddress = BA0_DBC3;
4213                         p->u32DCCnAddress = BA0_DCC3;
4214                         p->u32DMRnAddress = BA0_DMR3;
4215                         p->u32DCRnAddress = BA0_DCR3;
4216                         p->u32HDSRnAddress = BA0_HDSR3;
4217                         break;
4218                 }
4219                 default:
4220                         break;
4221         }
4222
4223 //
4224 // Initialize the dma values for this pipeline
4225 //
4226         p->u32DBAnValue = readl(s->pBA0 + p->u32DBAnAddress);
4227         p->u32DBCnValue = readl(s->pBA0 + p->u32DBCnAddress);
4228         p->u32DMRnValue = readl(s->pBA0 + p->u32DMRnAddress);
4229         p->u32DCRnValue = readl(s->pBA0 + p->u32DCRnAddress);
4230
4231 }
4232
4233 static void __devinit cs4281_InitPM(struct cs4281_state *s)
4234 {
4235         int i;
4236         struct cs4281_pipeline *p;
4237
4238         for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
4239         {
4240                 p = &s->pl[i];
4241                 p->number = i;
4242                 cs4281_BuildDMAengine(p,s);
4243                 cs4281_BuildFIFO(p,s);
4244         /*
4245         * currently only  2 pipelines are used
4246         * so, only set the valid bit on the playback and capture.
4247         */
4248                 if( (i == CS4281_PLAYBACK_PIPELINE_NUMBER) ||
4249                         (i == CS4281_CAPTURE_PIPELINE_NUMBER))
4250                         p->flags |= CS4281_PIPELINE_VALID;
4251         }
4252         s->pm.u32SSPM_BITS = 0x7e;  /* rev c, use 0x7c for rev a or b */
4253 }
4254 #endif
4255
4256 static int __devinit cs4281_probe(struct pci_dev *pcidev,
4257                                   const struct pci_device_id *pciid)
4258 {
4259 #ifndef NOT_CS4281_PM
4260         struct pm_dev *pmdev;
4261 #endif
4262         struct cs4281_state *s;
4263         dma_addr_t dma_mask;
4264         mm_segment_t fs;
4265         int i, val;
4266         unsigned int temp1, temp2;
4267
4268         CS_DBGOUT(CS_FUNCTION | CS_INIT, 2,
4269                   printk(KERN_INFO "cs4281: probe()+\n"));
4270
4271         if (pci_enable_device(pcidev)) {
4272                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4273                          "cs4281: pci_enable_device() failed\n"));
4274                 return -1;
4275         }
4276         if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM) ||
4277             !(pci_resource_flags(pcidev, 1) & IORESOURCE_MEM)) {
4278                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4279                          "cs4281: probe()- Memory region not assigned\n"));
4280                 return -ENODEV;
4281         }
4282         if (pcidev->irq == 0) {
4283                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4284                          "cs4281: probe() IRQ not assigned\n"));
4285                 return -ENODEV;
4286         }
4287         dma_mask = 0xffffffff;  /* this enables playback and recording */
4288         i = pci_set_dma_mask(pcidev, dma_mask);
4289         if (i) {
4290                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4291                       "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n"));
4292                 return i;
4293         }
4294         if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
4295                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4296                       "cs4281: probe() no memory for state struct.\n"));
4297                 return -1;
4298         }
4299         memset(s, 0, sizeof(struct cs4281_state));
4300         init_waitqueue_head(&s->dma_adc.wait);
4301         init_waitqueue_head(&s->dma_dac.wait);
4302         init_waitqueue_head(&s->open_wait);
4303         init_waitqueue_head(&s->open_wait_adc);
4304         init_waitqueue_head(&s->open_wait_dac);
4305         init_waitqueue_head(&s->midi.iwait);
4306         init_waitqueue_head(&s->midi.owait);
4307         init_MUTEX(&s->open_sem);
4308         init_MUTEX(&s->open_sem_adc);
4309         init_MUTEX(&s->open_sem_dac);
4310         spin_lock_init(&s->lock);
4311         s->pBA0phys = pci_resource_start(pcidev, 0);
4312         s->pBA1phys = pci_resource_start(pcidev, 1);
4313
4314         /* Convert phys to linear. */
4315         s->pBA0 = ioremap_nocache(s->pBA0phys, 4096);
4316         if (!s->pBA0) {
4317                 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4318                          "cs4281: BA0 I/O mapping failed. Skipping part.\n"));
4319                 goto err_free;
4320         }
4321         s->pBA1 = ioremap_nocache(s->pBA1phys, 65536);
4322         if (!s->pBA1) {
4323                 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4324                          "cs4281: BA1 I/O mapping failed. Skipping part.\n"));
4325                 goto err_unmap;
4326         }
4327
4328         temp1 = readl(s->pBA0 + BA0_PCICFG00);
4329         temp2 = readl(s->pBA0 + BA0_PCICFG04);
4330
4331         CS_DBGOUT(CS_INIT, 2,
4332                   printk(KERN_INFO
4333                          "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=%p pBA1=%p \n",
4334                          (unsigned) temp1, (unsigned) temp2, s->pBA0, s->pBA1));
4335         CS_DBGOUT(CS_INIT, 2,
4336                   printk(KERN_INFO
4337                          "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n",
4338                          (unsigned) s->pBA0phys, (unsigned) s->pBA1phys));
4339
4340 #ifndef NOT_CS4281_PM
4341         s->pm.flags = CS4281_PM_IDLE;
4342 #endif
4343         temp1 = cs4281_hw_init(s);
4344         if (temp1) {
4345                 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4346                          "cs4281: cs4281_hw_init() failed. Skipping part.\n"));
4347                 goto err_irq;
4348         }
4349         s->magic = CS4281_MAGIC;
4350         s->pcidev = pcidev;
4351         s->irq = pcidev->irq;
4352         if (request_irq
4353             (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) {
4354                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
4355                           printk(KERN_ERR "cs4281: irq %u in use\n", s->irq));
4356                 goto err_irq;
4357         }
4358         if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) <
4359             0) {
4360                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4361                          "cs4281: probe() register_sound_dsp() failed.\n"));
4362                 goto err_dev1;
4363         }
4364         if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) <
4365             0) {
4366                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4367                          "cs4281: probe() register_sound_mixer() failed.\n"));
4368                 goto err_dev2;
4369         }
4370         if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) {
4371                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4372                          "cs4281: probe() register_sound_midi() failed.\n"));
4373                 goto err_dev3;
4374         }
4375 #ifndef NOT_CS4281_PM
4376         cs4281_InitPM(s);
4377         pmdev = cs_pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev), cs4281_pm_callback);
4378         if (pmdev)
4379         {
4380                 CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO
4381                          "cs4281: probe() pm_register() succeeded (%p).\n", pmdev));
4382                 pmdev->data = s;
4383         }
4384         else
4385         {
4386                 CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO
4387                          "cs4281: probe() pm_register() failed (%p).\n", pmdev));
4388                 s->pm.flags |= CS4281_PM_NOT_REGISTERED;
4389         }
4390 #endif
4391
4392         pci_set_master(pcidev); // enable bus mastering
4393
4394         fs = get_fs();
4395         set_fs(KERNEL_DS);
4396         val = SOUND_MASK_LINE;
4397         mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
4398         for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
4399                 val = initvol[i].vol;
4400                 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
4401         }
4402         val = 1;                // enable mic preamp
4403         mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val);
4404         set_fs(fs);
4405
4406         pci_set_drvdata(pcidev, s);
4407         list_add(&s->list, &cs4281_devs);
4408         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4409                 "cs4281: probe()- device allocated successfully\n"));
4410         return 0;
4411
4412       err_dev3:
4413         unregister_sound_mixer(s->dev_mixer);
4414       err_dev2:
4415         unregister_sound_dsp(s->dev_audio);
4416       err_dev1:
4417         free_irq(s->irq, s);
4418       err_irq:
4419         iounmap(s->pBA1);
4420       err_unmap:
4421         iounmap(s->pBA0);
4422       err_free:
4423         kfree(s);
4424
4425         CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
4426                 "cs4281: probe()- no device allocated\n"));
4427         return -ENODEV;
4428 } // probe_cs4281
4429
4430
4431 // ---------------------------------------------------------------------
4432
4433 static void __devexit cs4281_remove(struct pci_dev *pci_dev)
4434 {
4435         struct cs4281_state *s = pci_get_drvdata(pci_dev);
4436         // stop DMA controller
4437         synchronize_irq(s->irq);
4438         free_irq(s->irq, s);
4439         unregister_sound_dsp(s->dev_audio);
4440         unregister_sound_mixer(s->dev_mixer);
4441         unregister_sound_midi(s->dev_midi);
4442         iounmap(s->pBA1);
4443         iounmap(s->pBA0);
4444         pci_set_drvdata(pci_dev,NULL);
4445         list_del(&s->list);
4446         kfree(s);
4447         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4448                  "cs4281: cs4281_remove()-: remove successful\n"));
4449 }
4450
4451 static struct pci_device_id cs4281_pci_tbl[] = {
4452         {
4453                 .vendor    = PCI_VENDOR_ID_CIRRUS,
4454                 .device    = PCI_DEVICE_ID_CRYSTAL_CS4281,
4455                 .subvendor = PCI_ANY_ID,
4456                 .subdevice = PCI_ANY_ID,
4457         },
4458         { 0, },
4459 };
4460
4461 MODULE_DEVICE_TABLE(pci, cs4281_pci_tbl);
4462
4463 static struct pci_driver cs4281_pci_driver = {
4464         .name     = "cs4281",
4465         .id_table = cs4281_pci_tbl,
4466         .probe    = cs4281_probe,
4467         .remove   = __devexit_p(cs4281_remove),
4468         .suspend  = CS4281_SUSPEND_TBL,
4469         .resume   = CS4281_RESUME_TBL,
4470 };
4471
4472 static int __init cs4281_init_module(void)
4473 {
4474         int rtn = 0;
4475         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4476                 "cs4281: cs4281_init_module()+ \n"));
4477         printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " "
4478                __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION,
4479                CS4281_ARCH);
4480         rtn = pci_module_init(&cs4281_pci_driver);
4481
4482         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4483                   printk(KERN_INFO "cs4281: cs4281_init_module()- (%d)\n",rtn));
4484         return rtn;
4485 }
4486
4487 static void __exit cs4281_cleanup_module(void)
4488 {
4489         pci_unregister_driver(&cs4281_pci_driver);
4490 #ifndef NOT_CS4281_PM
4491         cs_pm_unregister_all(cs4281_pm_callback);
4492 #endif
4493         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4494                   printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n"));
4495 }
4496 // ---------------------------------------------------------------------
4497
4498 MODULE_AUTHOR("gw boynton, audio@crystal.cirrus.com");
4499 MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
4500 MODULE_LICENSE("GPL");
4501
4502 // ---------------------------------------------------------------------
4503
4504 module_init(cs4281_init_module);
4505 module_exit(cs4281_cleanup_module);
4506