2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/spinlock.h>
29 #include <linux/module.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/phy.h>
36 #include <asm/uaccess.h>
38 #define MII_M1011_IEVENT 0x13
39 #define MII_M1011_IEVENT_CLEAR 0x0000
41 #define MII_M1011_IMASK 0x12
42 #define MII_M1011_IMASK_INIT 0x6400
43 #define MII_M1011_IMASK_CLEAR 0x0000
45 #define MII_M1011_PHY_SCR 0x10
46 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
48 #define MII_M1145_PHY_EXT_CR 0x14
49 #define MII_M1145_RGMII_RX_DELAY 0x0080
50 #define MII_M1145_RGMII_TX_DELAY 0x0002
52 #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
54 #define MII_M1111_PHY_LED_CONTROL 0x18
55 #define MII_M1111_PHY_LED_DIRECT 0x4100
56 #define MII_M1111_PHY_LED_COMBINE 0x411c
57 #define MII_M1111_PHY_EXT_CR 0x14
58 #define MII_M1111_RX_DELAY 0x80
59 #define MII_M1111_TX_DELAY 0x2
60 #define MII_M1111_PHY_EXT_SR 0x1b
62 #define MII_M1111_HWCFG_MODE_MASK 0xf
63 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
64 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
65 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
66 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
67 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
69 #define MII_M1111_COPPER 0
70 #define MII_M1111_FIBER 1
72 #define MII_M1011_PHY_STATUS 0x11
73 #define MII_M1011_PHY_STATUS_1000 0x8000
74 #define MII_M1011_PHY_STATUS_100 0x4000
75 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
76 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
77 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
78 #define MII_M1011_PHY_STATUS_LINK 0x0400
81 MODULE_DESCRIPTION("Marvell PHY driver");
82 MODULE_AUTHOR("Andy Fleming");
83 MODULE_LICENSE("GPL");
85 static int marvell_ack_interrupt(struct phy_device *phydev)
89 /* Clear the interrupts by reading the reg */
90 err = phy_read(phydev, MII_M1011_IEVENT);
98 static int marvell_config_intr(struct phy_device *phydev)
102 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
103 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
105 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
110 static int marvell_config_aneg(struct phy_device *phydev)
114 /* The Marvell PHY has an errata which requires
115 * that certain registers get written in order
116 * to restart autonegotiation */
117 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
122 err = phy_write(phydev, 0x1d, 0x1f);
126 err = phy_write(phydev, 0x1e, 0x200c);
130 err = phy_write(phydev, 0x1d, 0x5);
134 err = phy_write(phydev, 0x1e, 0);
138 err = phy_write(phydev, 0x1e, 0x100);
142 err = phy_write(phydev, MII_M1011_PHY_SCR,
143 MII_M1011_PHY_SCR_AUTO_CROSS);
147 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
148 MII_M1111_PHY_LED_DIRECT);
152 err = genphy_config_aneg(phydev);
157 static int m88e1111_config_init(struct phy_device *phydev)
162 /* Enable Fiber/Copper auto selection */
163 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
164 temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
165 phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
167 temp = phy_read(phydev, MII_BMCR);
169 phy_write(phydev, MII_BMCR, temp);
171 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
172 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
173 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
174 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
176 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
180 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
181 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
182 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
183 temp &= ~MII_M1111_TX_DELAY;
184 temp |= MII_M1111_RX_DELAY;
185 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
186 temp &= ~MII_M1111_RX_DELAY;
187 temp |= MII_M1111_TX_DELAY;
190 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
194 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
198 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
200 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
201 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
203 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
205 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
210 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
211 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
215 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
216 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
218 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
223 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
230 static int m88e1118_config_aneg(struct phy_device *phydev)
234 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
238 err = phy_write(phydev, MII_M1011_PHY_SCR,
239 MII_M1011_PHY_SCR_AUTO_CROSS);
243 err = genphy_config_aneg(phydev);
247 static int m88e1118_config_init(struct phy_device *phydev)
252 err = phy_write(phydev, 0x16, 0x0002);
256 /* Enable 1000 Mbit */
257 err = phy_write(phydev, 0x15, 0x1070);
262 err = phy_write(phydev, 0x16, 0x0003);
266 /* Adjust LED Control */
267 err = phy_write(phydev, 0x10, 0x021e);
272 err = phy_write(phydev, 0x16, 0x0);
276 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
283 static int m88e1145_config_init(struct phy_device *phydev)
287 /* Take care of errata E0 & E1 */
288 err = phy_write(phydev, 0x1d, 0x001b);
292 err = phy_write(phydev, 0x1e, 0x418f);
296 err = phy_write(phydev, 0x1d, 0x0016);
300 err = phy_write(phydev, 0x1e, 0xa2da);
304 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
305 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
309 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
311 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
315 if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
316 err = phy_write(phydev, 0x1d, 0x0012);
320 temp = phy_read(phydev, 0x1e);
325 temp |= 2 << 9; /* 36 ohm */
326 temp |= 2 << 6; /* 39 ohm */
328 err = phy_write(phydev, 0x1e, temp);
332 err = phy_write(phydev, 0x1d, 0x3);
336 err = phy_write(phydev, 0x1e, 0x8000);
345 /* marvell_read_status
347 * Generic status code does not detect Fiber correctly!
349 * Check the link, then figure out the current state
350 * by comparing what we advertise with what the link partner
351 * advertises. Start by checking the gigabit possibilities,
352 * then move on to 10/100.
354 static int marvell_read_status(struct phy_device *phydev)
361 /* Update the link, but return if there
363 err = genphy_update_link(phydev);
367 if (AUTONEG_ENABLE == phydev->autoneg) {
368 status = phy_read(phydev, MII_M1011_PHY_STATUS);
372 lpa = phy_read(phydev, MII_LPA);
376 adv = phy_read(phydev, MII_ADVERTISE);
382 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
383 phydev->duplex = DUPLEX_FULL;
385 phydev->duplex = DUPLEX_HALF;
387 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
388 phydev->pause = phydev->asym_pause = 0;
391 case MII_M1011_PHY_STATUS_1000:
392 phydev->speed = SPEED_1000;
395 case MII_M1011_PHY_STATUS_100:
396 phydev->speed = SPEED_100;
400 phydev->speed = SPEED_10;
404 if (phydev->duplex == DUPLEX_FULL) {
405 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
406 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
409 int bmcr = phy_read(phydev, MII_BMCR);
414 if (bmcr & BMCR_FULLDPLX)
415 phydev->duplex = DUPLEX_FULL;
417 phydev->duplex = DUPLEX_HALF;
419 if (bmcr & BMCR_SPEED1000)
420 phydev->speed = SPEED_1000;
421 else if (bmcr & BMCR_SPEED100)
422 phydev->speed = SPEED_100;
424 phydev->speed = SPEED_10;
426 phydev->pause = phydev->asym_pause = 0;
432 static struct phy_driver marvell_drivers[] = {
434 .phy_id = 0x01410c60,
435 .phy_id_mask = 0xfffffff0,
436 .name = "Marvell 88E1101",
437 .features = PHY_GBIT_FEATURES,
438 .flags = PHY_HAS_INTERRUPT,
439 .config_aneg = &marvell_config_aneg,
440 .read_status = &genphy_read_status,
441 .ack_interrupt = &marvell_ack_interrupt,
442 .config_intr = &marvell_config_intr,
443 .driver = { .owner = THIS_MODULE },
446 .phy_id = 0x01410c90,
447 .phy_id_mask = 0xfffffff0,
448 .name = "Marvell 88E1112",
449 .features = PHY_GBIT_FEATURES,
450 .flags = PHY_HAS_INTERRUPT,
451 .config_init = &m88e1111_config_init,
452 .config_aneg = &marvell_config_aneg,
453 .read_status = &genphy_read_status,
454 .ack_interrupt = &marvell_ack_interrupt,
455 .config_intr = &marvell_config_intr,
456 .driver = { .owner = THIS_MODULE },
459 .phy_id = 0x01410cc0,
460 .phy_id_mask = 0xfffffff0,
461 .name = "Marvell 88E1111",
462 .features = PHY_GBIT_FEATURES,
463 .flags = PHY_HAS_INTERRUPT,
464 .config_init = &m88e1111_config_init,
465 .config_aneg = &marvell_config_aneg,
466 .read_status = &marvell_read_status,
467 .ack_interrupt = &marvell_ack_interrupt,
468 .config_intr = &marvell_config_intr,
469 .driver = { .owner = THIS_MODULE },
472 .phy_id = 0x01410e10,
473 .phy_id_mask = 0xfffffff0,
474 .name = "Marvell 88E1118",
475 .features = PHY_GBIT_FEATURES,
476 .flags = PHY_HAS_INTERRUPT,
477 .config_init = &m88e1118_config_init,
478 .config_aneg = &m88e1118_config_aneg,
479 .read_status = &genphy_read_status,
480 .ack_interrupt = &marvell_ack_interrupt,
481 .config_intr = &marvell_config_intr,
482 .driver = {.owner = THIS_MODULE,},
485 .phy_id = 0x01410cd0,
486 .phy_id_mask = 0xfffffff0,
487 .name = "Marvell 88E1145",
488 .features = PHY_GBIT_FEATURES,
489 .flags = PHY_HAS_INTERRUPT,
490 .config_init = &m88e1145_config_init,
491 .config_aneg = &marvell_config_aneg,
492 .read_status = &genphy_read_status,
493 .ack_interrupt = &marvell_ack_interrupt,
494 .config_intr = &marvell_config_intr,
495 .driver = { .owner = THIS_MODULE },
498 .phy_id = 0x01410e30,
499 .phy_id_mask = 0xfffffff0,
500 .name = "Marvell 88E1240",
501 .features = PHY_GBIT_FEATURES,
502 .flags = PHY_HAS_INTERRUPT,
503 .config_init = &m88e1111_config_init,
504 .config_aneg = &marvell_config_aneg,
505 .read_status = &genphy_read_status,
506 .ack_interrupt = &marvell_ack_interrupt,
507 .config_intr = &marvell_config_intr,
508 .driver = { .owner = THIS_MODULE },
512 static int __init marvell_init(void)
517 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
518 ret = phy_driver_register(&marvell_drivers[i]);
522 phy_driver_unregister(&marvell_drivers[i]);
530 static void __exit marvell_exit(void)
534 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
535 phy_driver_unregister(&marvell_drivers[i]);
538 module_init(marvell_init);
539 module_exit(marvell_exit);