2 * Copyright 2004 James Cleverdon, IBM.
3 * Subject to the GNU Public License, v.2
5 * Flat APIC subarch code.
7 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
8 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
11 #include <linux/errno.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/hardirq.h>
21 #include <asm/genapic.h>
22 #include <mach_apicdef.h>
25 #include <acpi/acpi_bus.h>
28 static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
33 static const struct cpumask *flat_target_cpus(void)
35 return cpu_online_mask;
38 static void flat_vector_allocation_domain(int cpu, struct cpumask *retmask)
40 /* Careful. Some cpus do not strictly honor the set of cpus
41 * specified in the interrupt destination when using lowest
42 * priority interrupt delivery mode.
44 * In particular there was a hyperthreading cpu observed to
45 * deliver interrupts to the wrong hyperthread when only one
46 * hyperthread was specified in the interrupt desitination.
48 cpumask_clear(retmask);
49 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
53 * Set up the logical destination ID.
55 * Intel recommends to set DFR, LDR and TPR before enabling
56 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
57 * document number 292116). So here it goes...
59 static void flat_init_apic_ldr(void)
62 unsigned long num, id;
64 num = smp_processor_id();
66 apic_write(APIC_DFR, APIC_DFR_FLAT);
67 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
68 val |= SET_APIC_LOGICAL_ID(id);
69 apic_write(APIC_LDR, val);
72 static inline void _flat_send_IPI_mask(unsigned long mask, int vector)
76 local_irq_save(flags);
77 __send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL);
78 local_irq_restore(flags);
81 static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector)
83 unsigned long mask = cpumask_bits(cpumask)[0];
85 _flat_send_IPI_mask(mask, vector);
88 static void flat_send_IPI_mask_allbutself(const struct cpumask *cpumask,
91 unsigned long mask = cpumask_bits(cpumask)[0];
92 int cpu = smp_processor_id();
94 if (cpu < BITS_PER_LONG)
95 clear_bit(cpu, &mask);
96 _flat_send_IPI_mask(mask, vector);
99 static void flat_send_IPI_allbutself(int vector)
101 int cpu = smp_processor_id();
102 #ifdef CONFIG_HOTPLUG_CPU
107 if (hotplug || vector == NMI_VECTOR) {
108 if (!cpumask_equal(cpu_online_mask, cpumask_of(cpu))) {
109 unsigned long mask = cpumask_bits(cpu_online_mask)[0];
111 if (cpu < BITS_PER_LONG)
112 clear_bit(cpu, &mask);
114 _flat_send_IPI_mask(mask, vector);
116 } else if (num_online_cpus() > 1) {
117 __send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
121 static void flat_send_IPI_all(int vector)
123 if (vector == NMI_VECTOR)
124 flat_send_IPI_mask(cpu_online_mask, vector);
126 __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
129 static unsigned int get_apic_id(unsigned long x)
133 id = (((x)>>24) & 0xFFu);
137 static unsigned long set_apic_id(unsigned int id)
141 x = ((id & 0xFFu)<<24);
145 static unsigned int read_xapic_id(void)
149 id = get_apic_id(apic_read(APIC_ID));
153 static int flat_apic_id_registered(void)
155 return physid_isset(read_xapic_id(), phys_cpu_present_map);
158 static unsigned int flat_cpu_mask_to_apicid(const struct cpumask *cpumask)
160 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
163 static unsigned int flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
164 const struct cpumask *andmask)
166 unsigned long mask1 = cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
167 unsigned long mask2 = cpumask_bits(andmask)[0] & APIC_ALL_CPUS;
169 return mask1 & mask2;
172 static unsigned int phys_pkg_id(int index_msb)
174 return hard_smp_processor_id() >> index_msb;
177 struct genapic apic_flat = {
179 .acpi_madt_oem_check = flat_acpi_madt_oem_check,
180 .int_delivery_mode = dest_LowestPrio,
181 .int_dest_mode = (APIC_DEST_LOGICAL != 0),
182 .target_cpus = flat_target_cpus,
183 .vector_allocation_domain = flat_vector_allocation_domain,
184 .apic_id_registered = flat_apic_id_registered,
185 .init_apic_ldr = flat_init_apic_ldr,
186 .send_IPI_all = flat_send_IPI_all,
187 .send_IPI_allbutself = flat_send_IPI_allbutself,
188 .send_IPI_mask = flat_send_IPI_mask,
189 .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself,
190 .send_IPI_self = apic_send_IPI_self,
191 .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
192 .cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and,
193 .phys_pkg_id = phys_pkg_id,
194 .get_apic_id = get_apic_id,
195 .set_apic_id = set_apic_id,
196 .apic_id_mask = (0xFFu<<24),
200 * Physflat mode is used when there are more than 8 CPUs on a AMD system.
201 * We cannot use logical delivery in this case because the mask
202 * overflows, so use physical mode.
204 static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
208 * Quirk: some x86_64 machines can only use physical APIC mode
209 * regardless of how many processors are present (x86_64 ES7000
212 if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
213 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
214 printk(KERN_DEBUG "system APIC only can use physical flat");
222 static const struct cpumask *physflat_target_cpus(void)
224 return cpu_online_mask;
227 static void physflat_vector_allocation_domain(int cpu, struct cpumask *retmask)
229 cpumask_clear(retmask);
230 cpumask_set_cpu(cpu, retmask);
233 static void physflat_send_IPI_mask(const struct cpumask *cpumask, int vector)
235 send_IPI_mask_sequence(cpumask, vector);
238 static void physflat_send_IPI_mask_allbutself(const struct cpumask *cpumask,
241 send_IPI_mask_allbutself(cpumask, vector);
244 static void physflat_send_IPI_allbutself(int vector)
246 send_IPI_mask_allbutself(cpu_online_mask, vector);
249 static void physflat_send_IPI_all(int vector)
251 physflat_send_IPI_mask(cpu_online_mask, vector);
254 static unsigned int physflat_cpu_mask_to_apicid(const struct cpumask *cpumask)
259 * We're using fixed IRQ delivery, can only return one phys APIC ID.
260 * May as well be the first.
262 cpu = cpumask_first(cpumask);
263 if ((unsigned)cpu < nr_cpu_ids)
264 return per_cpu(x86_cpu_to_apicid, cpu);
270 physflat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
271 const struct cpumask *andmask)
276 * We're using fixed IRQ delivery, can only return one phys APIC ID.
277 * May as well be the first.
279 for_each_cpu_and(cpu, cpumask, andmask)
280 if (cpumask_test_cpu(cpu, cpu_online_mask))
282 if (cpu < nr_cpu_ids)
283 return per_cpu(x86_cpu_to_apicid, cpu);
287 struct genapic apic_physflat = {
288 .name = "physical flat",
289 .acpi_madt_oem_check = physflat_acpi_madt_oem_check,
290 .int_delivery_mode = dest_Fixed,
291 .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
292 .target_cpus = physflat_target_cpus,
293 .vector_allocation_domain = physflat_vector_allocation_domain,
294 .apic_id_registered = flat_apic_id_registered,
295 .init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
296 .send_IPI_all = physflat_send_IPI_all,
297 .send_IPI_allbutself = physflat_send_IPI_allbutself,
298 .send_IPI_mask = physflat_send_IPI_mask,
299 .send_IPI_mask_allbutself = physflat_send_IPI_mask_allbutself,
300 .send_IPI_self = apic_send_IPI_self,
301 .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
302 .cpu_mask_to_apicid_and = physflat_cpu_mask_to_apicid_and,
303 .phys_pkg_id = phys_pkg_id,
304 .get_apic_id = get_apic_id,
305 .set_apic_id = set_apic_id,
306 .apic_id_mask = (0xFFu<<24),