git.oblomov.eu Git - linux-2.6/blob - drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/mii.h>
  38 #include <linux/ethtool.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/pci.h>
  41 #include <linux/pci-aspm.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/aer.h>
  46 #ifdef CONFIG_IGB_DCA
  47 #include <linux/dca.h>
  48 #endif
  49 #include "igb.h"
  50
  51 #define DRV_VERSION "1.2.45-k2"
  52 char igb_driver_name[] = "igb";
  53 char igb_driver_version[] = DRV_VERSION;
  54 static const char igb_driver_string[] =
  55                                 "Intel(R) Gigabit Ethernet Network Driver";
  56 static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
  57
  58 static const struct e1000_info *igb_info_tbl[] = {
  59         [board_82575] = &e1000_82575_info,
  60 };
  61
  62 static struct pci_device_id igb_pci_tbl[] = {
  63         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  69         /* required last entry */
  70         {0, }
  71 };
  72
  73 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  74
  75 void igb_reset(struct igb_adapter *);
  76 static int igb_setup_all_tx_resources(struct igb_adapter *);
  77 static int igb_setup_all_rx_resources(struct igb_adapter *);
  78 static void igb_free_all_tx_resources(struct igb_adapter *);
  79 static void igb_free_all_rx_resources(struct igb_adapter *);
  80 void igb_update_stats(struct igb_adapter *);
  81 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  82 static void __devexit igb_remove(struct pci_dev *pdev);
  83 static int igb_sw_init(struct igb_adapter *);
  84 static int igb_open(struct net_device *);
  85 static int igb_close(struct net_device *);
  86 static void igb_configure_tx(struct igb_adapter *);
  87 static void igb_configure_rx(struct igb_adapter *);
  88 static void igb_setup_rctl(struct igb_adapter *);
  89 static void igb_clean_all_tx_rings(struct igb_adapter *);
  90 static void igb_clean_all_rx_rings(struct igb_adapter *);
  91 static void igb_clean_tx_ring(struct igb_ring *);
  92 static void igb_clean_rx_ring(struct igb_ring *);
  93 static void igb_set_multi(struct net_device *);
  94 static void igb_update_phy_info(unsigned long);
  95 static void igb_watchdog(unsigned long);
  96 static void igb_watchdog_task(struct work_struct *);
  97 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
  98                                   struct igb_ring *);
  99 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 100 static struct net_device_stats *igb_get_stats(struct net_device *);
 101 static int igb_change_mtu(struct net_device *, int);
 102 static int igb_set_mac(struct net_device *, void *);
 103 static irqreturn_t igb_intr(int irq, void *);
 104 static irqreturn_t igb_intr_msi(int irq, void *);
 105 static irqreturn_t igb_msix_other(int irq, void *);
 106 static irqreturn_t igb_msix_rx(int irq, void *);
 107 static irqreturn_t igb_msix_tx(int irq, void *);
 108 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
 109 #ifdef CONFIG_IGB_DCA
 110 static void igb_update_rx_dca(struct igb_ring *);
 111 static void igb_update_tx_dca(struct igb_ring *);
 112 static void igb_setup_dca(struct igb_adapter *);
 113 #endif /* CONFIG_IGB_DCA */
 114 static bool igb_clean_tx_irq(struct igb_ring *);
 115 static int igb_poll(struct napi_struct *, int);
 116 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 117 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 118 #ifdef CONFIG_IGB_LRO
 119 static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
 120 #endif
 121 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 122 static void igb_tx_timeout(struct net_device *);
 123 static void igb_reset_task(struct work_struct *);
 124 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 125 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 126 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 127 static void igb_restore_vlan(struct igb_adapter *);
 128
 129 static int igb_suspend(struct pci_dev *, pm_message_t);
 130 #ifdef CONFIG_PM
 131 static int igb_resume(struct pci_dev *);
 132 #endif
 133 static void igb_shutdown(struct pci_dev *);
 134 #ifdef CONFIG_IGB_DCA
 135 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 136 static struct notifier_block dca_notifier = {
 137         .notifier_call  = igb_notify_dca,
 138         .next           = NULL,
 139         .priority       = 0
 140 };
 141 #endif
 142
 143 #ifdef CONFIG_NET_POLL_CONTROLLER
 144 /* for netdump / net console */
 145 static void igb_netpoll(struct net_device *);
 146 #endif
 147
 148 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 149                      pci_channel_state_t);
 150 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 151 static void igb_io_resume(struct pci_dev *);
 152
 153 static struct pci_error_handlers igb_err_handler = {
 154         .error_detected = igb_io_error_detected,
 155         .slot_reset = igb_io_slot_reset,
 156         .resume = igb_io_resume,
 157 };
 158
 159
 160 static struct pci_driver igb_driver = {
 161         .name     = igb_driver_name,
 162         .id_table = igb_pci_tbl,
 163         .probe    = igb_probe,
 164         .remove   = __devexit_p(igb_remove),
 165 #ifdef CONFIG_PM
 166         /* Power Managment Hooks */
 167         .suspend  = igb_suspend,
 168         .resume   = igb_resume,
 169 #endif
 170         .shutdown = igb_shutdown,
 171         .err_handler = &igb_err_handler
 172 };
 173
 174 static int global_quad_port_a; /* global quad port a indication */
 175
 176 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 177 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 178 MODULE_LICENSE("GPL");
 179 MODULE_VERSION(DRV_VERSION);
 180
 181 #ifdef DEBUG
 182 /**
 183  * igb_get_hw_dev_name - return device name string
 184  * used by hardware layer to print debugging information
 185  **/
 186 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 187 {
 188         struct igb_adapter *adapter = hw->back;
 189         return adapter->netdev->name;
 190 }
 191 #endif
 192
 193 /**
 194  * igb_init_module - Driver Registration Routine
 195  *
 196  * igb_init_module is the first routine called when the driver is
 197  * loaded. All it does is register with the PCI subsystem.
 198  **/
 199 static int __init igb_init_module(void)
 200 {
 201         int ret;
 202         printk(KERN_INFO "%s - version %s\n",
 203                igb_driver_string, igb_driver_version);
 204
 205         printk(KERN_INFO "%s\n", igb_copyright);
 206
 207         global_quad_port_a = 0;
 208
 209         ret = pci_register_driver(&igb_driver);
 210 #ifdef CONFIG_IGB_DCA
 211         dca_register_notify(&dca_notifier);
 212 #endif
 213         return ret;
 214 }
 215
 216 module_init(igb_init_module);
 217
 218 /**
 219  * igb_exit_module - Driver Exit Cleanup Routine
 220  *
 221  * igb_exit_module is called just before the driver is removed
 222  * from memory.
 223  **/
 224 static void __exit igb_exit_module(void)
 225 {
 226 #ifdef CONFIG_IGB_DCA
 227         dca_unregister_notify(&dca_notifier);
 228 #endif
 229         pci_unregister_driver(&igb_driver);
 230 }
 231
 232 module_exit(igb_exit_module);
 233
 234 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 235 /**
 236  * igb_cache_ring_register - Descriptor ring to register mapping
 237  * @adapter: board private structure to initialize
 238  *
 239  * Once we know the feature-set enabled for the device, we'll cache
 240  * the register offset the descriptor ring is assigned to.
 241  **/
 242 static void igb_cache_ring_register(struct igb_adapter *adapter)
 243 {
 244         int i;
 245
 246         switch (adapter->hw.mac.type) {
 247         case e1000_82576:
 248                 /* The queues are allocated for virtualization such that VF 0
 249                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 250                  * In order to avoid collision we start at the first free queue
 251                  * and continue consuming queues in the same sequence
 252                  */
 253                 for (i = 0; i < adapter->num_rx_queues; i++)
 254                         adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
 255                 for (i = 0; i < adapter->num_tx_queues; i++)
 256                         adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
 257                 break;
 258         case e1000_82575:
 259         default:
 260                 for (i = 0; i < adapter->num_rx_queues; i++)
 261                         adapter->rx_ring[i].reg_idx = i;
 262                 for (i = 0; i < adapter->num_tx_queues; i++)
 263                         adapter->tx_ring[i].reg_idx = i;
 264                 break;
 265         }
 266 }
 267
 268 /**
 269  * igb_alloc_queues - Allocate memory for all rings
 270  * @adapter: board private structure to initialize
 271  *
 272  * We allocate one ring per queue at run-time since we don't know the
 273  * number of queues at compile-time.
 274  **/
 275 static int igb_alloc_queues(struct igb_adapter *adapter)
 276 {
 277         int i;
 278
 279         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 280                                    sizeof(struct igb_ring), GFP_KERNEL);
 281         if (!adapter->tx_ring)
 282                 return -ENOMEM;
 283
 284         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 285                                    sizeof(struct igb_ring), GFP_KERNEL);
 286         if (!adapter->rx_ring) {
 287                 kfree(adapter->tx_ring);
 288                 return -ENOMEM;
 289         }
 290
 291         adapter->rx_ring->buddy = adapter->tx_ring;
 292
 293         for (i = 0; i < adapter->num_tx_queues; i++) {
 294                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 295                 ring->count = adapter->tx_ring_count;
 296                 ring->adapter = adapter;
 297                 ring->queue_index = i;
 298         }
 299         for (i = 0; i < adapter->num_rx_queues; i++) {
 300                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 301                 ring->count = adapter->rx_ring_count;
 302                 ring->adapter = adapter;
 303                 ring->queue_index = i;
 304                 ring->itr_register = E1000_ITR;
 305
 306                 /* set a default napi handler for each rx_ring */
 307                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 308         }
 309
 310         igb_cache_ring_register(adapter);
 311         return 0;
 312 }
 313
 314 static void igb_free_queues(struct igb_adapter *adapter)
 315 {
 316         int i;
 317
 318         for (i = 0; i < adapter->num_rx_queues; i++)
 319                 netif_napi_del(&adapter->rx_ring[i].napi);
 320
 321         kfree(adapter->tx_ring);
 322         kfree(adapter->rx_ring);
 323 }
 324
 325 #define IGB_N0_QUEUE -1
 326 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 327                               int tx_queue, int msix_vector)
 328 {
 329         u32 msixbm = 0;
 330         struct e1000_hw *hw = &adapter->hw;
 331         u32 ivar, index;
 332
 333         switch (hw->mac.type) {
 334         case e1000_82575:
 335                 /* The 82575 assigns vectors using a bitmask, which matches the
 336                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 337                    or more queues to a vector, we write the appropriate bits
 338                    into the MSIXBM register for that vector. */
 339                 if (rx_queue > IGB_N0_QUEUE) {
 340                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 341                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 342                 }
 343                 if (tx_queue > IGB_N0_QUEUE) {
 344                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 345                         adapter->tx_ring[tx_queue].eims_value =
 346                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 347                 }
 348                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 349                 break;
 350         case e1000_82576:
 351                 /* 82576 uses a table-based method for assigning vectors.
 352                    Each queue has a single entry in the table to which we write
 353                    a vector number along with a "valid" bit.  Sadly, the layout
 354                    of the table is somewhat counterintuitive. */
 355                 if (rx_queue > IGB_N0_QUEUE) {
 356                         index = (rx_queue >> 1);
 357                         ivar = array_rd32(E1000_IVAR0, index);
 358                         if (rx_queue & 0x1) {
 359                                 /* vector goes into third byte of register */
 360                                 ivar = ivar & 0xFF00FFFF;
 361                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 362                         } else {
 363                                 /* vector goes into low byte of register */
 364                                 ivar = ivar & 0xFFFFFF00;
 365                                 ivar |= msix_vector | E1000_IVAR_VALID;
 366                         }
 367                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 368                         array_wr32(E1000_IVAR0, index, ivar);
 369                 }
 370                 if (tx_queue > IGB_N0_QUEUE) {
 371                         index = (tx_queue >> 1);
 372                         ivar = array_rd32(E1000_IVAR0, index);
 373                         if (tx_queue & 0x1) {
 374                                 /* vector goes into high byte of register */
 375                                 ivar = ivar & 0x00FFFFFF;
 376                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 377                         } else {
 378                                 /* vector goes into second byte of register */
 379                                 ivar = ivar & 0xFFFF00FF;
 380                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 381                         }
 382                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 383                         array_wr32(E1000_IVAR0, index, ivar);
 384                 }
 385                 break;
 386         default:
 387                 BUG();
 388                 break;
 389         }
 390 }
 391
 392 /**
 393  * igb_configure_msix - Configure MSI-X hardware
 394  *
 395  * igb_configure_msix sets up the hardware to properly
 396  * generate MSI-X interrupts.
 397  **/
 398 static void igb_configure_msix(struct igb_adapter *adapter)
 399 {
 400         u32 tmp;
 401         int i, vector = 0;
 402         struct e1000_hw *hw = &adapter->hw;
 403
 404         adapter->eims_enable_mask = 0;
 405         if (hw->mac.type == e1000_82576)
 406                 /* Turn on MSI-X capability first, or our settings
 407                  * won't stick.  And it will take days to debug. */
 408                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 409                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 410                                    E1000_GPIE_NSICR);
 411
 412         for (i = 0; i < adapter->num_tx_queues; i++) {
 413                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 414                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 415                 adapter->eims_enable_mask |= tx_ring->eims_value;
 416                 if (tx_ring->itr_val)
 417                         writel(tx_ring->itr_val,
 418                                hw->hw_addr + tx_ring->itr_register);
 419                 else
 420                         writel(1, hw->hw_addr + tx_ring->itr_register);
 421         }
 422
 423         for (i = 0; i < adapter->num_rx_queues; i++) {
 424                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 425                 rx_ring->buddy = NULL;
 426                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 427                 adapter->eims_enable_mask |= rx_ring->eims_value;
 428                 if (rx_ring->itr_val)
 429                         writel(rx_ring->itr_val,
 430                                hw->hw_addr + rx_ring->itr_register);
 431                 else
 432                         writel(1, hw->hw_addr + rx_ring->itr_register);
 433         }
 434
 435
 436         /* set vector for other causes, i.e. link changes */
 437         switch (hw->mac.type) {
 438         case e1000_82575:
 439                 array_wr32(E1000_MSIXBM(0), vector++,
 440                                       E1000_EIMS_OTHER);
 441
 442                 tmp = rd32(E1000_CTRL_EXT);
 443                 /* enable MSI-X PBA support*/
 444                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 445
 446                 /* Auto-Mask interrupts upon ICR read. */
 447                 tmp |= E1000_CTRL_EXT_EIAME;
 448                 tmp |= E1000_CTRL_EXT_IRCA;
 449
 450                 wr32(E1000_CTRL_EXT, tmp);
 451                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 452                 adapter->eims_other = E1000_EIMS_OTHER;
 453
 454                 break;
 455
 456         case e1000_82576:
 457                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 458                 wr32(E1000_IVAR_MISC, tmp);
 459
 460                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 461                 adapter->eims_other = 1 << (vector - 1);
 462                 break;
 463         default:
 464                 /* do nothing, since nothing else supports MSI-X */
 465                 break;
 466         } /* switch (hw->mac.type) */
 467         wrfl();
 468 }
 469
 470 /**
 471  * igb_request_msix - Initialize MSI-X interrupts
 472  *
 473  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 474  * kernel.
 475  **/
 476 static int igb_request_msix(struct igb_adapter *adapter)
 477 {
 478         struct net_device *netdev = adapter->netdev;
 479         int i, err = 0, vector = 0;
 480
 481         vector = 0;
 482
 483         for (i = 0; i < adapter->num_tx_queues; i++) {
 484                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 485                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 486                 err = request_irq(adapter->msix_entries[vector].vector,
 487                                   &igb_msix_tx, 0, ring->name,
 488                                   &(adapter->tx_ring[i]));
 489                 if (err)
 490                         goto out;
 491                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 492                 ring->itr_val = 976; /* ~4000 ints/sec */
 493                 vector++;
 494         }
 495         for (i = 0; i < adapter->num_rx_queues; i++) {
 496                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 497                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 498                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 499                 else
 500                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 501                 err = request_irq(adapter->msix_entries[vector].vector,
 502                                   &igb_msix_rx, 0, ring->name,
 503                                   &(adapter->rx_ring[i]));
 504                 if (err)
 505                         goto out;
 506                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 507                 ring->itr_val = adapter->itr;
 508                 /* overwrite the poll routine for MSIX, we've already done
 509                  * netif_napi_add */
 510                 ring->napi.poll = &igb_clean_rx_ring_msix;
 511                 vector++;
 512         }
 513
 514         err = request_irq(adapter->msix_entries[vector].vector,
 515                           &igb_msix_other, 0, netdev->name, netdev);
 516         if (err)
 517                 goto out;
 518
 519         igb_configure_msix(adapter);
 520         return 0;
 521 out:
 522         return err;
 523 }
 524
 525 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 526 {
 527         if (adapter->msix_entries) {
 528                 pci_disable_msix(adapter->pdev);
 529                 kfree(adapter->msix_entries);
 530                 adapter->msix_entries = NULL;
 531         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 532                 pci_disable_msi(adapter->pdev);
 533         return;
 534 }
 535
 536
 537 /**
 538  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 539  *
 540  * Attempt to configure interrupts using the best available
 541  * capabilities of the hardware and kernel.
 542  **/
 543 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 544 {
 545         int err;
 546         int numvecs, i;
 547
 548         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 549         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 550                                         GFP_KERNEL);
 551         if (!adapter->msix_entries)
 552                 goto msi_only;
 553
 554         for (i = 0; i < numvecs; i++)
 555                 adapter->msix_entries[i].entry = i;
 556
 557         err = pci_enable_msix(adapter->pdev,
 558                               adapter->msix_entries,
 559                               numvecs);
 560         if (err == 0)
 561                 goto out;
 562
 563         igb_reset_interrupt_capability(adapter);
 564
 565         /* If we can't do MSI-X, try MSI */
 566 msi_only:
 567         adapter->num_rx_queues = 1;
 568         adapter->num_tx_queues = 1;
 569         if (!pci_enable_msi(adapter->pdev))
 570                 adapter->flags |= IGB_FLAG_HAS_MSI;
 571 out:
 572         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 573         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 574         return;
 575 }
 576
 577 /**
 578  * igb_request_irq - initialize interrupts
 579  *
 580  * Attempts to configure interrupts using the best available
 581  * capabilities of the hardware and kernel.
 582  **/
 583 static int igb_request_irq(struct igb_adapter *adapter)
 584 {
 585         struct net_device *netdev = adapter->netdev;
 586         struct e1000_hw *hw = &adapter->hw;
 587         int err = 0;
 588
 589         if (adapter->msix_entries) {
 590                 err = igb_request_msix(adapter);
 591                 if (!err)
 592                         goto request_done;
 593                 /* fall back to MSI */
 594                 igb_reset_interrupt_capability(adapter);
 595                 if (!pci_enable_msi(adapter->pdev))
 596                         adapter->flags |= IGB_FLAG_HAS_MSI;
 597                 igb_free_all_tx_resources(adapter);
 598                 igb_free_all_rx_resources(adapter);
 599                 adapter->num_rx_queues = 1;
 600                 igb_alloc_queues(adapter);
 601         } else {
 602                 switch (hw->mac.type) {
 603                 case e1000_82575:
 604                         wr32(E1000_MSIXBM(0),
 605                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 606                         break;
 607                 case e1000_82576:
 608                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 609                         break;
 610                 default:
 611                         break;
 612                 }
 613         }
 614
 615         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 616                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 617                                   netdev->name, netdev);
 618                 if (!err)
 619                         goto request_done;
 620                 /* fall back to legacy interrupts */
 621                 igb_reset_interrupt_capability(adapter);
 622                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 623         }
 624
 625         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 626                           netdev->name, netdev);
 627
 628         if (err)
 629                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 630                         err);
 631
 632 request_done:
 633         return err;
 634 }
 635
 636 static void igb_free_irq(struct igb_adapter *adapter)
 637 {
 638         struct net_device *netdev = adapter->netdev;
 639
 640         if (adapter->msix_entries) {
 641                 int vector = 0, i;
 642
 643                 for (i = 0; i < adapter->num_tx_queues; i++)
 644                         free_irq(adapter->msix_entries[vector++].vector,
 645                                 &(adapter->tx_ring[i]));
 646                 for (i = 0; i < adapter->num_rx_queues; i++)
 647                         free_irq(adapter->msix_entries[vector++].vector,
 648                                 &(adapter->rx_ring[i]));
 649
 650                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 651                 return;
 652         }
 653
 654         free_irq(adapter->pdev->irq, netdev);
 655 }
 656
 657 /**
 658  * igb_irq_disable - Mask off interrupt generation on the NIC
 659  * @adapter: board private structure
 660  **/
 661 static void igb_irq_disable(struct igb_adapter *adapter)
 662 {
 663         struct e1000_hw *hw = &adapter->hw;
 664
 665         if (adapter->msix_entries) {
 666                 wr32(E1000_EIAM, 0);
 667                 wr32(E1000_EIMC, ~0);
 668                 wr32(E1000_EIAC, 0);
 669         }
 670
 671         wr32(E1000_IAM, 0);
 672         wr32(E1000_IMC, ~0);
 673         wrfl();
 674         synchronize_irq(adapter->pdev->irq);
 675 }
 676
 677 /**
 678  * igb_irq_enable - Enable default interrupt generation settings
 679  * @adapter: board private structure
 680  **/
 681 static void igb_irq_enable(struct igb_adapter *adapter)
 682 {
 683         struct e1000_hw *hw = &adapter->hw;
 684
 685         if (adapter->msix_entries) {
 686                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 687                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 688                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 689                 wr32(E1000_IMS, E1000_IMS_LSC);
 690         } else {
 691                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 692                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 693         }
 694 }
 695
 696 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 697 {
 698         struct net_device *netdev = adapter->netdev;
 699         u16 vid = adapter->hw.mng_cookie.vlan_id;
 700         u16 old_vid = adapter->mng_vlan_id;
 701         if (adapter->vlgrp) {
 702                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 703                         if (adapter->hw.mng_cookie.status &
 704                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 705                                 igb_vlan_rx_add_vid(netdev, vid);
 706                                 adapter->mng_vlan_id = vid;
 707                         } else
 708                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 709
 710                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 711                                         (vid != old_vid) &&
 712                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 713                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 714                 } else
 715                         adapter->mng_vlan_id = vid;
 716         }
 717 }
 718
 719 /**
 720  * igb_release_hw_control - release control of the h/w to f/w
 721  * @adapter: address of board private structure
 722  *
 723  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 724  * For ASF and Pass Through versions of f/w this means that the
 725  * driver is no longer loaded.
 726  *
 727  **/
 728 static void igb_release_hw_control(struct igb_adapter *adapter)
 729 {
 730         struct e1000_hw *hw = &adapter->hw;
 731         u32 ctrl_ext;
 732
 733         /* Let firmware take over control of h/w */
 734         ctrl_ext = rd32(E1000_CTRL_EXT);
 735         wr32(E1000_CTRL_EXT,
 736                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 737 }
 738
 739
 740 /**
 741  * igb_get_hw_control - get control of the h/w from f/w
 742  * @adapter: address of board private structure
 743  *
 744  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 745  * For ASF and Pass Through versions of f/w this means that
 746  * the driver is loaded.
 747  *
 748  **/
 749 static void igb_get_hw_control(struct igb_adapter *adapter)
 750 {
 751         struct e1000_hw *hw = &adapter->hw;
 752         u32 ctrl_ext;
 753
 754         /* Let firmware know the driver has taken over */
 755         ctrl_ext = rd32(E1000_CTRL_EXT);
 756         wr32(E1000_CTRL_EXT,
 757                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 758 }
 759
 760 /**
 761  * igb_configure - configure the hardware for RX and TX
 762  * @adapter: private board structure
 763  **/
 764 static void igb_configure(struct igb_adapter *adapter)
 765 {
 766         struct net_device *netdev = adapter->netdev;
 767         int i;
 768
 769         igb_get_hw_control(adapter);
 770         igb_set_multi(netdev);
 771
 772         igb_restore_vlan(adapter);
 773
 774         igb_configure_tx(adapter);
 775         igb_setup_rctl(adapter);
 776         igb_configure_rx(adapter);
 777
 778         igb_rx_fifo_flush_82575(&adapter->hw);
 779
 780         /* call IGB_DESC_UNUSED which always leaves
 781          * at least 1 descriptor unused to make sure
 782          * next_to_use != next_to_clean */
 783         for (i = 0; i < adapter->num_rx_queues; i++) {
 784                 struct igb_ring *ring = &adapter->rx_ring[i];
 785                 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
 786         }
 787
 788
 789         adapter->tx_queue_len = netdev->tx_queue_len;
 790 }
 791
 792
 793 /**
 794  * igb_up - Open the interface and prepare it to handle traffic
 795  * @adapter: board private structure
 796  **/
 797
 798 int igb_up(struct igb_adapter *adapter)
 799 {
 800         struct e1000_hw *hw = &adapter->hw;
 801         int i;
 802
 803         /* hardware has been reset, we need to reload some things */
 804         igb_configure(adapter);
 805
 806         clear_bit(__IGB_DOWN, &adapter->state);
 807
 808         for (i = 0; i < adapter->num_rx_queues; i++)
 809                 napi_enable(&adapter->rx_ring[i].napi);
 810         if (adapter->msix_entries)
 811                 igb_configure_msix(adapter);
 812
 813         /* Clear any pending interrupts. */
 814         rd32(E1000_ICR);
 815         igb_irq_enable(adapter);
 816
 817         /* Fire a link change interrupt to start the watchdog. */
 818         wr32(E1000_ICS, E1000_ICS_LSC);
 819         return 0;
 820 }
 821
 822 void igb_down(struct igb_adapter *adapter)
 823 {
 824         struct e1000_hw *hw = &adapter->hw;
 825         struct net_device *netdev = adapter->netdev;
 826         u32 tctl, rctl;
 827         int i;
 828
 829         /* signal that we're down so the interrupt handler does not
 830          * reschedule our watchdog timer */
 831         set_bit(__IGB_DOWN, &adapter->state);
 832
 833         /* disable receives in the hardware */
 834         rctl = rd32(E1000_RCTL);
 835         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 836         /* flush and sleep below */
 837
 838         netif_tx_stop_all_queues(netdev);
 839
 840         /* disable transmits in the hardware */
 841         tctl = rd32(E1000_TCTL);
 842         tctl &= ~E1000_TCTL_EN;
 843         wr32(E1000_TCTL, tctl);
 844         /* flush both disables and wait for them to finish */
 845         wrfl();
 846         msleep(10);
 847
 848         for (i = 0; i < adapter->num_rx_queues; i++)
 849                 napi_disable(&adapter->rx_ring[i].napi);
 850
 851         igb_irq_disable(adapter);
 852
 853         del_timer_sync(&adapter->watchdog_timer);
 854         del_timer_sync(&adapter->phy_info_timer);
 855
 856         netdev->tx_queue_len = adapter->tx_queue_len;
 857         netif_carrier_off(netdev);
 858         adapter->link_speed = 0;
 859         adapter->link_duplex = 0;
 860
 861         if (!pci_channel_offline(adapter->pdev))
 862                 igb_reset(adapter);
 863         igb_clean_all_tx_rings(adapter);
 864         igb_clean_all_rx_rings(adapter);
 865 }
 866
 867 void igb_reinit_locked(struct igb_adapter *adapter)
 868 {
 869         WARN_ON(in_interrupt());
 870         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 871                 msleep(1);
 872         igb_down(adapter);
 873         igb_up(adapter);
 874         clear_bit(__IGB_RESETTING, &adapter->state);
 875 }
 876
 877 void igb_reset(struct igb_adapter *adapter)
 878 {
 879         struct e1000_hw *hw = &adapter->hw;
 880         struct e1000_mac_info *mac = &hw->mac;
 881         struct e1000_fc_info *fc = &hw->fc;
 882         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
 883         u16 hwm;
 884
 885         /* Repartition Pba for greater than 9k mtu
 886          * To take effect CTRL.RST is required.
 887          */
 888         if (mac->type != e1000_82576) {
 889         pba = E1000_PBA_34K;
 890         }
 891         else {
 892                 pba = E1000_PBA_64K;
 893         }
 894
 895         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
 896             (mac->type < e1000_82576)) {
 897                 /* adjust PBA for jumbo frames */
 898                 wr32(E1000_PBA, pba);
 899
 900                 /* To maintain wire speed transmits, the Tx FIFO should be
 901                  * large enough to accommodate two full transmit packets,
 902                  * rounded up to the next 1KB and expressed in KB.  Likewise,
 903                  * the Rx FIFO should be large enough to accommodate at least
 904                  * one full receive packet and is similarly rounded up and
 905                  * expressed in KB. */
 906                 pba = rd32(E1000_PBA);
 907                 /* upper 16 bits has Tx packet buffer allocation size in KB */
 908                 tx_space = pba >> 16;
 909                 /* lower 16 bits has Rx packet buffer allocation size in KB */
 910                 pba &= 0xffff;
 911                 /* the tx fifo also stores 16 bytes of information about the tx
 912                  * but don't include ethernet FCS because hardware appends it */
 913                 min_tx_space = (adapter->max_frame_size +
 914                                 sizeof(struct e1000_tx_desc) -
 915                                 ETH_FCS_LEN) * 2;
 916                 min_tx_space = ALIGN(min_tx_space, 1024);
 917                 min_tx_space >>= 10;
 918                 /* software strips receive CRC, so leave room for it */
 919                 min_rx_space = adapter->max_frame_size;
 920                 min_rx_space = ALIGN(min_rx_space, 1024);
 921                 min_rx_space >>= 10;
 922
 923                 /* If current Tx allocation is less than the min Tx FIFO size,
 924                  * and the min Tx FIFO size is less than the current Rx FIFO
 925                  * allocation, take space away from current Rx allocation */
 926                 if (tx_space < min_tx_space &&
 927                     ((min_tx_space - tx_space) < pba)) {
 928                         pba = pba - (min_tx_space - tx_space);
 929
 930                         /* if short on rx space, rx wins and must trump tx
 931                          * adjustment */
 932                         if (pba < min_rx_space)
 933                                 pba = min_rx_space;
 934                 }
 935                 wr32(E1000_PBA, pba);
 936         }
 937
 938         /* flow control settings */
 939         /* The high water mark must be low enough to fit one full frame
 940          * (or the size used for early receive) above it in the Rx FIFO.
 941          * Set it to the lower of:
 942          * - 90% of the Rx FIFO size, or
 943          * - the full Rx FIFO size minus one full frame */
 944         hwm = min(((pba << 10) * 9 / 10),
 945                         ((pba << 10) - 2 * adapter->max_frame_size));
 946
 947         if (mac->type < e1000_82576) {
 948                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
 949                 fc->low_water = fc->high_water - 8;
 950         } else {
 951                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
 952                 fc->low_water = fc->high_water - 16;
 953         }
 954         fc->pause_time = 0xFFFF;
 955         fc->send_xon = 1;
 956         fc->type = fc->original_type;
 957
 958         /* Allow time for pending master requests to run */
 959         adapter->hw.mac.ops.reset_hw(&adapter->hw);
 960         wr32(E1000_WUC, 0);
 961
 962         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
 963                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
 964
 965         igb_update_mng_vlan(adapter);
 966
 967         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
 968         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
 969
 970         igb_reset_adaptive(&adapter->hw);
 971         igb_get_phy_info(&adapter->hw);
 972 }
 973
 974 /**
 975  * igb_is_need_ioport - determine if an adapter needs ioport resources or not
 976  * @pdev: PCI device information struct
 977  *
 978  * Returns true if an adapter needs ioport resources
 979  **/
 980 static int igb_is_need_ioport(struct pci_dev *pdev)
 981 {
 982         switch (pdev->device) {
 983         /* Currently there are no adapters that need ioport resources */
 984         default:
 985                 return false;
 986         }
 987 }
 988
 989 static const struct net_device_ops igb_netdev_ops = {
 990         .ndo_open               = igb_open,
 991         .ndo_stop               = igb_close,
 992         .ndo_start_xmit         = igb_xmit_frame_adv,
 993         .ndo_get_stats          = igb_get_stats,
 994         .ndo_set_multicast_list = igb_set_multi,
 995         .ndo_set_mac_address    = igb_set_mac,
 996         .ndo_change_mtu         = igb_change_mtu,
 997         .ndo_do_ioctl           = igb_ioctl,
 998         .ndo_tx_timeout         = igb_tx_timeout,
 999         .ndo_validate_addr      = eth_validate_addr,
1000         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1001         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1002         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1003 #ifdef CONFIG_NET_POLL_CONTROLLER
1004         .ndo_poll_controller    = igb_netpoll,
1005 #endif
1006 };
1007
1008 /**
1009  * igb_probe - Device Initialization Routine
1010  * @pdev: PCI device information struct
1011  * @ent: entry in igb_pci_tbl
1012  *
1013  * Returns 0 on success, negative on failure
1014  *
1015  * igb_probe initializes an adapter identified by a pci_dev structure.
1016  * The OS initialization, configuring of the adapter private structure,
1017  * and a hardware reset occur.
1018  **/
1019 static int __devinit igb_probe(struct pci_dev *pdev,
1020                                const struct pci_device_id *ent)
1021 {
1022         struct net_device *netdev;
1023         struct igb_adapter *adapter;
1024         struct e1000_hw *hw;
1025         struct pci_dev *us_dev;
1026         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1027         unsigned long mmio_start, mmio_len;
1028         int i, err, pci_using_dac, pos;
1029         u16 eeprom_data = 0, state = 0;
1030         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1031         u32 part_num;
1032         int bars, need_ioport;
1033
1034         /* do not allocate ioport bars when not needed */
1035         need_ioport = igb_is_need_ioport(pdev);
1036         if (need_ioport) {
1037                 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1038                 err = pci_enable_device(pdev);
1039         } else {
1040                 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1041                 err = pci_enable_device_mem(pdev);
1042         }
1043         if (err)
1044                 return err;
1045
1046         pci_using_dac = 0;
1047         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1048         if (!err) {
1049                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1050                 if (!err)
1051                         pci_using_dac = 1;
1052         } else {
1053                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1054                 if (err) {
1055                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1056                         if (err) {
1057                                 dev_err(&pdev->dev, "No usable DMA "
1058                                         "configuration, aborting\n");
1059                                 goto err_dma;
1060                         }
1061                 }
1062         }
1063
1064         /* 82575 requires that the pci-e link partner disable the L0s state */
1065         switch (pdev->device) {
1066         case E1000_DEV_ID_82575EB_COPPER:
1067         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1068         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1069                 us_dev = pdev->bus->self;
1070                 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1071                 if (pos) {
1072                         pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1073                                              &state);
1074                         state &= ~PCIE_LINK_STATE_L0S;
1075                         pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1076                                               state);
1077                         dev_info(&pdev->dev,
1078                                  "Disabling ASPM L0s upstream switch port %s\n",
1079                                  pci_name(us_dev));
1080                 }
1081         default:
1082                 break;
1083         }
1084
1085         err = pci_request_selected_regions(pdev, bars, igb_driver_name);
1086         if (err)
1087                 goto err_pci_reg;
1088
1089         err = pci_enable_pcie_error_reporting(pdev);
1090         if (err) {
1091                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1092                         "0x%x\n", err);
1093                 /* non-fatal, continue */
1094         }
1095
1096         pci_set_master(pdev);
1097         pci_save_state(pdev);
1098
1099         err = -ENOMEM;
1100         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1101         if (!netdev)
1102                 goto err_alloc_etherdev;
1103
1104         SET_NETDEV_DEV(netdev, &pdev->dev);
1105
1106         pci_set_drvdata(pdev, netdev);
1107         adapter = netdev_priv(netdev);
1108         adapter->netdev = netdev;
1109         adapter->pdev = pdev;
1110         hw = &adapter->hw;
1111         hw->back = adapter;
1112         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1113         adapter->bars = bars;
1114         adapter->need_ioport = need_ioport;
1115
1116         mmio_start = pci_resource_start(pdev, 0);
1117         mmio_len = pci_resource_len(pdev, 0);
1118
1119         err = -EIO;
1120         adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1121         if (!adapter->hw.hw_addr)
1122                 goto err_ioremap;
1123
1124         netdev->netdev_ops = &igb_netdev_ops;
1125         igb_set_ethtool_ops(netdev);
1126         netdev->watchdog_timeo = 5 * HZ;
1127
1128         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1129
1130         netdev->mem_start = mmio_start;
1131         netdev->mem_end = mmio_start + mmio_len;
1132
1133         /* PCI config space info */
1134         hw->vendor_id = pdev->vendor;
1135         hw->device_id = pdev->device;
1136         hw->revision_id = pdev->revision;
1137         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1138         hw->subsystem_device_id = pdev->subsystem_device;
1139
1140         /* setup the private structure */
1141         hw->back = adapter;
1142         /* Copy the default MAC, PHY and NVM function pointers */
1143         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1144         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1145         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1146         /* Initialize skew-specific constants */
1147         err = ei->get_invariants(hw);
1148         if (err)
1149                 goto err_hw_init;
1150
1151         err = igb_sw_init(adapter);
1152         if (err)
1153                 goto err_sw_init;
1154
1155         igb_get_bus_info_pcie(hw);
1156
1157         /* set flags */
1158         switch (hw->mac.type) {
1159         case e1000_82576:
1160         case e1000_82575:
1161                 adapter->flags |= IGB_FLAG_HAS_DCA;
1162                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1163                 break;
1164         default:
1165                 break;
1166         }
1167
1168         hw->phy.autoneg_wait_to_complete = false;
1169         hw->mac.adaptive_ifs = true;
1170
1171         /* Copper options */
1172         if (hw->phy.media_type == e1000_media_type_copper) {
1173                 hw->phy.mdix = AUTO_ALL_MODES;
1174                 hw->phy.disable_polarity_correction = false;
1175                 hw->phy.ms_type = e1000_ms_hw_default;
1176         }
1177
1178         if (igb_check_reset_block(hw))
1179                 dev_info(&pdev->dev,
1180                         "PHY reset is blocked due to SOL/IDER session.\n");
1181
1182         netdev->features = NETIF_F_SG |
1183                            NETIF_F_HW_CSUM |
1184                            NETIF_F_HW_VLAN_TX |
1185                            NETIF_F_HW_VLAN_RX |
1186                            NETIF_F_HW_VLAN_FILTER;
1187
1188         netdev->features |= NETIF_F_TSO;
1189         netdev->features |= NETIF_F_TSO6;
1190
1191 #ifdef CONFIG_IGB_LRO
1192         netdev->features |= NETIF_F_LRO;
1193 #endif
1194
1195         netdev->vlan_features |= NETIF_F_TSO;
1196         netdev->vlan_features |= NETIF_F_TSO6;
1197         netdev->vlan_features |= NETIF_F_HW_CSUM;
1198         netdev->vlan_features |= NETIF_F_SG;
1199
1200         if (pci_using_dac)
1201                 netdev->features |= NETIF_F_HIGHDMA;
1202
1203         netdev->features |= NETIF_F_LLTX;
1204         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1205
1206         /* before reading the NVM, reset the controller to put the device in a
1207          * known good starting state */
1208         hw->mac.ops.reset_hw(hw);
1209
1210         /* make sure the NVM is good */
1211         if (igb_validate_nvm_checksum(hw) < 0) {
1212                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1213                 err = -EIO;
1214                 goto err_eeprom;
1215         }
1216
1217         /* copy the MAC address out of the NVM */
1218         if (hw->mac.ops.read_mac_addr(hw))
1219                 dev_err(&pdev->dev, "NVM Read Error\n");
1220
1221         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1222         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1223
1224         if (!is_valid_ether_addr(netdev->perm_addr)) {
1225                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1226                 err = -EIO;
1227                 goto err_eeprom;
1228         }
1229
1230         init_timer(&adapter->watchdog_timer);
1231         adapter->watchdog_timer.function = &igb_watchdog;
1232         adapter->watchdog_timer.data = (unsigned long) adapter;
1233
1234         init_timer(&adapter->phy_info_timer);
1235         adapter->phy_info_timer.function = &igb_update_phy_info;
1236         adapter->phy_info_timer.data = (unsigned long) adapter;
1237
1238         INIT_WORK(&adapter->reset_task, igb_reset_task);
1239         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1240
1241         /* Initialize link & ring properties that are user-changeable */
1242         adapter->tx_ring->count = 256;
1243         for (i = 0; i < adapter->num_tx_queues; i++)
1244                 adapter->tx_ring[i].count = adapter->tx_ring->count;
1245         adapter->rx_ring->count = 256;
1246         for (i = 0; i < adapter->num_rx_queues; i++)
1247                 adapter->rx_ring[i].count = adapter->rx_ring->count;
1248
1249         adapter->fc_autoneg = true;
1250         hw->mac.autoneg = true;
1251         hw->phy.autoneg_advertised = 0x2f;
1252
1253         hw->fc.original_type = e1000_fc_default;
1254         hw->fc.type = e1000_fc_default;
1255
1256         adapter->itr_setting = 3;
1257         adapter->itr = IGB_START_ITR;
1258
1259         igb_validate_mdi_setting(hw);
1260
1261         adapter->rx_csum = 1;
1262
1263         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1264          * enable the ACPI Magic Packet filter
1265          */
1266
1267         if (hw->bus.func == 0 ||
1268             hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1269                 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1270                                      &eeprom_data);
1271
1272         if (eeprom_data & eeprom_apme_mask)
1273                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1274
1275         /* now that we have the eeprom settings, apply the special cases where
1276          * the eeprom may be wrong or the board simply won't support wake on
1277          * lan on a particular port */
1278         switch (pdev->device) {
1279         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1280                 adapter->eeprom_wol = 0;
1281                 break;
1282         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1283         case E1000_DEV_ID_82576_FIBER:
1284         case E1000_DEV_ID_82576_SERDES:
1285                 /* Wake events only supported on port A for dual fiber
1286                  * regardless of eeprom setting */
1287                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1288                         adapter->eeprom_wol = 0;
1289                 break;
1290         }
1291
1292         /* initialize the wol settings based on the eeprom settings */
1293         adapter->wol = adapter->eeprom_wol;
1294         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1295
1296         /* reset the hardware with the new settings */
1297         igb_reset(adapter);
1298
1299         /* let the f/w know that the h/w is now under the control of the
1300          * driver. */
1301         igb_get_hw_control(adapter);
1302
1303         /* tell the stack to leave us alone until igb_open() is called */
1304         netif_carrier_off(netdev);
1305         netif_tx_stop_all_queues(netdev);
1306
1307         strcpy(netdev->name, "eth%d");
1308         err = register_netdev(netdev);
1309         if (err)
1310                 goto err_register;
1311
1312 #ifdef CONFIG_IGB_DCA
1313         if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1314             (dca_add_requester(&pdev->dev) == 0)) {
1315                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1316                 dev_info(&pdev->dev, "DCA enabled\n");
1317                 /* Always use CB2 mode, difference is masked
1318                  * in the CB driver. */
1319                 wr32(E1000_DCA_CTRL, 2);
1320                 igb_setup_dca(adapter);
1321         }
1322 #endif
1323
1324         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1325         /* print bus type/speed/width info */
1326         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1327                  netdev->name,
1328                  ((hw->bus.speed == e1000_bus_speed_2500)
1329                   ? "2.5Gb/s" : "unknown"),
1330                  ((hw->bus.width == e1000_bus_width_pcie_x4)
1331                   ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1332                   ? "Width x1" : "unknown"),
1333                  netdev->dev_addr);
1334
1335         igb_read_part_num(hw, &part_num);
1336         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1337                 (part_num >> 8), (part_num & 0xff));
1338
1339         dev_info(&pdev->dev,
1340                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1341                 adapter->msix_entries ? "MSI-X" :
1342                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1343                 adapter->num_rx_queues, adapter->num_tx_queues);
1344
1345         return 0;
1346
1347 err_register:
1348         igb_release_hw_control(adapter);
1349 err_eeprom:
1350         if (!igb_check_reset_block(hw))
1351                 igb_reset_phy(hw);
1352
1353         if (hw->flash_address)
1354                 iounmap(hw->flash_address);
1355
1356         igb_remove_device(hw);
1357         igb_free_queues(adapter);
1358 err_sw_init:
1359 err_hw_init:
1360         iounmap(hw->hw_addr);
1361 err_ioremap:
1362         free_netdev(netdev);
1363 err_alloc_etherdev:
1364         pci_release_selected_regions(pdev, bars);
1365 err_pci_reg:
1366 err_dma:
1367         pci_disable_device(pdev);
1368         return err;
1369 }
1370
1371 /**
1372  * igb_remove - Device Removal Routine
1373  * @pdev: PCI device information struct
1374  *
1375  * igb_remove is called by the PCI subsystem to alert the driver
1376  * that it should release a PCI device.  The could be caused by a
1377  * Hot-Plug event, or because the driver is going to be removed from
1378  * memory.
1379  **/
1380 static void __devexit igb_remove(struct pci_dev *pdev)
1381 {
1382         struct net_device *netdev = pci_get_drvdata(pdev);
1383         struct igb_adapter *adapter = netdev_priv(netdev);
1384 #ifdef CONFIG_IGB_DCA
1385         struct e1000_hw *hw = &adapter->hw;
1386 #endif
1387         int err;
1388
1389         /* flush_scheduled work may reschedule our watchdog task, so
1390          * explicitly disable watchdog tasks from being rescheduled  */
1391         set_bit(__IGB_DOWN, &adapter->state);
1392         del_timer_sync(&adapter->watchdog_timer);
1393         del_timer_sync(&adapter->phy_info_timer);
1394
1395         flush_scheduled_work();
1396
1397 #ifdef CONFIG_IGB_DCA
1398         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1399                 dev_info(&pdev->dev, "DCA disabled\n");
1400                 dca_remove_requester(&pdev->dev);
1401                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1402                 wr32(E1000_DCA_CTRL, 1);
1403         }
1404 #endif
1405
1406         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1407          * would have already happened in close and is redundant. */
1408         igb_release_hw_control(adapter);
1409
1410         unregister_netdev(netdev);
1411
1412         if (!igb_check_reset_block(&adapter->hw))
1413                 igb_reset_phy(&adapter->hw);
1414
1415         igb_remove_device(&adapter->hw);
1416         igb_reset_interrupt_capability(adapter);
1417
1418         igb_free_queues(adapter);
1419
1420         iounmap(adapter->hw.hw_addr);
1421         if (adapter->hw.flash_address)
1422                 iounmap(adapter->hw.flash_address);
1423         pci_release_selected_regions(pdev, adapter->bars);
1424
1425         free_netdev(netdev);
1426
1427         err = pci_disable_pcie_error_reporting(pdev);
1428         if (err)
1429                 dev_err(&pdev->dev,
1430                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1431
1432         pci_disable_device(pdev);
1433 }
1434
1435 /**
1436  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1437  * @adapter: board private structure to initialize
1438  *
1439  * igb_sw_init initializes the Adapter private data structure.
1440  * Fields are initialized based on PCI device information and
1441  * OS network device settings (MTU size).
1442  **/
1443 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1444 {
1445         struct e1000_hw *hw = &adapter->hw;
1446         struct net_device *netdev = adapter->netdev;
1447         struct pci_dev *pdev = adapter->pdev;
1448
1449         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1450
1451         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1452         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1453         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1454         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1455         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1456         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1457
1458         /* Number of supported queues. */
1459         /* Having more queues than CPUs doesn't make sense. */
1460         adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1461         adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1462
1463         /* This call may decrease the number of queues depending on
1464          * interrupt mode. */
1465         igb_set_interrupt_capability(adapter);
1466
1467         if (igb_alloc_queues(adapter)) {
1468                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1469                 return -ENOMEM;
1470         }
1471
1472         /* Explicitly disable IRQ since the NIC can be in any state. */
1473         igb_irq_disable(adapter);
1474
1475         set_bit(__IGB_DOWN, &adapter->state);
1476         return 0;
1477 }
1478
1479 /**
1480  * igb_open - Called when a network interface is made active
1481  * @netdev: network interface device structure
1482  *
1483  * Returns 0 on success, negative value on failure
1484  *
1485  * The open entry point is called when a network interface is made
1486  * active by the system (IFF_UP).  At this point all resources needed
1487  * for transmit and receive operations are allocated, the interrupt
1488  * handler is registered with the OS, the watchdog timer is started,
1489  * and the stack is notified that the interface is ready.
1490  **/
1491 static int igb_open(struct net_device *netdev)
1492 {
1493         struct igb_adapter *adapter = netdev_priv(netdev);
1494         struct e1000_hw *hw = &adapter->hw;
1495         int err;
1496         int i;
1497
1498         /* disallow open during test */
1499         if (test_bit(__IGB_TESTING, &adapter->state))
1500                 return -EBUSY;
1501
1502         /* allocate transmit descriptors */
1503         err = igb_setup_all_tx_resources(adapter);
1504         if (err)
1505                 goto err_setup_tx;
1506
1507         /* allocate receive descriptors */
1508         err = igb_setup_all_rx_resources(adapter);
1509         if (err)
1510                 goto err_setup_rx;
1511
1512         /* e1000_power_up_phy(adapter); */
1513
1514         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1515         if ((adapter->hw.mng_cookie.status &
1516              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1517                 igb_update_mng_vlan(adapter);
1518
1519         /* before we allocate an interrupt, we must be ready to handle it.
1520          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1521          * as soon as we call pci_request_irq, so we have to setup our
1522          * clean_rx handler before we do so.  */
1523         igb_configure(adapter);
1524
1525         err = igb_request_irq(adapter);
1526         if (err)
1527                 goto err_req_irq;
1528
1529         /* From here on the code is the same as igb_up() */
1530         clear_bit(__IGB_DOWN, &adapter->state);
1531
1532         for (i = 0; i < adapter->num_rx_queues; i++)
1533                 napi_enable(&adapter->rx_ring[i].napi);
1534
1535         /* Clear any pending interrupts. */
1536         rd32(E1000_ICR);
1537
1538         igb_irq_enable(adapter);
1539
1540         netif_tx_start_all_queues(netdev);
1541
1542         /* Fire a link status change interrupt to start the watchdog. */
1543         wr32(E1000_ICS, E1000_ICS_LSC);
1544
1545         return 0;
1546
1547 err_req_irq:
1548         igb_release_hw_control(adapter);
1549         /* e1000_power_down_phy(adapter); */
1550         igb_free_all_rx_resources(adapter);
1551 err_setup_rx:
1552         igb_free_all_tx_resources(adapter);
1553 err_setup_tx:
1554         igb_reset(adapter);
1555
1556         return err;
1557 }
1558
1559 /**
1560  * igb_close - Disables a network interface
1561  * @netdev: network interface device structure
1562  *
1563  * Returns 0, this is not allowed to fail
1564  *
1565  * The close entry point is called when an interface is de-activated
1566  * by the OS.  The hardware is still under the driver's control, but
1567  * needs to be disabled.  A global MAC reset is issued to stop the
1568  * hardware, and all transmit and receive resources are freed.
1569  **/
1570 static int igb_close(struct net_device *netdev)
1571 {
1572         struct igb_adapter *adapter = netdev_priv(netdev);
1573
1574         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1575         igb_down(adapter);
1576
1577         igb_free_irq(adapter);
1578
1579         igb_free_all_tx_resources(adapter);
1580         igb_free_all_rx_resources(adapter);
1581
1582         /* kill manageability vlan ID if supported, but not if a vlan with
1583          * the same ID is registered on the host OS (let 8021q kill it) */
1584         if ((adapter->hw.mng_cookie.status &
1585                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1586              !(adapter->vlgrp &&
1587                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1588                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1589
1590         return 0;
1591 }
1592
1593 /**
1594  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1595  * @adapter: board private structure
1596  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1597  *
1598  * Return 0 on success, negative on failure
1599  **/
1600
1601 int igb_setup_tx_resources(struct igb_adapter *adapter,
1602                            struct igb_ring *tx_ring)
1603 {
1604         struct pci_dev *pdev = adapter->pdev;
1605         int size;
1606
1607         size = sizeof(struct igb_buffer) * tx_ring->count;
1608         tx_ring->buffer_info = vmalloc(size);
1609         if (!tx_ring->buffer_info)
1610                 goto err;
1611         memset(tx_ring->buffer_info, 0, size);
1612
1613         /* round up to nearest 4K */
1614         tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1615         tx_ring->size = ALIGN(tx_ring->size, 4096);
1616
1617         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1618                                              &tx_ring->dma);
1619
1620         if (!tx_ring->desc)
1621                 goto err;
1622
1623         tx_ring->adapter = adapter;
1624         tx_ring->next_to_use = 0;
1625         tx_ring->next_to_clean = 0;
1626         return 0;
1627
1628 err:
1629         vfree(tx_ring->buffer_info);
1630         dev_err(&adapter->pdev->dev,
1631                 "Unable to allocate memory for the transmit descriptor ring\n");
1632         return -ENOMEM;
1633 }
1634
1635 /**
1636  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1637  *                                (Descriptors) for all queues
1638  * @adapter: board private structure
1639  *
1640  * Return 0 on success, negative on failure
1641  **/
1642 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1643 {
1644         int i, err = 0;
1645         int r_idx;
1646
1647         for (i = 0; i < adapter->num_tx_queues; i++) {
1648                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1649                 if (err) {
1650                         dev_err(&adapter->pdev->dev,
1651                                 "Allocation for Tx Queue %u failed\n", i);
1652                         for (i--; i >= 0; i--)
1653                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1654                         break;
1655                 }
1656         }
1657
1658         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1659                 r_idx = i % adapter->num_tx_queues;
1660                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1661         }
1662         return err;
1663 }
1664
1665 /**
1666  * igb_configure_tx - Configure transmit Unit after Reset
1667  * @adapter: board private structure
1668  *
1669  * Configure the Tx unit of the MAC after a reset.
1670  **/
1671 static void igb_configure_tx(struct igb_adapter *adapter)
1672 {
1673         u64 tdba;
1674         struct e1000_hw *hw = &adapter->hw;
1675         u32 tctl;
1676         u32 txdctl, txctrl;
1677         int i, j;
1678
1679         for (i = 0; i < adapter->num_tx_queues; i++) {
1680                 struct igb_ring *ring = &(adapter->tx_ring[i]);
1681                 j = ring->reg_idx;
1682                 wr32(E1000_TDLEN(j),
1683                                 ring->count * sizeof(struct e1000_tx_desc));
1684                 tdba = ring->dma;
1685                 wr32(E1000_TDBAL(j),
1686                                 tdba & 0x00000000ffffffffULL);
1687                 wr32(E1000_TDBAH(j), tdba >> 32);
1688
1689                 ring->head = E1000_TDH(j);
1690                 ring->tail = E1000_TDT(j);
1691                 writel(0, hw->hw_addr + ring->tail);
1692                 writel(0, hw->hw_addr + ring->head);
1693                 txdctl = rd32(E1000_TXDCTL(j));
1694                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1695                 wr32(E1000_TXDCTL(j), txdctl);
1696
1697                 /* Turn off Relaxed Ordering on head write-backs.  The
1698                  * writebacks MUST be delivered in order or it will
1699                  * completely screw up our bookeeping.
1700                  */
1701                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1702                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1703                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1704         }
1705
1706
1707
1708         /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1709
1710         /* Program the Transmit Control Register */
1711
1712         tctl = rd32(E1000_TCTL);
1713         tctl &= ~E1000_TCTL_CT;
1714         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1715                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1716
1717         igb_config_collision_dist(hw);
1718
1719         /* Setup Transmit Descriptor Settings for eop descriptor */
1720         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1721
1722         /* Enable transmits */
1723         tctl |= E1000_TCTL_EN;
1724
1725         wr32(E1000_TCTL, tctl);
1726 }
1727
1728 /**
1729  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1730  * @adapter: board private structure
1731  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1732  *
1733  * Returns 0 on success, negative on failure
1734  **/
1735
1736 int igb_setup_rx_resources(struct igb_adapter *adapter,
1737                            struct igb_ring *rx_ring)
1738 {
1739         struct pci_dev *pdev = adapter->pdev;
1740         int size, desc_len;
1741
1742 #ifdef CONFIG_IGB_LRO
1743         size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1744         rx_ring->lro_mgr.lro_arr = vmalloc(size);
1745         if (!rx_ring->lro_mgr.lro_arr)
1746                 goto err;
1747         memset(rx_ring->lro_mgr.lro_arr, 0, size);
1748 #endif
1749
1750         size = sizeof(struct igb_buffer) * rx_ring->count;
1751         rx_ring->buffer_info = vmalloc(size);
1752         if (!rx_ring->buffer_info)
1753                 goto err;
1754         memset(rx_ring->buffer_info, 0, size);
1755
1756         desc_len = sizeof(union e1000_adv_rx_desc);
1757
1758         /* Round up to nearest 4K */
1759         rx_ring->size = rx_ring->count * desc_len;
1760         rx_ring->size = ALIGN(rx_ring->size, 4096);
1761
1762         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1763                                              &rx_ring->dma);
1764
1765         if (!rx_ring->desc)
1766                 goto err;
1767
1768         rx_ring->next_to_clean = 0;
1769         rx_ring->next_to_use = 0;
1770
1771         rx_ring->adapter = adapter;
1772
1773         return 0;
1774
1775 err:
1776 #ifdef CONFIG_IGB_LRO
1777         vfree(rx_ring->lro_mgr.lro_arr);
1778         rx_ring->lro_mgr.lro_arr = NULL;
1779 #endif
1780         vfree(rx_ring->buffer_info);
1781         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1782                 "the receive descriptor ring\n");
1783         return -ENOMEM;
1784 }
1785
1786 /**
1787  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1788  *                                (Descriptors) for all queues
1789  * @adapter: board private structure
1790  *
1791  * Return 0 on success, negative on failure
1792  **/
1793 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1794 {
1795         int i, err = 0;
1796
1797         for (i = 0; i < adapter->num_rx_queues; i++) {
1798                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1799                 if (err) {
1800                         dev_err(&adapter->pdev->dev,
1801                                 "Allocation for Rx Queue %u failed\n", i);
1802                         for (i--; i >= 0; i--)
1803                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1804                         break;
1805                 }
1806         }
1807
1808         return err;
1809 }
1810
1811 /**
1812  * igb_setup_rctl - configure the receive control registers
1813  * @adapter: Board private structure
1814  **/
1815 static void igb_setup_rctl(struct igb_adapter *adapter)
1816 {
1817         struct e1000_hw *hw = &adapter->hw;
1818         u32 rctl;
1819         u32 srrctl = 0;
1820         int i, j;
1821
1822         rctl = rd32(E1000_RCTL);
1823
1824         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1825         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1826
1827         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1828                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1829
1830         /*
1831          * enable stripping of CRC. It's unlikely this will break BMC
1832          * redirection as it did with e1000. Newer features require
1833          * that the HW strips the CRC.
1834         */
1835         rctl |= E1000_RCTL_SECRC;
1836
1837         /*
1838          * disable store bad packets, long packet enable, and clear size bits.
1839          */
1840         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_LPE | E1000_RCTL_SZ_256);
1841
1842         if (adapter->netdev->mtu > ETH_DATA_LEN)
1843                 rctl |= E1000_RCTL_LPE;
1844
1845         /* Setup buffer sizes */
1846         switch (adapter->rx_buffer_len) {
1847         case IGB_RXBUFFER_256:
1848                 rctl |= E1000_RCTL_SZ_256;
1849                 break;
1850         case IGB_RXBUFFER_512:
1851                 rctl |= E1000_RCTL_SZ_512;
1852                 break;
1853         default:
1854                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1855                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1856                 break;
1857         }
1858
1859         /* 82575 and greater support packet-split where the protocol
1860          * header is placed in skb->data and the packet data is
1861          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1862          * In the case of a non-split, skb->data is linearly filled,
1863          * followed by the page buffers.  Therefore, skb->data is
1864          * sized to hold the largest protocol header.
1865          */
1866         /* allocations using alloc_page take too long for regular MTU
1867          * so only enable packet split for jumbo frames */
1868         if (rctl & E1000_RCTL_LPE) {
1869                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1870                 srrctl |= adapter->rx_ps_hdr_size <<
1871                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1872                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1873         } else {
1874                 adapter->rx_ps_hdr_size = 0;
1875                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1876         }
1877
1878         for (i = 0; i < adapter->num_rx_queues; i++) {
1879                 j = adapter->rx_ring[i].reg_idx;
1880                 wr32(E1000_SRRCTL(j), srrctl);
1881         }
1882
1883         wr32(E1000_RCTL, rctl);
1884 }
1885
1886 /**
1887  * igb_configure_rx - Configure receive Unit after Reset
1888  * @adapter: board private structure
1889  *
1890  * Configure the Rx unit of the MAC after a reset.
1891  **/
1892 static void igb_configure_rx(struct igb_adapter *adapter)
1893 {
1894         u64 rdba;
1895         struct e1000_hw *hw = &adapter->hw;
1896         u32 rctl, rxcsum;
1897         u32 rxdctl;
1898         int i, j;
1899
1900         /* disable receives while setting up the descriptors */
1901         rctl = rd32(E1000_RCTL);
1902         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1903         wrfl();
1904         mdelay(10);
1905
1906         if (adapter->itr_setting > 3)
1907                 wr32(E1000_ITR, adapter->itr);
1908
1909         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1910          * the Base and Length of the Rx Descriptor Ring */
1911         for (i = 0; i < adapter->num_rx_queues; i++) {
1912                 struct igb_ring *ring = &(adapter->rx_ring[i]);
1913                 j = ring->reg_idx;
1914                 rdba = ring->dma;
1915                 wr32(E1000_RDBAL(j),
1916                                 rdba & 0x00000000ffffffffULL);
1917                 wr32(E1000_RDBAH(j), rdba >> 32);
1918                 wr32(E1000_RDLEN(j),
1919                                ring->count * sizeof(union e1000_adv_rx_desc));
1920
1921                 ring->head = E1000_RDH(j);
1922                 ring->tail = E1000_RDT(j);
1923                 writel(0, hw->hw_addr + ring->tail);
1924                 writel(0, hw->hw_addr + ring->head);
1925
1926                 rxdctl = rd32(E1000_RXDCTL(j));
1927                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1928                 rxdctl &= 0xFFF00000;
1929                 rxdctl |= IGB_RX_PTHRESH;
1930                 rxdctl |= IGB_RX_HTHRESH << 8;
1931                 rxdctl |= IGB_RX_WTHRESH << 16;
1932                 wr32(E1000_RXDCTL(j), rxdctl);
1933 #ifdef CONFIG_IGB_LRO
1934                 /* Intitial LRO Settings */
1935                 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1936                 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1937                 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1938                 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1939                 ring->lro_mgr.dev = adapter->netdev;
1940                 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1941                 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1942 #endif
1943         }
1944
1945         if (adapter->num_rx_queues > 1) {
1946                 u32 random[10];
1947                 u32 mrqc;
1948                 u32 j, shift;
1949                 union e1000_reta {
1950                         u32 dword;
1951                         u8  bytes[4];
1952                 } reta;
1953
1954                 get_random_bytes(&random[0], 40);
1955
1956                 if (hw->mac.type >= e1000_82576)
1957                         shift = 0;
1958                 else
1959                         shift = 6;
1960                 for (j = 0; j < (32 * 4); j++) {
1961                         reta.bytes[j & 3] =
1962                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
1963                         if ((j & 3) == 3)
1964                                 writel(reta.dword,
1965                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
1966                 }
1967                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1968
1969                 /* Fill out hash function seeds */
1970                 for (j = 0; j < 10; j++)
1971                         array_wr32(E1000_RSSRK(0), j, random[j]);
1972
1973                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1974                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
1975                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1976                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
1977                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1978                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
1979                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1980                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1981
1982
1983                 wr32(E1000_MRQC, mrqc);
1984
1985                 /* Multiqueue and raw packet checksumming are mutually
1986                  * exclusive.  Note that this not the same as TCP/IP
1987                  * checksumming, which works fine. */
1988                 rxcsum = rd32(E1000_RXCSUM);
1989                 rxcsum |= E1000_RXCSUM_PCSD;
1990                 wr32(E1000_RXCSUM, rxcsum);
1991         } else {
1992                 /* Enable Receive Checksum Offload for TCP and UDP */
1993                 rxcsum = rd32(E1000_RXCSUM);
1994                 if (adapter->rx_csum) {
1995                         rxcsum |= E1000_RXCSUM_TUOFL;
1996
1997                         /* Enable IPv4 payload checksum for UDP fragments
1998                          * Must be used in conjunction with packet-split. */
1999                         if (adapter->rx_ps_hdr_size)
2000                                 rxcsum |= E1000_RXCSUM_IPPCSE;
2001                 } else {
2002                         rxcsum &= ~E1000_RXCSUM_TUOFL;
2003                         /* don't need to clear IPPCSE as it defaults to 0 */
2004                 }
2005                 wr32(E1000_RXCSUM, rxcsum);
2006         }
2007
2008         if (adapter->vlgrp)
2009                 wr32(E1000_RLPML,
2010                                 adapter->max_frame_size + VLAN_TAG_SIZE);
2011         else
2012                 wr32(E1000_RLPML, adapter->max_frame_size);
2013
2014         /* Enable Receives */
2015         wr32(E1000_RCTL, rctl);
2016 }
2017
2018 /**
2019  * igb_free_tx_resources - Free Tx Resources per Queue
2020  * @tx_ring: Tx descriptor ring for a specific queue
2021  *
2022  * Free all transmit software resources
2023  **/
2024 void igb_free_tx_resources(struct igb_ring *tx_ring)
2025 {
2026         struct pci_dev *pdev = tx_ring->adapter->pdev;
2027
2028         igb_clean_tx_ring(tx_ring);
2029
2030         vfree(tx_ring->buffer_info);
2031         tx_ring->buffer_info = NULL;
2032
2033         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2034
2035         tx_ring->desc = NULL;
2036 }
2037
2038 /**
2039  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2040  * @adapter: board private structure
2041  *
2042  * Free all transmit software resources
2043  **/
2044 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2045 {
2046         int i;
2047
2048         for (i = 0; i < adapter->num_tx_queues; i++)
2049                 igb_free_tx_resources(&adapter->tx_ring[i]);
2050 }
2051
2052 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2053                                            struct igb_buffer *buffer_info)
2054 {
2055         if (buffer_info->dma) {
2056                 pci_unmap_page(adapter->pdev,
2057                                 buffer_info->dma,
2058                                 buffer_info->length,
2059                                 PCI_DMA_TODEVICE);
2060                 buffer_info->dma = 0;
2061         }
2062         if (buffer_info->skb) {
2063                 dev_kfree_skb_any(buffer_info->skb);
2064                 buffer_info->skb = NULL;
2065         }
2066         buffer_info->time_stamp = 0;
2067         /* buffer_info must be completely set up in the transmit path */
2068 }
2069
2070 /**
2071  * igb_clean_tx_ring - Free Tx Buffers
2072  * @tx_ring: ring to be cleaned
2073  **/
2074 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2075 {
2076         struct igb_adapter *adapter = tx_ring->adapter;
2077         struct igb_buffer *buffer_info;
2078         unsigned long size;
2079         unsigned int i;
2080
2081         if (!tx_ring->buffer_info)
2082                 return;
2083         /* Free all the Tx ring sk_buffs */
2084
2085         for (i = 0; i < tx_ring->count; i++) {
2086                 buffer_info = &tx_ring->buffer_info[i];
2087                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2088         }
2089
2090         size = sizeof(struct igb_buffer) * tx_ring->count;
2091         memset(tx_ring->buffer_info, 0, size);
2092
2093         /* Zero out the descriptor ring */
2094
2095         memset(tx_ring->desc, 0, tx_ring->size);
2096
2097         tx_ring->next_to_use = 0;
2098         tx_ring->next_to_clean = 0;
2099
2100         writel(0, adapter->hw.hw_addr + tx_ring->head);
2101         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2102 }
2103
2104 /**
2105  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2106  * @adapter: board private structure
2107  **/
2108 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2109 {
2110         int i;
2111
2112         for (i = 0; i < adapter->num_tx_queues; i++)
2113                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2114 }
2115
2116 /**
2117  * igb_free_rx_resources - Free Rx Resources
2118  * @rx_ring: ring to clean the resources from
2119  *
2120  * Free all receive software resources
2121  **/
2122 void igb_free_rx_resources(struct igb_ring *rx_ring)
2123 {
2124         struct pci_dev *pdev = rx_ring->adapter->pdev;
2125
2126         igb_clean_rx_ring(rx_ring);
2127
2128         vfree(rx_ring->buffer_info);
2129         rx_ring->buffer_info = NULL;
2130
2131 #ifdef CONFIG_IGB_LRO
2132         vfree(rx_ring->lro_mgr.lro_arr);
2133         rx_ring->lro_mgr.lro_arr = NULL;
2134 #endif
2135
2136         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2137
2138         rx_ring->desc = NULL;
2139 }
2140
2141 /**
2142  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2143  * @adapter: board private structure
2144  *
2145  * Free all receive software resources
2146  **/
2147 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2148 {
2149         int i;
2150
2151         for (i = 0; i < adapter->num_rx_queues; i++)
2152                 igb_free_rx_resources(&adapter->rx_ring[i]);
2153 }
2154
2155 /**
2156  * igb_clean_rx_ring - Free Rx Buffers per Queue
2157  * @rx_ring: ring to free buffers from
2158  **/
2159 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2160 {
2161         struct igb_adapter *adapter = rx_ring->adapter;
2162         struct igb_buffer *buffer_info;
2163         struct pci_dev *pdev = adapter->pdev;
2164         unsigned long size;
2165         unsigned int i;
2166
2167         if (!rx_ring->buffer_info)
2168                 return;
2169         /* Free all the Rx ring sk_buffs */
2170         for (i = 0; i < rx_ring->count; i++) {
2171                 buffer_info = &rx_ring->buffer_info[i];
2172                 if (buffer_info->dma) {
2173                         if (adapter->rx_ps_hdr_size)
2174                                 pci_unmap_single(pdev, buffer_info->dma,
2175                                                  adapter->rx_ps_hdr_size,
2176                                                  PCI_DMA_FROMDEVICE);
2177                         else
2178                                 pci_unmap_single(pdev, buffer_info->dma,
2179                                                  adapter->rx_buffer_len,
2180                                                  PCI_DMA_FROMDEVICE);
2181                         buffer_info->dma = 0;
2182                 }
2183
2184                 if (buffer_info->skb) {
2185                         dev_kfree_skb(buffer_info->skb);
2186                         buffer_info->skb = NULL;
2187                 }
2188                 if (buffer_info->page) {
2189                         if (buffer_info->page_dma)
2190                                 pci_unmap_page(pdev, buffer_info->page_dma,
2191                                                PAGE_SIZE / 2,
2192                                                PCI_DMA_FROMDEVICE);
2193                         put_page(buffer_info->page);
2194                         buffer_info->page = NULL;
2195                         buffer_info->page_dma = 0;
2196                         buffer_info->page_offset = 0;
2197                 }
2198         }
2199
2200         size = sizeof(struct igb_buffer) * rx_ring->count;
2201         memset(rx_ring->buffer_info, 0, size);
2202
2203         /* Zero out the descriptor ring */
2204         memset(rx_ring->desc, 0, rx_ring->size);
2205
2206         rx_ring->next_to_clean = 0;
2207         rx_ring->next_to_use = 0;
2208
2209         writel(0, adapter->hw.hw_addr + rx_ring->head);
2210         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2211 }
2212
2213 /**
2214  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2215  * @adapter: board private structure
2216  **/
2217 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2218 {
2219         int i;
2220
2221         for (i = 0; i < adapter->num_rx_queues; i++)
2222                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2223 }
2224
2225 /**
2226  * igb_set_mac - Change the Ethernet Address of the NIC
2227  * @netdev: network interface device structure
2228  * @p: pointer to an address structure
2229  *
2230  * Returns 0 on success, negative on failure
2231  **/
2232 static int igb_set_mac(struct net_device *netdev, void *p)
2233 {
2234         struct igb_adapter *adapter = netdev_priv(netdev);
2235         struct sockaddr *addr = p;
2236
2237         if (!is_valid_ether_addr(addr->sa_data))
2238                 return -EADDRNOTAVAIL;
2239
2240         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2241         memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2242
2243         adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2244
2245         return 0;
2246 }
2247
2248 /**
2249  * igb_set_multi - Multicast and Promiscuous mode set
2250  * @netdev: network interface device structure
2251  *
2252  * The set_multi entry point is called whenever the multicast address
2253  * list or the network interface flags are updated.  This routine is
2254  * responsible for configuring the hardware for proper multicast,
2255  * promiscuous mode, and all-multi behavior.
2256  **/
2257 static void igb_set_multi(struct net_device *netdev)
2258 {
2259         struct igb_adapter *adapter = netdev_priv(netdev);
2260         struct e1000_hw *hw = &adapter->hw;
2261         struct e1000_mac_info *mac = &hw->mac;
2262         struct dev_mc_list *mc_ptr;
2263         u8  *mta_list;
2264         u32 rctl;
2265         int i;
2266
2267         /* Check for Promiscuous and All Multicast modes */
2268
2269         rctl = rd32(E1000_RCTL);
2270
2271         if (netdev->flags & IFF_PROMISC) {
2272                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2273                 rctl &= ~E1000_RCTL_VFE;
2274         } else {
2275                 if (netdev->flags & IFF_ALLMULTI) {
2276                         rctl |= E1000_RCTL_MPE;
2277                         rctl &= ~E1000_RCTL_UPE;
2278                 } else
2279                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2280                 rctl |= E1000_RCTL_VFE;
2281         }
2282         wr32(E1000_RCTL, rctl);
2283
2284         if (!netdev->mc_count) {
2285                 /* nothing to program, so clear mc list */
2286                 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
2287                                           mac->rar_entry_count);
2288                 return;
2289         }
2290
2291         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2292         if (!mta_list)
2293                 return;
2294
2295         /* The shared function expects a packed array of only addresses. */
2296         mc_ptr = netdev->mc_list;
2297
2298         for (i = 0; i < netdev->mc_count; i++) {
2299                 if (!mc_ptr)
2300                         break;
2301                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2302                 mc_ptr = mc_ptr->next;
2303         }
2304         igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2305                                       mac->rar_entry_count);
2306         kfree(mta_list);
2307 }
2308
2309 /* Need to wait a few seconds after link up to get diagnostic information from
2310  * the phy */
2311 static void igb_update_phy_info(unsigned long data)
2312 {
2313         struct igb_adapter *adapter = (struct igb_adapter *) data;
2314         igb_get_phy_info(&adapter->hw);
2315 }
2316
2317 /**
2318  * igb_watchdog - Timer Call-back
2319  * @data: pointer to adapter cast into an unsigned long
2320  **/
2321 static void igb_watchdog(unsigned long data)
2322 {
2323         struct igb_adapter *adapter = (struct igb_adapter *)data;
2324         /* Do the rest outside of interrupt context */
2325         schedule_work(&adapter->watchdog_task);
2326 }
2327
2328 static void igb_watchdog_task(struct work_struct *work)
2329 {
2330         struct igb_adapter *adapter = container_of(work,
2331                                         struct igb_adapter, watchdog_task);
2332         struct e1000_hw *hw = &adapter->hw;
2333
2334         struct net_device *netdev = adapter->netdev;
2335         struct igb_ring *tx_ring = adapter->tx_ring;
2336         struct e1000_mac_info *mac = &adapter->hw.mac;
2337         u32 link;
2338         u32 eics = 0;
2339         s32 ret_val;
2340         int i;
2341
2342         if ((netif_carrier_ok(netdev)) &&
2343             (rd32(E1000_STATUS) & E1000_STATUS_LU))
2344                 goto link_up;
2345
2346         ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2347         if ((ret_val == E1000_ERR_PHY) &&
2348             (hw->phy.type == e1000_phy_igp_3) &&
2349             (rd32(E1000_CTRL) &
2350              E1000_PHY_CTRL_GBE_DISABLE))
2351                 dev_info(&adapter->pdev->dev,
2352                          "Gigabit has been disabled, downgrading speed\n");
2353
2354         if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2355             !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2356                 link = mac->serdes_has_link;
2357         else
2358                 link = rd32(E1000_STATUS) &
2359                                       E1000_STATUS_LU;
2360
2361         if (link) {
2362                 if (!netif_carrier_ok(netdev)) {
2363                         u32 ctrl;
2364                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2365                                                    &adapter->link_speed,
2366                                                    &adapter->link_duplex);
2367
2368                         ctrl = rd32(E1000_CTRL);
2369                         /* Links status message must follow this format */
2370                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2371                                  "Flow Control: %s\n",
2372                                  netdev->name,
2373                                  adapter->link_speed,
2374                                  adapter->link_duplex == FULL_DUPLEX ?
2375                                  "Full Duplex" : "Half Duplex",
2376                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2377                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2378                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2379                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2380
2381                         /* tweak tx_queue_len according to speed/duplex and
2382                          * adjust the timeout factor */
2383                         netdev->tx_queue_len = adapter->tx_queue_len;
2384                         adapter->tx_timeout_factor = 1;
2385                         switch (adapter->link_speed) {
2386                         case SPEED_10:
2387                                 netdev->tx_queue_len = 10;
2388                                 adapter->tx_timeout_factor = 14;
2389                                 break;
2390                         case SPEED_100:
2391                                 netdev->tx_queue_len = 100;
2392                                 /* maybe add some timeout factor ? */
2393                                 break;
2394                         }
2395
2396                         netif_carrier_on(netdev);
2397                         netif_tx_wake_all_queues(netdev);
2398
2399                         if (!test_bit(__IGB_DOWN, &adapter->state))
2400                                 mod_timer(&adapter->phy_info_timer,
2401                                           round_jiffies(jiffies + 2 * HZ));
2402                 }
2403         } else {
2404                 if (netif_carrier_ok(netdev)) {
2405                         adapter->link_speed = 0;
2406                         adapter->link_duplex = 0;
2407                         /* Links status message must follow this format */
2408                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2409                                netdev->name);
2410                         netif_carrier_off(netdev);
2411                         netif_tx_stop_all_queues(netdev);
2412                         if (!test_bit(__IGB_DOWN, &adapter->state))
2413                                 mod_timer(&adapter->phy_info_timer,
2414                                           round_jiffies(jiffies + 2 * HZ));
2415                 }
2416         }
2417
2418 link_up:
2419         igb_update_stats(adapter);
2420
2421         mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2422         adapter->tpt_old = adapter->stats.tpt;
2423         mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2424         adapter->colc_old = adapter->stats.colc;
2425
2426         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2427         adapter->gorc_old = adapter->stats.gorc;
2428         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2429         adapter->gotc_old = adapter->stats.gotc;
2430
2431         igb_update_adaptive(&adapter->hw);
2432
2433         if (!netif_carrier_ok(netdev)) {
2434                 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2435                         /* We've lost link, so the controller stops DMA,
2436                          * but we've got queued Tx work that's never going
2437                          * to get done, so reset controller to flush Tx.
2438                          * (Do the reset outside of interrupt context). */
2439                         adapter->tx_timeout_count++;
2440                         schedule_work(&adapter->reset_task);
2441                 }
2442         }
2443
2444         /* Cause software interrupt to ensure rx ring is cleaned */
2445         if (adapter->msix_entries) {
2446                 for (i = 0; i < adapter->num_rx_queues; i++)
2447                         eics |= adapter->rx_ring[i].eims_value;
2448                 wr32(E1000_EICS, eics);
2449         } else {
2450                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2451         }
2452
2453         /* Force detection of hung controller every watchdog period */
2454         tx_ring->detect_tx_hung = true;
2455
2456         /* Reset the timer */
2457         if (!test_bit(__IGB_DOWN, &adapter->state))
2458                 mod_timer(&adapter->watchdog_timer,
2459                           round_jiffies(jiffies + 2 * HZ));
2460 }
2461
2462 enum latency_range {
2463         lowest_latency = 0,
2464         low_latency = 1,
2465         bulk_latency = 2,
2466         latency_invalid = 255
2467 };
2468
2469
2470 /**
2471  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2472  *
2473  *      Stores a new ITR value based on strictly on packet size.  This
2474  *      algorithm is less sophisticated than that used in igb_update_itr,
2475  *      due to the difficulty of synchronizing statistics across multiple
2476  *      receive rings.  The divisors and thresholds used by this fuction
2477  *      were determined based on theoretical maximum wire speed and testing
2478  *      data, in order to minimize response time while increasing bulk
2479  *      throughput.
2480  *      This functionality is controlled by the InterruptThrottleRate module
2481  *      parameter (see igb_param.c)
2482  *      NOTE:  This function is called only when operating in a multiqueue
2483  *             receive environment.
2484  * @rx_ring: pointer to ring
2485  **/
2486 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2487 {
2488         int new_val = rx_ring->itr_val;
2489         int avg_wire_size = 0;
2490         struct igb_adapter *adapter = rx_ring->adapter;
2491
2492         if (!rx_ring->total_packets)
2493                 goto clear_counts; /* no packets, so don't do anything */
2494
2495         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2496          * ints/sec - ITR timer value of 120 ticks.
2497          */
2498         if (adapter->link_speed != SPEED_1000) {
2499                 new_val = 120;
2500                 goto set_itr_val;
2501         }
2502         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2503
2504         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2505         avg_wire_size += 24;
2506
2507         /* Don't starve jumbo frames */
2508         avg_wire_size = min(avg_wire_size, 3000);
2509
2510         /* Give a little boost to mid-size frames */
2511         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2512                 new_val = avg_wire_size / 3;
2513         else
2514                 new_val = avg_wire_size / 2;
2515
2516 set_itr_val:
2517         if (new_val != rx_ring->itr_val) {
2518                 rx_ring->itr_val = new_val;
2519                 rx_ring->set_itr = 1;
2520         }
2521 clear_counts:
2522         rx_ring->total_bytes = 0;
2523         rx_ring->total_packets = 0;
2524 }
2525
2526 /**
2527  * igb_update_itr - update the dynamic ITR value based on statistics
2528  *      Stores a new ITR value based on packets and byte
2529  *      counts during the last interrupt.  The advantage of per interrupt
2530  *      computation is faster updates and more accurate ITR for the current
2531  *      traffic pattern.  Constants in this function were computed
2532  *      based on theoretical maximum wire speed and thresholds were set based
2533  *      on testing data as well as attempting to minimize response time
2534  *      while increasing bulk throughput.
2535  *      this functionality is controlled by the InterruptThrottleRate module
2536  *      parameter (see igb_param.c)
2537  *      NOTE:  These calculations are only valid when operating in a single-
2538  *             queue environment.
2539  * @adapter: pointer to adapter
2540  * @itr_setting: current adapter->itr
2541  * @packets: the number of packets during this measurement interval
2542  * @bytes: the number of bytes during this measurement interval
2543  **/
2544 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2545                                    int packets, int bytes)
2546 {
2547         unsigned int retval = itr_setting;
2548
2549         if (packets == 0)
2550                 goto update_itr_done;
2551
2552         switch (itr_setting) {
2553         case lowest_latency:
2554                 /* handle TSO and jumbo frames */
2555                 if (bytes/packets > 8000)
2556                         retval = bulk_latency;
2557                 else if ((packets < 5) && (bytes > 512))
2558                         retval = low_latency;
2559                 break;
2560         case low_latency:  /* 50 usec aka 20000 ints/s */
2561                 if (bytes > 10000) {
2562                         /* this if handles the TSO accounting */
2563                         if (bytes/packets > 8000) {
2564                                 retval = bulk_latency;
2565                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2566                                 retval = bulk_latency;
2567                         } else if ((packets > 35)) {
2568                                 retval = lowest_latency;
2569                         }
2570                 } else if (bytes/packets > 2000) {
2571                         retval = bulk_latency;
2572                 } else if (packets <= 2 && bytes < 512) {
2573                         retval = lowest_latency;
2574                 }
2575                 break;
2576         case bulk_latency: /* 250 usec aka 4000 ints/s */
2577                 if (bytes > 25000) {
2578                         if (packets > 35)
2579                                 retval = low_latency;
2580                 } else if (bytes < 6000) {
2581                         retval = low_latency;
2582                 }
2583                 break;
2584         }
2585
2586 update_itr_done:
2587         return retval;
2588 }
2589
2590 static void igb_set_itr(struct igb_adapter *adapter)
2591 {
2592         u16 current_itr;
2593         u32 new_itr = adapter->itr;
2594
2595         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2596         if (adapter->link_speed != SPEED_1000) {
2597                 current_itr = 0;
2598                 new_itr = 4000;
2599                 goto set_itr_now;
2600         }
2601
2602         adapter->rx_itr = igb_update_itr(adapter,
2603                                     adapter->rx_itr,
2604                                     adapter->rx_ring->total_packets,
2605                                     adapter->rx_ring->total_bytes);
2606
2607         if (adapter->rx_ring->buddy) {
2608                 adapter->tx_itr = igb_update_itr(adapter,
2609                                             adapter->tx_itr,
2610                                             adapter->tx_ring->total_packets,
2611                                             adapter->tx_ring->total_bytes);
2612
2613                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2614         } else {
2615                 current_itr = adapter->rx_itr;
2616         }
2617
2618         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2619         if (adapter->itr_setting == 3 &&
2620             current_itr == lowest_latency)
2621                 current_itr = low_latency;
2622
2623         switch (current_itr) {
2624         /* counts and packets in update_itr are dependent on these numbers */
2625         case lowest_latency:
2626                 new_itr = 70000;
2627                 break;
2628         case low_latency:
2629                 new_itr = 20000; /* aka hwitr = ~200 */
2630                 break;
2631         case bulk_latency:
2632                 new_itr = 4000;
2633                 break;
2634         default:
2635                 break;
2636         }
2637
2638 set_itr_now:
2639         adapter->rx_ring->total_bytes = 0;
2640         adapter->rx_ring->total_packets = 0;
2641         if (adapter->rx_ring->buddy) {
2642                 adapter->rx_ring->buddy->total_bytes = 0;
2643                 adapter->rx_ring->buddy->total_packets = 0;
2644         }
2645
2646         if (new_itr != adapter->itr) {
2647                 /* this attempts to bias the interrupt rate towards Bulk
2648                  * by adding intermediate steps when interrupt rate is
2649                  * increasing */
2650                 new_itr = new_itr > adapter->itr ?
2651                              min(adapter->itr + (new_itr >> 2), new_itr) :
2652                              new_itr;
2653                 /* Don't write the value here; it resets the adapter's
2654                  * internal timer, and causes us to delay far longer than
2655                  * we should between interrupts.  Instead, we write the ITR
2656                  * value at the beginning of the next interrupt so the timing
2657                  * ends up being correct.
2658                  */
2659                 adapter->itr = new_itr;
2660                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2661                 adapter->rx_ring->set_itr = 1;
2662         }
2663
2664         return;
2665 }
2666
2667
2668 #define IGB_TX_FLAGS_CSUM               0x00000001
2669 #define IGB_TX_FLAGS_VLAN               0x00000002
2670 #define IGB_TX_FLAGS_TSO                0x00000004
2671 #define IGB_TX_FLAGS_IPV4               0x00000008
2672 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2673 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2674
2675 static inline int igb_tso_adv(struct igb_adapter *adapter,
2676                               struct igb_ring *tx_ring,
2677                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2678 {
2679         struct e1000_adv_tx_context_desc *context_desc;
2680         unsigned int i;
2681         int err;
2682         struct igb_buffer *buffer_info;
2683         u32 info = 0, tu_cmd = 0;
2684         u32 mss_l4len_idx, l4len;
2685         *hdr_len = 0;
2686
2687         if (skb_header_cloned(skb)) {
2688                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2689                 if (err)
2690                         return err;
2691         }
2692
2693         l4len = tcp_hdrlen(skb);
2694         *hdr_len += l4len;
2695
2696         if (skb->protocol == htons(ETH_P_IP)) {
2697                 struct iphdr *iph = ip_hdr(skb);
2698                 iph->tot_len = 0;
2699                 iph->check = 0;
2700                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2701                                                          iph->daddr, 0,
2702                                                          IPPROTO_TCP,
2703                                                          0);
2704         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2705                 ipv6_hdr(skb)->payload_len = 0;
2706                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2707                                                        &ipv6_hdr(skb)->daddr,
2708                                                        0, IPPROTO_TCP, 0);
2709         }
2710
2711         i = tx_ring->next_to_use;
2712
2713         buffer_info = &tx_ring->buffer_info[i];
2714         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2715         /* VLAN MACLEN IPLEN */
2716         if (tx_flags & IGB_TX_FLAGS_VLAN)
2717                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2718         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2719         *hdr_len += skb_network_offset(skb);
2720         info |= skb_network_header_len(skb);
2721         *hdr_len += skb_network_header_len(skb);
2722         context_desc->vlan_macip_lens = cpu_to_le32(info);
2723
2724         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2725         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2726
2727         if (skb->protocol == htons(ETH_P_IP))
2728                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2729         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2730
2731         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2732
2733         /* MSS L4LEN IDX */
2734         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2735         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2736
2737         /* Context index must be unique per ring. */
2738         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2739                 mss_l4len_idx |= tx_ring->queue_index << 4;
2740
2741         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2742         context_desc->seqnum_seed = 0;
2743
2744         buffer_info->time_stamp = jiffies;
2745         buffer_info->next_to_watch = i;
2746         buffer_info->dma = 0;
2747         i++;
2748         if (i == tx_ring->count)
2749                 i = 0;
2750
2751         tx_ring->next_to_use = i;
2752
2753         return true;
2754 }
2755
2756 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2757                                         struct igb_ring *tx_ring,
2758                                         struct sk_buff *skb, u32 tx_flags)
2759 {
2760         struct e1000_adv_tx_context_desc *context_desc;
2761         unsigned int i;
2762         struct igb_buffer *buffer_info;
2763         u32 info = 0, tu_cmd = 0;
2764
2765         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2766             (tx_flags & IGB_TX_FLAGS_VLAN)) {
2767                 i = tx_ring->next_to_use;
2768                 buffer_info = &tx_ring->buffer_info[i];
2769                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2770
2771                 if (tx_flags & IGB_TX_FLAGS_VLAN)
2772                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2773                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2774                 if (skb->ip_summed == CHECKSUM_PARTIAL)
2775                         info |= skb_network_header_len(skb);
2776
2777                 context_desc->vlan_macip_lens = cpu_to_le32(info);
2778
2779                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2780
2781                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2782                         switch (skb->protocol) {
2783                         case __constant_htons(ETH_P_IP):
2784                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2785                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2786                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2787                                 break;
2788                         case __constant_htons(ETH_P_IPV6):
2789                                 /* XXX what about other V6 headers?? */
2790                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2791                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2792                                 break;
2793                         default:
2794                                 if (unlikely(net_ratelimit()))
2795                                         dev_warn(&adapter->pdev->dev,
2796                                             "partial checksum but proto=%x!\n",
2797                                             skb->protocol);
2798                                 break;
2799                         }
2800                 }
2801
2802                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2803                 context_desc->seqnum_seed = 0;
2804                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2805                         context_desc->mss_l4len_idx =
2806                                 cpu_to_le32(tx_ring->queue_index << 4);
2807
2808                 buffer_info->time_stamp = jiffies;
2809                 buffer_info->next_to_watch = i;
2810                 buffer_info->dma = 0;
2811
2812                 i++;
2813                 if (i == tx_ring->count)
2814                         i = 0;
2815                 tx_ring->next_to_use = i;
2816
2817                 return true;
2818         }
2819
2820
2821         return false;
2822 }
2823
2824 #define IGB_MAX_TXD_PWR 16
2825 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
2826
2827 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2828                                  struct igb_ring *tx_ring, struct sk_buff *skb,
2829                                  unsigned int first)
2830 {
2831         struct igb_buffer *buffer_info;
2832         unsigned int len = skb_headlen(skb);
2833         unsigned int count = 0, i;
2834         unsigned int f;
2835
2836         i = tx_ring->next_to_use;
2837
2838         buffer_info = &tx_ring->buffer_info[i];
2839         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2840         buffer_info->length = len;
2841         /* set time_stamp *before* dma to help avoid a possible race */
2842         buffer_info->time_stamp = jiffies;
2843         buffer_info->next_to_watch = i;
2844         buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2845                                           PCI_DMA_TODEVICE);
2846         count++;
2847         i++;
2848         if (i == tx_ring->count)
2849                 i = 0;
2850
2851         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2852                 struct skb_frag_struct *frag;
2853
2854                 frag = &skb_shinfo(skb)->frags[f];
2855                 len = frag->size;
2856
2857                 buffer_info = &tx_ring->buffer_info[i];
2858                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2859                 buffer_info->length = len;
2860                 buffer_info->time_stamp = jiffies;
2861                 buffer_info->next_to_watch = i;
2862                 buffer_info->dma = pci_map_page(adapter->pdev,
2863                                                 frag->page,
2864                                                 frag->page_offset,
2865                                                 len,
2866                                                 PCI_DMA_TODEVICE);
2867
2868                 count++;
2869                 i++;
2870                 if (i == tx_ring->count)
2871                         i = 0;
2872         }
2873
2874         i = ((i == 0) ? tx_ring->count - 1 : i - 1);
2875         tx_ring->buffer_info[i].skb = skb;
2876         tx_ring->buffer_info[first].next_to_watch = i;
2877
2878         return count;
2879 }
2880
2881 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2882                                     struct igb_ring *tx_ring,
2883                                     int tx_flags, int count, u32 paylen,
2884                                     u8 hdr_len)
2885 {
2886         union e1000_adv_tx_desc *tx_desc = NULL;
2887         struct igb_buffer *buffer_info;
2888         u32 olinfo_status = 0, cmd_type_len;
2889         unsigned int i;
2890
2891         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2892                         E1000_ADVTXD_DCMD_DEXT);
2893
2894         if (tx_flags & IGB_TX_FLAGS_VLAN)
2895                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2896
2897         if (tx_flags & IGB_TX_FLAGS_TSO) {
2898                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2899
2900                 /* insert tcp checksum */
2901                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2902
2903                 /* insert ip checksum */
2904                 if (tx_flags & IGB_TX_FLAGS_IPV4)
2905                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2906
2907         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2908                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2909         }
2910
2911         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2912             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2913                          IGB_TX_FLAGS_VLAN)))
2914                 olinfo_status |= tx_ring->queue_index << 4;
2915
2916         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2917
2918         i = tx_ring->next_to_use;
2919         while (count--) {
2920                 buffer_info = &tx_ring->buffer_info[i];
2921                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2922                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2923                 tx_desc->read.cmd_type_len =
2924                         cpu_to_le32(cmd_type_len | buffer_info->length);
2925                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2926                 i++;
2927                 if (i == tx_ring->count)
2928                         i = 0;
2929         }
2930
2931         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2932         /* Force memory writes to complete before letting h/w
2933          * know there are new descriptors to fetch.  (Only
2934          * applicable for weak-ordered memory model archs,
2935          * such as IA-64). */
2936         wmb();
2937
2938         tx_ring->next_to_use = i;
2939         writel(i, adapter->hw.hw_addr + tx_ring->tail);
2940         /* we need this if more than one processor can write to our tail
2941          * at a time, it syncronizes IO on IA64/Altix systems */
2942         mmiowb();
2943 }
2944
2945 static int __igb_maybe_stop_tx(struct net_device *netdev,
2946                                struct igb_ring *tx_ring, int size)
2947 {
2948         struct igb_adapter *adapter = netdev_priv(netdev);
2949
2950         netif_stop_subqueue(netdev, tx_ring->queue_index);
2951
2952         /* Herbert's original patch had:
2953          *  smp_mb__after_netif_stop_queue();
2954          * but since that doesn't exist yet, just open code it. */
2955         smp_mb();
2956
2957         /* We need to check again in a case another CPU has just
2958          * made room available. */
2959         if (IGB_DESC_UNUSED(tx_ring) < size)
2960                 return -EBUSY;
2961
2962         /* A reprieve! */
2963         netif_wake_subqueue(netdev, tx_ring->queue_index);
2964         ++adapter->restart_queue;
2965         return 0;
2966 }
2967
2968 static int igb_maybe_stop_tx(struct net_device *netdev,
2969                              struct igb_ring *tx_ring, int size)
2970 {
2971         if (IGB_DESC_UNUSED(tx_ring) >= size)
2972                 return 0;
2973         return __igb_maybe_stop_tx(netdev, tx_ring, size);
2974 }
2975
2976 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2977
2978 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2979                                    struct net_device *netdev,
2980                                    struct igb_ring *tx_ring)
2981 {
2982         struct igb_adapter *adapter = netdev_priv(netdev);
2983         unsigned int first;
2984         unsigned int tx_flags = 0;
2985         unsigned int len;
2986         u8 hdr_len = 0;
2987         int tso = 0;
2988
2989         len = skb_headlen(skb);
2990
2991         if (test_bit(__IGB_DOWN, &adapter->state)) {
2992                 dev_kfree_skb_any(skb);
2993                 return NETDEV_TX_OK;
2994         }
2995
2996         if (skb->len <= 0) {
2997                 dev_kfree_skb_any(skb);
2998                 return NETDEV_TX_OK;
2999         }
3000
3001         /* need: 1 descriptor per page,
3002          *       + 2 desc gap to keep tail from touching head,
3003          *       + 1 desc for skb->data,
3004          *       + 1 desc for context descriptor,
3005          * otherwise try next time */
3006         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3007                 /* this is a hard error */
3008                 return NETDEV_TX_BUSY;
3009         }
3010         skb_orphan(skb);
3011
3012         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3013                 tx_flags |= IGB_TX_FLAGS_VLAN;
3014                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3015         }
3016
3017         if (skb->protocol == htons(ETH_P_IP))
3018                 tx_flags |= IGB_TX_FLAGS_IPV4;
3019
3020         first = tx_ring->next_to_use;
3021
3022         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3023                                               &hdr_len) : 0;
3024
3025         if (tso < 0) {
3026                 dev_kfree_skb_any(skb);
3027                 return NETDEV_TX_OK;
3028         }
3029
3030         if (tso)
3031                 tx_flags |= IGB_TX_FLAGS_TSO;
3032         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3033                         if (skb->ip_summed == CHECKSUM_PARTIAL)
3034                                 tx_flags |= IGB_TX_FLAGS_CSUM;
3035
3036         igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3037                          igb_tx_map_adv(adapter, tx_ring, skb, first),
3038                          skb->len, hdr_len);
3039
3040         netdev->trans_start = jiffies;
3041
3042         /* Make sure there is space in the ring for the next send. */
3043         igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3044
3045         return NETDEV_TX_OK;
3046 }
3047
3048 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3049 {
3050         struct igb_adapter *adapter = netdev_priv(netdev);
3051         struct igb_ring *tx_ring;
3052
3053         int r_idx = 0;
3054         r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3055         tx_ring = adapter->multi_tx_table[r_idx];
3056
3057         /* This goes back to the question of how to logically map a tx queue
3058          * to a flow.  Right now, performance is impacted slightly negatively
3059          * if using multiple tx queues.  If the stack breaks away from a
3060          * single qdisc implementation, we can look at this again. */
3061         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3062 }
3063
3064 /**
3065  * igb_tx_timeout - Respond to a Tx Hang
3066  * @netdev: network interface device structure
3067  **/
3068 static void igb_tx_timeout(struct net_device *netdev)
3069 {
3070         struct igb_adapter *adapter = netdev_priv(netdev);
3071         struct e1000_hw *hw = &adapter->hw;
3072
3073         /* Do the reset outside of interrupt context */
3074         adapter->tx_timeout_count++;
3075         schedule_work(&adapter->reset_task);
3076         wr32(E1000_EICS, adapter->eims_enable_mask &
3077                 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3078 }
3079
3080 static void igb_reset_task(struct work_struct *work)
3081 {
3082         struct igb_adapter *adapter;
3083         adapter = container_of(work, struct igb_adapter, reset_task);
3084
3085         igb_reinit_locked(adapter);
3086 }
3087
3088 /**
3089  * igb_get_stats - Get System Network Statistics
3090  * @netdev: network interface device structure
3091  *
3092  * Returns the address of the device statistics structure.
3093  * The statistics are actually updated from the timer callback.
3094  **/
3095 static struct net_device_stats *
3096 igb_get_stats(struct net_device *netdev)
3097 {
3098         struct igb_adapter *adapter = netdev_priv(netdev);
3099
3100         /* only return the current stats */
3101         return &adapter->net_stats;
3102 }
3103
3104 /**
3105  * igb_change_mtu - Change the Maximum Transfer Unit
3106  * @netdev: network interface device structure
3107  * @new_mtu: new value for maximum frame size
3108  *
3109  * Returns 0 on success, negative on failure
3110  **/
3111 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3112 {
3113         struct igb_adapter *adapter = netdev_priv(netdev);
3114         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3115
3116         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3117             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3118                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3119                 return -EINVAL;
3120         }
3121
3122 #define MAX_STD_JUMBO_FRAME_SIZE 9234
3123         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3124                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3125                 return -EINVAL;
3126         }
3127
3128         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3129                 msleep(1);
3130         /* igb_down has a dependency on max_frame_size */
3131         adapter->max_frame_size = max_frame;
3132         if (netif_running(netdev))
3133                 igb_down(adapter);
3134
3135         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3136          * means we reserve 2 more, this pushes us to allocate from the next
3137          * larger slab size.
3138          * i.e. RXBUFFER_2048 --> size-4096 slab
3139          */
3140
3141         if (max_frame <= IGB_RXBUFFER_256)
3142                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3143         else if (max_frame <= IGB_RXBUFFER_512)
3144                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3145         else if (max_frame <= IGB_RXBUFFER_1024)
3146                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3147         else if (max_frame <= IGB_RXBUFFER_2048)
3148                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3149         else
3150 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3151                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3152 #else
3153                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3154 #endif
3155         /* adjust allocation if LPE protects us, and we aren't using SBP */
3156         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3157              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3158                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3159
3160         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3161                  netdev->mtu, new_mtu);
3162         netdev->mtu = new_mtu;
3163
3164         if (netif_running(netdev))
3165                 igb_up(adapter);
3166         else
3167                 igb_reset(adapter);
3168
3169         clear_bit(__IGB_RESETTING, &adapter->state);
3170
3171         return 0;
3172 }
3173
3174 /**
3175  * igb_update_stats - Update the board statistics counters
3176  * @adapter: board private structure
3177  **/
3178
3179 void igb_update_stats(struct igb_adapter *adapter)
3180 {
3181         struct e1000_hw *hw = &adapter->hw;
3182         struct pci_dev *pdev = adapter->pdev;
3183         u16 phy_tmp;
3184
3185 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3186
3187         /*
3188          * Prevent stats update while adapter is being reset, or if the pci
3189          * connection is down.
3190          */
3191         if (adapter->link_speed == 0)
3192                 return;
3193         if (pci_channel_offline(pdev))
3194                 return;
3195
3196         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3197         adapter->stats.gprc += rd32(E1000_GPRC);
3198         adapter->stats.gorc += rd32(E1000_GORCL);
3199         rd32(E1000_GORCH); /* clear GORCL */
3200         adapter->stats.bprc += rd32(E1000_BPRC);
3201         adapter->stats.mprc += rd32(E1000_MPRC);
3202         adapter->stats.roc += rd32(E1000_ROC);
3203
3204         adapter->stats.prc64 += rd32(E1000_PRC64);
3205         adapter->stats.prc127 += rd32(E1000_PRC127);
3206         adapter->stats.prc255 += rd32(E1000_PRC255);
3207         adapter->stats.prc511 += rd32(E1000_PRC511);
3208         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3209         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3210         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3211         adapter->stats.sec += rd32(E1000_SEC);
3212
3213         adapter->stats.mpc += rd32(E1000_MPC);
3214         adapter->stats.scc += rd32(E1000_SCC);
3215         adapter->stats.ecol += rd32(E1000_ECOL);
3216         adapter->stats.mcc += rd32(E1000_MCC);
3217         adapter->stats.latecol += rd32(E1000_LATECOL);
3218         adapter->stats.dc += rd32(E1000_DC);
3219         adapter->stats.rlec += rd32(E1000_RLEC);
3220         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3221         adapter->stats.xontxc += rd32(E1000_XONTXC);
3222         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3223         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3224         adapter->stats.fcruc += rd32(E1000_FCRUC);
3225         adapter->stats.gptc += rd32(E1000_GPTC);
3226         adapter->stats.gotc += rd32(E1000_GOTCL);
3227         rd32(E1000_GOTCH); /* clear GOTCL */
3228         adapter->stats.rnbc += rd32(E1000_RNBC);
3229         adapter->stats.ruc += rd32(E1000_RUC);
3230         adapter->stats.rfc += rd32(E1000_RFC);
3231         adapter->stats.rjc += rd32(E1000_RJC);
3232         adapter->stats.tor += rd32(E1000_TORH);
3233         adapter->stats.tot += rd32(E1000_TOTH);
3234         adapter->stats.tpr += rd32(E1000_TPR);
3235
3236         adapter->stats.ptc64 += rd32(E1000_PTC64);
3237         adapter->stats.ptc127 += rd32(E1000_PTC127);
3238         adapter->stats.ptc255 += rd32(E1000_PTC255);
3239         adapter->stats.ptc511 += rd32(E1000_PTC511);
3240         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3241         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3242
3243         adapter->stats.mptc += rd32(E1000_MPTC);
3244         adapter->stats.bptc += rd32(E1000_BPTC);
3245
3246         /* used for adaptive IFS */
3247
3248         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3249         adapter->stats.tpt += hw->mac.tx_packet_delta;
3250         hw->mac.collision_delta = rd32(E1000_COLC);
3251         adapter->stats.colc += hw->mac.collision_delta;
3252
3253         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3254         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3255         adapter->stats.tncrs += rd32(E1000_TNCRS);
3256         adapter->stats.tsctc += rd32(E1000_TSCTC);
3257         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3258
3259         adapter->stats.iac += rd32(E1000_IAC);
3260         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3261         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3262         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3263         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3264         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3265         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3266         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3267         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3268
3269         /* Fill out the OS statistics structure */
3270         adapter->net_stats.multicast = adapter->stats.mprc;
3271         adapter->net_stats.collisions = adapter->stats.colc;
3272
3273         /* Rx Errors */
3274
3275         /* RLEC on some newer hardware can be incorrect so build
3276         * our own version based on RUC and ROC */
3277         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3278                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3279                 adapter->stats.ruc + adapter->stats.roc +
3280                 adapter->stats.cexterr;
3281         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3282                                               adapter->stats.roc;
3283         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3284         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3285         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3286
3287         /* Tx Errors */
3288         adapter->net_stats.tx_errors = adapter->stats.ecol +
3289                                        adapter->stats.latecol;
3290         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3291         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3292         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3293
3294         /* Tx Dropped needs to be maintained elsewhere */
3295
3296         /* Phy Stats */
3297         if (hw->phy.media_type == e1000_media_type_copper) {
3298                 if ((adapter->link_speed == SPEED_1000) &&
3299                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
3300                                               &phy_tmp))) {
3301                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3302                         adapter->phy_stats.idle_errors += phy_tmp;
3303                 }
3304         }
3305
3306         /* Management Stats */
3307         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3308         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3309         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3310 }
3311
3312
3313 static irqreturn_t igb_msix_other(int irq, void *data)
3314 {
3315         struct net_device *netdev = data;
3316         struct igb_adapter *adapter = netdev_priv(netdev);
3317         struct e1000_hw *hw = &adapter->hw;
3318         u32 icr = rd32(E1000_ICR);
3319
3320         /* reading ICR causes bit 31 of EICR to be cleared */
3321         if (!(icr & E1000_ICR_LSC))
3322                 goto no_link_interrupt;
3323         hw->mac.get_link_status = 1;
3324         /* guard against interrupt when we're going down */
3325         if (!test_bit(__IGB_DOWN, &adapter->state))
3326                 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3327
3328 no_link_interrupt:
3329         wr32(E1000_IMS, E1000_IMS_LSC);
3330         wr32(E1000_EIMS, adapter->eims_other);
3331
3332         return IRQ_HANDLED;
3333 }
3334
3335 static irqreturn_t igb_msix_tx(int irq, void *data)
3336 {
3337         struct igb_ring *tx_ring = data;
3338         struct igb_adapter *adapter = tx_ring->adapter;
3339         struct e1000_hw *hw = &adapter->hw;
3340
3341 #ifdef CONFIG_IGB_DCA
3342         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3343                 igb_update_tx_dca(tx_ring);
3344 #endif
3345         tx_ring->total_bytes = 0;
3346         tx_ring->total_packets = 0;
3347
3348         /* auto mask will automatically reenable the interrupt when we write
3349          * EICS */
3350         if (!igb_clean_tx_irq(tx_ring))
3351                 /* Ring was not completely cleaned, so fire another interrupt */
3352                 wr32(E1000_EICS, tx_ring->eims_value);
3353         else
3354                 wr32(E1000_EIMS, tx_ring->eims_value);
3355
3356         return IRQ_HANDLED;
3357 }
3358
3359 static void igb_write_itr(struct igb_ring *ring)
3360 {
3361         struct e1000_hw *hw = &ring->adapter->hw;
3362         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3363                 switch (hw->mac.type) {
3364                 case e1000_82576:
3365                         wr32(ring->itr_register,
3366                              ring->itr_val |
3367                              0x80000000);
3368                         break;
3369                 default:
3370                         wr32(ring->itr_register,
3371                              ring->itr_val |
3372                              (ring->itr_val << 16));
3373                         break;
3374                 }
3375                 ring->set_itr = 0;
3376         }
3377 }
3378
3379 static irqreturn_t igb_msix_rx(int irq, void *data)
3380 {
3381         struct igb_ring *rx_ring = data;
3382
3383         /* Write the ITR value calculated at the end of the
3384          * previous interrupt.
3385          */
3386
3387         igb_write_itr(rx_ring);
3388
3389         if (netif_rx_schedule_prep(&rx_ring->napi))
3390                 __netif_rx_schedule(&rx_ring->napi);
3391
3392 #ifdef CONFIG_IGB_DCA
3393         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3394                 igb_update_rx_dca(rx_ring);
3395 #endif
3396                 return IRQ_HANDLED;
3397 }
3398
3399 #ifdef CONFIG_IGB_DCA
3400 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3401 {
3402         u32 dca_rxctrl;
3403         struct igb_adapter *adapter = rx_ring->adapter;
3404         struct e1000_hw *hw = &adapter->hw;
3405         int cpu = get_cpu();
3406         int q = rx_ring->reg_idx;
3407
3408         if (rx_ring->cpu != cpu) {
3409                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3410                 if (hw->mac.type == e1000_82576) {
3411                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3412                         dca_rxctrl |= dca_get_tag(cpu) <<
3413                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3414                 } else {
3415                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3416                         dca_rxctrl |= dca_get_tag(cpu);
3417                 }
3418                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3419                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3420                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3421                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3422                 rx_ring->cpu = cpu;
3423         }
3424         put_cpu();
3425 }
3426
3427 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3428 {
3429         u32 dca_txctrl;
3430         struct igb_adapter *adapter = tx_ring->adapter;
3431         struct e1000_hw *hw = &adapter->hw;
3432         int cpu = get_cpu();
3433         int q = tx_ring->reg_idx;
3434
3435         if (tx_ring->cpu != cpu) {
3436                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3437                 if (hw->mac.type == e1000_82576) {
3438                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3439                         dca_txctrl |= dca_get_tag(cpu) <<
3440                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3441                 } else {
3442                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3443                         dca_txctrl |= dca_get_tag(cpu);
3444                 }
3445                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3446                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3447                 tx_ring->cpu = cpu;
3448         }
3449         put_cpu();
3450 }
3451
3452 static void igb_setup_dca(struct igb_adapter *adapter)
3453 {
3454         int i;
3455
3456         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3457                 return;
3458
3459         for (i = 0; i < adapter->num_tx_queues; i++) {
3460                 adapter->tx_ring[i].cpu = -1;
3461                 igb_update_tx_dca(&adapter->tx_ring[i]);
3462         }
3463         for (i = 0; i < adapter->num_rx_queues; i++) {
3464                 adapter->rx_ring[i].cpu = -1;
3465                 igb_update_rx_dca(&adapter->rx_ring[i]);
3466         }
3467 }
3468
3469 static int __igb_notify_dca(struct device *dev, void *data)
3470 {
3471         struct net_device *netdev = dev_get_drvdata(dev);
3472         struct igb_adapter *adapter = netdev_priv(netdev);
3473         struct e1000_hw *hw = &adapter->hw;
3474         unsigned long event = *(unsigned long *)data;
3475
3476         if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3477                 goto out;
3478
3479         switch (event) {
3480         case DCA_PROVIDER_ADD:
3481                 /* if already enabled, don't do it again */
3482                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3483                         break;
3484                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3485                 /* Always use CB2 mode, difference is masked
3486                  * in the CB driver. */
3487                 wr32(E1000_DCA_CTRL, 2);
3488                 if (dca_add_requester(dev) == 0) {
3489                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3490                         igb_setup_dca(adapter);
3491                         break;
3492                 }
3493                 /* Fall Through since DCA is disabled. */
3494         case DCA_PROVIDER_REMOVE:
3495                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3496                         /* without this a class_device is left
3497                          * hanging around in the sysfs model */
3498                         dca_remove_requester(dev);
3499                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3500                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3501                         wr32(E1000_DCA_CTRL, 1);
3502                 }
3503                 break;
3504         }
3505 out:
3506         return 0;
3507 }
3508
3509 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3510                           void *p)
3511 {
3512         int ret_val;
3513
3514         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3515                                          __igb_notify_dca);
3516
3517         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3518 }
3519 #endif /* CONFIG_IGB_DCA */
3520
3521 /**
3522  * igb_intr_msi - Interrupt Handler
3523  * @irq: interrupt number
3524  * @data: pointer to a network interface device structure
3525  **/
3526 static irqreturn_t igb_intr_msi(int irq, void *data)
3527 {
3528         struct net_device *netdev = data;
3529         struct igb_adapter *adapter = netdev_priv(netdev);
3530         struct e1000_hw *hw = &adapter->hw;
3531         /* read ICR disables interrupts using IAM */
3532         u32 icr = rd32(E1000_ICR);
3533
3534         igb_write_itr(adapter->rx_ring);
3535
3536         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3537                 hw->mac.get_link_status = 1;
3538                 if (!test_bit(__IGB_DOWN, &adapter->state))
3539                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3540         }
3541
3542         netif_rx_schedule(&adapter->rx_ring[0].napi);
3543
3544         return IRQ_HANDLED;
3545 }
3546
3547 /**
3548  * igb_intr - Interrupt Handler
3549  * @irq: interrupt number
3550  * @data: pointer to a network interface device structure
3551  **/
3552 static irqreturn_t igb_intr(int irq, void *data)
3553 {
3554         struct net_device *netdev = data;
3555         struct igb_adapter *adapter = netdev_priv(netdev);
3556         struct e1000_hw *hw = &adapter->hw;
3557         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
3558          * need for the IMC write */
3559         u32 icr = rd32(E1000_ICR);
3560         u32 eicr = 0;
3561         if (!icr)
3562                 return IRQ_NONE;  /* Not our interrupt */
3563
3564         igb_write_itr(adapter->rx_ring);
3565
3566         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3567          * not set, then the adapter didn't send an interrupt */
3568         if (!(icr & E1000_ICR_INT_ASSERTED))
3569                 return IRQ_NONE;
3570
3571         eicr = rd32(E1000_EICR);
3572
3573         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3574                 hw->mac.get_link_status = 1;
3575                 /* guard against interrupt when we're going down */
3576                 if (!test_bit(__IGB_DOWN, &adapter->state))
3577                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3578         }
3579
3580         netif_rx_schedule(&adapter->rx_ring[0].napi);
3581
3582         return IRQ_HANDLED;
3583 }
3584
3585 /**
3586  * igb_poll - NAPI Rx polling callback
3587  * @napi: napi polling structure
3588  * @budget: count of how many packets we should handle
3589  **/
3590 static int igb_poll(struct napi_struct *napi, int budget)
3591 {
3592         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3593         struct igb_adapter *adapter = rx_ring->adapter;
3594         struct net_device *netdev = adapter->netdev;
3595         int tx_clean_complete, work_done = 0;
3596
3597         /* this poll routine only supports one tx and one rx queue */
3598 #ifdef CONFIG_IGB_DCA
3599         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3600                 igb_update_tx_dca(&adapter->tx_ring[0]);
3601 #endif
3602         tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3603
3604 #ifdef CONFIG_IGB_DCA
3605         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3606                 igb_update_rx_dca(&adapter->rx_ring[0]);
3607 #endif
3608         igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3609
3610         /* If no Tx and not enough Rx work done, exit the polling mode */
3611         if ((tx_clean_complete && (work_done < budget)) ||
3612             !netif_running(netdev)) {
3613                 if (adapter->itr_setting & 3)
3614                         igb_set_itr(adapter);
3615                 netif_rx_complete(napi);
3616                 if (!test_bit(__IGB_DOWN, &adapter->state))
3617                         igb_irq_enable(adapter);
3618                 return 0;
3619         }
3620
3621         return 1;
3622 }
3623
3624 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3625 {
3626         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3627         struct igb_adapter *adapter = rx_ring->adapter;
3628         struct e1000_hw *hw = &adapter->hw;
3629         struct net_device *netdev = adapter->netdev;
3630         int work_done = 0;
3631
3632 #ifdef CONFIG_IGB_DCA
3633         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3634                 igb_update_rx_dca(rx_ring);
3635 #endif
3636         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3637
3638
3639         /* If not enough Rx work done, exit the polling mode */
3640         if ((work_done == 0) || !netif_running(netdev)) {
3641                 netif_rx_complete(napi);
3642
3643                 if (adapter->itr_setting & 3) {
3644                         if (adapter->num_rx_queues == 1)
3645                                 igb_set_itr(adapter);
3646                         else
3647                                 igb_update_ring_itr(rx_ring);
3648                 }
3649
3650                 if (!test_bit(__IGB_DOWN, &adapter->state))
3651                         wr32(E1000_EIMS, rx_ring->eims_value);
3652
3653                 return 0;
3654         }
3655
3656         return 1;
3657 }
3658
3659 /**
3660  * igb_clean_tx_irq - Reclaim resources after transmit completes
3661  * @adapter: board private structure
3662  * returns true if ring is completely cleaned
3663  **/
3664 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3665 {
3666         struct igb_adapter *adapter = tx_ring->adapter;
3667         struct net_device *netdev = adapter->netdev;
3668         struct e1000_hw *hw = &adapter->hw;
3669         struct igb_buffer *buffer_info;
3670         struct sk_buff *skb;
3671         union e1000_adv_tx_desc *tx_desc, *eop_desc;
3672         unsigned int total_bytes = 0, total_packets = 0;
3673         unsigned int i, eop, count = 0;
3674         bool cleaned = false;
3675
3676         i = tx_ring->next_to_clean;
3677         eop = tx_ring->buffer_info[i].next_to_watch;
3678         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3679
3680         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3681                (count < tx_ring->count)) {
3682                 for (cleaned = false; !cleaned; count++) {
3683                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3684                         buffer_info = &tx_ring->buffer_info[i];
3685                         cleaned = (i == eop);
3686                         skb = buffer_info->skb;
3687
3688                         if (skb) {
3689                                 unsigned int segs, bytecount;
3690                                 /* gso_segs is currently only valid for tcp */
3691                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
3692                                 /* multiply data chunks by size of headers */
3693                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
3694                                             skb->len;
3695                                 total_packets += segs;
3696                                 total_bytes += bytecount;
3697                         }
3698
3699                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
3700                         tx_desc->wb.status = 0;
3701
3702                         i++;
3703                         if (i == tx_ring->count)
3704                                 i = 0;
3705                 }
3706
3707                 eop = tx_ring->buffer_info[i].next_to_watch;
3708                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3709         }
3710
3711         tx_ring->next_to_clean = i;
3712
3713         if (unlikely(count &&
3714                      netif_carrier_ok(netdev) &&
3715                      IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3716                 /* Make sure that anybody stopping the queue after this
3717                  * sees the new next_to_clean.
3718                  */
3719                 smp_mb();
3720                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3721                     !(test_bit(__IGB_DOWN, &adapter->state))) {
3722                         netif_wake_subqueue(netdev, tx_ring->queue_index);
3723                         ++adapter->restart_queue;
3724                 }
3725         }
3726
3727         if (tx_ring->detect_tx_hung) {
3728                 /* Detect a transmit hang in hardware, this serializes the
3729                  * check with the clearing of time_stamp and movement of i */
3730                 tx_ring->detect_tx_hung = false;
3731                 if (tx_ring->buffer_info[i].time_stamp &&
3732                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3733                                (adapter->tx_timeout_factor * HZ))
3734                     && !(rd32(E1000_STATUS) &
3735                          E1000_STATUS_TXOFF)) {
3736
3737                         /* detected Tx unit hang */
3738                         dev_err(&adapter->pdev->dev,
3739                                 "Detected Tx Unit Hang\n"
3740                                 "  Tx Queue             <%d>\n"
3741                                 "  TDH                  <%x>\n"
3742                                 "  TDT                  <%x>\n"
3743                                 "  next_to_use          <%x>\n"
3744                                 "  next_to_clean        <%x>\n"
3745                                 "buffer_info[next_to_clean]\n"
3746                                 "  time_stamp           <%lx>\n"
3747                                 "  next_to_watch        <%x>\n"
3748                                 "  jiffies              <%lx>\n"
3749                                 "  desc.status          <%x>\n",
3750                                 tx_ring->queue_index,
3751                                 readl(adapter->hw.hw_addr + tx_ring->head),
3752                                 readl(adapter->hw.hw_addr + tx_ring->tail),
3753                                 tx_ring->next_to_use,
3754                                 tx_ring->next_to_clean,
3755                                 tx_ring->buffer_info[i].time_stamp,
3756                                 eop,
3757                                 jiffies,
3758                                 eop_desc->wb.status);
3759                         netif_stop_subqueue(netdev, tx_ring->queue_index);
3760                 }
3761         }
3762         tx_ring->total_bytes += total_bytes;
3763         tx_ring->total_packets += total_packets;
3764         tx_ring->tx_stats.bytes += total_bytes;
3765         tx_ring->tx_stats.packets += total_packets;
3766         adapter->net_stats.tx_bytes += total_bytes;
3767         adapter->net_stats.tx_packets += total_packets;
3768         return (count < tx_ring->count);
3769 }
3770
3771 #ifdef CONFIG_IGB_LRO
3772  /**
3773  * igb_get_skb_hdr - helper function for LRO header processing
3774  * @skb: pointer to sk_buff to be added to LRO packet
3775  * @iphdr: pointer to ip header structure
3776  * @tcph: pointer to tcp header structure
3777  * @hdr_flags: pointer to header flags
3778  * @priv: pointer to the receive descriptor for the current sk_buff
3779  **/
3780 static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3781                            u64 *hdr_flags, void *priv)
3782 {
3783         union e1000_adv_rx_desc *rx_desc = priv;
3784         u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3785                        (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3786
3787         /* Verify that this is a valid IPv4 TCP packet */
3788         if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3789                           E1000_RXDADV_PKTTYPE_TCP))
3790                 return -1;
3791
3792         /* Set network headers */
3793         skb_reset_network_header(skb);
3794         skb_set_transport_header(skb, ip_hdrlen(skb));
3795         *iphdr = ip_hdr(skb);
3796         *tcph = tcp_hdr(skb);
3797         *hdr_flags = LRO_IPV4 | LRO_TCP;
3798
3799         return 0;
3800
3801 }
3802 #endif /* CONFIG_IGB_LRO */
3803
3804 /**
3805  * igb_receive_skb - helper function to handle rx indications
3806  * @ring: pointer to receive ring receving this packet
3807  * @status: descriptor status field as written by hardware
3808  * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3809  * @skb: pointer to sk_buff to be indicated to stack
3810  **/
3811 static void igb_receive_skb(struct igb_ring *ring, u8 status,
3812                             union e1000_adv_rx_desc * rx_desc,
3813                             struct sk_buff *skb)
3814 {
3815         struct igb_adapter * adapter = ring->adapter;
3816         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3817
3818 #ifdef CONFIG_IGB_LRO
3819         if (adapter->netdev->features & NETIF_F_LRO &&
3820             skb->ip_summed == CHECKSUM_UNNECESSARY) {
3821                 if (vlan_extracted)
3822                         lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3823                                            adapter->vlgrp,
3824                                            le16_to_cpu(rx_desc->wb.upper.vlan),
3825                                            rx_desc);
3826                 else
3827                         lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3828                 ring->lro_used = 1;
3829         } else {
3830 #endif
3831                 if (vlan_extracted)
3832                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3833                                           le16_to_cpu(rx_desc->wb.upper.vlan));
3834                 else
3835
3836                         netif_receive_skb(skb);
3837 #ifdef CONFIG_IGB_LRO
3838         }
3839 #endif
3840 }
3841
3842
3843 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3844                                        u32 status_err, struct sk_buff *skb)
3845 {
3846         skb->ip_summed = CHECKSUM_NONE;
3847
3848         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3849         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3850                 return;
3851         /* TCP/UDP checksum error bit is set */
3852         if (status_err &
3853             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3854                 /* let the stack verify checksum errors */
3855                 adapter->hw_csum_err++;
3856                 return;
3857         }
3858         /* It must be a TCP or UDP packet with a valid checksum */
3859         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3860                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3861
3862         adapter->hw_csum_good++;
3863 }
3864
3865 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3866                                  int *work_done, int budget)
3867 {
3868         struct igb_adapter *adapter = rx_ring->adapter;
3869         struct net_device *netdev = adapter->netdev;
3870         struct pci_dev *pdev = adapter->pdev;
3871         union e1000_adv_rx_desc *rx_desc , *next_rxd;
3872         struct igb_buffer *buffer_info , *next_buffer;
3873         struct sk_buff *skb;
3874         unsigned int i;
3875         u32 length, hlen, staterr;
3876         bool cleaned = false;
3877         int cleaned_count = 0;
3878         unsigned int total_bytes = 0, total_packets = 0;
3879
3880         i = rx_ring->next_to_clean;
3881         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3882         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3883
3884         while (staterr & E1000_RXD_STAT_DD) {
3885                 if (*work_done >= budget)
3886                         break;
3887                 (*work_done)++;
3888                 buffer_info = &rx_ring->buffer_info[i];
3889
3890                 /* HW will not DMA in data larger than the given buffer, even
3891                  * if it parses the (NFS, of course) header to be larger.  In
3892                  * that case, it fills the header buffer and spills the rest
3893                  * into the page.
3894                  */
3895                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3896                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3897                 if (hlen > adapter->rx_ps_hdr_size)
3898                         hlen = adapter->rx_ps_hdr_size;
3899
3900                 length = le16_to_cpu(rx_desc->wb.upper.length);
3901                 cleaned = true;
3902                 cleaned_count++;
3903
3904                 skb = buffer_info->skb;
3905                 prefetch(skb->data - NET_IP_ALIGN);
3906                 buffer_info->skb = NULL;
3907                 if (!adapter->rx_ps_hdr_size) {
3908                         pci_unmap_single(pdev, buffer_info->dma,
3909                                          adapter->rx_buffer_len +
3910                                            NET_IP_ALIGN,
3911                                          PCI_DMA_FROMDEVICE);
3912                         skb_put(skb, length);
3913                         goto send_up;
3914                 }
3915
3916                 if (!skb_shinfo(skb)->nr_frags) {
3917                         pci_unmap_single(pdev, buffer_info->dma,
3918                                          adapter->rx_ps_hdr_size +
3919                                            NET_IP_ALIGN,
3920                                          PCI_DMA_FROMDEVICE);
3921                         skb_put(skb, hlen);
3922                 }
3923
3924                 if (length) {
3925                         pci_unmap_page(pdev, buffer_info->page_dma,
3926                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3927                         buffer_info->page_dma = 0;
3928
3929                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3930                                                 buffer_info->page,
3931                                                 buffer_info->page_offset,
3932                                                 length);
3933
3934                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3935                             (page_count(buffer_info->page) != 1))
3936                                 buffer_info->page = NULL;
3937                         else
3938                                 get_page(buffer_info->page);
3939
3940                         skb->len += length;
3941                         skb->data_len += length;
3942
3943                         skb->truesize += length;
3944                 }
3945 send_up:
3946                 i++;
3947                 if (i == rx_ring->count)
3948                         i = 0;
3949                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3950                 prefetch(next_rxd);
3951                 next_buffer = &rx_ring->buffer_info[i];
3952
3953                 if (!(staterr & E1000_RXD_STAT_EOP)) {
3954                         buffer_info->skb = next_buffer->skb;
3955                         buffer_info->dma = next_buffer->dma;
3956                         next_buffer->skb = skb;
3957                         next_buffer->dma = 0;
3958                         goto next_desc;
3959                 }
3960
3961                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3962                         dev_kfree_skb_irq(skb);
3963                         goto next_desc;
3964                 }
3965
3966                 total_bytes += skb->len;
3967                 total_packets++;
3968
3969                 igb_rx_checksum_adv(adapter, staterr, skb);
3970
3971                 skb->protocol = eth_type_trans(skb, netdev);
3972
3973                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3974
3975 next_desc:
3976                 rx_desc->wb.upper.status_error = 0;
3977
3978                 /* return some buffers to hardware, one at a time is too slow */
3979                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3980                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3981                         cleaned_count = 0;
3982                 }
3983
3984                 /* use prefetched values */
3985                 rx_desc = next_rxd;
3986                 buffer_info = next_buffer;
3987
3988                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3989         }
3990
3991         rx_ring->next_to_clean = i;
3992         cleaned_count = IGB_DESC_UNUSED(rx_ring);
3993
3994 #ifdef CONFIG_IGB_LRO
3995         if (rx_ring->lro_used) {
3996                 lro_flush_all(&rx_ring->lro_mgr);
3997                 rx_ring->lro_used = 0;
3998         }
3999 #endif
4000
4001         if (cleaned_count)
4002                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4003
4004         rx_ring->total_packets += total_packets;
4005         rx_ring->total_bytes += total_bytes;
4006         rx_ring->rx_stats.packets += total_packets;
4007         rx_ring->rx_stats.bytes += total_bytes;
4008         adapter->net_stats.rx_bytes += total_bytes;
4009         adapter->net_stats.rx_packets += total_packets;
4010         return cleaned;
4011 }
4012
4013
4014 /**
4015  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4016  * @adapter: address of board private structure
4017  **/
4018 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4019                                      int cleaned_count)
4020 {
4021         struct igb_adapter *adapter = rx_ring->adapter;
4022         struct net_device *netdev = adapter->netdev;
4023         struct pci_dev *pdev = adapter->pdev;
4024         union e1000_adv_rx_desc *rx_desc;
4025         struct igb_buffer *buffer_info;
4026         struct sk_buff *skb;
4027         unsigned int i;
4028
4029         i = rx_ring->next_to_use;
4030         buffer_info = &rx_ring->buffer_info[i];
4031
4032         while (cleaned_count--) {
4033                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4034
4035                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4036                         if (!buffer_info->page) {
4037                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4038                                 if (!buffer_info->page) {
4039                                         adapter->alloc_rx_buff_failed++;
4040                                         goto no_buffers;
4041                                 }
4042                                 buffer_info->page_offset = 0;
4043                         } else {
4044                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4045                         }
4046                         buffer_info->page_dma =
4047                                 pci_map_page(pdev,
4048                                              buffer_info->page,
4049                                              buffer_info->page_offset,
4050                                              PAGE_SIZE / 2,
4051                                              PCI_DMA_FROMDEVICE);
4052                 }
4053
4054                 if (!buffer_info->skb) {
4055                         int bufsz;
4056
4057                         if (adapter->rx_ps_hdr_size)
4058                                 bufsz = adapter->rx_ps_hdr_size;
4059                         else
4060                                 bufsz = adapter->rx_buffer_len;
4061                         bufsz += NET_IP_ALIGN;
4062                         skb = netdev_alloc_skb(netdev, bufsz);
4063
4064                         if (!skb) {
4065                                 adapter->alloc_rx_buff_failed++;
4066                                 goto no_buffers;
4067                         }
4068
4069                         /* Make buffer alignment 2 beyond a 16 byte boundary
4070                          * this will result in a 16 byte aligned IP header after
4071                          * the 14 byte MAC header is removed
4072                          */
4073                         skb_reserve(skb, NET_IP_ALIGN);
4074
4075                         buffer_info->skb = skb;
4076                         buffer_info->dma = pci_map_single(pdev, skb->data,
4077                                                           bufsz,
4078                                                           PCI_DMA_FROMDEVICE);
4079
4080                 }
4081                 /* Refresh the desc even if buffer_addrs didn't change because
4082                  * each write-back erases this info. */
4083                 if (adapter->rx_ps_hdr_size) {
4084                         rx_desc->read.pkt_addr =
4085                              cpu_to_le64(buffer_info->page_dma);
4086                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4087                 } else {
4088                         rx_desc->read.pkt_addr =
4089                              cpu_to_le64(buffer_info->dma);
4090                         rx_desc->read.hdr_addr = 0;
4091                 }
4092
4093                 i++;
4094                 if (i == rx_ring->count)
4095                         i = 0;
4096                 buffer_info = &rx_ring->buffer_info[i];
4097         }
4098
4099 no_buffers:
4100         if (rx_ring->next_to_use != i) {
4101                 rx_ring->next_to_use = i;
4102                 if (i == 0)
4103                         i = (rx_ring->count - 1);
4104                 else
4105                         i--;
4106
4107                 /* Force memory writes to complete before letting h/w
4108                  * know there are new descriptors to fetch.  (Only
4109                  * applicable for weak-ordered memory model archs,
4110                  * such as IA-64). */
4111                 wmb();
4112                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4113         }
4114 }
4115
4116 /**
4117  * igb_mii_ioctl -
4118  * @netdev:
4119  * @ifreq:
4120  * @cmd:
4121  **/
4122 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4123 {
4124         struct igb_adapter *adapter = netdev_priv(netdev);
4125         struct mii_ioctl_data *data = if_mii(ifr);
4126
4127         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4128                 return -EOPNOTSUPP;
4129
4130         switch (cmd) {
4131         case SIOCGMIIPHY:
4132                 data->phy_id = adapter->hw.phy.addr;
4133                 break;
4134         case SIOCGMIIREG:
4135                 if (!capable(CAP_NET_ADMIN))
4136                         return -EPERM;
4137                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4138                                      &data->val_out))
4139                         return -EIO;
4140                 break;
4141         case SIOCSMIIREG:
4142         default:
4143                 return -EOPNOTSUPP;
4144         }
4145         return 0;
4146 }
4147
4148 /**
4149  * igb_ioctl -
4150  * @netdev:
4151  * @ifreq:
4152  * @cmd:
4153  **/
4154 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4155 {
4156         switch (cmd) {
4157         case SIOCGMIIPHY:
4158         case SIOCGMIIREG:
4159         case SIOCSMIIREG:
4160                 return igb_mii_ioctl(netdev, ifr, cmd);
4161         default:
4162                 return -EOPNOTSUPP;
4163         }
4164 }
4165
4166 static void igb_vlan_rx_register(struct net_device *netdev,
4167                                  struct vlan_group *grp)
4168 {
4169         struct igb_adapter *adapter = netdev_priv(netdev);
4170         struct e1000_hw *hw = &adapter->hw;
4171         u32 ctrl, rctl;
4172
4173         igb_irq_disable(adapter);
4174         adapter->vlgrp = grp;
4175
4176         if (grp) {
4177                 /* enable VLAN tag insert/strip */
4178                 ctrl = rd32(E1000_CTRL);
4179                 ctrl |= E1000_CTRL_VME;
4180                 wr32(E1000_CTRL, ctrl);
4181
4182                 /* enable VLAN receive filtering */
4183                 rctl = rd32(E1000_RCTL);
4184                 rctl &= ~E1000_RCTL_CFIEN;
4185                 wr32(E1000_RCTL, rctl);
4186                 igb_update_mng_vlan(adapter);
4187                 wr32(E1000_RLPML,
4188                                 adapter->max_frame_size + VLAN_TAG_SIZE);
4189         } else {
4190                 /* disable VLAN tag insert/strip */
4191                 ctrl = rd32(E1000_CTRL);
4192                 ctrl &= ~E1000_CTRL_VME;
4193                 wr32(E1000_CTRL, ctrl);
4194
4195                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4196                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4197                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4198                 }
4199                 wr32(E1000_RLPML,
4200                                 adapter->max_frame_size);
4201         }
4202
4203         if (!test_bit(__IGB_DOWN, &adapter->state))
4204                 igb_irq_enable(adapter);
4205 }
4206
4207 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4208 {
4209         struct igb_adapter *adapter = netdev_priv(netdev);
4210         struct e1000_hw *hw = &adapter->hw;
4211         u32 vfta, index;
4212
4213         if ((adapter->hw.mng_cookie.status &
4214              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4215             (vid == adapter->mng_vlan_id))
4216                 return;
4217         /* add VID to filter table */
4218         index = (vid >> 5) & 0x7F;
4219         vfta = array_rd32(E1000_VFTA, index);
4220         vfta |= (1 << (vid & 0x1F));
4221         igb_write_vfta(&adapter->hw, index, vfta);
4222 }
4223
4224 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4225 {
4226         struct igb_adapter *adapter = netdev_priv(netdev);
4227         struct e1000_hw *hw = &adapter->hw;
4228         u32 vfta, index;
4229
4230         igb_irq_disable(adapter);
4231         vlan_group_set_device(adapter->vlgrp, vid, NULL);
4232
4233         if (!test_bit(__IGB_DOWN, &adapter->state))
4234                 igb_irq_enable(adapter);
4235
4236         if ((adapter->hw.mng_cookie.status &
4237              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4238             (vid == adapter->mng_vlan_id)) {
4239                 /* release control to f/w */
4240                 igb_release_hw_control(adapter);
4241                 return;
4242         }
4243
4244         /* remove VID from filter table */
4245         index = (vid >> 5) & 0x7F;
4246         vfta = array_rd32(E1000_VFTA, index);
4247         vfta &= ~(1 << (vid & 0x1F));
4248         igb_write_vfta(&adapter->hw, index, vfta);
4249 }
4250
4251 static void igb_restore_vlan(struct igb_adapter *adapter)
4252 {
4253         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4254
4255         if (adapter->vlgrp) {
4256                 u16 vid;
4257                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4258                         if (!vlan_group_get_device(adapter->vlgrp, vid))
4259                                 continue;
4260                         igb_vlan_rx_add_vid(adapter->netdev, vid);
4261                 }
4262         }
4263 }
4264
4265 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4266 {
4267         struct e1000_mac_info *mac = &adapter->hw.mac;
4268
4269         mac->autoneg = 0;
4270
4271         /* Fiber NICs only allow 1000 gbps Full duplex */
4272         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4273                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4274                 dev_err(&adapter->pdev->dev,
4275                         "Unsupported Speed/Duplex configuration\n");
4276                 return -EINVAL;
4277         }
4278
4279         switch (spddplx) {
4280         case SPEED_10 + DUPLEX_HALF:
4281                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4282                 break;
4283         case SPEED_10 + DUPLEX_FULL:
4284                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4285                 break;
4286         case SPEED_100 + DUPLEX_HALF:
4287                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4288                 break;
4289         case SPEED_100 + DUPLEX_FULL:
4290                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4291                 break;
4292         case SPEED_1000 + DUPLEX_FULL:
4293                 mac->autoneg = 1;
4294                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4295                 break;
4296         case SPEED_1000 + DUPLEX_HALF: /* not supported */
4297         default:
4298                 dev_err(&adapter->pdev->dev,
4299                         "Unsupported Speed/Duplex configuration\n");
4300                 return -EINVAL;
4301         }
4302         return 0;
4303 }
4304
4305
4306 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4307 {
4308         struct net_device *netdev = pci_get_drvdata(pdev);
4309         struct igb_adapter *adapter = netdev_priv(netdev);
4310         struct e1000_hw *hw = &adapter->hw;
4311         u32 ctrl, rctl, status;
4312         u32 wufc = adapter->wol;
4313 #ifdef CONFIG_PM
4314         int retval = 0;
4315 #endif
4316
4317         netif_device_detach(netdev);
4318
4319         if (netif_running(netdev))
4320                 igb_close(netdev);
4321
4322         igb_reset_interrupt_capability(adapter);
4323
4324         igb_free_queues(adapter);
4325
4326 #ifdef CONFIG_PM
4327         retval = pci_save_state(pdev);
4328         if (retval)
4329                 return retval;
4330 #endif
4331
4332         status = rd32(E1000_STATUS);
4333         if (status & E1000_STATUS_LU)
4334                 wufc &= ~E1000_WUFC_LNKC;
4335
4336         if (wufc) {
4337                 igb_setup_rctl(adapter);
4338                 igb_set_multi(netdev);
4339
4340                 /* turn on all-multi mode if wake on multicast is enabled */
4341                 if (wufc & E1000_WUFC_MC) {
4342                         rctl = rd32(E1000_RCTL);
4343                         rctl |= E1000_RCTL_MPE;
4344                         wr32(E1000_RCTL, rctl);
4345                 }
4346
4347                 ctrl = rd32(E1000_CTRL);
4348                 /* advertise wake from D3Cold */
4349                 #define E1000_CTRL_ADVD3WUC 0x00100000
4350                 /* phy power management enable */
4351                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4352                 ctrl |= E1000_CTRL_ADVD3WUC;
4353                 wr32(E1000_CTRL, ctrl);
4354
4355                 /* Allow time for pending master requests to run */
4356                 igb_disable_pcie_master(&adapter->hw);
4357
4358                 wr32(E1000_WUC, E1000_WUC_PME_EN);
4359                 wr32(E1000_WUFC, wufc);
4360         } else {
4361                 wr32(E1000_WUC, 0);
4362                 wr32(E1000_WUFC, 0);
4363         }
4364
4365         /* make sure adapter isn't asleep if manageability/wol is enabled */
4366         if (wufc || adapter->en_mng_pt) {
4367                 pci_enable_wake(pdev, PCI_D3hot, 1);
4368                 pci_enable_wake(pdev, PCI_D3cold, 1);
4369         } else {
4370                 igb_shutdown_fiber_serdes_link_82575(hw);
4371                 pci_enable_wake(pdev, PCI_D3hot, 0);
4372                 pci_enable_wake(pdev, PCI_D3cold, 0);
4373         }
4374
4375         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
4376          * would have already happened in close and is redundant. */
4377         igb_release_hw_control(adapter);
4378
4379         pci_disable_device(pdev);
4380
4381         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4382
4383         return 0;
4384 }
4385
4386 #ifdef CONFIG_PM
4387 static int igb_resume(struct pci_dev *pdev)
4388 {
4389         struct net_device *netdev = pci_get_drvdata(pdev);
4390         struct igb_adapter *adapter = netdev_priv(netdev);
4391         struct e1000_hw *hw = &adapter->hw;
4392         u32 err;
4393
4394         pci_set_power_state(pdev, PCI_D0);
4395         pci_restore_state(pdev);
4396
4397         if (adapter->need_ioport)
4398                 err = pci_enable_device(pdev);
4399         else
4400                 err = pci_enable_device_mem(pdev);
4401         if (err) {
4402                 dev_err(&pdev->dev,
4403                         "igb: Cannot enable PCI device from suspend\n");
4404                 return err;
4405         }
4406         pci_set_master(pdev);
4407
4408         pci_enable_wake(pdev, PCI_D3hot, 0);
4409         pci_enable_wake(pdev, PCI_D3cold, 0);
4410
4411         igb_set_interrupt_capability(adapter);
4412
4413         if (igb_alloc_queues(adapter)) {
4414                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4415                 return -ENOMEM;
4416         }
4417
4418         /* e1000_power_up_phy(adapter); */
4419
4420         igb_reset(adapter);
4421         wr32(E1000_WUS, ~0);
4422
4423         if (netif_running(netdev)) {
4424                 err = igb_open(netdev);
4425                 if (err)
4426                         return err;
4427         }
4428
4429         netif_device_attach(netdev);
4430
4431         /* let the f/w know that the h/w is now under the control of the
4432          * driver. */
4433         igb_get_hw_control(adapter);
4434
4435         return 0;
4436 }
4437 #endif
4438
4439 static void igb_shutdown(struct pci_dev *pdev)
4440 {
4441         igb_suspend(pdev, PMSG_SUSPEND);
4442 }
4443
4444 #ifdef CONFIG_NET_POLL_CONTROLLER
4445 /*
4446  * Polling 'interrupt' - used by things like netconsole to send skbs
4447  * without having to re-enable interrupts. It's not called while
4448  * the interrupt routine is executing.
4449  */
4450 static void igb_netpoll(struct net_device *netdev)
4451 {
4452         struct igb_adapter *adapter = netdev_priv(netdev);
4453         int i;
4454         int work_done = 0;
4455
4456         igb_irq_disable(adapter);
4457         adapter->flags |= IGB_FLAG_IN_NETPOLL;
4458
4459         for (i = 0; i < adapter->num_tx_queues; i++)
4460                 igb_clean_tx_irq(&adapter->tx_ring[i]);
4461
4462         for (i = 0; i < adapter->num_rx_queues; i++)
4463                 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4464                                      &work_done,
4465                                      adapter->rx_ring[i].napi.weight);
4466
4467         adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
4468         igb_irq_enable(adapter);
4469 }
4470 #endif /* CONFIG_NET_POLL_CONTROLLER */
4471
4472 /**
4473  * igb_io_error_detected - called when PCI error is detected
4474  * @pdev: Pointer to PCI device
4475  * @state: The current pci connection state
4476  *
4477  * This function is called after a PCI bus error affecting
4478  * this device has been detected.
4479  */
4480 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4481                                               pci_channel_state_t state)
4482 {
4483         struct net_device *netdev = pci_get_drvdata(pdev);
4484         struct igb_adapter *adapter = netdev_priv(netdev);
4485
4486         netif_device_detach(netdev);
4487
4488         if (netif_running(netdev))
4489                 igb_down(adapter);
4490         pci_disable_device(pdev);
4491
4492         /* Request a slot slot reset. */
4493         return PCI_ERS_RESULT_NEED_RESET;
4494 }
4495
4496 /**
4497  * igb_io_slot_reset - called after the pci bus has been reset.
4498  * @pdev: Pointer to PCI device
4499  *
4500  * Restart the card from scratch, as if from a cold-boot. Implementation
4501  * resembles the first-half of the igb_resume routine.
4502  */
4503 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4504 {
4505         struct net_device *netdev = pci_get_drvdata(pdev);
4506         struct igb_adapter *adapter = netdev_priv(netdev);
4507         struct e1000_hw *hw = &adapter->hw;
4508         pci_ers_result_t result;
4509         int err;
4510
4511         if (adapter->need_ioport)
4512                 err = pci_enable_device(pdev);
4513         else
4514                 err = pci_enable_device_mem(pdev);
4515
4516         if (err) {
4517                 dev_err(&pdev->dev,
4518                         "Cannot re-enable PCI device after reset.\n");
4519                 result = PCI_ERS_RESULT_DISCONNECT;
4520         } else {
4521                 pci_set_master(pdev);
4522                 pci_restore_state(pdev);
4523
4524                 pci_enable_wake(pdev, PCI_D3hot, 0);
4525                 pci_enable_wake(pdev, PCI_D3cold, 0);
4526
4527                 igb_reset(adapter);
4528                 wr32(E1000_WUS, ~0);
4529                 result = PCI_ERS_RESULT_RECOVERED;
4530         }
4531
4532         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4533         if (err) {
4534                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4535                         "failed 0x%0x\n", err);
4536                 /* non-fatal, continue */
4537         }
4538
4539         return result;
4540 }
4541
4542 /**
4543  * igb_io_resume - called when traffic can start flowing again.
4544  * @pdev: Pointer to PCI device
4545  *
4546  * This callback is called when the error recovery driver tells us that
4547  * its OK to resume normal operation. Implementation resembles the
4548  * second-half of the igb_resume routine.
4549  */
4550 static void igb_io_resume(struct pci_dev *pdev)
4551 {
4552         struct net_device *netdev = pci_get_drvdata(pdev);
4553         struct igb_adapter *adapter = netdev_priv(netdev);
4554
4555         if (netif_running(netdev)) {
4556                 if (igb_up(adapter)) {
4557                         dev_err(&pdev->dev, "igb_up failed after reset\n");
4558                         return;
4559                 }
4560         }
4561
4562         netif_device_attach(netdev);
4563
4564         /* let the f/w know that the h/w is now under the control of the
4565          * driver. */
4566         igb_get_hw_control(adapter);
4567 }
4568
4569 /* igb_main.c */