Merge branch 'merge'
[linux-2.6] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * Copyright 2007 Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Kevin E. Martin <martin@valinux.com>
29  *    Gareth Hughes <gareth@valinux.com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
36 #include "r300_reg.h"
37
38 #include "radeon_microcode.h"
39
40 #define RADEON_FIFO_DEBUG       0
41
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
44
45 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
46 {
47         u32 ret;
48         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
49         ret = RADEON_READ(R520_MC_IND_DATA);
50         RADEON_WRITE(R520_MC_IND_INDEX, 0);
51         return ret;
52 }
53
54 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
55 {
56         u32 ret;
57         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
58         ret = RADEON_READ(RS480_NB_MC_DATA);
59         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
60         return ret;
61 }
62
63 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
64 {
65         u32 ret;
66         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
67         ret = RADEON_READ(RS690_MC_DATA);
68         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
69         return ret;
70 }
71
72 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 {
74         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
75             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
76                 return RS690_READ_MCIND(dev_priv, addr);
77         else
78                 return RS480_READ_MCIND(dev_priv, addr);
79 }
80
81 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 {
83
84         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
85                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
86         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
87                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
88                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
89         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
90                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
91         else
92                 return RADEON_READ(RADEON_MC_FB_LOCATION);
93 }
94
95 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
96 {
97         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
98                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
99         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
100                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
101                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
102         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
103                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
104         else
105                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
106 }
107
108 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
109 {
110         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
111                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
112         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
113                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
114                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
115         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
116                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
117         else
118                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
119 }
120
121 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
122 {
123         u32 agp_base_hi = upper_32_bits(agp_base);
124         u32 agp_base_lo = agp_base & 0xffffffff;
125
126         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
127                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
128                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
129         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
130                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
131                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
132                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
133         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
134                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
135                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
136         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
137                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
138                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
139                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
140         } else {
141                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
142                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
143                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
144         }
145 }
146
147 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
148 {
149         drm_radeon_private_t *dev_priv = dev->dev_private;
150
151         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
152         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
153 }
154
155 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
156 {
157         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
158         return RADEON_READ(RADEON_PCIE_DATA);
159 }
160
161 #if RADEON_FIFO_DEBUG
162 static void radeon_status(drm_radeon_private_t * dev_priv)
163 {
164         printk("%s:\n", __func__);
165         printk("RBBM_STATUS = 0x%08x\n",
166                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
167         printk("CP_RB_RTPR = 0x%08x\n",
168                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
169         printk("CP_RB_WTPR = 0x%08x\n",
170                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
171         printk("AIC_CNTL = 0x%08x\n",
172                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
173         printk("AIC_STAT = 0x%08x\n",
174                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
175         printk("AIC_PT_BASE = 0x%08x\n",
176                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
177         printk("TLB_ADDR = 0x%08x\n",
178                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
179         printk("TLB_DATA = 0x%08x\n",
180                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
181 }
182 #endif
183
184 /* ================================================================
185  * Engine, FIFO control
186  */
187
188 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
189 {
190         u32 tmp;
191         int i;
192
193         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
194
195         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
196                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
197                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
198                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
199
200                 for (i = 0; i < dev_priv->usec_timeout; i++) {
201                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
202                               & RADEON_RB3D_DC_BUSY)) {
203                                 return 0;
204                         }
205                         DRM_UDELAY(1);
206                 }
207         } else {
208                 /* don't flush or purge cache here or lockup */
209                 return 0;
210         }
211
212 #if RADEON_FIFO_DEBUG
213         DRM_ERROR("failed!\n");
214         radeon_status(dev_priv);
215 #endif
216         return -EBUSY;
217 }
218
219 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
220 {
221         int i;
222
223         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
224
225         for (i = 0; i < dev_priv->usec_timeout; i++) {
226                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
227                              & RADEON_RBBM_FIFOCNT_MASK);
228                 if (slots >= entries)
229                         return 0;
230                 DRM_UDELAY(1);
231         }
232         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
233                  RADEON_READ(RADEON_RBBM_STATUS),
234                  RADEON_READ(R300_VAP_CNTL_STATUS));
235
236 #if RADEON_FIFO_DEBUG
237         DRM_ERROR("failed!\n");
238         radeon_status(dev_priv);
239 #endif
240         return -EBUSY;
241 }
242
243 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
244 {
245         int i, ret;
246
247         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
248
249         ret = radeon_do_wait_for_fifo(dev_priv, 64);
250         if (ret)
251                 return ret;
252
253         for (i = 0; i < dev_priv->usec_timeout; i++) {
254                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
255                       & RADEON_RBBM_ACTIVE)) {
256                         radeon_do_pixcache_flush(dev_priv);
257                         return 0;
258                 }
259                 DRM_UDELAY(1);
260         }
261         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
262                  RADEON_READ(RADEON_RBBM_STATUS),
263                  RADEON_READ(R300_VAP_CNTL_STATUS));
264
265 #if RADEON_FIFO_DEBUG
266         DRM_ERROR("failed!\n");
267         radeon_status(dev_priv);
268 #endif
269         return -EBUSY;
270 }
271
272 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
273 {
274         uint32_t gb_tile_config, gb_pipe_sel = 0;
275
276         /* RS4xx/RS6xx/R4xx/R5xx */
277         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
278                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
279                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
280         } else {
281                 /* R3xx */
282                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
283                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
284                         dev_priv->num_gb_pipes = 2;
285                 } else {
286                         /* R3Vxx */
287                         dev_priv->num_gb_pipes = 1;
288                 }
289         }
290         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
291
292         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
293
294         switch (dev_priv->num_gb_pipes) {
295         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
296         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
297         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
298         default:
299         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
300         }
301
302         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
303                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
304                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
305         }
306         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
307         radeon_do_wait_for_idle(dev_priv);
308         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
309         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
310                                                R300_DC_AUTOFLUSH_ENABLE |
311                                                R300_DC_DC_DISABLE_IGNORE_PE));
312
313
314 }
315
316 /* ================================================================
317  * CP control, initialization
318  */
319
320 /* Load the microcode for the CP */
321 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
322 {
323         int i;
324         DRM_DEBUG("\n");
325
326         radeon_do_wait_for_idle(dev_priv);
327
328         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
329         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
330             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
331             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
332             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
333             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
334                 DRM_INFO("Loading R100 Microcode\n");
335                 for (i = 0; i < 256; i++) {
336                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
337                                      R100_cp_microcode[i][1]);
338                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
339                                      R100_cp_microcode[i][0]);
340                 }
341         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
342                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
343                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
344                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
345                 DRM_INFO("Loading R200 Microcode\n");
346                 for (i = 0; i < 256; i++) {
347                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
348                                      R200_cp_microcode[i][1]);
349                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
350                                      R200_cp_microcode[i][0]);
351                 }
352         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
353                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
354                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
355                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
356                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
357                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
358                 DRM_INFO("Loading R300 Microcode\n");
359                 for (i = 0; i < 256; i++) {
360                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
361                                      R300_cp_microcode[i][1]);
362                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
363                                      R300_cp_microcode[i][0]);
364                 }
365         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
366                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
367                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
368                 DRM_INFO("Loading R400 Microcode\n");
369                 for (i = 0; i < 256; i++) {
370                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
371                                      R420_cp_microcode[i][1]);
372                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
373                                      R420_cp_microcode[i][0]);
374                 }
375         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
376                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
377                 DRM_INFO("Loading RS690/RS740 Microcode\n");
378                 for (i = 0; i < 256; i++) {
379                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
380                                      RS690_cp_microcode[i][1]);
381                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
382                                      RS690_cp_microcode[i][0]);
383                 }
384         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
385                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
386                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
387                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
388                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
389                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
390                 DRM_INFO("Loading R500 Microcode\n");
391                 for (i = 0; i < 256; i++) {
392                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
393                                      R520_cp_microcode[i][1]);
394                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
395                                      R520_cp_microcode[i][0]);
396                 }
397         }
398 }
399
400 /* Flush any pending commands to the CP.  This should only be used just
401  * prior to a wait for idle, as it informs the engine that the command
402  * stream is ending.
403  */
404 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
405 {
406         DRM_DEBUG("\n");
407 #if 0
408         u32 tmp;
409
410         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
411         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
412 #endif
413 }
414
415 /* Wait for the CP to go idle.
416  */
417 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
418 {
419         RING_LOCALS;
420         DRM_DEBUG("\n");
421
422         BEGIN_RING(6);
423
424         RADEON_PURGE_CACHE();
425         RADEON_PURGE_ZCACHE();
426         RADEON_WAIT_UNTIL_IDLE();
427
428         ADVANCE_RING();
429         COMMIT_RING();
430
431         return radeon_do_wait_for_idle(dev_priv);
432 }
433
434 /* Start the Command Processor.
435  */
436 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
437 {
438         RING_LOCALS;
439         DRM_DEBUG("\n");
440
441         radeon_do_wait_for_idle(dev_priv);
442
443         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
444
445         dev_priv->cp_running = 1;
446
447         BEGIN_RING(8);
448         /* isync can only be written through cp on r5xx write it here */
449         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
450         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
451                  RADEON_ISYNC_ANY3D_IDLE2D |
452                  RADEON_ISYNC_WAIT_IDLEGUI |
453                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
454         RADEON_PURGE_CACHE();
455         RADEON_PURGE_ZCACHE();
456         RADEON_WAIT_UNTIL_IDLE();
457         ADVANCE_RING();
458         COMMIT_RING();
459
460         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
461 }
462
463 /* Reset the Command Processor.  This will not flush any pending
464  * commands, so you must wait for the CP command stream to complete
465  * before calling this routine.
466  */
467 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
468 {
469         u32 cur_read_ptr;
470         DRM_DEBUG("\n");
471
472         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
473         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
474         SET_RING_HEAD(dev_priv, cur_read_ptr);
475         dev_priv->ring.tail = cur_read_ptr;
476 }
477
478 /* Stop the Command Processor.  This will not flush any pending
479  * commands, so you must flush the command stream and wait for the CP
480  * to go idle before calling this routine.
481  */
482 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
483 {
484         DRM_DEBUG("\n");
485
486         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
487
488         dev_priv->cp_running = 0;
489 }
490
491 /* Reset the engine.  This will stop the CP if it is running.
492  */
493 static int radeon_do_engine_reset(struct drm_device * dev)
494 {
495         drm_radeon_private_t *dev_priv = dev->dev_private;
496         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
497         DRM_DEBUG("\n");
498
499         radeon_do_pixcache_flush(dev_priv);
500
501         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
502                 /* may need something similar for newer chips */
503                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
504                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
505
506                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
507                                                     RADEON_FORCEON_MCLKA |
508                                                     RADEON_FORCEON_MCLKB |
509                                                     RADEON_FORCEON_YCLKA |
510                                                     RADEON_FORCEON_YCLKB |
511                                                     RADEON_FORCEON_MC |
512                                                     RADEON_FORCEON_AIC));
513         }
514
515         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
516
517         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
518                                               RADEON_SOFT_RESET_CP |
519                                               RADEON_SOFT_RESET_HI |
520                                               RADEON_SOFT_RESET_SE |
521                                               RADEON_SOFT_RESET_RE |
522                                               RADEON_SOFT_RESET_PP |
523                                               RADEON_SOFT_RESET_E2 |
524                                               RADEON_SOFT_RESET_RB));
525         RADEON_READ(RADEON_RBBM_SOFT_RESET);
526         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
527                                               ~(RADEON_SOFT_RESET_CP |
528                                                 RADEON_SOFT_RESET_HI |
529                                                 RADEON_SOFT_RESET_SE |
530                                                 RADEON_SOFT_RESET_RE |
531                                                 RADEON_SOFT_RESET_PP |
532                                                 RADEON_SOFT_RESET_E2 |
533                                                 RADEON_SOFT_RESET_RB)));
534         RADEON_READ(RADEON_RBBM_SOFT_RESET);
535
536         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
537                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
538                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
539                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
540         }
541
542         /* setup the raster pipes */
543         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
544             radeon_init_pipes(dev_priv);
545
546         /* Reset the CP ring */
547         radeon_do_cp_reset(dev_priv);
548
549         /* The CP is no longer running after an engine reset */
550         dev_priv->cp_running = 0;
551
552         /* Reset any pending vertex, indirect buffers */
553         radeon_freelist_reset(dev);
554
555         return 0;
556 }
557
558 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
559                                        drm_radeon_private_t * dev_priv)
560 {
561         u32 ring_start, cur_read_ptr;
562         u32 tmp;
563
564         /* Initialize the memory controller. With new memory map, the fb location
565          * is not changed, it should have been properly initialized already. Part
566          * of the problem is that the code below is bogus, assuming the GART is
567          * always appended to the fb which is not necessarily the case
568          */
569         if (!dev_priv->new_memmap)
570                 radeon_write_fb_location(dev_priv,
571                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
572                              | (dev_priv->fb_location >> 16));
573
574 #if __OS_HAS_AGP
575         if (dev_priv->flags & RADEON_IS_AGP) {
576                 radeon_write_agp_base(dev_priv, dev->agp->base);
577
578                 radeon_write_agp_location(dev_priv,
579                              (((dev_priv->gart_vm_start - 1 +
580                                 dev_priv->gart_size) & 0xffff0000) |
581                               (dev_priv->gart_vm_start >> 16)));
582
583                 ring_start = (dev_priv->cp_ring->offset
584                               - dev->agp->base
585                               + dev_priv->gart_vm_start);
586         } else
587 #endif
588                 ring_start = (dev_priv->cp_ring->offset
589                               - (unsigned long)dev->sg->virtual
590                               + dev_priv->gart_vm_start);
591
592         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
593
594         /* Set the write pointer delay */
595         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
596
597         /* Initialize the ring buffer's read and write pointers */
598         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
599         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
600         SET_RING_HEAD(dev_priv, cur_read_ptr);
601         dev_priv->ring.tail = cur_read_ptr;
602
603 #if __OS_HAS_AGP
604         if (dev_priv->flags & RADEON_IS_AGP) {
605                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
606                              dev_priv->ring_rptr->offset
607                              - dev->agp->base + dev_priv->gart_vm_start);
608         } else
609 #endif
610         {
611                 struct drm_sg_mem *entry = dev->sg;
612                 unsigned long tmp_ofs, page_ofs;
613
614                 tmp_ofs = dev_priv->ring_rptr->offset -
615                                 (unsigned long)dev->sg->virtual;
616                 page_ofs = tmp_ofs >> PAGE_SHIFT;
617
618                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
619                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
620                           (unsigned long)entry->busaddr[page_ofs],
621                           entry->handle + tmp_ofs);
622         }
623
624         /* Set ring buffer size */
625 #ifdef __BIG_ENDIAN
626         RADEON_WRITE(RADEON_CP_RB_CNTL,
627                      RADEON_BUF_SWAP_32BIT |
628                      (dev_priv->ring.fetch_size_l2ow << 18) |
629                      (dev_priv->ring.rptr_update_l2qw << 8) |
630                      dev_priv->ring.size_l2qw);
631 #else
632         RADEON_WRITE(RADEON_CP_RB_CNTL,
633                      (dev_priv->ring.fetch_size_l2ow << 18) |
634                      (dev_priv->ring.rptr_update_l2qw << 8) |
635                      dev_priv->ring.size_l2qw);
636 #endif
637
638
639         /* Initialize the scratch register pointer.  This will cause
640          * the scratch register values to be written out to memory
641          * whenever they are updated.
642          *
643          * We simply put this behind the ring read pointer, this works
644          * with PCI GART as well as (whatever kind of) AGP GART
645          */
646         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
647                      + RADEON_SCRATCH_REG_OFFSET);
648
649         dev_priv->scratch = ((__volatile__ u32 *)
650                              dev_priv->ring_rptr->handle +
651                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
652
653         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
654
655         /* Turn on bus mastering */
656         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
657             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
658                 /* rs600/rs690/rs740 */
659                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
660                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
661         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
662                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
663                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
664                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
665                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
666                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
667                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
668         } /* PCIE cards appears to not need this */
669
670         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
671         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
672
673         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
674         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
675                      dev_priv->sarea_priv->last_dispatch);
676
677         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
678         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
679
680         radeon_do_wait_for_idle(dev_priv);
681
682         /* Sync everything up */
683         RADEON_WRITE(RADEON_ISYNC_CNTL,
684                      (RADEON_ISYNC_ANY2D_IDLE3D |
685                       RADEON_ISYNC_ANY3D_IDLE2D |
686                       RADEON_ISYNC_WAIT_IDLEGUI |
687                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
688
689 }
690
691 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
692 {
693         u32 tmp;
694
695         /* Start with assuming that writeback doesn't work */
696         dev_priv->writeback_works = 0;
697
698         /* Writeback doesn't seem to work everywhere, test it here and possibly
699          * enable it if it appears to work
700          */
701         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
702         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
703
704         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
705                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
706                     0xdeadbeef)
707                         break;
708                 DRM_UDELAY(1);
709         }
710
711         if (tmp < dev_priv->usec_timeout) {
712                 dev_priv->writeback_works = 1;
713                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
714         } else {
715                 dev_priv->writeback_works = 0;
716                 DRM_INFO("writeback test failed\n");
717         }
718         if (radeon_no_wb == 1) {
719                 dev_priv->writeback_works = 0;
720                 DRM_INFO("writeback forced off\n");
721         }
722
723         if (!dev_priv->writeback_works) {
724                 /* Disable writeback to avoid unnecessary bus master transfer */
725                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
726                              RADEON_RB_NO_UPDATE);
727                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
728         }
729 }
730
731 /* Enable or disable IGP GART on the chip */
732 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
733 {
734         u32 temp;
735
736         if (on) {
737                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
738                           dev_priv->gart_vm_start,
739                           (long)dev_priv->gart_info.bus_addr,
740                           dev_priv->gart_size);
741
742                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
743                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
744                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
745                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
746                                                              RS690_BLOCK_GFX_D3_EN));
747                 else
748                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
749
750                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
751                                                                RS480_VA_SIZE_32MB));
752
753                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
754                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
755                                                         RS480_TLB_ENABLE |
756                                                         RS480_GTW_LAC_EN |
757                                                         RS480_1LEVEL_GART));
758
759                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
760                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
761                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
762
763                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
764                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
765                                                       RS480_REQ_TYPE_SNOOP_DIS));
766
767                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
768
769                 dev_priv->gart_size = 32*1024*1024;
770                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
771                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
772
773                 radeon_write_agp_location(dev_priv, temp);
774
775                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
776                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
777                                                                RS480_VA_SIZE_32MB));
778
779                 do {
780                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
781                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
782                                 break;
783                         DRM_UDELAY(1);
784                 } while (1);
785
786                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
787                                 RS480_GART_CACHE_INVALIDATE);
788
789                 do {
790                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
791                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
792                                 break;
793                         DRM_UDELAY(1);
794                 } while (1);
795
796                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
797         } else {
798                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
799         }
800 }
801
802 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
803 {
804         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
805         if (on) {
806
807                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
808                           dev_priv->gart_vm_start,
809                           (long)dev_priv->gart_info.bus_addr,
810                           dev_priv->gart_size);
811                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
812                                   dev_priv->gart_vm_start);
813                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
814                                   dev_priv->gart_info.bus_addr);
815                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
816                                   dev_priv->gart_vm_start);
817                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
818                                   dev_priv->gart_vm_start +
819                                   dev_priv->gart_size - 1);
820
821                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
822
823                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
824                                   RADEON_PCIE_TX_GART_EN);
825         } else {
826                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
827                                   tmp & ~RADEON_PCIE_TX_GART_EN);
828         }
829 }
830
831 /* Enable or disable PCI GART on the chip */
832 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
833 {
834         u32 tmp;
835
836         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
837             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
838             (dev_priv->flags & RADEON_IS_IGPGART)) {
839                 radeon_set_igpgart(dev_priv, on);
840                 return;
841         }
842
843         if (dev_priv->flags & RADEON_IS_PCIE) {
844                 radeon_set_pciegart(dev_priv, on);
845                 return;
846         }
847
848         tmp = RADEON_READ(RADEON_AIC_CNTL);
849
850         if (on) {
851                 RADEON_WRITE(RADEON_AIC_CNTL,
852                              tmp | RADEON_PCIGART_TRANSLATE_EN);
853
854                 /* set PCI GART page-table base address
855                  */
856                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
857
858                 /* set address range for PCI address translate
859                  */
860                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
861                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
862                              + dev_priv->gart_size - 1);
863
864                 /* Turn off AGP aperture -- is this required for PCI GART?
865                  */
866                 radeon_write_agp_location(dev_priv, 0xffffffc0);
867                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
868         } else {
869                 RADEON_WRITE(RADEON_AIC_CNTL,
870                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
871         }
872 }
873
874 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
875 {
876         drm_radeon_private_t *dev_priv = dev->dev_private;
877
878         DRM_DEBUG("\n");
879
880         /* if we require new memory map but we don't have it fail */
881         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
882                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
883                 radeon_do_cleanup_cp(dev);
884                 return -EINVAL;
885         }
886
887         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
888                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
889                 dev_priv->flags &= ~RADEON_IS_AGP;
890         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
891                    && !init->is_pci) {
892                 DRM_DEBUG("Restoring AGP flag\n");
893                 dev_priv->flags |= RADEON_IS_AGP;
894         }
895
896         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
897                 DRM_ERROR("PCI GART memory not allocated!\n");
898                 radeon_do_cleanup_cp(dev);
899                 return -EINVAL;
900         }
901
902         dev_priv->usec_timeout = init->usec_timeout;
903         if (dev_priv->usec_timeout < 1 ||
904             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
905                 DRM_DEBUG("TIMEOUT problem!\n");
906                 radeon_do_cleanup_cp(dev);
907                 return -EINVAL;
908         }
909
910         /* Enable vblank on CRTC1 for older X servers
911          */
912         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
913
914         switch(init->func) {
915         case RADEON_INIT_R200_CP:
916                 dev_priv->microcode_version = UCODE_R200;
917                 break;
918         case RADEON_INIT_R300_CP:
919                 dev_priv->microcode_version = UCODE_R300;
920                 break;
921         default:
922                 dev_priv->microcode_version = UCODE_R100;
923         }
924
925         dev_priv->do_boxes = 0;
926         dev_priv->cp_mode = init->cp_mode;
927
928         /* We don't support anything other than bus-mastering ring mode,
929          * but the ring can be in either AGP or PCI space for the ring
930          * read pointer.
931          */
932         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
933             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
934                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
935                 radeon_do_cleanup_cp(dev);
936                 return -EINVAL;
937         }
938
939         switch (init->fb_bpp) {
940         case 16:
941                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
942                 break;
943         case 32:
944         default:
945                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
946                 break;
947         }
948         dev_priv->front_offset = init->front_offset;
949         dev_priv->front_pitch = init->front_pitch;
950         dev_priv->back_offset = init->back_offset;
951         dev_priv->back_pitch = init->back_pitch;
952
953         switch (init->depth_bpp) {
954         case 16:
955                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
956                 break;
957         case 32:
958         default:
959                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
960                 break;
961         }
962         dev_priv->depth_offset = init->depth_offset;
963         dev_priv->depth_pitch = init->depth_pitch;
964
965         /* Hardware state for depth clears.  Remove this if/when we no
966          * longer clear the depth buffer with a 3D rectangle.  Hard-code
967          * all values to prevent unwanted 3D state from slipping through
968          * and screwing with the clear operation.
969          */
970         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
971                                            (dev_priv->color_fmt << 10) |
972                                            (dev_priv->microcode_version ==
973                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
974
975         dev_priv->depth_clear.rb3d_zstencilcntl =
976             (dev_priv->depth_fmt |
977              RADEON_Z_TEST_ALWAYS |
978              RADEON_STENCIL_TEST_ALWAYS |
979              RADEON_STENCIL_S_FAIL_REPLACE |
980              RADEON_STENCIL_ZPASS_REPLACE |
981              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
982
983         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
984                                          RADEON_BFACE_SOLID |
985                                          RADEON_FFACE_SOLID |
986                                          RADEON_FLAT_SHADE_VTX_LAST |
987                                          RADEON_DIFFUSE_SHADE_FLAT |
988                                          RADEON_ALPHA_SHADE_FLAT |
989                                          RADEON_SPECULAR_SHADE_FLAT |
990                                          RADEON_FOG_SHADE_FLAT |
991                                          RADEON_VTX_PIX_CENTER_OGL |
992                                          RADEON_ROUND_MODE_TRUNC |
993                                          RADEON_ROUND_PREC_8TH_PIX);
994
995
996         dev_priv->ring_offset = init->ring_offset;
997         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
998         dev_priv->buffers_offset = init->buffers_offset;
999         dev_priv->gart_textures_offset = init->gart_textures_offset;
1000
1001         dev_priv->sarea = drm_getsarea(dev);
1002         if (!dev_priv->sarea) {
1003                 DRM_ERROR("could not find sarea!\n");
1004                 radeon_do_cleanup_cp(dev);
1005                 return -EINVAL;
1006         }
1007
1008         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1009         if (!dev_priv->cp_ring) {
1010                 DRM_ERROR("could not find cp ring region!\n");
1011                 radeon_do_cleanup_cp(dev);
1012                 return -EINVAL;
1013         }
1014         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1015         if (!dev_priv->ring_rptr) {
1016                 DRM_ERROR("could not find ring read pointer!\n");
1017                 radeon_do_cleanup_cp(dev);
1018                 return -EINVAL;
1019         }
1020         dev->agp_buffer_token = init->buffers_offset;
1021         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1022         if (!dev->agp_buffer_map) {
1023                 DRM_ERROR("could not find dma buffer region!\n");
1024                 radeon_do_cleanup_cp(dev);
1025                 return -EINVAL;
1026         }
1027
1028         if (init->gart_textures_offset) {
1029                 dev_priv->gart_textures =
1030                     drm_core_findmap(dev, init->gart_textures_offset);
1031                 if (!dev_priv->gart_textures) {
1032                         DRM_ERROR("could not find GART texture region!\n");
1033                         radeon_do_cleanup_cp(dev);
1034                         return -EINVAL;
1035                 }
1036         }
1037
1038         dev_priv->sarea_priv =
1039             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1040                                     init->sarea_priv_offset);
1041
1042 #if __OS_HAS_AGP
1043         if (dev_priv->flags & RADEON_IS_AGP) {
1044                 drm_core_ioremap(dev_priv->cp_ring, dev);
1045                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1046                 drm_core_ioremap(dev->agp_buffer_map, dev);
1047                 if (!dev_priv->cp_ring->handle ||
1048                     !dev_priv->ring_rptr->handle ||
1049                     !dev->agp_buffer_map->handle) {
1050                         DRM_ERROR("could not find ioremap agp regions!\n");
1051                         radeon_do_cleanup_cp(dev);
1052                         return -EINVAL;
1053                 }
1054         } else
1055 #endif
1056         {
1057                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1058                 dev_priv->ring_rptr->handle =
1059                     (void *)dev_priv->ring_rptr->offset;
1060                 dev->agp_buffer_map->handle =
1061                     (void *)dev->agp_buffer_map->offset;
1062
1063                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1064                           dev_priv->cp_ring->handle);
1065                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1066                           dev_priv->ring_rptr->handle);
1067                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1068                           dev->agp_buffer_map->handle);
1069         }
1070
1071         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1072         dev_priv->fb_size =
1073                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1074                 - dev_priv->fb_location;
1075
1076         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1077                                         ((dev_priv->front_offset
1078                                           + dev_priv->fb_location) >> 10));
1079
1080         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1081                                        ((dev_priv->back_offset
1082                                          + dev_priv->fb_location) >> 10));
1083
1084         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1085                                         ((dev_priv->depth_offset
1086                                           + dev_priv->fb_location) >> 10));
1087
1088         dev_priv->gart_size = init->gart_size;
1089
1090         /* New let's set the memory map ... */
1091         if (dev_priv->new_memmap) {
1092                 u32 base = 0;
1093
1094                 DRM_INFO("Setting GART location based on new memory map\n");
1095
1096                 /* If using AGP, try to locate the AGP aperture at the same
1097                  * location in the card and on the bus, though we have to
1098                  * align it down.
1099                  */
1100 #if __OS_HAS_AGP
1101                 if (dev_priv->flags & RADEON_IS_AGP) {
1102                         base = dev->agp->base;
1103                         /* Check if valid */
1104                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1105                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1106                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1107                                          dev->agp->base);
1108                                 base = 0;
1109                         }
1110                 }
1111 #endif
1112                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1113                 if (base == 0) {
1114                         base = dev_priv->fb_location + dev_priv->fb_size;
1115                         if (base < dev_priv->fb_location ||
1116                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1117                                 base = dev_priv->fb_location
1118                                         - dev_priv->gart_size;
1119                 }
1120                 dev_priv->gart_vm_start = base & 0xffc00000u;
1121                 if (dev_priv->gart_vm_start != base)
1122                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1123                                  base, dev_priv->gart_vm_start);
1124         } else {
1125                 DRM_INFO("Setting GART location based on old memory map\n");
1126                 dev_priv->gart_vm_start = dev_priv->fb_location +
1127                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1128         }
1129
1130 #if __OS_HAS_AGP
1131         if (dev_priv->flags & RADEON_IS_AGP)
1132                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1133                                                  - dev->agp->base
1134                                                  + dev_priv->gart_vm_start);
1135         else
1136 #endif
1137                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1138                                         - (unsigned long)dev->sg->virtual
1139                                         + dev_priv->gart_vm_start);
1140
1141         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1142         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1143         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1144                   dev_priv->gart_buffers_offset);
1145
1146         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1147         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1148                               + init->ring_size / sizeof(u32));
1149         dev_priv->ring.size = init->ring_size;
1150         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1151
1152         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1153         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1154
1155         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1156         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1157         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1158
1159         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1160
1161 #if __OS_HAS_AGP
1162         if (dev_priv->flags & RADEON_IS_AGP) {
1163                 /* Turn off PCI GART */
1164                 radeon_set_pcigart(dev_priv, 0);
1165         } else
1166 #endif
1167         {
1168                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1169                 /* if we have an offset set from userspace */
1170                 if (dev_priv->pcigart_offset_set) {
1171                         dev_priv->gart_info.bus_addr =
1172                             dev_priv->pcigart_offset + dev_priv->fb_location;
1173                         dev_priv->gart_info.mapping.offset =
1174                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1175                         dev_priv->gart_info.mapping.size =
1176                             dev_priv->gart_info.table_size;
1177
1178                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1179                         dev_priv->gart_info.addr =
1180                             dev_priv->gart_info.mapping.handle;
1181
1182                         if (dev_priv->flags & RADEON_IS_PCIE)
1183                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1184                         else
1185                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1186                         dev_priv->gart_info.gart_table_location =
1187                             DRM_ATI_GART_FB;
1188
1189                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1190                                   dev_priv->gart_info.addr,
1191                                   dev_priv->pcigart_offset);
1192                 } else {
1193                         if (dev_priv->flags & RADEON_IS_IGPGART)
1194                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1195                         else
1196                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1197                         dev_priv->gart_info.gart_table_location =
1198                             DRM_ATI_GART_MAIN;
1199                         dev_priv->gart_info.addr = NULL;
1200                         dev_priv->gart_info.bus_addr = 0;
1201                         if (dev_priv->flags & RADEON_IS_PCIE) {
1202                                 DRM_ERROR
1203                                     ("Cannot use PCI Express without GART in FB memory\n");
1204                                 radeon_do_cleanup_cp(dev);
1205                                 return -EINVAL;
1206                         }
1207                 }
1208
1209                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1210                         DRM_ERROR("failed to init PCI GART!\n");
1211                         radeon_do_cleanup_cp(dev);
1212                         return -ENOMEM;
1213                 }
1214
1215                 /* Turn on PCI GART */
1216                 radeon_set_pcigart(dev_priv, 1);
1217         }
1218
1219         radeon_cp_load_microcode(dev_priv);
1220         radeon_cp_init_ring_buffer(dev, dev_priv);
1221
1222         dev_priv->last_buf = 0;
1223
1224         radeon_do_engine_reset(dev);
1225         radeon_test_writeback(dev_priv);
1226
1227         return 0;
1228 }
1229
1230 static int radeon_do_cleanup_cp(struct drm_device * dev)
1231 {
1232         drm_radeon_private_t *dev_priv = dev->dev_private;
1233         DRM_DEBUG("\n");
1234
1235         /* Make sure interrupts are disabled here because the uninstall ioctl
1236          * may not have been called from userspace and after dev_private
1237          * is freed, it's too late.
1238          */
1239         if (dev->irq_enabled)
1240                 drm_irq_uninstall(dev);
1241
1242 #if __OS_HAS_AGP
1243         if (dev_priv->flags & RADEON_IS_AGP) {
1244                 if (dev_priv->cp_ring != NULL) {
1245                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1246                         dev_priv->cp_ring = NULL;
1247                 }
1248                 if (dev_priv->ring_rptr != NULL) {
1249                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1250                         dev_priv->ring_rptr = NULL;
1251                 }
1252                 if (dev->agp_buffer_map != NULL) {
1253                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1254                         dev->agp_buffer_map = NULL;
1255                 }
1256         } else
1257 #endif
1258         {
1259
1260                 if (dev_priv->gart_info.bus_addr) {
1261                         /* Turn off PCI GART */
1262                         radeon_set_pcigart(dev_priv, 0);
1263                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1264                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1265                 }
1266
1267                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1268                 {
1269                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1270                         dev_priv->gart_info.addr = 0;
1271                 }
1272         }
1273         /* only clear to the start of flags */
1274         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1275
1276         return 0;
1277 }
1278
1279 /* This code will reinit the Radeon CP hardware after a resume from disc.
1280  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1281  * here we make sure that all Radeon hardware initialisation is re-done without
1282  * affecting running applications.
1283  *
1284  * Charl P. Botha <http://cpbotha.net>
1285  */
1286 static int radeon_do_resume_cp(struct drm_device * dev)
1287 {
1288         drm_radeon_private_t *dev_priv = dev->dev_private;
1289
1290         if (!dev_priv) {
1291                 DRM_ERROR("Called with no initialization\n");
1292                 return -EINVAL;
1293         }
1294
1295         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1296
1297 #if __OS_HAS_AGP
1298         if (dev_priv->flags & RADEON_IS_AGP) {
1299                 /* Turn off PCI GART */
1300                 radeon_set_pcigart(dev_priv, 0);
1301         } else
1302 #endif
1303         {
1304                 /* Turn on PCI GART */
1305                 radeon_set_pcigart(dev_priv, 1);
1306         }
1307
1308         radeon_cp_load_microcode(dev_priv);
1309         radeon_cp_init_ring_buffer(dev, dev_priv);
1310
1311         radeon_do_engine_reset(dev);
1312         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1313
1314         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1315
1316         return 0;
1317 }
1318
1319 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1320 {
1321         drm_radeon_init_t *init = data;
1322
1323         LOCK_TEST_WITH_RETURN(dev, file_priv);
1324
1325         if (init->func == RADEON_INIT_R300_CP)
1326                 r300_init_reg_flags(dev);
1327
1328         switch (init->func) {
1329         case RADEON_INIT_CP:
1330         case RADEON_INIT_R200_CP:
1331         case RADEON_INIT_R300_CP:
1332                 return radeon_do_init_cp(dev, init);
1333         case RADEON_CLEANUP_CP:
1334                 return radeon_do_cleanup_cp(dev);
1335         }
1336
1337         return -EINVAL;
1338 }
1339
1340 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1341 {
1342         drm_radeon_private_t *dev_priv = dev->dev_private;
1343         DRM_DEBUG("\n");
1344
1345         LOCK_TEST_WITH_RETURN(dev, file_priv);
1346
1347         if (dev_priv->cp_running) {
1348                 DRM_DEBUG("while CP running\n");
1349                 return 0;
1350         }
1351         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1352                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1353                           dev_priv->cp_mode);
1354                 return 0;
1355         }
1356
1357         radeon_do_cp_start(dev_priv);
1358
1359         return 0;
1360 }
1361
1362 /* Stop the CP.  The engine must have been idled before calling this
1363  * routine.
1364  */
1365 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1366 {
1367         drm_radeon_private_t *dev_priv = dev->dev_private;
1368         drm_radeon_cp_stop_t *stop = data;
1369         int ret;
1370         DRM_DEBUG("\n");
1371
1372         LOCK_TEST_WITH_RETURN(dev, file_priv);
1373
1374         if (!dev_priv->cp_running)
1375                 return 0;
1376
1377         /* Flush any pending CP commands.  This ensures any outstanding
1378          * commands are exectuted by the engine before we turn it off.
1379          */
1380         if (stop->flush) {
1381                 radeon_do_cp_flush(dev_priv);
1382         }
1383
1384         /* If we fail to make the engine go idle, we return an error
1385          * code so that the DRM ioctl wrapper can try again.
1386          */
1387         if (stop->idle) {
1388                 ret = radeon_do_cp_idle(dev_priv);
1389                 if (ret)
1390                         return ret;
1391         }
1392
1393         /* Finally, we can turn off the CP.  If the engine isn't idle,
1394          * we will get some dropped triangles as they won't be fully
1395          * rendered before the CP is shut down.
1396          */
1397         radeon_do_cp_stop(dev_priv);
1398
1399         /* Reset the engine */
1400         radeon_do_engine_reset(dev);
1401
1402         return 0;
1403 }
1404
1405 void radeon_do_release(struct drm_device * dev)
1406 {
1407         drm_radeon_private_t *dev_priv = dev->dev_private;
1408         int i, ret;
1409
1410         if (dev_priv) {
1411                 if (dev_priv->cp_running) {
1412                         /* Stop the cp */
1413                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1414                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1415 #ifdef __linux__
1416                                 schedule();
1417 #else
1418                                 tsleep(&ret, PZERO, "rdnrel", 1);
1419 #endif
1420                         }
1421                         radeon_do_cp_stop(dev_priv);
1422                         radeon_do_engine_reset(dev);
1423                 }
1424
1425                 /* Disable *all* interrupts */
1426                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1427                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1428
1429                 if (dev_priv->mmio) {   /* remove all surfaces */
1430                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1431                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1432                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1433                                              16 * i, 0);
1434                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1435                                              16 * i, 0);
1436                         }
1437                 }
1438
1439                 /* Free memory heap structures */
1440                 radeon_mem_takedown(&(dev_priv->gart_heap));
1441                 radeon_mem_takedown(&(dev_priv->fb_heap));
1442
1443                 /* deallocate kernel resources */
1444                 radeon_do_cleanup_cp(dev);
1445         }
1446 }
1447
1448 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1449  */
1450 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1451 {
1452         drm_radeon_private_t *dev_priv = dev->dev_private;
1453         DRM_DEBUG("\n");
1454
1455         LOCK_TEST_WITH_RETURN(dev, file_priv);
1456
1457         if (!dev_priv) {
1458                 DRM_DEBUG("called before init done\n");
1459                 return -EINVAL;
1460         }
1461
1462         radeon_do_cp_reset(dev_priv);
1463
1464         /* The CP is no longer running after an engine reset */
1465         dev_priv->cp_running = 0;
1466
1467         return 0;
1468 }
1469
1470 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1471 {
1472         drm_radeon_private_t *dev_priv = dev->dev_private;
1473         DRM_DEBUG("\n");
1474
1475         LOCK_TEST_WITH_RETURN(dev, file_priv);
1476
1477         return radeon_do_cp_idle(dev_priv);
1478 }
1479
1480 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1481  */
1482 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1483 {
1484
1485         return radeon_do_resume_cp(dev);
1486 }
1487
1488 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1489 {
1490         DRM_DEBUG("\n");
1491
1492         LOCK_TEST_WITH_RETURN(dev, file_priv);
1493
1494         return radeon_do_engine_reset(dev);
1495 }
1496
1497 /* ================================================================
1498  * Fullscreen mode
1499  */
1500
1501 /* KW: Deprecated to say the least:
1502  */
1503 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1504 {
1505         return 0;
1506 }
1507
1508 /* ================================================================
1509  * Freelist management
1510  */
1511
1512 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1513  *   bufs until freelist code is used.  Note this hides a problem with
1514  *   the scratch register * (used to keep track of last buffer
1515  *   completed) being written to before * the last buffer has actually
1516  *   completed rendering.
1517  *
1518  * KW:  It's also a good way to find free buffers quickly.
1519  *
1520  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1521  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1522  * we essentially have to do this, else old clients will break.
1523  *
1524  * However, it does leave open a potential deadlock where all the
1525  * buffers are held by other clients, which can't release them because
1526  * they can't get the lock.
1527  */
1528
1529 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1530 {
1531         struct drm_device_dma *dma = dev->dma;
1532         drm_radeon_private_t *dev_priv = dev->dev_private;
1533         drm_radeon_buf_priv_t *buf_priv;
1534         struct drm_buf *buf;
1535         int i, t;
1536         int start;
1537
1538         if (++dev_priv->last_buf >= dma->buf_count)
1539                 dev_priv->last_buf = 0;
1540
1541         start = dev_priv->last_buf;
1542
1543         for (t = 0; t < dev_priv->usec_timeout; t++) {
1544                 u32 done_age = GET_SCRATCH(1);
1545                 DRM_DEBUG("done_age = %d\n", done_age);
1546                 for (i = start; i < dma->buf_count; i++) {
1547                         buf = dma->buflist[i];
1548                         buf_priv = buf->dev_private;
1549                         if (buf->file_priv == NULL || (buf->pending &&
1550                                                        buf_priv->age <=
1551                                                        done_age)) {
1552                                 dev_priv->stats.requested_bufs++;
1553                                 buf->pending = 0;
1554                                 return buf;
1555                         }
1556                         start = 0;
1557                 }
1558
1559                 if (t) {
1560                         DRM_UDELAY(1);
1561                         dev_priv->stats.freelist_loops++;
1562                 }
1563         }
1564
1565         DRM_DEBUG("returning NULL!\n");
1566         return NULL;
1567 }
1568
1569 #if 0
1570 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1571 {
1572         struct drm_device_dma *dma = dev->dma;
1573         drm_radeon_private_t *dev_priv = dev->dev_private;
1574         drm_radeon_buf_priv_t *buf_priv;
1575         struct drm_buf *buf;
1576         int i, t;
1577         int start;
1578         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1579
1580         if (++dev_priv->last_buf >= dma->buf_count)
1581                 dev_priv->last_buf = 0;
1582
1583         start = dev_priv->last_buf;
1584         dev_priv->stats.freelist_loops++;
1585
1586         for (t = 0; t < 2; t++) {
1587                 for (i = start; i < dma->buf_count; i++) {
1588                         buf = dma->buflist[i];
1589                         buf_priv = buf->dev_private;
1590                         if (buf->file_priv == 0 || (buf->pending &&
1591                                                     buf_priv->age <=
1592                                                     done_age)) {
1593                                 dev_priv->stats.requested_bufs++;
1594                                 buf->pending = 0;
1595                                 return buf;
1596                         }
1597                 }
1598                 start = 0;
1599         }
1600
1601         return NULL;
1602 }
1603 #endif
1604
1605 void radeon_freelist_reset(struct drm_device * dev)
1606 {
1607         struct drm_device_dma *dma = dev->dma;
1608         drm_radeon_private_t *dev_priv = dev->dev_private;
1609         int i;
1610
1611         dev_priv->last_buf = 0;
1612         for (i = 0; i < dma->buf_count; i++) {
1613                 struct drm_buf *buf = dma->buflist[i];
1614                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1615                 buf_priv->age = 0;
1616         }
1617 }
1618
1619 /* ================================================================
1620  * CP command submission
1621  */
1622
1623 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1624 {
1625         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1626         int i;
1627         u32 last_head = GET_RING_HEAD(dev_priv);
1628
1629         for (i = 0; i < dev_priv->usec_timeout; i++) {
1630                 u32 head = GET_RING_HEAD(dev_priv);
1631
1632                 ring->space = (head - ring->tail) * sizeof(u32);
1633                 if (ring->space <= 0)
1634                         ring->space += ring->size;
1635                 if (ring->space > n)
1636                         return 0;
1637
1638                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1639
1640                 if (head != last_head)
1641                         i = 0;
1642                 last_head = head;
1643
1644                 DRM_UDELAY(1);
1645         }
1646
1647         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1648 #if RADEON_FIFO_DEBUG
1649         radeon_status(dev_priv);
1650         DRM_ERROR("failed!\n");
1651 #endif
1652         return -EBUSY;
1653 }
1654
1655 static int radeon_cp_get_buffers(struct drm_device *dev,
1656                                  struct drm_file *file_priv,
1657                                  struct drm_dma * d)
1658 {
1659         int i;
1660         struct drm_buf *buf;
1661
1662         for (i = d->granted_count; i < d->request_count; i++) {
1663                 buf = radeon_freelist_get(dev);
1664                 if (!buf)
1665                         return -EBUSY;  /* NOTE: broken client */
1666
1667                 buf->file_priv = file_priv;
1668
1669                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1670                                      sizeof(buf->idx)))
1671                         return -EFAULT;
1672                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1673                                      sizeof(buf->total)))
1674                         return -EFAULT;
1675
1676                 d->granted_count++;
1677         }
1678         return 0;
1679 }
1680
1681 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1682 {
1683         struct drm_device_dma *dma = dev->dma;
1684         int ret = 0;
1685         struct drm_dma *d = data;
1686
1687         LOCK_TEST_WITH_RETURN(dev, file_priv);
1688
1689         /* Please don't send us buffers.
1690          */
1691         if (d->send_count != 0) {
1692                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1693                           DRM_CURRENTPID, d->send_count);
1694                 return -EINVAL;
1695         }
1696
1697         /* We'll send you buffers.
1698          */
1699         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1700                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1701                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1702                 return -EINVAL;
1703         }
1704
1705         d->granted_count = 0;
1706
1707         if (d->request_count) {
1708                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1709         }
1710
1711         return ret;
1712 }
1713
1714 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1715 {
1716         drm_radeon_private_t *dev_priv;
1717         int ret = 0;
1718
1719         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1720         if (dev_priv == NULL)
1721                 return -ENOMEM;
1722
1723         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1724         dev->dev_private = (void *)dev_priv;
1725         dev_priv->flags = flags;
1726
1727         switch (flags & RADEON_FAMILY_MASK) {
1728         case CHIP_R100:
1729         case CHIP_RV200:
1730         case CHIP_R200:
1731         case CHIP_R300:
1732         case CHIP_R350:
1733         case CHIP_R420:
1734         case CHIP_R423:
1735         case CHIP_RV410:
1736         case CHIP_RV515:
1737         case CHIP_R520:
1738         case CHIP_RV570:
1739         case CHIP_R580:
1740                 dev_priv->flags |= RADEON_HAS_HIERZ;
1741                 break;
1742         default:
1743                 /* all other chips have no hierarchical z buffer */
1744                 break;
1745         }
1746
1747         if (drm_device_is_agp(dev))
1748                 dev_priv->flags |= RADEON_IS_AGP;
1749         else if (drm_device_is_pcie(dev))
1750                 dev_priv->flags |= RADEON_IS_PCIE;
1751         else
1752                 dev_priv->flags |= RADEON_IS_PCI;
1753
1754         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1755                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1756                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1757         if (ret != 0)
1758                 return ret;
1759
1760         ret = drm_vblank_init(dev, 2);
1761         if (ret) {
1762                 radeon_driver_unload(dev);
1763                 return ret;
1764         }
1765
1766         DRM_DEBUG("%s card detected\n",
1767                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1768         return ret;
1769 }
1770
1771 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1772  * have to find them.
1773  */
1774 int radeon_driver_firstopen(struct drm_device *dev)
1775 {
1776         int ret;
1777         drm_local_map_t *map;
1778         drm_radeon_private_t *dev_priv = dev->dev_private;
1779
1780         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1781
1782         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1783         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1784                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1785                          _DRM_WRITE_COMBINING, &map);
1786         if (ret != 0)
1787                 return ret;
1788
1789         return 0;
1790 }
1791
1792 int radeon_driver_unload(struct drm_device *dev)
1793 {
1794         drm_radeon_private_t *dev_priv = dev->dev_private;
1795
1796         DRM_DEBUG("\n");
1797
1798         drm_rmmap(dev, dev_priv->mmio);
1799
1800         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1801
1802         dev->dev_private = NULL;
1803         return 0;
1804 }