2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * Implementation of transmit path.
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 #define OFDM_SIFS_TIME 16
40 static u32 bits_per_symbol[][2] = {
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
68 static void ath_tx_txqaddbuf(struct ath_softc *sc,
69 struct ath_txq *txq, struct list_head *head)
71 struct ath_hal *ah = sc->sc_ah;
74 * Insert the frame on the outbound list and
75 * pass it on to the hardware.
81 bf = list_first_entry(head, struct ath_buf, list);
83 list_splice_tail_init(head, &txq->axq_q);
85 txq->axq_totalqueued++;
86 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
88 DPRINTF(sc, ATH_DBG_QUEUE,
89 "%s: txq depth = %d\n", __func__, txq->axq_depth);
91 if (txq->axq_link == NULL) {
92 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
93 DPRINTF(sc, ATH_DBG_XMIT,
94 "%s: TXDP[%u] = %llx (%p)\n",
95 __func__, txq->axq_qnum,
96 ito64(bf->bf_daddr), bf->bf_desc);
98 *txq->axq_link = bf->bf_daddr;
99 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
101 txq->axq_qnum, txq->axq_link,
102 ito64(bf->bf_daddr), bf->bf_desc);
104 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
105 ath9k_hw_txstart(ah, txq->axq_qnum);
108 /* Get transmit rate index using rate in Kbps */
110 static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
115 for (i = 0; i < rt->rateCount; i++) {
116 if (rt->info[i].rateKbps == rate) {
125 /* Check if it's okay to send out aggregates */
127 static int ath_aggr_query(struct ath_softc *sc,
128 struct ath_node *an, u8 tidno)
130 struct ath_atx_tid *tid;
131 tid = ATH_AN_2_TID(an, tidno);
133 if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress)
139 /* Calculate Atheros packet type from IEEE80211 packet header */
141 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
143 struct ieee80211_hdr *hdr;
144 enum ath9k_pkt_type htype;
147 hdr = (struct ieee80211_hdr *)skb->data;
148 fc = hdr->frame_control;
150 if (ieee80211_is_beacon(fc))
151 htype = ATH9K_PKT_TYPE_BEACON;
152 else if (ieee80211_is_probe_resp(fc))
153 htype = ATH9K_PKT_TYPE_PROBE_RESP;
154 else if (ieee80211_is_atim(fc))
155 htype = ATH9K_PKT_TYPE_ATIM;
156 else if (ieee80211_is_pspoll(fc))
157 htype = ATH9K_PKT_TYPE_PSPOLL;
159 htype = ATH9K_PKT_TYPE_NORMAL;
164 static bool check_min_rate(struct sk_buff *skb)
166 struct ieee80211_hdr *hdr;
167 bool use_minrate = false;
170 hdr = (struct ieee80211_hdr *)skb->data;
171 fc = hdr->frame_control;
173 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
175 } else if (ieee80211_is_data(fc)) {
176 if (ieee80211_is_nullfunc(fc) ||
177 /* Port Access Entity (IEEE 802.1X) */
178 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
186 static int get_hw_crypto_keytype(struct sk_buff *skb)
188 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
190 if (tx_info->control.hw_key) {
191 if (tx_info->control.hw_key->alg == ALG_WEP)
192 return ATH9K_KEY_TYPE_WEP;
193 else if (tx_info->control.hw_key->alg == ALG_TKIP)
194 return ATH9K_KEY_TYPE_TKIP;
195 else if (tx_info->control.hw_key->alg == ALG_CCMP)
196 return ATH9K_KEY_TYPE_AES;
199 return ATH9K_KEY_TYPE_CLEAR;
202 static void setup_rate_retries(struct ath_softc *sc, struct sk_buff *skb)
204 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
205 struct ath_tx_info_priv *tx_info_priv;
206 struct ath_rc_series *rcs;
207 struct ieee80211_hdr *hdr;
208 const struct ath9k_rate_table *rt;
213 rt = sc->sc_currates;
216 hdr = (struct ieee80211_hdr *)skb->data;
217 fc = hdr->frame_control;
218 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; /* HACK */
219 rcs = tx_info_priv->rcs;
221 /* Check if min rates have to be used */
222 use_minrate = check_min_rate(skb);
224 if (ieee80211_is_data(fc) && !use_minrate) {
225 if (is_multicast_ether_addr(hdr->addr1)) {
227 ath_tx_findindex(rt, tx_info_priv->min_rate);
228 /* mcast packets are not re-tried */
232 /* for management and control frames,
233 or for NULL and EAPOL frames */
235 rcs[0].rix = ath_rate_findrateix(sc, tx_info_priv->min_rate);
238 rcs[0].tries = ATH_MGT_TXMAXTRY;
243 if (ieee80211_has_morefrags(fc) ||
244 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
245 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
246 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
247 /* reset tries but keep rate index */
248 rcs[0].tries = ATH_TXMAXTRY;
252 /* Called only when tx aggregation is enabled and HT is supported */
254 static void assign_aggr_tid_seqno(struct sk_buff *skb,
257 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
258 struct ieee80211_hdr *hdr;
260 struct ath_atx_tid *tid;
264 if (!tx_info->control.sta)
267 an = (struct ath_node *)tx_info->control.sta->drv_priv;
268 hdr = (struct ieee80211_hdr *)skb->data;
269 fc = hdr->frame_control;
273 if (ieee80211_is_data_qos(fc)) {
274 qc = ieee80211_get_qos_ctl(hdr);
275 bf->bf_tidno = qc[0] & 0xf;
280 if (ieee80211_is_data(fc) && !check_min_rate(skb)) {
281 /* For HT capable stations, we save tidno for later use.
282 * We also override seqno set by upper layer with the one
283 * in tx aggregation state.
285 * If fragmentation is on, the sequence number is
286 * not overridden, since it has been
287 * incremented by the fragmentation routine.
289 * FIXME: check if the fragmentation threshold exceeds
292 tid = ATH_AN_2_TID(an, bf->bf_tidno);
293 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
294 IEEE80211_SEQ_SEQ_SHIFT);
295 bf->bf_seqno = tid->seq_next;
296 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
300 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
303 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
306 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
307 flags |= ATH9K_TXDESC_INTREQ;
309 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
310 flags |= ATH9K_TXDESC_NOACK;
311 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
312 flags |= ATH9K_TXDESC_RTSENA;
317 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
319 struct ath_buf *bf = NULL;
321 spin_lock_bh(&sc->sc_txbuflock);
323 if (unlikely(list_empty(&sc->sc_txbuf))) {
324 spin_unlock_bh(&sc->sc_txbuflock);
328 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
331 spin_unlock_bh(&sc->sc_txbuflock);
336 /* To complete a chain of buffers associated a frame */
338 static void ath_tx_complete_buf(struct ath_softc *sc,
340 struct list_head *bf_q,
341 int txok, int sendbar)
343 struct sk_buff *skb = bf->bf_mpdu;
344 struct ath_xmit_status tx_status;
347 * Set retry information.
348 * NB: Don't use the information in the descriptor, because the frame
349 * could be software retried.
351 tx_status.retries = bf->bf_retries;
355 tx_status.flags = ATH_TX_BAR;
358 tx_status.flags |= ATH_TX_ERROR;
360 if (bf_isxretried(bf))
361 tx_status.flags |= ATH_TX_XRETRY;
363 /* Unmap this frame */
364 pci_unmap_single(sc->pdev,
368 /* complete this frame */
369 ath_tx_complete(sc, skb, &tx_status);
372 * Return the list of ath_buf of this mpdu to free queue
374 spin_lock_bh(&sc->sc_txbuflock);
375 list_splice_tail_init(bf_q, &sc->sc_txbuf);
376 spin_unlock_bh(&sc->sc_txbuflock);
380 * queue up a dest/ac pair for tx scheduling
381 * NB: must be called with txq lock held
384 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
386 struct ath_atx_ac *ac = tid->ac;
389 * if tid is paused, hold off
395 * add tid to ac atmost once
401 list_add_tail(&tid->list, &ac->tid_q);
404 * add node ac to txq atmost once
410 list_add_tail(&ac->list, &txq->axq_acq);
415 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
417 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
419 spin_lock_bh(&txq->axq_lock);
423 spin_unlock_bh(&txq->axq_lock);
426 /* resume a tid and schedule aggregate */
428 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
430 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
432 ASSERT(tid->paused > 0);
433 spin_lock_bh(&txq->axq_lock);
440 if (list_empty(&tid->buf_q))
444 * Add this TID to scheduler and try to send out aggregates
446 ath_tx_queue_tid(txq, tid);
447 ath_txq_schedule(sc, txq);
449 spin_unlock_bh(&txq->axq_lock);
452 /* Compute the number of bad frames */
454 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
457 struct ath_buf *bf_last = bf->bf_lastbf;
458 struct ath_desc *ds = bf_last->bf_desc;
460 u32 ba[WME_BA_BMP_SIZE >> 5];
465 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
468 isaggr = bf_isaggr(bf);
470 seq_st = ATH_DS_BA_SEQ(ds);
471 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
475 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
476 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
485 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
488 struct ieee80211_hdr *hdr;
490 bf->bf_state.bf_type |= BUF_RETRY;
494 hdr = (struct ieee80211_hdr *)skb->data;
495 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
498 /* Update block ack window */
500 static void ath_tx_update_baw(struct ath_softc *sc,
501 struct ath_atx_tid *tid, int seqno)
505 index = ATH_BA_INDEX(tid->seq_start, seqno);
506 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
508 tid->tx_buf[cindex] = NULL;
510 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
511 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
512 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
517 * ath_pkt_dur - compute packet duration (NB: not NAV)
520 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
521 * width - 0 for 20 MHz, 1 for 40 MHz
522 * half_gi - to use 4us v/s 3.6 us for symbol time
525 static u32 ath_pkt_duration(struct ath_softc *sc,
532 const struct ath9k_rate_table *rt = sc->sc_currates;
533 u32 nbits, nsymbits, duration, nsymbols;
537 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
538 rc = rt->info[rix].rateCode;
541 * for legacy rates, use old function to compute packet duration
544 return ath9k_hw_computetxtime(sc->sc_ah,
550 * find number of symbols: PLCP + data
552 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
553 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
554 nsymbols = (nbits + nsymbits - 1) / nsymbits;
557 duration = SYMBOL_TIME(nsymbols);
559 duration = SYMBOL_TIME_HALFGI(nsymbols);
562 * addup duration for legacy/ht training and signal fields
564 streams = HT_RC_2_STREAMS(rc);
565 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
569 /* Rate module function to set rate related fields in tx descriptor */
571 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
573 struct ath_hal *ah = sc->sc_ah;
574 const struct ath9k_rate_table *rt;
575 struct ath_desc *ds = bf->bf_desc;
576 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
577 struct ath9k_11n_rate_series series[4];
578 int i, flags, rtsctsena = 0, dynamic_mimops = 0;
580 u8 rix = 0, cix, ctsrate = 0;
581 u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit;
582 struct ath_node *an = NULL;
584 struct ieee80211_tx_info *tx_info;
586 skb = (struct sk_buff *)bf->bf_mpdu;
587 tx_info = IEEE80211_SKB_CB(skb);
589 if (tx_info->control.sta)
590 an = (struct ath_node *)tx_info->control.sta->drv_priv;
593 * get the cix for the lowest valid rix.
595 rt = sc->sc_currates;
597 if (bf->bf_rcs[i].tries) {
598 rix = bf->bf_rcs[i].rix;
602 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
603 cix = rt->info[rix].controlRate;
606 * If 802.11g protection is enabled, determine whether
607 * to use RTS/CTS or just CTS. Note that this is only
608 * done for OFDM/HT unicast frames.
610 if (sc->sc_protmode != PROT_M_NONE &&
611 (rt->info[rix].phy == PHY_OFDM ||
612 rt->info[rix].phy == PHY_HT) &&
613 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
614 if (sc->sc_protmode == PROT_M_RTSCTS)
615 flags = ATH9K_TXDESC_RTSENA;
616 else if (sc->sc_protmode == PROT_M_CTSONLY)
617 flags = ATH9K_TXDESC_CTSENA;
619 cix = rt->info[sc->sc_protrix].controlRate;
623 /* For 11n, the default behavior is to enable RTS for
624 * hw retried frames. We enable the global flag here and
625 * let rate series flags determine which rates will actually
628 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
630 * 802.11g protection not needed, use our default behavior
633 flags = ATH9K_TXDESC_RTSENA;
635 * For dynamic MIMO PS, RTS needs to precede the first aggregate
636 * and the second aggregate should have any protection at all.
638 if (an && an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
639 if (!bf_isaggrburst(bf)) {
640 flags = ATH9K_TXDESC_RTSENA;
649 * Set protection if aggregate protection on
651 if (sc->sc_config.ath_aggr_prot &&
652 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
653 flags = ATH9K_TXDESC_RTSENA;
654 cix = rt->info[sc->sc_protrix].controlRate;
659 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
661 if (bf_isaggr(bf) && (bf->bf_al > aggr_limit_with_rts)) {
663 * Ensure that in the case of SM Dynamic power save
664 * while we are bursting the second aggregate the
667 flags &= ~(ATH9K_TXDESC_RTSENA);
671 * CTS transmit rate is derived from the transmit rate
672 * by looking in the h/w rate table. We must also factor
673 * in whether or not a short preamble is to be used.
675 /* NB: cix is set above where RTS/CTS is enabled */
677 ctsrate = rt->info[cix].rateCode |
678 (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0);
681 * Setup HAL rate series
683 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
685 for (i = 0; i < 4; i++) {
686 if (!bf->bf_rcs[i].tries)
689 rix = bf->bf_rcs[i].rix;
691 series[i].Rate = rt->info[rix].rateCode |
692 (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0);
694 series[i].Tries = bf->bf_rcs[i].tries;
696 series[i].RateFlags = (
697 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
698 ATH9K_RATESERIES_RTS_CTS : 0) |
699 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
700 ATH9K_RATESERIES_2040 : 0) |
701 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
702 ATH9K_RATESERIES_HALFGI : 0);
704 series[i].PktDuration = ath_pkt_duration(
706 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
707 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
708 bf_isshpreamble(bf));
710 if (an && (an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
711 (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
713 * When sending to an HT node that has enabled static
714 * SM/MIMO power save, send at single stream rates but
715 * use maximum allowed transmit chains per user,
716 * hardware, regulatory, or country limits for
719 series[i].ChSel = sc->sc_tx_chainmask;
723 ath_chainmask_sel_logic(sc, an);
725 series[i].ChSel = sc->sc_tx_chainmask;
729 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
732 * Set RTS for all rates if node is in dynamic powersave
733 * mode and we are using dual stream rates.
735 if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
736 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
740 * For non-HT devices, calculate RTS/CTS duration in software
741 * and disable multi-rate retry.
743 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
745 * Compute the transmit duration based on the frame
746 * size and the size of an ACK frame. We call into the
747 * HAL to do the computation since it depends on the
748 * characteristics of the actual PHY being used.
750 * NB: CTS is assumed the same size as an ACK so we can
751 * use the precalculated ACK durations.
753 if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */
754 ctsduration += bf_isshpreamble(bf) ?
755 rt->info[cix].spAckDuration :
756 rt->info[cix].lpAckDuration;
759 ctsduration += series[0].PktDuration;
761 if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
762 ctsduration += bf_isshpreamble(bf) ?
763 rt->info[rix].spAckDuration :
764 rt->info[rix].lpAckDuration;
768 * Disable multi-rate retry when using RTS/CTS by clearing
771 memset(&series[1], 0, sizeof(struct ath9k_11n_rate_series) * 3);
775 * set dur_update_en for l-sig computation except for PS-Poll frames
777 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
782 if (sc->sc_config.ath_aggr_prot && flags)
783 ath9k_hw_set11n_burstduration(ah, ds, 8192);
787 * Function to send a normal HT (non-AMPDU) frame
788 * NB: must be called with txq lock held
791 static int ath_tx_send_normal(struct ath_softc *sc,
793 struct ath_atx_tid *tid,
794 struct list_head *bf_head)
798 struct ieee80211_tx_info *tx_info;
799 struct ath_tx_info_priv *tx_info_priv;
801 BUG_ON(list_empty(bf_head));
803 bf = list_first_entry(bf_head, struct ath_buf, list);
804 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
806 skb = (struct sk_buff *)bf->bf_mpdu;
807 tx_info = IEEE80211_SKB_CB(skb);
810 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
811 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
813 /* update starting sequence number for subsequent ADDBA request */
814 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
816 /* Queue to h/w without aggregation */
818 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
819 ath_buf_set_rate(sc, bf);
820 ath_tx_txqaddbuf(sc, txq, bf_head);
825 /* flush tid's software queue and send frames as non-ampdu's */
827 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
829 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
831 struct list_head bf_head;
832 INIT_LIST_HEAD(&bf_head);
834 ASSERT(tid->paused > 0);
835 spin_lock_bh(&txq->axq_lock);
839 if (tid->paused > 0) {
840 spin_unlock_bh(&txq->axq_lock);
844 while (!list_empty(&tid->buf_q)) {
845 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
846 ASSERT(!bf_isretried(bf));
847 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
848 ath_tx_send_normal(sc, txq, tid, &bf_head);
851 spin_unlock_bh(&txq->axq_lock);
854 /* Completion routine of an aggregate */
856 static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
859 struct list_head *bf_q,
862 struct ath_node *an = NULL;
864 struct ieee80211_tx_info *tx_info;
865 struct ath_atx_tid *tid = NULL;
866 struct ath_buf *bf_last = bf->bf_lastbf;
867 struct ath_desc *ds = bf_last->bf_desc;
868 struct ath_buf *bf_next, *bf_lastq = NULL;
869 struct list_head bf_head, bf_pending;
871 u32 ba[WME_BA_BMP_SIZE >> 5];
872 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
874 skb = (struct sk_buff *)bf->bf_mpdu;
875 tx_info = IEEE80211_SKB_CB(skb);
877 if (tx_info->control.sta) {
878 an = (struct ath_node *)tx_info->control.sta->drv_priv;
879 tid = ATH_AN_2_TID(an, bf->bf_tidno);
882 isaggr = bf_isaggr(bf);
885 if (ATH_DS_TX_BA(ds)) {
887 * extract starting sequence and
890 seq_st = ATH_DS_BA_SEQ(ds);
892 ATH_DS_BA_BITMAP(ds),
893 WME_BA_BMP_SIZE >> 3);
895 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
898 * AR5416 can become deaf/mute when BA
899 * issue happens. Chip needs to be reset.
900 * But AP code may have sychronization issues
901 * when perform internal reset in this routine.
902 * Only enable reset in STA mode for now.
904 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
908 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
912 INIT_LIST_HEAD(&bf_pending);
913 INIT_LIST_HEAD(&bf_head);
916 txfail = txpending = 0;
917 bf_next = bf->bf_next;
919 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
920 /* transmit completion, subframe is
921 * acked by block ack */
922 } else if (!isaggr && txok) {
923 /* transmit completion */
926 if (!tid->cleanup_inprogress &&
927 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
928 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
929 ath_tx_set_retry(sc, bf);
932 bf->bf_state.bf_type |= BUF_XRETRY;
938 * cleanup in progress, just fail
939 * the un-acked sub-frames
945 * Remove ath_buf's of this sub-frame from aggregate queue.
947 if (bf_next == NULL) { /* last subframe in the aggregate */
948 ASSERT(bf->bf_lastfrm == bf_last);
951 * The last descriptor of the last sub frame could be
952 * a holding descriptor for h/w. If that's the case,
953 * bf->bf_lastfrm won't be in the bf_q.
954 * Make sure we handle bf_q properly here.
957 if (!list_empty(bf_q)) {
958 bf_lastq = list_entry(bf_q->prev,
959 struct ath_buf, list);
960 list_cut_position(&bf_head,
961 bf_q, &bf_lastq->list);
964 * XXX: if the last subframe only has one
965 * descriptor which is also being used as
966 * a holding descriptor. Then the ath_buf
967 * is not in the bf_q at all.
969 INIT_LIST_HEAD(&bf_head);
972 ASSERT(!list_empty(bf_q));
973 list_cut_position(&bf_head,
974 bf_q, &bf->bf_lastfrm->list);
979 * complete the acked-ones/xretried ones; update
982 spin_lock_bh(&txq->axq_lock);
983 ath_tx_update_baw(sc, tid, bf->bf_seqno);
984 spin_unlock_bh(&txq->axq_lock);
986 /* complete this sub-frame */
987 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
990 * retry the un-acked ones
993 * XXX: if the last descriptor is holding descriptor,
994 * in order to requeue the frame to software queue, we
995 * need to allocate a new descriptor and
996 * copy the content of holding descriptor to it.
998 if (bf->bf_next == NULL &&
999 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
1000 struct ath_buf *tbf;
1002 /* allocate new descriptor */
1003 spin_lock_bh(&sc->sc_txbuflock);
1004 ASSERT(!list_empty((&sc->sc_txbuf)));
1005 tbf = list_first_entry(&sc->sc_txbuf,
1006 struct ath_buf, list);
1007 list_del(&tbf->list);
1008 spin_unlock_bh(&sc->sc_txbuflock);
1010 ATH_TXBUF_RESET(tbf);
1012 /* copy descriptor content */
1013 tbf->bf_mpdu = bf_last->bf_mpdu;
1014 tbf->bf_buf_addr = bf_last->bf_buf_addr;
1015 *(tbf->bf_desc) = *(bf_last->bf_desc);
1017 /* link it to the frame */
1019 bf_lastq->bf_desc->ds_link =
1021 bf->bf_lastfrm = tbf;
1022 ath9k_hw_cleartxdesc(sc->sc_ah,
1023 bf->bf_lastfrm->bf_desc);
1025 tbf->bf_state = bf_last->bf_state;
1026 tbf->bf_lastfrm = tbf;
1027 ath9k_hw_cleartxdesc(sc->sc_ah,
1028 tbf->bf_lastfrm->bf_desc);
1030 /* copy the DMA context */
1031 tbf->bf_dmacontext =
1032 bf_last->bf_dmacontext;
1034 list_add_tail(&tbf->list, &bf_head);
1037 * Clear descriptor status words for
1040 ath9k_hw_cleartxdesc(sc->sc_ah,
1041 bf->bf_lastfrm->bf_desc);
1045 * Put this buffer to the temporary pending
1046 * queue to retain ordering
1048 list_splice_tail_init(&bf_head, &bf_pending);
1054 if (tid->cleanup_inprogress) {
1055 /* check to see if we're done with cleaning the h/w queue */
1056 spin_lock_bh(&txq->axq_lock);
1058 if (tid->baw_head == tid->baw_tail) {
1059 tid->addba_exchangecomplete = 0;
1060 tid->addba_exchangeattempts = 0;
1061 spin_unlock_bh(&txq->axq_lock);
1063 tid->cleanup_inprogress = false;
1065 /* send buffered frames as singles */
1066 ath_tx_flush_tid(sc, tid);
1068 spin_unlock_bh(&txq->axq_lock);
1074 * prepend un-acked frames to the beginning of the pending frame queue
1076 if (!list_empty(&bf_pending)) {
1077 spin_lock_bh(&txq->axq_lock);
1078 /* Note: we _prepend_, we _do_not_ at to
1079 * the end of the queue ! */
1080 list_splice(&bf_pending, &tid->buf_q);
1081 ath_tx_queue_tid(txq, tid);
1082 spin_unlock_bh(&txq->axq_lock);
1086 ath_reset(sc, false);
1091 /* Process completed xmit descriptors from the specified queue */
1093 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1095 struct ath_hal *ah = sc->sc_ah;
1096 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1097 struct list_head bf_head;
1098 struct ath_desc *ds, *tmp_ds;
1099 struct sk_buff *skb;
1100 struct ieee80211_tx_info *tx_info;
1101 struct ath_tx_info_priv *tx_info_priv;
1102 int nacked, txok, nbad = 0, isrifs = 0;
1105 DPRINTF(sc, ATH_DBG_QUEUE,
1106 "%s: tx queue %d (%x), link %p\n", __func__,
1107 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1112 spin_lock_bh(&txq->axq_lock);
1113 if (list_empty(&txq->axq_q)) {
1114 txq->axq_link = NULL;
1115 txq->axq_linkbuf = NULL;
1116 spin_unlock_bh(&txq->axq_lock);
1119 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1122 * There is a race condition that a BH gets scheduled
1123 * after sw writes TxE and before hw re-load the last
1124 * descriptor to get the newly chained one.
1125 * Software must keep the last DONE descriptor as a
1126 * holding descriptor - software does so by marking
1127 * it with the STALE flag.
1130 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1132 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1134 * The holding descriptor is the last
1135 * descriptor in queue. It's safe to remove
1136 * the last holding descriptor in BH context.
1138 spin_unlock_bh(&txq->axq_lock);
1141 /* Lets work with the next buffer now */
1142 bf = list_entry(bf_held->list.next,
1143 struct ath_buf, list);
1147 lastbf = bf->bf_lastbf;
1148 ds = lastbf->bf_desc; /* NB: last decriptor */
1150 status = ath9k_hw_txprocdesc(ah, ds);
1151 if (status == -EINPROGRESS) {
1152 spin_unlock_bh(&txq->axq_lock);
1155 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1156 txq->axq_lastdsWithCTS = NULL;
1157 if (ds == txq->axq_gatingds)
1158 txq->axq_gatingds = NULL;
1161 * Remove ath_buf's of the same transmit unit from txq,
1162 * however leave the last descriptor back as the holding
1163 * descriptor for hw.
1165 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1166 INIT_LIST_HEAD(&bf_head);
1168 if (!list_is_singular(&lastbf->list))
1169 list_cut_position(&bf_head,
1170 &txq->axq_q, lastbf->list.prev);
1175 txq->axq_aggr_depth--;
1177 txok = (ds->ds_txstat.ts_status == 0);
1179 spin_unlock_bh(&txq->axq_lock);
1182 list_del(&bf_held->list);
1183 spin_lock_bh(&sc->sc_txbuflock);
1184 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1185 spin_unlock_bh(&sc->sc_txbuflock);
1188 if (!bf_isampdu(bf)) {
1190 * This frame is sent out as a single frame.
1191 * Use hardware retry status for this frame.
1193 bf->bf_retries = ds->ds_txstat.ts_longretry;
1194 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1195 bf->bf_state.bf_type |= BUF_XRETRY;
1198 nbad = ath_tx_num_badfrms(sc, bf, txok);
1201 tx_info = IEEE80211_SKB_CB(skb);
1204 tx_info_priv = (struct ath_tx_info_priv *) tx_info->control.vif;
1205 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1206 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1207 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1208 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1209 if (ds->ds_txstat.ts_status == 0)
1212 if (bf_isdata(bf)) {
1214 tmp_ds = bf->bf_rifslast->bf_desc;
1217 memcpy(&tx_info_priv->tx,
1219 sizeof(tx_info_priv->tx));
1220 tx_info_priv->n_frames = bf->bf_nframes;
1221 tx_info_priv->n_bad_frames = nbad;
1226 * Complete this transmit unit
1229 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1231 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1233 /* Wake up mac80211 queue */
1235 spin_lock_bh(&txq->axq_lock);
1236 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1239 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1241 ieee80211_wake_queue(sc->hw, qnum);
1248 * schedule any pending packets if aggregation is enabled
1250 if (sc->sc_flags & SC_OP_TXAGGR)
1251 ath_txq_schedule(sc, txq);
1252 spin_unlock_bh(&txq->axq_lock);
1257 static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1259 struct ath_hal *ah = sc->sc_ah;
1261 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1262 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1263 __func__, txq->axq_qnum,
1264 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1267 /* Drain only the data queues */
1269 static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1271 struct ath_hal *ah = sc->sc_ah;
1275 /* XXX return value */
1276 if (!(sc->sc_flags & SC_OP_INVALID)) {
1277 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1278 if (ATH_TXQ_SETUP(sc, i)) {
1279 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1281 /* The TxDMA may not really be stopped.
1282 * Double check the hal tx pending count */
1283 npend += ath9k_hw_numtxpending(ah,
1284 sc->sc_txq[i].axq_qnum);
1292 /* TxDMA not stopped, reset the hal */
1293 DPRINTF(sc, ATH_DBG_XMIT,
1294 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1296 spin_lock_bh(&sc->sc_resetlock);
1297 if (!ath9k_hw_reset(ah,
1298 sc->sc_ah->ah_curchan,
1299 sc->sc_ht_info.tx_chan_width,
1300 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1301 sc->sc_ht_extprotspacing, true, &status)) {
1303 DPRINTF(sc, ATH_DBG_FATAL,
1304 "%s: unable to reset hardware; hal status %u\n",
1308 spin_unlock_bh(&sc->sc_resetlock);
1311 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1312 if (ATH_TXQ_SETUP(sc, i))
1313 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1317 /* Add a sub-frame to block ack window */
1319 static void ath_tx_addto_baw(struct ath_softc *sc,
1320 struct ath_atx_tid *tid,
1325 if (bf_isretried(bf))
1328 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1329 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1331 ASSERT(tid->tx_buf[cindex] == NULL);
1332 tid->tx_buf[cindex] = bf;
1334 if (index >= ((tid->baw_tail - tid->baw_head) &
1335 (ATH_TID_MAX_BUFS - 1))) {
1336 tid->baw_tail = cindex;
1337 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1342 * Function to send an A-MPDU
1343 * NB: must be called with txq lock held
1346 static int ath_tx_send_ampdu(struct ath_softc *sc,
1347 struct ath_atx_tid *tid,
1348 struct list_head *bf_head,
1349 struct ath_tx_control *txctl)
1352 struct sk_buff *skb;
1353 struct ieee80211_tx_info *tx_info;
1354 struct ath_tx_info_priv *tx_info_priv;
1356 BUG_ON(list_empty(bf_head));
1358 bf = list_first_entry(bf_head, struct ath_buf, list);
1359 bf->bf_state.bf_type |= BUF_AMPDU;
1362 * Do not queue to h/w when any of the following conditions is true:
1363 * - there are pending frames in software queue
1364 * - the TID is currently paused for ADDBA/BAR request
1365 * - seqno is not within block-ack window
1366 * - h/w queue depth exceeds low water mark
1368 if (!list_empty(&tid->buf_q) || tid->paused ||
1369 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1370 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1372 * Add this frame to software queue for scheduling later
1375 list_splice_tail_init(bf_head, &tid->buf_q);
1376 ath_tx_queue_tid(txctl->txq, tid);
1380 skb = (struct sk_buff *)bf->bf_mpdu;
1381 tx_info = IEEE80211_SKB_CB(skb);
1383 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
1384 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1386 /* Add sub-frame to BAW */
1387 ath_tx_addto_baw(sc, tid, bf);
1389 /* Queue to h/w without aggregation */
1391 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1392 ath_buf_set_rate(sc, bf);
1393 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1399 * returns aggr limit based on lowest of the rates
1402 static u32 ath_lookup_rate(struct ath_softc *sc,
1404 struct ath_atx_tid *tid)
1406 const struct ath9k_rate_table *rt = sc->sc_currates;
1407 struct sk_buff *skb;
1408 struct ieee80211_tx_info *tx_info;
1409 struct ath_tx_info_priv *tx_info_priv;
1410 u32 max_4ms_framelen, frame_length;
1411 u16 aggr_limit, legacy = 0, maxampdu;
1415 skb = (struct sk_buff *)bf->bf_mpdu;
1416 tx_info = IEEE80211_SKB_CB(skb);
1417 tx_info_priv = (struct ath_tx_info_priv *)
1418 tx_info->control.vif; /* XXX: HACK! */
1420 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1423 * Find the lowest frame length among the rate series that will have a
1424 * 4ms transmit duration.
1425 * TODO - TXOP limit needs to be considered.
1427 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1429 for (i = 0; i < 4; i++) {
1430 if (bf->bf_rcs[i].tries) {
1431 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1433 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1438 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1443 * limit aggregate size by the minimum rate if rate selected is
1444 * not a probe rate, if rate selected is a probe rate then
1445 * avoid aggregation of this packet.
1447 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1450 aggr_limit = min(max_4ms_framelen,
1451 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1454 * h/w can accept aggregates upto 16 bit lengths (65535).
1455 * The IE, however can hold upto 65536, which shows up here
1456 * as zero. Ignore 65536 since we are constrained by hw.
1458 maxampdu = tid->an->maxampdu;
1460 aggr_limit = min(aggr_limit, maxampdu);
1466 * returns the number of delimiters to be added to
1467 * meet the minimum required mpdudensity.
1468 * caller should make sure that the rate is HT rate .
1471 static int ath_compute_num_delims(struct ath_softc *sc,
1472 struct ath_atx_tid *tid,
1476 const struct ath9k_rate_table *rt = sc->sc_currates;
1477 u32 nsymbits, nsymbols, mpdudensity;
1480 int width, half_gi, ndelim, mindelim;
1482 /* Select standard number of delimiters based on frame length alone */
1483 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1486 * If encryption enabled, hardware requires some more padding between
1488 * TODO - this could be improved to be dependent on the rate.
1489 * The hardware can keep up at lower rates, but not higher rates
1491 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1492 ndelim += ATH_AGGR_ENCRYPTDELIM;
1495 * Convert desired mpdu density from microeconds to bytes based
1496 * on highest rate in rate series (i.e. first rate) to determine
1497 * required minimum length for subframe. Take into account
1498 * whether high rate is 20 or 40Mhz and half or full GI.
1500 mpdudensity = tid->an->mpdudensity;
1503 * If there is no mpdu density restriction, no further calculation
1506 if (mpdudensity == 0)
1509 rix = bf->bf_rcs[0].rix;
1510 flags = bf->bf_rcs[0].flags;
1511 rc = rt->info[rix].rateCode;
1512 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1513 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1516 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1518 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1523 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1524 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1526 /* Is frame shorter than required minimum length? */
1527 if (frmlen < minlen) {
1528 /* Get the minimum number of delimiters required. */
1529 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1530 ndelim = max(mindelim, ndelim);
1537 * For aggregation from software buffer queue.
1538 * NB: must be called with txq lock held
1541 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1542 struct ath_atx_tid *tid,
1543 struct list_head *bf_q,
1544 struct ath_buf **bf_last,
1545 struct aggr_rifs_param *param,
1548 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1549 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1550 struct list_head bf_head;
1551 int rl = 0, nframes = 0, ndelim;
1552 u16 aggr_limit = 0, al = 0, bpad = 0,
1553 al_delta, h_baw = tid->baw_size / 2;
1554 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1555 int prev_al = 0, is_ds_rate = 0;
1556 INIT_LIST_HEAD(&bf_head);
1558 BUG_ON(list_empty(&tid->buf_q));
1560 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1563 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1566 * do not step over block-ack window
1568 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1569 status = ATH_AGGR_BAW_CLOSED;
1574 aggr_limit = ath_lookup_rate(sc, bf, tid);
1577 * Is rate dual stream
1580 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1584 * do not exceed aggregation limit
1586 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1588 if (nframes && (aggr_limit <
1589 (al + bpad + al_delta + prev_al))) {
1590 status = ATH_AGGR_LIMITED;
1595 * do not exceed subframe limit
1597 if ((nframes + *prev_frames) >=
1598 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1599 status = ATH_AGGR_LIMITED;
1604 * add padding for previous frame to aggregation length
1606 al += bpad + al_delta;
1609 * Get the delimiters needed to meet the MPDU
1610 * density for this node.
1612 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
1614 bpad = PADBYTES(al_delta) + (ndelim << 2);
1617 bf->bf_lastfrm->bf_desc->ds_link = 0;
1620 * this packet is part of an aggregate
1621 * - remove all descriptors belonging to this frame from
1623 * - add it to block ack window
1624 * - set up descriptors for aggregation
1626 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1627 ath_tx_addto_baw(sc, tid, bf);
1629 list_for_each_entry(tbf, &bf_head, list) {
1630 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1631 tbf->bf_desc, ndelim);
1635 * link buffers of this frame to the aggregate
1637 list_splice_tail_init(&bf_head, bf_q);
1641 bf_prev->bf_next = bf;
1642 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1648 * terminate aggregation on a small packet boundary
1650 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1651 status = ATH_AGGR_SHORTPKT;
1655 } while (!list_empty(&tid->buf_q));
1657 bf_first->bf_al = al;
1658 bf_first->bf_nframes = nframes;
1665 * process pending frames possibly doing a-mpdu aggregation
1666 * NB: must be called with txq lock held
1669 static void ath_tx_sched_aggr(struct ath_softc *sc,
1670 struct ath_txq *txq, struct ath_atx_tid *tid)
1672 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1673 enum ATH_AGGR_STATUS status;
1674 struct list_head bf_q;
1675 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1676 int prev_frames = 0;
1679 if (list_empty(&tid->buf_q))
1682 INIT_LIST_HEAD(&bf_q);
1684 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, ¶m,
1688 * no frames picked up to be aggregated; block-ack
1689 * window is not open
1691 if (list_empty(&bf_q))
1694 bf = list_first_entry(&bf_q, struct ath_buf, list);
1695 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1696 bf->bf_lastbf = bf_last;
1699 * if only one frame, send as non-aggregate
1701 if (bf->bf_nframes == 1) {
1702 ASSERT(bf->bf_lastfrm == bf_last);
1704 bf->bf_state.bf_type &= ~BUF_AGGR;
1706 * clear aggr bits for every descriptor
1707 * XXX TODO: is there a way to optimize it?
1709 list_for_each_entry(tbf, &bf_q, list) {
1710 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1713 ath_buf_set_rate(sc, bf);
1714 ath_tx_txqaddbuf(sc, txq, &bf_q);
1719 * setup first desc with rate and aggr info
1721 bf->bf_state.bf_type |= BUF_AGGR;
1722 ath_buf_set_rate(sc, bf);
1723 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1726 * anchor last frame of aggregate correctly
1728 ASSERT(bf_lastaggr);
1729 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1731 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1733 /* XXX: We don't enter into this loop, consider removing this */
1734 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1735 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1736 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1739 txq->axq_aggr_depth++;
1742 * Normal aggregate, queue to hardware
1744 ath_tx_txqaddbuf(sc, txq, &bf_q);
1746 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1747 status != ATH_AGGR_BAW_CLOSED);
1750 /* Called with txq lock held */
1752 static void ath_tid_drain(struct ath_softc *sc,
1753 struct ath_txq *txq,
1754 struct ath_atx_tid *tid)
1758 struct list_head bf_head;
1759 INIT_LIST_HEAD(&bf_head);
1762 if (list_empty(&tid->buf_q))
1764 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1766 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1768 /* update baw for software retried frame */
1769 if (bf_isretried(bf))
1770 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1773 * do not indicate packets while holding txq spinlock.
1774 * unlock is intentional here
1776 spin_unlock(&txq->axq_lock);
1778 /* complete this sub-frame */
1779 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1781 spin_lock(&txq->axq_lock);
1785 * TODO: For frame(s) that are in the retry state, we will reuse the
1786 * sequence number(s) without setting the retry bit. The
1787 * alternative is to give up on these and BAR the receiver's window
1790 tid->seq_next = tid->seq_start;
1791 tid->baw_tail = tid->baw_head;
1795 * Drain all pending buffers
1796 * NB: must be called with txq lock held
1799 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1800 struct ath_txq *txq)
1802 struct ath_atx_ac *ac, *ac_tmp;
1803 struct ath_atx_tid *tid, *tid_tmp;
1805 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1806 list_del(&ac->list);
1808 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1809 list_del(&tid->list);
1811 ath_tid_drain(sc, txq, tid);
1816 static void ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
1817 struct sk_buff *skb, struct scatterlist *sg,
1818 struct ath_tx_control *txctl)
1820 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1821 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1822 struct ath_tx_info_priv *tx_info_priv;
1823 struct ath_rc_series *rcs;
1827 tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
1828 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1829 fc = hdr->frame_control;
1830 rcs = tx_info_priv->rcs;
1832 ATH_TXBUF_RESET(bf);
1836 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1838 ieee80211_is_data(fc) ?
1839 (bf->bf_state.bf_type |= BUF_DATA) :
1840 (bf->bf_state.bf_type &= ~BUF_DATA);
1841 ieee80211_is_back_req(fc) ?
1842 (bf->bf_state.bf_type |= BUF_BAR) :
1843 (bf->bf_state.bf_type &= ~BUF_BAR);
1844 ieee80211_is_pspoll(fc) ?
1845 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1846 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
1847 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
1848 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1849 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1850 (sc->hw->conf.ht.enabled &&
1851 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ?
1852 (bf->bf_state.bf_type |= BUF_HT) :
1853 (bf->bf_state.bf_type &= ~BUF_HT);
1855 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1859 bf->bf_keytype = get_hw_crypto_keytype(skb);
1861 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1862 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1863 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1865 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1870 setup_rate_retries(sc, skb);
1872 bf->bf_rcs[0] = rcs[0];
1873 bf->bf_rcs[1] = rcs[1];
1874 bf->bf_rcs[2] = rcs[2];
1875 bf->bf_rcs[3] = rcs[3];
1877 /* Assign seqno, tidno */
1879 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR))
1880 assign_aggr_tid_seqno(skb, bf);
1885 bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data,
1886 skb->len, PCI_DMA_TODEVICE);
1887 bf->bf_buf_addr = bf->bf_dmacontext;
1890 /* FIXME: tx power */
1891 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1892 struct scatterlist *sg, u32 n_sg,
1893 struct ath_tx_control *txctl)
1895 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1896 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1897 struct ath_node *an = NULL;
1898 struct list_head bf_head;
1899 struct ath_desc *ds;
1900 struct ath_atx_tid *tid;
1901 struct ath_hal *ah = sc->sc_ah;
1904 if (tx_info->control.sta) {
1905 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1906 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1909 frm_type = get_hw_packet_type(skb);
1911 INIT_LIST_HEAD(&bf_head);
1912 list_add_tail(&bf->list, &bf_head);
1914 /* setup descriptor */
1918 ds->ds_data = bf->bf_buf_addr;
1920 /* Formulate first tx descriptor with tx controls */
1922 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1923 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1925 ath9k_hw_filltxdesc(ah, ds,
1926 sg_dma_len(sg), /* segment length */
1927 true, /* first segment */
1928 (n_sg == 1) ? true : false, /* last segment */
1929 ds); /* first descriptor */
1931 bf->bf_lastfrm = bf;
1933 spin_lock_bh(&txctl->txq->axq_lock);
1935 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1936 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1938 * Try aggregation if it's a unicast data frame
1939 * and the destination is HT capable.
1941 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1944 * Send this frame as regular when ADDBA
1945 * exchange is neither complete nor pending.
1947 ath_tx_send_normal(sc, txctl->txq,
1954 ath_buf_set_rate(sc, bf);
1955 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1958 spin_unlock_bh(&txctl->txq->axq_lock);
1961 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1962 struct ath_tx_control *txctl)
1965 struct scatterlist sg;
1967 /* Check if a tx buffer is available */
1969 bf = ath_tx_get_buffer(sc);
1971 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX buffers are full\n",
1976 ath_tx_setup_buffer(sc, bf, skb, &sg, txctl);
1980 memset(&sg, 0, sizeof(struct scatterlist));
1981 sg_dma_address(&sg) = bf->bf_dmacontext;
1982 sg_dma_len(&sg) = skb->len;
1984 ath_tx_start_dma(sc, bf, &sg, 1, txctl);
1989 /* Initialize TX queue and h/w */
1991 int ath_tx_init(struct ath_softc *sc, int nbufs)
1996 spin_lock_init(&sc->sc_txbuflock);
1998 /* Setup tx descriptors */
1999 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2002 DPRINTF(sc, ATH_DBG_FATAL,
2003 "%s: failed to allocate tx descriptors: %d\n",
2008 /* XXX allocate beacon state together with vap */
2009 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2010 "beacon", ATH_BCBUF, 1);
2012 DPRINTF(sc, ATH_DBG_FATAL,
2013 "%s: failed to allocate "
2014 "beacon descripotrs: %d\n",
2027 /* Reclaim all tx queue resources */
2029 int ath_tx_cleanup(struct ath_softc *sc)
2031 /* cleanup beacon descriptors */
2032 if (sc->sc_bdma.dd_desc_len != 0)
2033 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2035 /* cleanup tx descriptors */
2036 if (sc->sc_txdma.dd_desc_len != 0)
2037 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2042 /* Setup a h/w transmit queue */
2044 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2046 struct ath_hal *ah = sc->sc_ah;
2047 struct ath9k_tx_queue_info qi;
2050 memset(&qi, 0, sizeof(qi));
2051 qi.tqi_subtype = subtype;
2052 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
2053 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
2054 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
2055 qi.tqi_physCompBuf = 0;
2058 * Enable interrupts only for EOL and DESC conditions.
2059 * We mark tx descriptors to receive a DESC interrupt
2060 * when a tx queue gets deep; otherwise waiting for the
2061 * EOL to reap descriptors. Note that this is done to
2062 * reduce interrupt load and this only defers reaping
2063 * descriptors, never transmitting frames. Aside from
2064 * reducing interrupts this also permits more concurrency.
2065 * The only potential downside is if the tx queue backs
2066 * up in which case the top half of the kernel may backup
2067 * due to a lack of tx descriptors.
2069 * The UAPSD queue is an exception, since we take a desc-
2070 * based intr on the EOSP frames.
2072 if (qtype == ATH9K_TX_QUEUE_UAPSD)
2073 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2075 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2076 TXQ_FLAG_TXDESCINT_ENABLE;
2077 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2080 * NB: don't print a message, this happens
2081 * normally on parts with too few tx queues
2085 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2086 DPRINTF(sc, ATH_DBG_FATAL,
2087 "%s: hal qnum %u out of range, max %u!\n",
2088 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2089 ath9k_hw_releasetxqueue(ah, qnum);
2092 if (!ATH_TXQ_SETUP(sc, qnum)) {
2093 struct ath_txq *txq = &sc->sc_txq[qnum];
2095 txq->axq_qnum = qnum;
2096 txq->axq_link = NULL;
2097 INIT_LIST_HEAD(&txq->axq_q);
2098 INIT_LIST_HEAD(&txq->axq_acq);
2099 spin_lock_init(&txq->axq_lock);
2101 txq->axq_aggr_depth = 0;
2102 txq->axq_totalqueued = 0;
2103 txq->axq_linkbuf = NULL;
2104 sc->sc_txqsetup |= 1<<qnum;
2106 return &sc->sc_txq[qnum];
2109 /* Reclaim resources for a setup queue */
2111 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2113 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2114 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2118 * Setup a hardware data transmit queue for the specified
2119 * access control. The hal may not support all requested
2120 * queues in which case it will return a reference to a
2121 * previously setup queue. We record the mapping from ac's
2122 * to h/w queues for use by ath_tx_start and also track
2123 * the set of h/w queues being used to optimize work in the
2124 * transmit interrupt handler and related routines.
2127 int ath_tx_setup(struct ath_softc *sc, int haltype)
2129 struct ath_txq *txq;
2131 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2132 DPRINTF(sc, ATH_DBG_FATAL,
2133 "%s: HAL AC %u out of range, max %zu!\n",
2134 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2137 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
2139 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2145 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2150 case ATH9K_TX_QUEUE_DATA:
2151 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2152 DPRINTF(sc, ATH_DBG_FATAL,
2153 "%s: HAL AC %u out of range, max %zu!\n",
2155 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2158 qnum = sc->sc_haltype2q[haltype];
2160 case ATH9K_TX_QUEUE_BEACON:
2161 qnum = sc->sc_bhalq;
2163 case ATH9K_TX_QUEUE_CAB:
2164 qnum = sc->sc_cabq->axq_qnum;
2172 /* Get a transmit queue, if available */
2174 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
2176 struct ath_txq *txq = NULL;
2179 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
2180 txq = &sc->sc_txq[qnum];
2182 spin_lock_bh(&txq->axq_lock);
2184 /* Try to avoid running out of descriptors */
2185 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
2186 DPRINTF(sc, ATH_DBG_FATAL,
2187 "%s: TX queue: %d is full, depth: %d\n",
2188 __func__, qnum, txq->axq_depth);
2189 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
2191 spin_unlock_bh(&txq->axq_lock);
2195 spin_unlock_bh(&txq->axq_lock);
2200 /* Update parameters for a transmit queue */
2202 int ath_txq_update(struct ath_softc *sc, int qnum,
2203 struct ath9k_tx_queue_info *qinfo)
2205 struct ath_hal *ah = sc->sc_ah;
2207 struct ath9k_tx_queue_info qi;
2209 if (qnum == sc->sc_bhalq) {
2211 * XXX: for beacon queue, we just save the parameter.
2212 * It will be picked up by ath_beaconq_config when
2215 sc->sc_beacon_qi = *qinfo;
2219 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2221 ath9k_hw_get_txq_props(ah, qnum, &qi);
2222 qi.tqi_aifs = qinfo->tqi_aifs;
2223 qi.tqi_cwmin = qinfo->tqi_cwmin;
2224 qi.tqi_cwmax = qinfo->tqi_cwmax;
2225 qi.tqi_burstTime = qinfo->tqi_burstTime;
2226 qi.tqi_readyTime = qinfo->tqi_readyTime;
2228 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2229 DPRINTF(sc, ATH_DBG_FATAL,
2230 "%s: unable to update hardware queue %u!\n",
2234 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2240 int ath_cabq_update(struct ath_softc *sc)
2242 struct ath9k_tx_queue_info qi;
2243 int qnum = sc->sc_cabq->axq_qnum;
2244 struct ath_beacon_config conf;
2246 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
2248 * Ensure the readytime % is within the bounds.
2250 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2251 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2252 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2253 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2255 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2257 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2258 ath_txq_update(sc, qnum, &qi);
2263 /* Deferred processing of transmit interrupt */
2265 void ath_tx_tasklet(struct ath_softc *sc)
2268 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2270 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2273 * Process each active queue.
2275 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2276 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2277 ath_tx_processq(sc, &sc->sc_txq[i]);
2281 void ath_tx_draintxq(struct ath_softc *sc,
2282 struct ath_txq *txq, bool retry_tx)
2284 struct ath_buf *bf, *lastbf;
2285 struct list_head bf_head;
2287 INIT_LIST_HEAD(&bf_head);
2290 * NB: this assumes output has been stopped and
2291 * we do not need to block ath_tx_tasklet
2294 spin_lock_bh(&txq->axq_lock);
2296 if (list_empty(&txq->axq_q)) {
2297 txq->axq_link = NULL;
2298 txq->axq_linkbuf = NULL;
2299 spin_unlock_bh(&txq->axq_lock);
2303 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2305 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2306 list_del(&bf->list);
2307 spin_unlock_bh(&txq->axq_lock);
2309 spin_lock_bh(&sc->sc_txbuflock);
2310 list_add_tail(&bf->list, &sc->sc_txbuf);
2311 spin_unlock_bh(&sc->sc_txbuflock);
2315 lastbf = bf->bf_lastbf;
2317 lastbf->bf_desc->ds_txstat.ts_flags =
2318 ATH9K_TX_SW_ABORTED;
2320 /* remove ath_buf's of the same mpdu from txq */
2321 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2324 spin_unlock_bh(&txq->axq_lock);
2327 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2329 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2332 /* flush any pending frames if aggregation is enabled */
2333 if (sc->sc_flags & SC_OP_TXAGGR) {
2335 spin_lock_bh(&txq->axq_lock);
2336 ath_txq_drain_pending_buffers(sc, txq);
2337 spin_unlock_bh(&txq->axq_lock);
2342 /* Drain the transmit queues and reclaim resources */
2344 void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2346 /* stop beacon queue. The beacon will be freed when
2347 * we go to INIT state */
2348 if (!(sc->sc_flags & SC_OP_INVALID)) {
2349 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2350 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2351 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2354 ath_drain_txdataq(sc, retry_tx);
2357 u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2359 return sc->sc_txq[qnum].axq_depth;
2362 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2364 return sc->sc_txq[qnum].axq_aggr_depth;
2367 /* Check if an ADDBA is required. A valid node must be passed. */
2368 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
2369 struct ath_node *an,
2372 struct ath_atx_tid *txtid;
2374 if (!(sc->sc_flags & SC_OP_TXAGGR))
2375 return AGGR_NOT_REQUIRED;
2377 /* ADDBA exchange must be completed before sending aggregates */
2378 txtid = ATH_AN_2_TID(an, tidno);
2380 if (txtid->addba_exchangecomplete)
2381 return AGGR_EXCHANGE_DONE;
2383 if (txtid->cleanup_inprogress)
2384 return AGGR_CLEANUP_PROGRESS;
2386 if (txtid->addba_exchangeinprogress)
2387 return AGGR_EXCHANGE_PROGRESS;
2389 if (!txtid->addba_exchangecomplete) {
2390 if (!txtid->addba_exchangeinprogress &&
2391 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2392 txtid->addba_exchangeattempts++;
2393 return AGGR_REQUIRED;
2397 return AGGR_NOT_REQUIRED;
2400 /* Start TX aggregation */
2402 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
2405 struct ath_atx_tid *txtid;
2406 struct ath_node *an;
2408 an = (struct ath_node *)sta->drv_priv;
2410 if (sc->sc_flags & SC_OP_TXAGGR) {
2411 txtid = ATH_AN_2_TID(an, tid);
2412 txtid->addba_exchangeinprogress = 1;
2413 ath_tx_pause_tid(sc, txtid);
2419 /* Stop tx aggregation */
2421 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2423 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2425 ath_tx_aggr_teardown(sc, an, tid);
2430 * Performs transmit side cleanup when TID changes from aggregated to
2432 * - Pause the TID and mark cleanup in progress
2433 * - Discard all retry frames from the s/w queue.
2436 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
2438 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2439 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2441 struct list_head bf_head;
2442 INIT_LIST_HEAD(&bf_head);
2444 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2446 if (txtid->cleanup_inprogress) /* cleanup is in progress */
2449 if (!txtid->addba_exchangecomplete) {
2450 txtid->addba_exchangeattempts = 0;
2454 /* TID must be paused first */
2455 ath_tx_pause_tid(sc, txtid);
2457 /* drop all software retried frames and mark this TID */
2458 spin_lock_bh(&txq->axq_lock);
2459 while (!list_empty(&txtid->buf_q)) {
2460 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2461 if (!bf_isretried(bf)) {
2463 * NB: it's based on the assumption that
2464 * software retried frame will always stay
2465 * at the head of software queue.
2469 list_cut_position(&bf_head,
2470 &txtid->buf_q, &bf->bf_lastfrm->list);
2471 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2473 /* complete this sub-frame */
2474 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2477 if (txtid->baw_head != txtid->baw_tail) {
2478 spin_unlock_bh(&txq->axq_lock);
2479 txtid->cleanup_inprogress = true;
2481 txtid->addba_exchangecomplete = 0;
2482 txtid->addba_exchangeattempts = 0;
2483 spin_unlock_bh(&txq->axq_lock);
2484 ath_tx_flush_tid(sc, txtid);
2489 * Tx scheduling logic
2490 * NB: must be called with txq lock held
2493 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2495 struct ath_atx_ac *ac;
2496 struct ath_atx_tid *tid;
2498 /* nothing to schedule */
2499 if (list_empty(&txq->axq_acq))
2502 * get the first node/ac pair on the queue
2504 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2505 list_del(&ac->list);
2509 * process a single tid per destination
2512 /* nothing to schedule */
2513 if (list_empty(&ac->tid_q))
2516 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2517 list_del(&tid->list);
2520 if (tid->paused) /* check next tid to keep h/w busy */
2523 if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) ||
2524 ((txq->axq_depth % 2) == 0)) {
2525 ath_tx_sched_aggr(sc, txq, tid);
2529 * add tid to round-robin queue if more frames
2530 * are pending for the tid
2532 if (!list_empty(&tid->buf_q))
2533 ath_tx_queue_tid(txq, tid);
2535 /* only schedule one TID at a time */
2537 } while (!list_empty(&ac->tid_q));
2540 * schedule AC if more TIDs need processing
2542 if (!list_empty(&ac->tid_q)) {
2544 * add dest ac to txq if not already added
2548 list_add_tail(&ac->list, &txq->axq_acq);
2553 /* Initialize per-node transmit state */
2555 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2557 struct ath_atx_tid *tid;
2558 struct ath_atx_ac *ac;
2562 * Init per tid tx state
2564 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2565 tidno < WME_NUM_TID;
2569 tid->seq_start = tid->seq_next = 0;
2570 tid->baw_size = WME_MAX_BA;
2571 tid->baw_head = tid->baw_tail = 0;
2573 tid->paused = false;
2574 tid->cleanup_inprogress = false;
2575 INIT_LIST_HEAD(&tid->buf_q);
2577 acno = TID_TO_WME_AC(tidno);
2578 tid->ac = &an->an_aggr.tx.ac[acno];
2581 tid->addba_exchangecomplete = 0;
2582 tid->addba_exchangeinprogress = 0;
2583 tid->addba_exchangeattempts = 0;
2587 * Init per ac tx state
2589 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2590 acno < WME_NUM_AC; acno++, ac++) {
2592 INIT_LIST_HEAD(&ac->tid_q);
2596 ac->qnum = ath_tx_get_qnum(sc,
2597 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2600 ac->qnum = ath_tx_get_qnum(sc,
2601 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2604 ac->qnum = ath_tx_get_qnum(sc,
2605 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2608 ac->qnum = ath_tx_get_qnum(sc,
2609 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2615 /* Cleanupthe pending buffers for the node. */
2617 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2620 struct ath_atx_ac *ac, *ac_tmp;
2621 struct ath_atx_tid *tid, *tid_tmp;
2622 struct ath_txq *txq;
2623 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2624 if (ATH_TXQ_SETUP(sc, i)) {
2625 txq = &sc->sc_txq[i];
2627 spin_lock(&txq->axq_lock);
2629 list_for_each_entry_safe(ac,
2630 ac_tmp, &txq->axq_acq, list) {
2631 tid = list_first_entry(&ac->tid_q,
2632 struct ath_atx_tid, list);
2633 if (tid && tid->an != an)
2635 list_del(&ac->list);
2638 list_for_each_entry_safe(tid,
2639 tid_tmp, &ac->tid_q, list) {
2640 list_del(&tid->list);
2642 ath_tid_drain(sc, txq, tid);
2643 tid->addba_exchangecomplete = 0;
2644 tid->addba_exchangeattempts = 0;
2645 tid->cleanup_inprogress = false;
2649 spin_unlock(&txq->axq_lock);
2654 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2656 int hdrlen, padsize;
2657 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2658 struct ath_tx_control txctl;
2660 memset(&txctl, 0, sizeof(struct ath_tx_control));
2663 * As a temporary workaround, assign seq# here; this will likely need
2664 * to be cleaned up to work better with Beacon transmission and virtual
2667 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2668 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2669 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2671 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2672 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2675 /* Add the padding after the header if this is not already done */
2676 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2678 padsize = hdrlen % 4;
2679 if (skb_headroom(skb) < padsize) {
2680 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding "
2681 "failed\n", __func__);
2682 dev_kfree_skb_any(skb);
2685 skb_push(skb, padsize);
2686 memmove(skb->data, skb->data + padsize, hdrlen);
2689 txctl.txq = sc->sc_cabq;
2691 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
2695 if (ath_tx_start(sc, skb, &txctl) != 0) {
2696 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
2702 dev_kfree_skb_any(skb);