git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/advansys.c

   1 #define DRV_NAME "advansys"
   2 #define ASC_VERSION "3.4"       /* AdvanSys Driver Version */
   3
   4 /*
   5  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   6  *
   7  * Copyright (c) 1995-2000 Advanced System Products, Inc.
   8  * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
   9  * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  10  * All Rights Reserved.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  */
  17
  18 /*
  19  * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  20  * changed its name to ConnectCom Solutions, Inc.
  21  * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/ioport.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/mm.h>
  33 #include <linux/proc_fs.h>
  34 #include <linux/init.h>
  35 #include <linux/blkdev.h>
  36 #include <linux/isa.h>
  37 #include <linux/eisa.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/system.h>
  44 #include <asm/dma.h>
  45
  46 #include <scsi/scsi_cmnd.h>
  47 #include <scsi/scsi_device.h>
  48 #include <scsi/scsi_tcq.h>
  49 #include <scsi/scsi.h>
  50 #include <scsi/scsi_host.h>
  51
  52 /* FIXME:
  53  *
  54  *  1. Although all of the necessary command mapping places have the
  55  *     appropriate dma_map.. APIs, the driver still processes its internal
  56  *     queue using bus_to_virt() and virt_to_bus() which are illegal under
  57  *     the API.  The entire queue processing structure will need to be
  58  *     altered to fix this.
  59  *  2. Need to add memory mapping workaround. Test the memory mapping.
  60  *     If it doesn't work revert to I/O port access. Can a test be done
  61  *     safely?
  62  *  3. Handle an interrupt not working. Keep an interrupt counter in
  63  *     the interrupt handler. In the timeout function if the interrupt
  64  *     has not occurred then print a message and run in polled mode.
  65  *  4. Need to add support for target mode commands, cf. CAM XPT.
  66  *  5. check DMA mapping functions for failure
  67  *  6. Use scsi_transport_spi
  68  *  7. advansys_info is not safe against multiple simultaneous callers
  69  *  8. Add module_param to override ISA/VLB ioport array
  70  */
  71 #warning this driver is still not properly converted to the DMA API
  72
  73 /* Enable driver /proc statistics. */
  74 #define ADVANSYS_STATS
  75
  76 /* Enable driver tracing. */
  77 #undef ADVANSYS_DEBUG
  78
  79 /*
  80  * Portable Data Types
  81  *
  82  * Any instance where a 32-bit long or pointer type is assumed
  83  * for precision or HW defined structures, the following define
  84  * types must be used. In Linux the char, short, and int types
  85  * are all consistent at 8, 16, and 32 bits respectively. Pointers
  86  * and long types are 64 bits on Alpha and UltraSPARC.
  87  */
  88 #define ASC_PADDR __u32         /* Physical/Bus address data type. */
  89 #define ASC_VADDR __u32         /* Virtual address data type. */
  90 #define ASC_DCNT  __u32         /* Unsigned Data count type. */
  91 #define ASC_SDCNT __s32         /* Signed Data count type. */
  92
  93 /*
  94  * These macros are used to convert a virtual address to a
  95  * 32-bit value. This currently can be used on Linux Alpha
  96  * which uses 64-bit virtual address but a 32-bit bus address.
  97  * This is likely to break in the future, but doing this now
  98  * will give us time to change the HW and FW to handle 64-bit
  99  * addresses.
 100  */
 101 #define ASC_VADDR_TO_U32   virt_to_bus
 102 #define ASC_U32_TO_VADDR   bus_to_virt
 103
 104 typedef unsigned char uchar;
 105
 106 #ifndef TRUE
 107 #define TRUE     (1)
 108 #endif
 109 #ifndef FALSE
 110 #define FALSE    (0)
 111 #endif
 112
 113 #define ERR      (-1)
 114 #define UW_ERR   (uint)(0xFFFF)
 115 #define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
 116
 117 #define PCI_VENDOR_ID_ASP               0x10cd
 118 #define PCI_DEVICE_ID_ASP_1200A         0x1100
 119 #define PCI_DEVICE_ID_ASP_ABP940        0x1200
 120 #define PCI_DEVICE_ID_ASP_ABP940U       0x1300
 121 #define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
 122 #define PCI_DEVICE_ID_38C0800_REV1      0x2500
 123 #define PCI_DEVICE_ID_38C1600_REV1      0x2700
 124
 125 /*
 126  * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
 127  * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
 128  * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
 129  * SRB structure.
 130  */
 131 #define CC_VERY_LONG_SG_LIST 0
 132 #define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
 133
 134 #define PortAddr                 unsigned short /* port address size  */
 135 #define inp(port)                inb(port)
 136 #define outp(port, byte)         outb((byte), (port))
 137
 138 #define inpw(port)               inw(port)
 139 #define outpw(port, word)        outw((word), (port))
 140
 141 #define ASC_MAX_SG_QUEUE    7
 142 #define ASC_MAX_SG_LIST     255
 143
 144 #define ASC_CS_TYPE  unsigned short
 145
 146 #define ASC_IS_ISA          (0x0001)
 147 #define ASC_IS_ISAPNP       (0x0081)
 148 #define ASC_IS_EISA         (0x0002)
 149 #define ASC_IS_PCI          (0x0004)
 150 #define ASC_IS_PCI_ULTRA    (0x0104)
 151 #define ASC_IS_PCMCIA       (0x0008)
 152 #define ASC_IS_MCA          (0x0020)
 153 #define ASC_IS_VL           (0x0040)
 154 #define ASC_IS_WIDESCSI_16  (0x0100)
 155 #define ASC_IS_WIDESCSI_32  (0x0200)
 156 #define ASC_IS_BIG_ENDIAN   (0x8000)
 157
 158 #define ASC_CHIP_MIN_VER_VL      (0x01)
 159 #define ASC_CHIP_MAX_VER_VL      (0x07)
 160 #define ASC_CHIP_MIN_VER_PCI     (0x09)
 161 #define ASC_CHIP_MAX_VER_PCI     (0x0F)
 162 #define ASC_CHIP_VER_PCI_BIT     (0x08)
 163 #define ASC_CHIP_MIN_VER_ISA     (0x11)
 164 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
 165 #define ASC_CHIP_MAX_VER_ISA     (0x27)
 166 #define ASC_CHIP_VER_ISA_BIT     (0x30)
 167 #define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
 168 #define ASC_CHIP_VER_ASYN_BUG    (0x21)
 169 #define ASC_CHIP_VER_PCI             0x08
 170 #define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
 171 #define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
 172 #define ASC_CHIP_MIN_VER_EISA (0x41)
 173 #define ASC_CHIP_MAX_VER_EISA (0x47)
 174 #define ASC_CHIP_VER_EISA_BIT (0x40)
 175 #define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
 176 #define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
 177 #define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
 178 #define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
 179
 180 #define ASC_SCSI_ID_BITS  3
 181 #define ASC_SCSI_TIX_TYPE     uchar
 182 #define ASC_ALL_DEVICE_BIT_SET  0xFF
 183 #define ASC_SCSI_BIT_ID_TYPE  uchar
 184 #define ASC_MAX_TID       7
 185 #define ASC_MAX_LUN       7
 186 #define ASC_SCSI_WIDTH_BIT_SET  0xFF
 187 #define ASC_MAX_SENSE_LEN   32
 188 #define ASC_MIN_SENSE_LEN   14
 189 #define ASC_SCSI_RESET_HOLD_TIME_US  60
 190
 191 /*
 192  * Narrow boards only support 12-byte commands, while wide boards
 193  * extend to 16-byte commands.
 194  */
 195 #define ASC_MAX_CDB_LEN     12
 196 #define ADV_MAX_CDB_LEN     16
 197
 198 #define MS_SDTR_LEN    0x03
 199 #define MS_WDTR_LEN    0x02
 200
 201 #define ASC_SG_LIST_PER_Q   7
 202 #define QS_FREE        0x00
 203 #define QS_READY       0x01
 204 #define QS_DISC1       0x02
 205 #define QS_DISC2       0x04
 206 #define QS_BUSY        0x08
 207 #define QS_ABORTED     0x40
 208 #define QS_DONE        0x80
 209 #define QC_NO_CALLBACK   0x01
 210 #define QC_SG_SWAP_QUEUE 0x02
 211 #define QC_SG_HEAD       0x04
 212 #define QC_DATA_IN       0x08
 213 #define QC_DATA_OUT      0x10
 214 #define QC_URGENT        0x20
 215 #define QC_MSG_OUT       0x40
 216 #define QC_REQ_SENSE     0x80
 217 #define QCSG_SG_XFER_LIST  0x02
 218 #define QCSG_SG_XFER_MORE  0x04
 219 #define QCSG_SG_XFER_END   0x08
 220 #define QD_IN_PROGRESS       0x00
 221 #define QD_NO_ERROR          0x01
 222 #define QD_ABORTED_BY_HOST   0x02
 223 #define QD_WITH_ERROR        0x04
 224 #define QD_INVALID_REQUEST   0x80
 225 #define QD_INVALID_HOST_NUM  0x81
 226 #define QD_INVALID_DEVICE    0x82
 227 #define QD_ERR_INTERNAL      0xFF
 228 #define QHSTA_NO_ERROR               0x00
 229 #define QHSTA_M_SEL_TIMEOUT          0x11
 230 #define QHSTA_M_DATA_OVER_RUN        0x12
 231 #define QHSTA_M_DATA_UNDER_RUN       0x12
 232 #define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
 233 #define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
 234 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 235 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 236 #define QHSTA_D_HOST_ABORT_FAILED       0x23
 237 #define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 238 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 239 #define QHSTA_D_ASPI_NO_BUF_POOL        0x26
 240 #define QHSTA_M_WTM_TIMEOUT         0x41
 241 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
 242 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
 243 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
 244 #define QHSTA_M_TARGET_STATUS_BUSY  0x45
 245 #define QHSTA_M_BAD_TAG_CODE        0x46
 246 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 247 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 248 #define QHSTA_D_LRAM_CMP_ERROR        0x81
 249 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
 250 #define ASC_FLAG_SCSIQ_REQ        0x01
 251 #define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
 252 #define ASC_FLAG_BIOS_ASYNC_IO    0x04
 253 #define ASC_FLAG_SRB_LINEAR_ADDR  0x08
 254 #define ASC_FLAG_WIN16            0x10
 255 #define ASC_FLAG_WIN32            0x20
 256 #define ASC_FLAG_ISA_OVER_16MB    0x40
 257 #define ASC_FLAG_DOS_VM_CALLBACK  0x80
 258 #define ASC_TAG_FLAG_EXTRA_BYTES               0x10
 259 #define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
 260 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 261 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 262 #define ASC_SCSIQ_CPY_BEG              4
 263 #define ASC_SCSIQ_SGHD_CPY_BEG         2
 264 #define ASC_SCSIQ_B_FWD                0
 265 #define ASC_SCSIQ_B_BWD                1
 266 #define ASC_SCSIQ_B_STATUS             2
 267 #define ASC_SCSIQ_B_QNO                3
 268 #define ASC_SCSIQ_B_CNTL               4
 269 #define ASC_SCSIQ_B_SG_QUEUE_CNT       5
 270 #define ASC_SCSIQ_D_DATA_ADDR          8
 271 #define ASC_SCSIQ_D_DATA_CNT          12
 272 #define ASC_SCSIQ_B_SENSE_LEN         20
 273 #define ASC_SCSIQ_DONE_INFO_BEG       22
 274 #define ASC_SCSIQ_D_SRBPTR            22
 275 #define ASC_SCSIQ_B_TARGET_IX         26
 276 #define ASC_SCSIQ_B_CDB_LEN           28
 277 #define ASC_SCSIQ_B_TAG_CODE          29
 278 #define ASC_SCSIQ_W_VM_ID             30
 279 #define ASC_SCSIQ_DONE_STATUS         32
 280 #define ASC_SCSIQ_HOST_STATUS         33
 281 #define ASC_SCSIQ_SCSI_STATUS         34
 282 #define ASC_SCSIQ_CDB_BEG             36
 283 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
 284 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
 285 #define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
 286 #define ASC_SCSIQ_B_SG_WK_QP          49
 287 #define ASC_SCSIQ_B_SG_WK_IX          50
 288 #define ASC_SCSIQ_W_ALT_DC1           52
 289 #define ASC_SCSIQ_B_LIST_CNT          6
 290 #define ASC_SCSIQ_B_CUR_LIST_CNT      7
 291 #define ASC_SGQ_B_SG_CNTL             4
 292 #define ASC_SGQ_B_SG_HEAD_QP          5
 293 #define ASC_SGQ_B_SG_LIST_CNT         6
 294 #define ASC_SGQ_B_SG_CUR_LIST_CNT     7
 295 #define ASC_SGQ_LIST_BEG              8
 296 #define ASC_DEF_SCSI1_QNG    4
 297 #define ASC_MAX_SCSI1_QNG    4
 298 #define ASC_DEF_SCSI2_QNG    16
 299 #define ASC_MAX_SCSI2_QNG    32
 300 #define ASC_TAG_CODE_MASK    0x23
 301 #define ASC_STOP_REQ_RISC_STOP      0x01
 302 #define ASC_STOP_ACK_RISC_STOP      0x03
 303 #define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
 304 #define ASC_STOP_CLEAN_UP_DISC_Q    0x20
 305 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
 306 #define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
 307 #define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
 308 #define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
 309 #define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
 310 #define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
 311 #define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
 312 #define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
 313
 314 typedef struct asc_scsiq_1 {
 315         uchar status;
 316         uchar q_no;
 317         uchar cntl;
 318         uchar sg_queue_cnt;
 319         uchar target_id;
 320         uchar target_lun;
 321         ASC_PADDR data_addr;
 322         ASC_DCNT data_cnt;
 323         ASC_PADDR sense_addr;
 324         uchar sense_len;
 325         uchar extra_bytes;
 326 } ASC_SCSIQ_1;
 327
 328 typedef struct asc_scsiq_2 {
 329         ASC_VADDR srb_ptr;
 330         uchar target_ix;
 331         uchar flag;
 332         uchar cdb_len;
 333         uchar tag_code;
 334         ushort vm_id;
 335 } ASC_SCSIQ_2;
 336
 337 typedef struct asc_scsiq_3 {
 338         uchar done_stat;
 339         uchar host_stat;
 340         uchar scsi_stat;
 341         uchar scsi_msg;
 342 } ASC_SCSIQ_3;
 343
 344 typedef struct asc_scsiq_4 {
 345         uchar cdb[ASC_MAX_CDB_LEN];
 346         uchar y_first_sg_list_qp;
 347         uchar y_working_sg_qp;
 348         uchar y_working_sg_ix;
 349         uchar y_res;
 350         ushort x_req_count;
 351         ushort x_reconnect_rtn;
 352         ASC_PADDR x_saved_data_addr;
 353         ASC_DCNT x_saved_data_cnt;
 354 } ASC_SCSIQ_4;
 355
 356 typedef struct asc_q_done_info {
 357         ASC_SCSIQ_2 d2;
 358         ASC_SCSIQ_3 d3;
 359         uchar q_status;
 360         uchar q_no;
 361         uchar cntl;
 362         uchar sense_len;
 363         uchar extra_bytes;
 364         uchar res;
 365         ASC_DCNT remain_bytes;
 366 } ASC_QDONE_INFO;
 367
 368 typedef struct asc_sg_list {
 369         ASC_PADDR addr;
 370         ASC_DCNT bytes;
 371 } ASC_SG_LIST;
 372
 373 typedef struct asc_sg_head {
 374         ushort entry_cnt;
 375         ushort queue_cnt;
 376         ushort entry_to_copy;
 377         ushort res;
 378         ASC_SG_LIST sg_list[0];
 379 } ASC_SG_HEAD;
 380
 381 typedef struct asc_scsi_q {
 382         ASC_SCSIQ_1 q1;
 383         ASC_SCSIQ_2 q2;
 384         uchar *cdbptr;
 385         ASC_SG_HEAD *sg_head;
 386         ushort remain_sg_entry_cnt;
 387         ushort next_sg_index;
 388 } ASC_SCSI_Q;
 389
 390 typedef struct asc_scsi_req_q {
 391         ASC_SCSIQ_1 r1;
 392         ASC_SCSIQ_2 r2;
 393         uchar *cdbptr;
 394         ASC_SG_HEAD *sg_head;
 395         uchar *sense_ptr;
 396         ASC_SCSIQ_3 r3;
 397         uchar cdb[ASC_MAX_CDB_LEN];
 398         uchar sense[ASC_MIN_SENSE_LEN];
 399 } ASC_SCSI_REQ_Q;
 400
 401 typedef struct asc_scsi_bios_req_q {
 402         ASC_SCSIQ_1 r1;
 403         ASC_SCSIQ_2 r2;
 404         uchar *cdbptr;
 405         ASC_SG_HEAD *sg_head;
 406         uchar *sense_ptr;
 407         ASC_SCSIQ_3 r3;
 408         uchar cdb[ASC_MAX_CDB_LEN];
 409         uchar sense[ASC_MIN_SENSE_LEN];
 410 } ASC_SCSI_BIOS_REQ_Q;
 411
 412 typedef struct asc_risc_q {
 413         uchar fwd;
 414         uchar bwd;
 415         ASC_SCSIQ_1 i1;
 416         ASC_SCSIQ_2 i2;
 417         ASC_SCSIQ_3 i3;
 418         ASC_SCSIQ_4 i4;
 419 } ASC_RISC_Q;
 420
 421 typedef struct asc_sg_list_q {
 422         uchar seq_no;
 423         uchar q_no;
 424         uchar cntl;
 425         uchar sg_head_qp;
 426         uchar sg_list_cnt;
 427         uchar sg_cur_list_cnt;
 428 } ASC_SG_LIST_Q;
 429
 430 typedef struct asc_risc_sg_list_q {
 431         uchar fwd;
 432         uchar bwd;
 433         ASC_SG_LIST_Q sg;
 434         ASC_SG_LIST sg_list[7];
 435 } ASC_RISC_SG_LIST_Q;
 436
 437 #define ASCQ_ERR_Q_STATUS             0x0D
 438 #define ASCQ_ERR_CUR_QNG              0x17
 439 #define ASCQ_ERR_SG_Q_LINKS           0x18
 440 #define ASCQ_ERR_ISR_RE_ENTRY         0x1A
 441 #define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
 442 #define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
 443
 444 /*
 445  * Warning code values are set in ASC_DVC_VAR  'warn_code'.
 446  */
 447 #define ASC_WARN_NO_ERROR             0x0000
 448 #define ASC_WARN_IO_PORT_ROTATE       0x0001
 449 #define ASC_WARN_EEPROM_CHKSUM        0x0002
 450 #define ASC_WARN_IRQ_MODIFIED         0x0004
 451 #define ASC_WARN_AUTO_CONFIG          0x0008
 452 #define ASC_WARN_CMD_QNG_CONFLICT     0x0010
 453 #define ASC_WARN_EEPROM_RECOVER       0x0020
 454 #define ASC_WARN_CFG_MSW_RECOVER      0x0040
 455
 456 /*
 457  * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
 458  */
 459 #define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
 460 #define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
 461 #define ASC_IERR_SET_PC_ADDR            0x0004
 462 #define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
 463 #define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
 464 #define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
 465 #define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
 466 #define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
 467 #define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
 468 #define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
 469 #define ASC_IERR_NO_BUS_TYPE            0x0400
 470 #define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
 471 #define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
 472 #define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
 473
 474 #define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
 475 #define ASC_MIN_TAG_Q_PER_DVC   (0x04)
 476 #define ASC_MIN_FREE_Q        (0x02)
 477 #define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
 478 #define ASC_MAX_TOTAL_QNG 240
 479 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 480 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
 481 #define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
 482 #define ASC_MAX_INRAM_TAG_QNG   16
 483 #define ASC_IOADR_GAP   0x10
 484 #define ASC_SYN_MAX_OFFSET         0x0F
 485 #define ASC_DEF_SDTR_OFFSET        0x0F
 486 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
 487 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
 488
 489 /* The narrow chip only supports a limited selection of transfer rates.
 490  * These are encoded in the range 0..7 or 0..15 depending whether the chip
 491  * is Ultra-capable or not.  These tables let us convert from one to the other.
 492  */
 493 static const unsigned char asc_syn_xfer_period[8] = {
 494         25, 30, 35, 40, 50, 60, 70, 85
 495 };
 496
 497 static const unsigned char asc_syn_ultra_xfer_period[16] = {
 498         12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
 499 };
 500
 501 typedef struct ext_msg {
 502         uchar msg_type;
 503         uchar msg_len;
 504         uchar msg_req;
 505         union {
 506                 struct {
 507                         uchar sdtr_xfer_period;
 508                         uchar sdtr_req_ack_offset;
 509                 } sdtr;
 510                 struct {
 511                         uchar wdtr_width;
 512                 } wdtr;
 513                 struct {
 514                         uchar mdp_b3;
 515                         uchar mdp_b2;
 516                         uchar mdp_b1;
 517                         uchar mdp_b0;
 518                 } mdp;
 519         } u_ext_msg;
 520         uchar res;
 521 } EXT_MSG;
 522
 523 #define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
 524 #define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
 525 #define wdtr_width      u_ext_msg.wdtr.wdtr_width
 526 #define mdp_b3          u_ext_msg.mdp_b3
 527 #define mdp_b2          u_ext_msg.mdp_b2
 528 #define mdp_b1          u_ext_msg.mdp_b1
 529 #define mdp_b0          u_ext_msg.mdp_b0
 530
 531 typedef struct asc_dvc_cfg {
 532         ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
 533         ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
 534         ASC_SCSI_BIT_ID_TYPE disc_enable;
 535         ASC_SCSI_BIT_ID_TYPE sdtr_enable;
 536         uchar chip_scsi_id;
 537         uchar isa_dma_speed;
 538         uchar isa_dma_channel;
 539         uchar chip_version;
 540         ushort mcode_date;
 541         ushort mcode_version;
 542         uchar max_tag_qng[ASC_MAX_TID + 1];
 543         uchar *overrun_buf;
 544         uchar sdtr_period_offset[ASC_MAX_TID + 1];
 545         uchar adapter_info[6];
 546 } ASC_DVC_CFG;
 547
 548 #define ASC_DEF_DVC_CNTL       0xFFFF
 549 #define ASC_DEF_CHIP_SCSI_ID   7
 550 #define ASC_DEF_ISA_DMA_SPEED  4
 551 #define ASC_INIT_STATE_BEG_GET_CFG   0x0001
 552 #define ASC_INIT_STATE_END_GET_CFG   0x0002
 553 #define ASC_INIT_STATE_BEG_SET_CFG   0x0004
 554 #define ASC_INIT_STATE_END_SET_CFG   0x0008
 555 #define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
 556 #define ASC_INIT_STATE_END_LOAD_MC   0x0020
 557 #define ASC_INIT_STATE_BEG_INQUIRY   0x0040
 558 #define ASC_INIT_STATE_END_INQUIRY   0x0080
 559 #define ASC_INIT_RESET_SCSI_DONE     0x0100
 560 #define ASC_INIT_STATE_WITHOUT_EEP   0x8000
 561 #define ASC_BUG_FIX_IF_NOT_DWB       0x0001
 562 #define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
 563 #define ASC_MIN_TAGGED_CMD  7
 564 #define ASC_MAX_SCSI_RESET_WAIT      30
 565
 566 struct asc_dvc_var;             /* Forward Declaration. */
 567
 568 typedef struct asc_dvc_var {
 569         PortAddr iop_base;
 570         ushort err_code;
 571         ushort dvc_cntl;
 572         ushort bug_fix_cntl;
 573         ushort bus_type;
 574         ASC_SCSI_BIT_ID_TYPE init_sdtr;
 575         ASC_SCSI_BIT_ID_TYPE sdtr_done;
 576         ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
 577         ASC_SCSI_BIT_ID_TYPE unit_not_ready;
 578         ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
 579         ASC_SCSI_BIT_ID_TYPE start_motor;
 580         uchar scsi_reset_wait;
 581         uchar chip_no;
 582         char is_in_int;
 583         uchar max_total_qng;
 584         uchar cur_total_qng;
 585         uchar in_critical_cnt;
 586         uchar last_q_shortage;
 587         ushort init_state;
 588         uchar cur_dvc_qng[ASC_MAX_TID + 1];
 589         uchar max_dvc_qng[ASC_MAX_TID + 1];
 590         ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
 591         ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
 592         const uchar *sdtr_period_tbl;
 593         ASC_DVC_CFG *cfg;
 594         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
 595         char redo_scam;
 596         ushort res2;
 597         uchar dos_int13_table[ASC_MAX_TID + 1];
 598         ASC_DCNT max_dma_count;
 599         ASC_SCSI_BIT_ID_TYPE no_scam;
 600         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
 601         uchar min_sdtr_index;
 602         uchar max_sdtr_index;
 603         struct asc_board *drv_ptr;
 604         ASC_DCNT uc_break;
 605 } ASC_DVC_VAR;
 606
 607 typedef struct asc_dvc_inq_info {
 608         uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 609 } ASC_DVC_INQ_INFO;
 610
 611 typedef struct asc_cap_info {
 612         ASC_DCNT lba;
 613         ASC_DCNT blk_size;
 614 } ASC_CAP_INFO;
 615
 616 typedef struct asc_cap_info_array {
 617         ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 618 } ASC_CAP_INFO_ARRAY;
 619
 620 #define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
 621 #define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
 622 #define ASC_CNTL_INITIATOR         (ushort)0x0001
 623 #define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
 624 #define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
 625 #define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
 626 #define ASC_CNTL_NO_SCAM           (ushort)0x0010
 627 #define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
 628 #define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
 629 #define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
 630 #define ASC_CNTL_RESET_SCSI        (ushort)0x0200
 631 #define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
 632 #define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
 633 #define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
 634 #define ASC_CNTL_BURST_MODE        (ushort)0x2000
 635 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
 636 #define ASC_EEP_DVC_CFG_BEG_VL    2
 637 #define ASC_EEP_MAX_DVC_ADDR_VL   15
 638 #define ASC_EEP_DVC_CFG_BEG      32
 639 #define ASC_EEP_MAX_DVC_ADDR     45
 640 #define ASC_EEP_MAX_RETRY        20
 641
 642 /*
 643  * These macros keep the chip SCSI id and ISA DMA speed
 644  * bitfields in board order. C bitfields aren't portable
 645  * between big and little-endian platforms so they are
 646  * not used.
 647  */
 648
 649 #define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
 650 #define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
 651 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
 652    ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
 653 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
 654    ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
 655
 656 typedef struct asceep_config {
 657         ushort cfg_lsw;
 658         ushort cfg_msw;
 659         uchar init_sdtr;
 660         uchar disc_enable;
 661         uchar use_cmd_qng;
 662         uchar start_motor;
 663         uchar max_total_qng;
 664         uchar max_tag_qng;
 665         uchar bios_scan;
 666         uchar power_up_wait;
 667         uchar no_scam;
 668         uchar id_speed;         /* low order 4 bits is chip scsi id */
 669         /* high order 4 bits is isa dma speed */
 670         uchar dos_int13_table[ASC_MAX_TID + 1];
 671         uchar adapter_info[6];
 672         ushort cntl;
 673         ushort chksum;
 674 } ASCEEP_CONFIG;
 675
 676 #define ASC_EEP_CMD_READ          0x80
 677 #define ASC_EEP_CMD_WRITE         0x40
 678 #define ASC_EEP_CMD_WRITE_ABLE    0x30
 679 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
 680 #define ASC_OVERRUN_BSIZE  0x00000048UL
 681 #define ASCV_MSGOUT_BEG         0x0000
 682 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
 683 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
 684 #define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
 685 #define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
 686 #define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
 687 #define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
 688 #define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
 689 #define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
 690 #define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
 691 #define ASCV_BREAK_ADDR           (ushort)0x0028
 692 #define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
 693 #define ASCV_BREAK_CONTROL        (ushort)0x002C
 694 #define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
 695
 696 #define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
 697 #define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
 698 #define ASCV_MCODE_SIZE_W     (ushort)0x0034
 699 #define ASCV_STOP_CODE_B      (ushort)0x0036
 700 #define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
 701 #define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
 702 #define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
 703 #define ASCV_HALTCODE_W       (ushort)0x0040
 704 #define ASCV_CHKSUM_W         (ushort)0x0042
 705 #define ASCV_MC_DATE_W        (ushort)0x0044
 706 #define ASCV_MC_VER_W         (ushort)0x0046
 707 #define ASCV_NEXTRDY_B        (ushort)0x0048
 708 #define ASCV_DONENEXT_B       (ushort)0x0049
 709 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
 710 #define ASCV_SCSIBUSY_B       (ushort)0x004B
 711 #define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
 712 #define ASCV_CURCDB_B         (ushort)0x004D
 713 #define ASCV_RCLUN_B          (ushort)0x004E
 714 #define ASCV_BUSY_QHEAD_B     (ushort)0x004F
 715 #define ASCV_DISC1_QHEAD_B    (ushort)0x0050
 716 #define ASCV_DISC_ENABLE_B    (ushort)0x0052
 717 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
 718 #define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
 719 #define ASCV_MCODE_CNTL_B     (ushort)0x0056
 720 #define ASCV_NULL_TARGET_B    (ushort)0x0057
 721 #define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
 722 #define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
 723 #define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
 724 #define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
 725 #define ASCV_HOST_FLAG_B      (ushort)0x005D
 726 #define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
 727 #define ASCV_VER_SERIAL_B     (ushort)0x0065
 728 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
 729 #define ASCV_WTM_FLAG_B       (ushort)0x0068
 730 #define ASCV_RISC_FLAG_B      (ushort)0x006A
 731 #define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
 732 #define ASC_HOST_FLAG_IN_ISR        0x01
 733 #define ASC_HOST_FLAG_ACK_INT       0x02
 734 #define ASC_RISC_FLAG_GEN_INT      0x01
 735 #define ASC_RISC_FLAG_REQ_SG_LIST  0x02
 736 #define IOP_CTRL         (0x0F)
 737 #define IOP_STATUS       (0x0E)
 738 #define IOP_INT_ACK      IOP_STATUS
 739 #define IOP_REG_IFC      (0x0D)
 740 #define IOP_SYN_OFFSET    (0x0B)
 741 #define IOP_EXTRA_CONTROL (0x0D)
 742 #define IOP_REG_PC        (0x0C)
 743 #define IOP_RAM_ADDR      (0x0A)
 744 #define IOP_RAM_DATA      (0x08)
 745 #define IOP_EEP_DATA      (0x06)
 746 #define IOP_EEP_CMD       (0x07)
 747 #define IOP_VERSION       (0x03)
 748 #define IOP_CONFIG_HIGH   (0x04)
 749 #define IOP_CONFIG_LOW    (0x02)
 750 #define IOP_SIG_BYTE      (0x01)
 751 #define IOP_SIG_WORD      (0x00)
 752 #define IOP_REG_DC1      (0x0E)
 753 #define IOP_REG_DC0      (0x0C)
 754 #define IOP_REG_SB       (0x0B)
 755 #define IOP_REG_DA1      (0x0A)
 756 #define IOP_REG_DA0      (0x08)
 757 #define IOP_REG_SC       (0x09)
 758 #define IOP_DMA_SPEED    (0x07)
 759 #define IOP_REG_FLAG     (0x07)
 760 #define IOP_FIFO_H       (0x06)
 761 #define IOP_FIFO_L       (0x04)
 762 #define IOP_REG_ID       (0x05)
 763 #define IOP_REG_QP       (0x03)
 764 #define IOP_REG_IH       (0x02)
 765 #define IOP_REG_IX       (0x01)
 766 #define IOP_REG_AX       (0x00)
 767 #define IFC_REG_LOCK      (0x00)
 768 #define IFC_REG_UNLOCK    (0x09)
 769 #define IFC_WR_EN_FILTER  (0x10)
 770 #define IFC_RD_NO_EEPROM  (0x10)
 771 #define IFC_SLEW_RATE     (0x20)
 772 #define IFC_ACT_NEG       (0x40)
 773 #define IFC_INP_FILTER    (0x80)
 774 #define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
 775 #define SC_SEL   (uchar)(0x80)
 776 #define SC_BSY   (uchar)(0x40)
 777 #define SC_ACK   (uchar)(0x20)
 778 #define SC_REQ   (uchar)(0x10)
 779 #define SC_ATN   (uchar)(0x08)
 780 #define SC_IO    (uchar)(0x04)
 781 #define SC_CD    (uchar)(0x02)
 782 #define SC_MSG   (uchar)(0x01)
 783 #define SEC_SCSI_CTL         (uchar)(0x80)
 784 #define SEC_ACTIVE_NEGATE    (uchar)(0x40)
 785 #define SEC_SLEW_RATE        (uchar)(0x20)
 786 #define SEC_ENABLE_FILTER    (uchar)(0x10)
 787 #define ASC_HALT_EXTMSG_IN     (ushort)0x8000
 788 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
 789 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
 790 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
 791 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
 792 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
 793 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
 794 #define ASC_MAX_QNO        0xF8
 795 #define ASC_DATA_SEC_BEG   (ushort)0x0080
 796 #define ASC_DATA_SEC_END   (ushort)0x0080
 797 #define ASC_CODE_SEC_BEG   (ushort)0x0080
 798 #define ASC_CODE_SEC_END   (ushort)0x0080
 799 #define ASC_QADR_BEG       (0x4000)
 800 #define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
 801 #define ASC_QADR_END       (ushort)0x7FFF
 802 #define ASC_QLAST_ADR      (ushort)0x7FC0
 803 #define ASC_QBLK_SIZE      0x40
 804 #define ASC_BIOS_DATA_QBEG 0xF8
 805 #define ASC_MIN_ACTIVE_QNO 0x01
 806 #define ASC_QLINK_END      0xFF
 807 #define ASC_EEPROM_WORDS   0x10
 808 #define ASC_MAX_MGS_LEN    0x10
 809 #define ASC_BIOS_ADDR_DEF  0xDC00
 810 #define ASC_BIOS_SIZE      0x3800
 811 #define ASC_BIOS_RAM_OFF   0x3800
 812 #define ASC_BIOS_RAM_SIZE  0x800
 813 #define ASC_BIOS_MIN_ADDR  0xC000
 814 #define ASC_BIOS_MAX_ADDR  0xEC00
 815 #define ASC_BIOS_BANK_SIZE 0x0400
 816 #define ASC_MCODE_START_ADDR  0x0080
 817 #define ASC_CFG0_HOST_INT_ON    0x0020
 818 #define ASC_CFG0_BIOS_ON        0x0040
 819 #define ASC_CFG0_VERA_BURST_ON  0x0080
 820 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
 821 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
 822 #define ASC_CFG1_LRAM_8BITS_ON  0x0800
 823 #define ASC_CFG_MSW_CLR_MASK    0x3080
 824 #define CSW_TEST1             (ASC_CS_TYPE)0x8000
 825 #define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
 826 #define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
 827 #define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
 828 #define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
 829 #define CSW_TEST2             (ASC_CS_TYPE)0x0400
 830 #define CSW_TEST3             (ASC_CS_TYPE)0x0200
 831 #define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
 832 #define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
 833 #define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
 834 #define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
 835 #define CSW_HALTED            (ASC_CS_TYPE)0x0010
 836 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
 837 #define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
 838 #define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
 839 #define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
 840 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
 841 #define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
 842 #define CIW_TEST1        (ASC_CS_TYPE)0x0200
 843 #define CIW_TEST2        (ASC_CS_TYPE)0x0400
 844 #define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
 845 #define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
 846 #define CC_CHIP_RESET   (uchar)0x80
 847 #define CC_SCSI_RESET   (uchar)0x40
 848 #define CC_HALT         (uchar)0x20
 849 #define CC_SINGLE_STEP  (uchar)0x10
 850 #define CC_DMA_ABLE     (uchar)0x08
 851 #define CC_TEST         (uchar)0x04
 852 #define CC_BANK_ONE     (uchar)0x02
 853 #define CC_DIAG         (uchar)0x01
 854 #define ASC_1000_ID0W      0x04C1
 855 #define ASC_1000_ID0W_FIX  0x00C1
 856 #define ASC_1000_ID1B      0x25
 857 #define ASC_EISA_REV_IOP_MASK  (0x0C83)
 858 #define ASC_EISA_CFG_IOP_MASK  (0x0C86)
 859 #define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
 860 #define INS_HALTINT        (ushort)0x6281
 861 #define INS_HALT           (ushort)0x6280
 862 #define INS_SINT           (ushort)0x6200
 863 #define INS_RFLAG_WTM      (ushort)0x7380
 864 #define ASC_MC_SAVE_CODE_WSIZE  0x500
 865 #define ASC_MC_SAVE_DATA_WSIZE  0x40
 866
 867 typedef struct asc_mc_saved {
 868         ushort data[ASC_MC_SAVE_DATA_WSIZE];
 869         ushort code[ASC_MC_SAVE_CODE_WSIZE];
 870 } ASC_MC_SAVED;
 871
 872 #define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
 873 #define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
 874 #define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
 875 #define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
 876 #define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
 877 #define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
 878 #define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
 879 #define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
 880 #define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
 881 #define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
 882 #define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
 883 #define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
 884 #define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
 885 #define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
 886 #define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
 887 #define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
 888 #define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
 889 #define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
 890 #define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
 891 #define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
 892 #define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
 893 #define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
 894 #define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
 895 #define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
 896 #define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
 897 #define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
 898 #define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
 899 #define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
 900 #define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
 901 #define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
 902 #define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
 903 #define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
 904 #define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
 905 #define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
 906 #define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
 907 #define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
 908 #define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
 909 #define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
 910 #define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
 911 #define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
 912 #define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
 913 #define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
 914 #define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
 915 #define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
 916 #define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
 917 #define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
 918 #define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
 919 #define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
 920 #define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
 921 #define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
 922 #define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
 923 #define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
 924 #define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
 925 #define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
 926 #define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
 927 #define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
 928 #define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
 929 #define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
 930 #define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
 931 #define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
 932 #define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
 933 #define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
 934 #define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
 935 #define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
 936 #define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
 937 #define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
 938 #define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
 939
 940 /*
 941  * Portable Data Types
 942  *
 943  * Any instance where a 32-bit long or pointer type is assumed
 944  * for precision or HW defined structures, the following define
 945  * types must be used. In Linux the char, short, and int types
 946  * are all consistent at 8, 16, and 32 bits respectively. Pointers
 947  * and long types are 64 bits on Alpha and UltraSPARC.
 948  */
 949 #define ADV_PADDR __u32         /* Physical address data type. */
 950 #define ADV_VADDR __u32         /* Virtual address data type. */
 951 #define ADV_DCNT  __u32         /* Unsigned Data count type. */
 952 #define ADV_SDCNT __s32         /* Signed Data count type. */
 953
 954 /*
 955  * These macros are used to convert a virtual address to a
 956  * 32-bit value. This currently can be used on Linux Alpha
 957  * which uses 64-bit virtual address but a 32-bit bus address.
 958  * This is likely to break in the future, but doing this now
 959  * will give us time to change the HW and FW to handle 64-bit
 960  * addresses.
 961  */
 962 #define ADV_VADDR_TO_U32   virt_to_bus
 963 #define ADV_U32_TO_VADDR   bus_to_virt
 964
 965 #define AdvPortAddr  void __iomem *     /* Virtual memory address size */
 966
 967 /*
 968  * Define Adv Library required memory access macros.
 969  */
 970 #define ADV_MEM_READB(addr) readb(addr)
 971 #define ADV_MEM_READW(addr) readw(addr)
 972 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
 973 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
 974 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
 975
 976 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
 977
 978 /*
 979  * Define total number of simultaneous maximum element scatter-gather
 980  * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
 981  * maximum number of outstanding commands per wide host adapter. Each
 982  * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
 983  * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
 984  * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
 985  * structures or 255 scatter-gather elements.
 986  */
 987 #define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
 988
 989 /*
 990  * Define maximum number of scatter-gather elements per request.
 991  */
 992 #define ADV_MAX_SG_LIST         255
 993 #define NO_OF_SG_PER_BLOCK              15
 994
 995 #define ADV_EEP_DVC_CFG_BEGIN           (0x00)
 996 #define ADV_EEP_DVC_CFG_END             (0x15)
 997 #define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
 998 #define ADV_EEP_MAX_WORD_ADDR           (0x1E)
 999
1000 #define ADV_EEP_DELAY_MS                100
1001
1002 #define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
1003 #define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
1004 /*
1005  * For the ASC3550 Bit 13 is Termination Polarity control bit.
1006  * For later ICs Bit 13 controls whether the CIS (Card Information
1007  * Service Section) is loaded from EEPROM.
1008  */
1009 #define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
1010 #define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
1011 /*
1012  * ASC38C1600 Bit 11
1013  *
1014  * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1015  * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1016  * Function 0 will specify INT B.
1017  *
1018  * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1019  * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1020  * Function 1 will specify INT A.
1021  */
1022 #define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
1023
1024 typedef struct adveep_3550_config {
1025         /* Word Offset, Description */
1026
1027         ushort cfg_lsw;         /* 00 power up initialization */
1028         /*  bit 13 set - Term Polarity Control */
1029         /*  bit 14 set - BIOS Enable */
1030         /*  bit 15 set - Big Endian Mode */
1031         ushort cfg_msw;         /* 01 unused      */
1032         ushort disc_enable;     /* 02 disconnect enable */
1033         ushort wdtr_able;       /* 03 Wide DTR able */
1034         ushort sdtr_able;       /* 04 Synchronous DTR able */
1035         ushort start_motor;     /* 05 send start up motor */
1036         ushort tagqng_able;     /* 06 tag queuing able */
1037         ushort bios_scan;       /* 07 BIOS device control */
1038         ushort scam_tolerant;   /* 08 no scam */
1039
1040         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1041         uchar bios_boot_delay;  /*    power up wait */
1042
1043         uchar scsi_reset_delay; /* 10 reset delay */
1044         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1045         /*    high nibble is lun */
1046         /*    low nibble is scsi id */
1047
1048         uchar termination;      /* 11 0 - automatic */
1049         /*    1 - low off / high off */
1050         /*    2 - low off / high on */
1051         /*    3 - low on  / high on */
1052         /*    There is no low on  / high off */
1053
1054         uchar reserved1;        /*    reserved byte (not used) */
1055
1056         ushort bios_ctrl;       /* 12 BIOS control bits */
1057         /*  bit 0  BIOS don't act as initiator. */
1058         /*  bit 1  BIOS > 1 GB support */
1059         /*  bit 2  BIOS > 2 Disk Support */
1060         /*  bit 3  BIOS don't support removables */
1061         /*  bit 4  BIOS support bootable CD */
1062         /*  bit 5  BIOS scan enabled */
1063         /*  bit 6  BIOS support multiple LUNs */
1064         /*  bit 7  BIOS display of message */
1065         /*  bit 8  SCAM disabled */
1066         /*  bit 9  Reset SCSI bus during init. */
1067         /*  bit 10 */
1068         /*  bit 11 No verbose initialization. */
1069         /*  bit 12 SCSI parity enabled */
1070         /*  bit 13 */
1071         /*  bit 14 */
1072         /*  bit 15 */
1073         ushort ultra_able;      /* 13 ULTRA speed able */
1074         ushort reserved2;       /* 14 reserved */
1075         uchar max_host_qng;     /* 15 maximum host queuing */
1076         uchar max_dvc_qng;      /*    maximum per device queuing */
1077         ushort dvc_cntl;        /* 16 control bit for driver */
1078         ushort bug_fix;         /* 17 control bit for bug fix */
1079         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1080         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1081         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1082         ushort check_sum;       /* 21 EEP check sum */
1083         uchar oem_name[16];     /* 22 OEM name */
1084         ushort dvc_err_code;    /* 30 last device driver error code */
1085         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1086         ushort adv_err_addr;    /* 32 last uc error address */
1087         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1088         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1089         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1090         ushort num_of_err;      /* 36 number of error */
1091 } ADVEEP_3550_CONFIG;
1092
1093 typedef struct adveep_38C0800_config {
1094         /* Word Offset, Description */
1095
1096         ushort cfg_lsw;         /* 00 power up initialization */
1097         /*  bit 13 set - Load CIS */
1098         /*  bit 14 set - BIOS Enable */
1099         /*  bit 15 set - Big Endian Mode */
1100         ushort cfg_msw;         /* 01 unused      */
1101         ushort disc_enable;     /* 02 disconnect enable */
1102         ushort wdtr_able;       /* 03 Wide DTR able */
1103         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1104         ushort start_motor;     /* 05 send start up motor */
1105         ushort tagqng_able;     /* 06 tag queuing able */
1106         ushort bios_scan;       /* 07 BIOS device control */
1107         ushort scam_tolerant;   /* 08 no scam */
1108
1109         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1110         uchar bios_boot_delay;  /*    power up wait */
1111
1112         uchar scsi_reset_delay; /* 10 reset delay */
1113         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1114         /*    high nibble is lun */
1115         /*    low nibble is scsi id */
1116
1117         uchar termination_se;   /* 11 0 - automatic */
1118         /*    1 - low off / high off */
1119         /*    2 - low off / high on */
1120         /*    3 - low on  / high on */
1121         /*    There is no low on  / high off */
1122
1123         uchar termination_lvd;  /* 11 0 - automatic */
1124         /*    1 - low off / high off */
1125         /*    2 - low off / high on */
1126         /*    3 - low on  / high on */
1127         /*    There is no low on  / high off */
1128
1129         ushort bios_ctrl;       /* 12 BIOS control bits */
1130         /*  bit 0  BIOS don't act as initiator. */
1131         /*  bit 1  BIOS > 1 GB support */
1132         /*  bit 2  BIOS > 2 Disk Support */
1133         /*  bit 3  BIOS don't support removables */
1134         /*  bit 4  BIOS support bootable CD */
1135         /*  bit 5  BIOS scan enabled */
1136         /*  bit 6  BIOS support multiple LUNs */
1137         /*  bit 7  BIOS display of message */
1138         /*  bit 8  SCAM disabled */
1139         /*  bit 9  Reset SCSI bus during init. */
1140         /*  bit 10 */
1141         /*  bit 11 No verbose initialization. */
1142         /*  bit 12 SCSI parity enabled */
1143         /*  bit 13 */
1144         /*  bit 14 */
1145         /*  bit 15 */
1146         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1147         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1148         uchar max_host_qng;     /* 15 maximum host queueing */
1149         uchar max_dvc_qng;      /*    maximum per device queuing */
1150         ushort dvc_cntl;        /* 16 control bit for driver */
1151         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1152         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1153         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1154         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1155         ushort check_sum;       /* 21 EEP check sum */
1156         uchar oem_name[16];     /* 22 OEM name */
1157         ushort dvc_err_code;    /* 30 last device driver error code */
1158         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1159         ushort adv_err_addr;    /* 32 last uc error address */
1160         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1161         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1162         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1163         ushort reserved36;      /* 36 reserved */
1164         ushort reserved37;      /* 37 reserved */
1165         ushort reserved38;      /* 38 reserved */
1166         ushort reserved39;      /* 39 reserved */
1167         ushort reserved40;      /* 40 reserved */
1168         ushort reserved41;      /* 41 reserved */
1169         ushort reserved42;      /* 42 reserved */
1170         ushort reserved43;      /* 43 reserved */
1171         ushort reserved44;      /* 44 reserved */
1172         ushort reserved45;      /* 45 reserved */
1173         ushort reserved46;      /* 46 reserved */
1174         ushort reserved47;      /* 47 reserved */
1175         ushort reserved48;      /* 48 reserved */
1176         ushort reserved49;      /* 49 reserved */
1177         ushort reserved50;      /* 50 reserved */
1178         ushort reserved51;      /* 51 reserved */
1179         ushort reserved52;      /* 52 reserved */
1180         ushort reserved53;      /* 53 reserved */
1181         ushort reserved54;      /* 54 reserved */
1182         ushort reserved55;      /* 55 reserved */
1183         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1184         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1185         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1186         ushort subsysid;        /* 59 SubSystem ID */
1187         ushort reserved60;      /* 60 reserved */
1188         ushort reserved61;      /* 61 reserved */
1189         ushort reserved62;      /* 62 reserved */
1190         ushort reserved63;      /* 63 reserved */
1191 } ADVEEP_38C0800_CONFIG;
1192
1193 typedef struct adveep_38C1600_config {
1194         /* Word Offset, Description */
1195
1196         ushort cfg_lsw;         /* 00 power up initialization */
1197         /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1198         /*       clear - Func. 0 INTA, Func. 1 INTB */
1199         /*  bit 13 set - Load CIS */
1200         /*  bit 14 set - BIOS Enable */
1201         /*  bit 15 set - Big Endian Mode */
1202         ushort cfg_msw;         /* 01 unused */
1203         ushort disc_enable;     /* 02 disconnect enable */
1204         ushort wdtr_able;       /* 03 Wide DTR able */
1205         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1206         ushort start_motor;     /* 05 send start up motor */
1207         ushort tagqng_able;     /* 06 tag queuing able */
1208         ushort bios_scan;       /* 07 BIOS device control */
1209         ushort scam_tolerant;   /* 08 no scam */
1210
1211         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1212         uchar bios_boot_delay;  /*    power up wait */
1213
1214         uchar scsi_reset_delay; /* 10 reset delay */
1215         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1216         /*    high nibble is lun */
1217         /*    low nibble is scsi id */
1218
1219         uchar termination_se;   /* 11 0 - automatic */
1220         /*    1 - low off / high off */
1221         /*    2 - low off / high on */
1222         /*    3 - low on  / high on */
1223         /*    There is no low on  / high off */
1224
1225         uchar termination_lvd;  /* 11 0 - automatic */
1226         /*    1 - low off / high off */
1227         /*    2 - low off / high on */
1228         /*    3 - low on  / high on */
1229         /*    There is no low on  / high off */
1230
1231         ushort bios_ctrl;       /* 12 BIOS control bits */
1232         /*  bit 0  BIOS don't act as initiator. */
1233         /*  bit 1  BIOS > 1 GB support */
1234         /*  bit 2  BIOS > 2 Disk Support */
1235         /*  bit 3  BIOS don't support removables */
1236         /*  bit 4  BIOS support bootable CD */
1237         /*  bit 5  BIOS scan enabled */
1238         /*  bit 6  BIOS support multiple LUNs */
1239         /*  bit 7  BIOS display of message */
1240         /*  bit 8  SCAM disabled */
1241         /*  bit 9  Reset SCSI bus during init. */
1242         /*  bit 10 Basic Integrity Checking disabled */
1243         /*  bit 11 No verbose initialization. */
1244         /*  bit 12 SCSI parity enabled */
1245         /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1246         /*  bit 14 */
1247         /*  bit 15 */
1248         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1249         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1250         uchar max_host_qng;     /* 15 maximum host queueing */
1251         uchar max_dvc_qng;      /*    maximum per device queuing */
1252         ushort dvc_cntl;        /* 16 control bit for driver */
1253         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1254         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1255         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1256         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1257         ushort check_sum;       /* 21 EEP check sum */
1258         uchar oem_name[16];     /* 22 OEM name */
1259         ushort dvc_err_code;    /* 30 last device driver error code */
1260         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1261         ushort adv_err_addr;    /* 32 last uc error address */
1262         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1263         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1264         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1265         ushort reserved36;      /* 36 reserved */
1266         ushort reserved37;      /* 37 reserved */
1267         ushort reserved38;      /* 38 reserved */
1268         ushort reserved39;      /* 39 reserved */
1269         ushort reserved40;      /* 40 reserved */
1270         ushort reserved41;      /* 41 reserved */
1271         ushort reserved42;      /* 42 reserved */
1272         ushort reserved43;      /* 43 reserved */
1273         ushort reserved44;      /* 44 reserved */
1274         ushort reserved45;      /* 45 reserved */
1275         ushort reserved46;      /* 46 reserved */
1276         ushort reserved47;      /* 47 reserved */
1277         ushort reserved48;      /* 48 reserved */
1278         ushort reserved49;      /* 49 reserved */
1279         ushort reserved50;      /* 50 reserved */
1280         ushort reserved51;      /* 51 reserved */
1281         ushort reserved52;      /* 52 reserved */
1282         ushort reserved53;      /* 53 reserved */
1283         ushort reserved54;      /* 54 reserved */
1284         ushort reserved55;      /* 55 reserved */
1285         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1286         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1287         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1288         ushort subsysid;        /* 59 SubSystem ID */
1289         ushort reserved60;      /* 60 reserved */
1290         ushort reserved61;      /* 61 reserved */
1291         ushort reserved62;      /* 62 reserved */
1292         ushort reserved63;      /* 63 reserved */
1293 } ADVEEP_38C1600_CONFIG;
1294
1295 /*
1296  * EEPROM Commands
1297  */
1298 #define ASC_EEP_CMD_DONE             0x0200
1299
1300 /* bios_ctrl */
1301 #define BIOS_CTRL_BIOS               0x0001
1302 #define BIOS_CTRL_EXTENDED_XLAT      0x0002
1303 #define BIOS_CTRL_GT_2_DISK          0x0004
1304 #define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1305 #define BIOS_CTRL_BOOTABLE_CD        0x0010
1306 #define BIOS_CTRL_MULTIPLE_LUN       0x0040
1307 #define BIOS_CTRL_DISPLAY_MSG        0x0080
1308 #define BIOS_CTRL_NO_SCAM            0x0100
1309 #define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1310 #define BIOS_CTRL_INIT_VERBOSE       0x0800
1311 #define BIOS_CTRL_SCSI_PARITY        0x1000
1312 #define BIOS_CTRL_AIPP_DIS           0x2000
1313
1314 #define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1315
1316 #define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1317
1318 /*
1319  * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1320  * a special 16K Adv Library and Microcode version. After the issue is
1321  * resolved, should restore 32K support.
1322  *
1323  * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1324  */
1325 #define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1326
1327 /*
1328  * Byte I/O register address from base of 'iop_base'.
1329  */
1330 #define IOPB_INTR_STATUS_REG    0x00
1331 #define IOPB_CHIP_ID_1          0x01
1332 #define IOPB_INTR_ENABLES       0x02
1333 #define IOPB_CHIP_TYPE_REV      0x03
1334 #define IOPB_RES_ADDR_4         0x04
1335 #define IOPB_RES_ADDR_5         0x05
1336 #define IOPB_RAM_DATA           0x06
1337 #define IOPB_RES_ADDR_7         0x07
1338 #define IOPB_FLAG_REG           0x08
1339 #define IOPB_RES_ADDR_9         0x09
1340 #define IOPB_RISC_CSR           0x0A
1341 #define IOPB_RES_ADDR_B         0x0B
1342 #define IOPB_RES_ADDR_C         0x0C
1343 #define IOPB_RES_ADDR_D         0x0D
1344 #define IOPB_SOFT_OVER_WR       0x0E
1345 #define IOPB_RES_ADDR_F         0x0F
1346 #define IOPB_MEM_CFG            0x10
1347 #define IOPB_RES_ADDR_11        0x11
1348 #define IOPB_GPIO_DATA          0x12
1349 #define IOPB_RES_ADDR_13        0x13
1350 #define IOPB_FLASH_PAGE         0x14
1351 #define IOPB_RES_ADDR_15        0x15
1352 #define IOPB_GPIO_CNTL          0x16
1353 #define IOPB_RES_ADDR_17        0x17
1354 #define IOPB_FLASH_DATA         0x18
1355 #define IOPB_RES_ADDR_19        0x19
1356 #define IOPB_RES_ADDR_1A        0x1A
1357 #define IOPB_RES_ADDR_1B        0x1B
1358 #define IOPB_RES_ADDR_1C        0x1C
1359 #define IOPB_RES_ADDR_1D        0x1D
1360 #define IOPB_RES_ADDR_1E        0x1E
1361 #define IOPB_RES_ADDR_1F        0x1F
1362 #define IOPB_DMA_CFG0           0x20
1363 #define IOPB_DMA_CFG1           0x21
1364 #define IOPB_TICKLE             0x22
1365 #define IOPB_DMA_REG_WR         0x23
1366 #define IOPB_SDMA_STATUS        0x24
1367 #define IOPB_SCSI_BYTE_CNT      0x25
1368 #define IOPB_HOST_BYTE_CNT      0x26
1369 #define IOPB_BYTE_LEFT_TO_XFER  0x27
1370 #define IOPB_BYTE_TO_XFER_0     0x28
1371 #define IOPB_BYTE_TO_XFER_1     0x29
1372 #define IOPB_BYTE_TO_XFER_2     0x2A
1373 #define IOPB_BYTE_TO_XFER_3     0x2B
1374 #define IOPB_ACC_GRP            0x2C
1375 #define IOPB_RES_ADDR_2D        0x2D
1376 #define IOPB_DEV_ID             0x2E
1377 #define IOPB_RES_ADDR_2F        0x2F
1378 #define IOPB_SCSI_DATA          0x30
1379 #define IOPB_RES_ADDR_31        0x31
1380 #define IOPB_RES_ADDR_32        0x32
1381 #define IOPB_SCSI_DATA_HSHK     0x33
1382 #define IOPB_SCSI_CTRL          0x34
1383 #define IOPB_RES_ADDR_35        0x35
1384 #define IOPB_RES_ADDR_36        0x36
1385 #define IOPB_RES_ADDR_37        0x37
1386 #define IOPB_RAM_BIST           0x38
1387 #define IOPB_PLL_TEST           0x39
1388 #define IOPB_PCI_INT_CFG        0x3A
1389 #define IOPB_RES_ADDR_3B        0x3B
1390 #define IOPB_RFIFO_CNT          0x3C
1391 #define IOPB_RES_ADDR_3D        0x3D
1392 #define IOPB_RES_ADDR_3E        0x3E
1393 #define IOPB_RES_ADDR_3F        0x3F
1394
1395 /*
1396  * Word I/O register address from base of 'iop_base'.
1397  */
1398 #define IOPW_CHIP_ID_0          0x00    /* CID0  */
1399 #define IOPW_CTRL_REG           0x02    /* CC    */
1400 #define IOPW_RAM_ADDR           0x04    /* LA    */
1401 #define IOPW_RAM_DATA           0x06    /* LD    */
1402 #define IOPW_RES_ADDR_08        0x08
1403 #define IOPW_RISC_CSR           0x0A    /* CSR   */
1404 #define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1405 #define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1406 #define IOPW_RES_ADDR_10        0x10
1407 #define IOPW_SEL_MASK           0x12    /* SM    */
1408 #define IOPW_RES_ADDR_14        0x14
1409 #define IOPW_FLASH_ADDR         0x16    /* FA    */
1410 #define IOPW_RES_ADDR_18        0x18
1411 #define IOPW_EE_CMD             0x1A    /* EC    */
1412 #define IOPW_EE_DATA            0x1C    /* ED    */
1413 #define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1414 #define IOPW_RES_ADDR_20        0x20
1415 #define IOPW_Q_BASE             0x22    /* QB    */
1416 #define IOPW_QP                 0x24    /* QP    */
1417 #define IOPW_IX                 0x26    /* IX    */
1418 #define IOPW_SP                 0x28    /* SP    */
1419 #define IOPW_PC                 0x2A    /* PC    */
1420 #define IOPW_RES_ADDR_2C        0x2C
1421 #define IOPW_RES_ADDR_2E        0x2E
1422 #define IOPW_SCSI_DATA          0x30    /* SD    */
1423 #define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1424 #define IOPW_SCSI_CTRL          0x34    /* SC    */
1425 #define IOPW_HSHK_CFG           0x36    /* HCFG  */
1426 #define IOPW_SXFR_STATUS        0x36    /* SXS   */
1427 #define IOPW_SXFR_CNTL          0x38    /* SXL   */
1428 #define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1429 #define IOPW_RES_ADDR_3C        0x3C
1430 #define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1431
1432 /*
1433  * Doubleword I/O register address from base of 'iop_base'.
1434  */
1435 #define IOPDW_RES_ADDR_0         0x00
1436 #define IOPDW_RAM_DATA           0x04
1437 #define IOPDW_RES_ADDR_8         0x08
1438 #define IOPDW_RES_ADDR_C         0x0C
1439 #define IOPDW_RES_ADDR_10        0x10
1440 #define IOPDW_COMMA              0x14
1441 #define IOPDW_COMMB              0x18
1442 #define IOPDW_RES_ADDR_1C        0x1C
1443 #define IOPDW_SDMA_ADDR0         0x20
1444 #define IOPDW_SDMA_ADDR1         0x24
1445 #define IOPDW_SDMA_COUNT         0x28
1446 #define IOPDW_SDMA_ERROR         0x2C
1447 #define IOPDW_RDMA_ADDR0         0x30
1448 #define IOPDW_RDMA_ADDR1         0x34
1449 #define IOPDW_RDMA_COUNT         0x38
1450 #define IOPDW_RDMA_ERROR         0x3C
1451
1452 #define ADV_CHIP_ID_BYTE         0x25
1453 #define ADV_CHIP_ID_WORD         0x04C1
1454
1455 #define ADV_INTR_ENABLE_HOST_INTR                   0x01
1456 #define ADV_INTR_ENABLE_SEL_INTR                    0x02
1457 #define ADV_INTR_ENABLE_DPR_INTR                    0x04
1458 #define ADV_INTR_ENABLE_RTA_INTR                    0x08
1459 #define ADV_INTR_ENABLE_RMA_INTR                    0x10
1460 #define ADV_INTR_ENABLE_RST_INTR                    0x20
1461 #define ADV_INTR_ENABLE_DPE_INTR                    0x40
1462 #define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1463
1464 #define ADV_INTR_STATUS_INTRA            0x01
1465 #define ADV_INTR_STATUS_INTRB            0x02
1466 #define ADV_INTR_STATUS_INTRC            0x04
1467
1468 #define ADV_RISC_CSR_STOP           (0x0000)
1469 #define ADV_RISC_TEST_COND          (0x2000)
1470 #define ADV_RISC_CSR_RUN            (0x4000)
1471 #define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1472
1473 #define ADV_CTRL_REG_HOST_INTR      0x0100
1474 #define ADV_CTRL_REG_SEL_INTR       0x0200
1475 #define ADV_CTRL_REG_DPR_INTR       0x0400
1476 #define ADV_CTRL_REG_RTA_INTR       0x0800
1477 #define ADV_CTRL_REG_RMA_INTR       0x1000
1478 #define ADV_CTRL_REG_RES_BIT14      0x2000
1479 #define ADV_CTRL_REG_DPE_INTR       0x4000
1480 #define ADV_CTRL_REG_POWER_DONE     0x8000
1481 #define ADV_CTRL_REG_ANY_INTR       0xFF00
1482
1483 #define ADV_CTRL_REG_CMD_RESET             0x00C6
1484 #define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1485 #define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1486 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1487 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1488
1489 #define ADV_TICKLE_NOP                      0x00
1490 #define ADV_TICKLE_A                        0x01
1491 #define ADV_TICKLE_B                        0x02
1492 #define ADV_TICKLE_C                        0x03
1493
1494 #define AdvIsIntPending(port) \
1495     (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1496
1497 /*
1498  * SCSI_CFG0 Register bit definitions
1499  */
1500 #define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1501 #define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1502 #define EVEN_PARITY     0x1000  /* Select Even Parity */
1503 #define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1504 #define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1505 #define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1506 #define SCAM_EN         0x0080  /* Enable SCAM selection */
1507 #define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1508 #define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1509 #define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1510 #define OUR_ID          0x000F  /* SCSI ID */
1511
1512 /*
1513  * SCSI_CFG1 Register bit definitions
1514  */
1515 #define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1516 #define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1517 #define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1518 #define FILTER_SEL      0x0C00  /* Filter Period Selection */
1519 #define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1520 #define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1521 #define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1522 #define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1523 #define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1524 #define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1525 #define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1526 #define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1527 #define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1528 #define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1529 #define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1530
1531 /*
1532  * Addendum for ASC-38C0800 Chip
1533  *
1534  * The ASC-38C1600 Chip uses the same definitions except that the
1535  * bus mode override bits [12:10] have been moved to byte register
1536  * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1537  * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1538  * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1539  * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1540  * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1541  */
1542 #define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1543 #define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1544 #define  HVD             0x1000 /* HVD Device Detect */
1545 #define  LVD             0x0800 /* LVD Device Detect */
1546 #define  SE              0x0400 /* SE Device Detect */
1547 #define TERM_LVD        0x00C0  /* LVD Termination Bits */
1548 #define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1549 #define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1550 #define TERM_SE         0x0030  /* SE Termination Bits */
1551 #define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1552 #define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1553 #define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1554 #define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1555 #define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1556 #define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1557 #define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1558 #define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1559
1560 #define CABLE_ILLEGAL_A 0x7
1561     /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1562
1563 #define CABLE_ILLEGAL_B 0xB
1564     /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1565
1566 /*
1567  * MEM_CFG Register bit definitions
1568  */
1569 #define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1570 #define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1571 #define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1572 #define  RAM_SZ_2KB      0x00   /* 2 KB */
1573 #define  RAM_SZ_4KB      0x04   /* 4 KB */
1574 #define  RAM_SZ_8KB      0x08   /* 8 KB */
1575 #define  RAM_SZ_16KB     0x0C   /* 16 KB */
1576 #define  RAM_SZ_32KB     0x10   /* 32 KB */
1577 #define  RAM_SZ_64KB     0x14   /* 64 KB */
1578
1579 /*
1580  * DMA_CFG0 Register bit definitions
1581  *
1582  * This register is only accessible to the host.
1583  */
1584 #define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1585 #define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1586 #define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1587 #define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1588 #define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1589 #define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1590 #define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1591 #define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1592 #define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1593 #define START_CTL       0x0C    /* DMA start conditions */
1594 #define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1595 #define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1596 #define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1597 #define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1598 #define READ_CMD        0x03    /* Memory Read Method */
1599 #define  READ_CMD_MR     0x00   /* Memory Read */
1600 #define  READ_CMD_MRL    0x02   /* Memory Read Long */
1601 #define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1602
1603 /*
1604  * ASC-38C0800 RAM BIST Register bit definitions
1605  */
1606 #define RAM_TEST_MODE         0x80
1607 #define PRE_TEST_MODE         0x40
1608 #define NORMAL_MODE           0x00
1609 #define RAM_TEST_DONE         0x10
1610 #define RAM_TEST_STATUS       0x0F
1611 #define  RAM_TEST_HOST_ERROR   0x08
1612 #define  RAM_TEST_INTRAM_ERROR 0x04
1613 #define  RAM_TEST_RISC_ERROR   0x02
1614 #define  RAM_TEST_SCSI_ERROR   0x01
1615 #define  RAM_TEST_SUCCESS      0x00
1616 #define PRE_TEST_VALUE        0x05
1617 #define NORMAL_VALUE          0x00
1618
1619 /*
1620  * ASC38C1600 Definitions
1621  *
1622  * IOPB_PCI_INT_CFG Bit Field Definitions
1623  */
1624
1625 #define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1626
1627 /*
1628  * Bit 1 can be set to change the interrupt for the Function to operate in
1629  * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1630  * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1631  * mode, otherwise the operating mode is undefined.
1632  */
1633 #define TOTEMPOLE       0x02
1634
1635 /*
1636  * Bit 0 can be used to change the Int Pin for the Function. The value is
1637  * 0 by default for both Functions with Function 0 using INT A and Function
1638  * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1639  * INT A is used.
1640  *
1641  * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1642  * value specified in the PCI Configuration Space.
1643  */
1644 #define INTAB           0x01
1645
1646 /*
1647  * Adv Library Status Definitions
1648  */
1649 #define ADV_TRUE        1
1650 #define ADV_FALSE       0
1651 #define ADV_SUCCESS     1
1652 #define ADV_BUSY        0
1653 #define ADV_ERROR       (-1)
1654
1655 /*
1656  * ADV_DVC_VAR 'warn_code' values
1657  */
1658 #define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1659 #define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1660 #define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1661 #define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1662
1663 #define ADV_MAX_TID                     15      /* max. target identifier */
1664 #define ADV_MAX_LUN                     7       /* max. logical unit number */
1665
1666 /*
1667  * Fixed locations of microcode operating variables.
1668  */
1669 #define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1670 #define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1671 #define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1672 #define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1673 #define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1674 #define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1675 #define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1676 #define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1677 #define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1678 #define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1679 #define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1680 #define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1681 #define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1682 #define ASC_MC_CHIP_TYPE                0x009A
1683 #define ASC_MC_INTRB_CODE               0x009B
1684 #define ASC_MC_WDTR_ABLE                0x009C
1685 #define ASC_MC_SDTR_ABLE                0x009E
1686 #define ASC_MC_TAGQNG_ABLE              0x00A0
1687 #define ASC_MC_DISC_ENABLE              0x00A2
1688 #define ASC_MC_IDLE_CMD_STATUS          0x00A4
1689 #define ASC_MC_IDLE_CMD                 0x00A6
1690 #define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1691 #define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1692 #define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1693 #define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1694 #define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1695 #define ASC_MC_SDTR_DONE                0x00B6
1696 #define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1697 #define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1698 #define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1699 #define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1700 #define ASC_MC_WDTR_DONE                0x0124
1701 #define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1702 #define ASC_MC_ICQ                      0x0160
1703 #define ASC_MC_IRQ                      0x0164
1704 #define ASC_MC_PPR_ABLE                 0x017A
1705
1706 /*
1707  * BIOS LRAM variable absolute offsets.
1708  */
1709 #define BIOS_CODESEG    0x54
1710 #define BIOS_CODELEN    0x56
1711 #define BIOS_SIGNATURE  0x58
1712 #define BIOS_VERSION    0x5A
1713
1714 /*
1715  * Microcode Control Flags
1716  *
1717  * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1718  * and handled by the microcode.
1719  */
1720 #define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1721 #define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1722
1723 /*
1724  * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1725  */
1726 #define HSHK_CFG_WIDE_XFR       0x8000
1727 #define HSHK_CFG_RATE           0x0F00
1728 #define HSHK_CFG_OFFSET         0x001F
1729
1730 #define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1731 #define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1732 #define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1733 #define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1734
1735 #define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1736 #define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1737 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1738 #define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1739 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1740
1741 #define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1742 #define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1743 #define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1744 #define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1745 #define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1746 /*
1747  * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1748  * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1749  */
1750 #define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1751 #define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1752
1753 /*
1754  * All fields here are accessed by the board microcode and need to be
1755  * little-endian.
1756  */
1757 typedef struct adv_carr_t {
1758         ADV_VADDR carr_va;      /* Carrier Virtual Address */
1759         ADV_PADDR carr_pa;      /* Carrier Physical Address */
1760         ADV_VADDR areq_vpa;     /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1761         /*
1762          * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1763          *
1764          * next_vpa [3:1]             Reserved Bits
1765          * next_vpa [0]               Done Flag set in Response Queue.
1766          */
1767         ADV_VADDR next_vpa;
1768 } ADV_CARR_T;
1769
1770 /*
1771  * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1772  */
1773 #define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1774
1775 #define ASC_RQ_DONE             0x00000001
1776 #define ASC_RQ_GOOD             0x00000002
1777 #define ASC_CQ_STOPPER          0x00000000
1778
1779 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1780
1781 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1782     (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1783
1784 #define ADV_CARRIER_BUFSIZE \
1785     ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1786
1787 /*
1788  * ASC_SCSI_REQ_Q 'a_flag' definitions
1789  *
1790  * The Adv Library should limit use to the lower nibble (4 bits) of
1791  * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1792  */
1793 #define ADV_POLL_REQUEST                0x01    /* poll for request completion */
1794 #define ADV_SCSIQ_DONE                  0x02    /* request done */
1795 #define ADV_DONT_RETRY                  0x08    /* don't do retry */
1796
1797 #define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1798 #define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1799 #define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1800
1801 /*
1802  * Adapter temporary configuration structure
1803  *
1804  * This structure can be discarded after initialization. Don't add
1805  * fields here needed after initialization.
1806  *
1807  * Field naming convention:
1808  *
1809  *  *_enable indicates the field enables or disables a feature. The
1810  *  value of the field is never reset.
1811  */
1812 typedef struct adv_dvc_cfg {
1813         ushort disc_enable;     /* enable disconnection */
1814         uchar chip_version;     /* chip version */
1815         uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1816         ushort control_flag;    /* Microcode Control Flag */
1817         ushort mcode_date;      /* Microcode date */
1818         ushort mcode_version;   /* Microcode version */
1819         ushort serial1;         /* EEPROM serial number word 1 */
1820         ushort serial2;         /* EEPROM serial number word 2 */
1821         ushort serial3;         /* EEPROM serial number word 3 */
1822 } ADV_DVC_CFG;
1823
1824 struct adv_dvc_var;
1825 struct adv_scsi_req_q;
1826
1827 typedef struct asc_sg_block {
1828         uchar reserved1;
1829         uchar reserved2;
1830         uchar reserved3;
1831         uchar sg_cnt;           /* Valid entries in block. */
1832         ADV_PADDR sg_ptr;       /* Pointer to next sg block. */
1833         struct {
1834                 ADV_PADDR sg_addr;      /* SG element address. */
1835                 ADV_DCNT sg_count;      /* SG element count. */
1836         } sg_list[NO_OF_SG_PER_BLOCK];
1837 } ADV_SG_BLOCK;
1838
1839 /*
1840  * ADV_SCSI_REQ_Q - microcode request structure
1841  *
1842  * All fields in this structure up to byte 60 are used by the microcode.
1843  * The microcode makes assumptions about the size and ordering of fields
1844  * in this structure. Do not change the structure definition here without
1845  * coordinating the change with the microcode.
1846  *
1847  * All fields accessed by microcode must be maintained in little_endian
1848  * order.
1849  */
1850 typedef struct adv_scsi_req_q {
1851         uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1852         uchar target_cmd;
1853         uchar target_id;        /* Device target identifier. */
1854         uchar target_lun;       /* Device target logical unit number. */
1855         ADV_PADDR data_addr;    /* Data buffer physical address. */
1856         ADV_DCNT data_cnt;      /* Data count. Ucode sets to residual. */
1857         ADV_PADDR sense_addr;
1858         ADV_PADDR carr_pa;
1859         uchar mflag;
1860         uchar sense_len;
1861         uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1862         uchar scsi_cntl;
1863         uchar done_status;      /* Completion status. */
1864         uchar scsi_status;      /* SCSI status byte. */
1865         uchar host_status;      /* Ucode host status. */
1866         uchar sg_working_ix;
1867         uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1868         ADV_PADDR sg_real_addr; /* SG list physical address. */
1869         ADV_PADDR scsiq_rptr;
1870         uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1871         ADV_VADDR scsiq_ptr;
1872         ADV_VADDR carr_va;
1873         /*
1874          * End of microcode structure - 60 bytes. The rest of the structure
1875          * is used by the Adv Library and ignored by the microcode.
1876          */
1877         ADV_VADDR srb_ptr;
1878         ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1879         char *vdata_addr;       /* Data buffer virtual address. */
1880         uchar a_flag;
1881         uchar pad[2];           /* Pad out to a word boundary. */
1882 } ADV_SCSI_REQ_Q;
1883
1884 /*
1885  * The following two structures are used to process Wide Board requests.
1886  *
1887  * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1888  * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1889  * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1890  * Mid-Level SCSI request structure.
1891  *
1892  * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1893  * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1894  * up to 255 scatter-gather elements may be used per request or
1895  * ADV_SCSI_REQ_Q.
1896  *
1897  * Both structures must be 32 byte aligned.
1898  */
1899 typedef struct adv_sgblk {
1900         ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1901         uchar align[32];        /* Sgblock structure padding. */
1902         struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1903 } adv_sgblk_t;
1904
1905 typedef struct adv_req {
1906         ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1907         uchar align[32];        /* Request structure padding. */
1908         struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1909         adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1910         struct adv_req *next_reqp;      /* Next Request Structure. */
1911 } adv_req_t;
1912
1913 /*
1914  * Adapter operation variable structure.
1915  *
1916  * One structure is required per host adapter.
1917  *
1918  * Field naming convention:
1919  *
1920  *  *_able indicates both whether a feature should be enabled or disabled
1921  *  and whether a device isi capable of the feature. At initialization
1922  *  this field may be set, but later if a device is found to be incapable
1923  *  of the feature, the field is cleared.
1924  */
1925 typedef struct adv_dvc_var {
1926         AdvPortAddr iop_base;   /* I/O port address */
1927         ushort err_code;        /* fatal error code */
1928         ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1929         ushort wdtr_able;       /* try WDTR for a device */
1930         ushort sdtr_able;       /* try SDTR for a device */
1931         ushort ultra_able;      /* try SDTR Ultra speed for a device */
1932         ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1933         ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1934         ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1935         ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1936         ushort tagqng_able;     /* try tagged queuing with a device */
1937         ushort ppr_able;        /* PPR message capable per TID bitmask. */
1938         uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1939         ushort start_motor;     /* start motor command allowed */
1940         uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1941         uchar chip_no;          /* should be assigned by caller */
1942         uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1943         ushort no_scam;         /* scam_tolerant of EEPROM */
1944         struct asc_board *drv_ptr;      /* driver pointer to private structure */
1945         uchar chip_scsi_id;     /* chip SCSI target ID */
1946         uchar chip_type;
1947         uchar bist_err_code;
1948         ADV_CARR_T *carrier_buf;
1949         ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1950         ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1951         ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1952         ushort carr_pending_cnt;        /* Count of pending carriers. */
1953         struct adv_req *orig_reqp;      /* adv_req_t memory block. */
1954         /*
1955          * Note: The following fields will not be used after initialization. The
1956          * driver may discard the buffer after initialization is done.
1957          */
1958         ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1959 } ADV_DVC_VAR;
1960
1961 /*
1962  * Microcode idle loop commands
1963  */
1964 #define IDLE_CMD_COMPLETED           0
1965 #define IDLE_CMD_STOP_CHIP           0x0001
1966 #define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1967 #define IDLE_CMD_SEND_INT            0x0004
1968 #define IDLE_CMD_ABORT               0x0008
1969 #define IDLE_CMD_DEVICE_RESET        0x0010
1970 #define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1971 #define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1972 #define IDLE_CMD_SCSIREQ             0x0080
1973
1974 #define IDLE_CMD_STATUS_SUCCESS      0x0001
1975 #define IDLE_CMD_STATUS_FAILURE      0x0002
1976
1977 /*
1978  * AdvSendIdleCmd() flag definitions.
1979  */
1980 #define ADV_NOWAIT     0x01
1981
1982 /*
1983  * Wait loop time out values.
1984  */
1985 #define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1986 #define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1987 #define SCSI_MAX_RETRY               10 /* retry count */
1988
1989 #define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1990 #define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1991 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1992 #define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1993
1994 #define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1995
1996 /* Read byte from a register. */
1997 #define AdvReadByteRegister(iop_base, reg_off) \
1998      (ADV_MEM_READB((iop_base) + (reg_off)))
1999
2000 /* Write byte to a register. */
2001 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2002      (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2003
2004 /* Read word (2 bytes) from a register. */
2005 #define AdvReadWordRegister(iop_base, reg_off) \
2006      (ADV_MEM_READW((iop_base) + (reg_off)))
2007
2008 /* Write word (2 bytes) to a register. */
2009 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2010      (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2011
2012 /* Write dword (4 bytes) to a register. */
2013 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2014      (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2015
2016 /* Read byte from LRAM. */
2017 #define AdvReadByteLram(iop_base, addr, byte) \
2018 do { \
2019     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2020     (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2021 } while (0)
2022
2023 /* Write byte to LRAM. */
2024 #define AdvWriteByteLram(iop_base, addr, byte) \
2025     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2026      ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2027
2028 /* Read word (2 bytes) from LRAM. */
2029 #define AdvReadWordLram(iop_base, addr, word) \
2030 do { \
2031     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2032     (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2033 } while (0)
2034
2035 /* Write word (2 bytes) to LRAM. */
2036 #define AdvWriteWordLram(iop_base, addr, word) \
2037     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2038      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2039
2040 /* Write little-endian double word (4 bytes) to LRAM */
2041 /* Because of unspecified C language ordering don't use auto-increment. */
2042 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2043     ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2044       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2045                      cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2046      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2047       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2048                      cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2049
2050 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2051 #define AdvReadWordAutoIncLram(iop_base) \
2052      (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2053
2054 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2055 #define AdvWriteWordAutoIncLram(iop_base, word) \
2056      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2057
2058 /*
2059  * Define macro to check for Condor signature.
2060  *
2061  * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2062  * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2063  */
2064 #define AdvFindSignature(iop_base) \
2065     (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2066     ADV_CHIP_ID_BYTE) && \
2067      (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2068     ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2069
2070 /*
2071  * Define macro to Return the version number of the chip at 'iop_base'.
2072  *
2073  * The second parameter 'bus_type' is currently unused.
2074  */
2075 #define AdvGetChipVersion(iop_base, bus_type) \
2076     AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2077
2078 /*
2079  * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2080  * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2081  *
2082  * If the request has not yet been sent to the device it will simply be
2083  * aborted from RISC memory. If the request is disconnected it will be
2084  * aborted on reselection by sending an Abort Message to the target ID.
2085  *
2086  * Return value:
2087  *      ADV_TRUE(1) - Queue was successfully aborted.
2088  *      ADV_FALSE(0) - Queue was not found on the active queue list.
2089  */
2090 #define AdvAbortQueue(asc_dvc, scsiq) \
2091         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2092                        (ADV_DCNT) (scsiq))
2093
2094 /*
2095  * Send a Bus Device Reset Message to the specified target ID.
2096  *
2097  * All outstanding commands will be purged if sending the
2098  * Bus Device Reset Message is successful.
2099  *
2100  * Return Value:
2101  *      ADV_TRUE(1) - All requests on the target are purged.
2102  *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2103  *                     are not purged.
2104  */
2105 #define AdvResetDevice(asc_dvc, target_id) \
2106         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2107                     (ADV_DCNT) (target_id))
2108
2109 /*
2110  * SCSI Wide Type definition.
2111  */
2112 #define ADV_SCSI_BIT_ID_TYPE   ushort
2113
2114 /*
2115  * AdvInitScsiTarget() 'cntl_flag' options.
2116  */
2117 #define ADV_SCAN_LUN           0x01
2118 #define ADV_CAPINFO_NOLUN      0x02
2119
2120 /*
2121  * Convert target id to target id bit mask.
2122  */
2123 #define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2124
2125 /*
2126  * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2127  */
2128
2129 #define QD_NO_STATUS         0x00       /* Request not completed yet. */
2130 #define QD_NO_ERROR          0x01
2131 #define QD_ABORTED_BY_HOST   0x02
2132 #define QD_WITH_ERROR        0x04
2133
2134 #define QHSTA_NO_ERROR              0x00
2135 #define QHSTA_M_SEL_TIMEOUT         0x11
2136 #define QHSTA_M_DATA_OVER_RUN       0x12
2137 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2138 #define QHSTA_M_QUEUE_ABORTED       0x15
2139 #define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2140 #define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2141 #define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2142 #define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2143 #define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2144 #define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2145 #define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2146 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2147 #define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2148 #define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2149 #define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2150 #define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2151 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2152 #define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2153 #define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2154 #define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2155 #define QHSTA_M_WTM_TIMEOUT         0x41
2156 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2157 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2158 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2159 #define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2160 #define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2161 #define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2162
2163 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2164 #define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2165 #define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2166 #define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2167
2168 /*
2169  * Total contiguous memory needed for driver SG blocks.
2170  *
2171  * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2172  * number of scatter-gather elements the driver supports in a
2173  * single request.
2174  */
2175
2176 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2177          (sizeof(ADV_SG_BLOCK) * \
2178           ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2179
2180 /* struct asc_board flags */
2181 #define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2182
2183 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2184
2185 #define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2186
2187 #define ASC_INFO_SIZE           128     /* advansys_info() line size */
2188
2189 #ifdef CONFIG_PROC_FS
2190 /* /proc/scsi/advansys/[0...] related definitions */
2191 #define ASC_PRTBUF_SIZE         2048
2192 #define ASC_PRTLINE_SIZE        160
2193
2194 #define ASC_PRT_NEXT() \
2195     if (cp) { \
2196         totlen += len; \
2197         leftlen -= len; \
2198         if (leftlen == 0) { \
2199             return totlen; \
2200         } \
2201         cp += len; \
2202     }
2203 #endif /* CONFIG_PROC_FS */
2204
2205 /* Asc Library return codes */
2206 #define ASC_TRUE        1
2207 #define ASC_FALSE       0
2208 #define ASC_NOERROR     1
2209 #define ASC_BUSY        0
2210 #define ASC_ERROR       (-1)
2211
2212 /* struct scsi_cmnd function return codes */
2213 #define STATUS_BYTE(byte)   (byte)
2214 #define MSG_BYTE(byte)      ((byte) << 8)
2215 #define HOST_BYTE(byte)     ((byte) << 16)
2216 #define DRIVER_BYTE(byte)   ((byte) << 24)
2217
2218 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2219 #ifndef ADVANSYS_STATS
2220 #define ASC_STATS_ADD(shost, counter, count)
2221 #else /* ADVANSYS_STATS */
2222 #define ASC_STATS_ADD(shost, counter, count) \
2223         (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2224 #endif /* ADVANSYS_STATS */
2225
2226 /* If the result wraps when calculating tenths, return 0. */
2227 #define ASC_TENTHS(num, den) \
2228     (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2229     0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2230
2231 /*
2232  * Display a message to the console.
2233  */
2234 #define ASC_PRINT(s) \
2235     { \
2236         printk("advansys: "); \
2237         printk(s); \
2238     }
2239
2240 #define ASC_PRINT1(s, a1) \
2241     { \
2242         printk("advansys: "); \
2243         printk((s), (a1)); \
2244     }
2245
2246 #define ASC_PRINT2(s, a1, a2) \
2247     { \
2248         printk("advansys: "); \
2249         printk((s), (a1), (a2)); \
2250     }
2251
2252 #define ASC_PRINT3(s, a1, a2, a3) \
2253     { \
2254         printk("advansys: "); \
2255         printk((s), (a1), (a2), (a3)); \
2256     }
2257
2258 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2259     { \
2260         printk("advansys: "); \
2261         printk((s), (a1), (a2), (a3), (a4)); \
2262     }
2263
2264 #ifndef ADVANSYS_DEBUG
2265
2266 #define ASC_DBG(lvl, s...)
2267 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2268 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2269 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2270 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2271 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2272 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2273 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2274 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2275 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2276
2277 #else /* ADVANSYS_DEBUG */
2278
2279 /*
2280  * Debugging Message Levels:
2281  * 0: Errors Only
2282  * 1: High-Level Tracing
2283  * 2-N: Verbose Tracing
2284  */
2285
2286 #define ASC_DBG(lvl, format, arg...) {                                  \
2287         if (asc_dbglvl >= (lvl))                                        \
2288                 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2289                         __FUNCTION__ , ## arg);                         \
2290 }
2291
2292 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2293     { \
2294         if (asc_dbglvl >= (lvl)) { \
2295             asc_prt_scsi_host(s); \
2296         } \
2297     }
2298
2299 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2300     { \
2301         if (asc_dbglvl >= (lvl)) { \
2302             asc_prt_asc_scsi_q(scsiqp); \
2303         } \
2304     }
2305
2306 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2307     { \
2308         if (asc_dbglvl >= (lvl)) { \
2309             asc_prt_asc_qdone_info(qdone); \
2310         } \
2311     }
2312
2313 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2314     { \
2315         if (asc_dbglvl >= (lvl)) { \
2316             asc_prt_adv_scsi_req_q(scsiqp); \
2317         } \
2318     }
2319
2320 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2321     { \
2322         if (asc_dbglvl >= (lvl)) { \
2323             asc_prt_hex((name), (start), (length)); \
2324         } \
2325     }
2326
2327 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2328         ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2329
2330 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2331         ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2332
2333 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2334         ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2335 #endif /* ADVANSYS_DEBUG */
2336
2337 #ifdef ADVANSYS_STATS
2338
2339 /* Per board statistics structure */
2340 struct asc_stats {
2341         /* Driver Entrypoint Statistics */
2342         ADV_DCNT queuecommand;  /* # calls to advansys_queuecommand() */
2343         ADV_DCNT reset;         /* # calls to advansys_eh_bus_reset() */
2344         ADV_DCNT biosparam;     /* # calls to advansys_biosparam() */
2345         ADV_DCNT interrupt;     /* # advansys_interrupt() calls */
2346         ADV_DCNT callback;      /* # calls to asc/adv_isr_callback() */
2347         ADV_DCNT done;          /* # calls to request's scsi_done function */
2348         ADV_DCNT build_error;   /* # asc/adv_build_req() ASC_ERROR returns. */
2349         ADV_DCNT adv_build_noreq;       /* # adv_build_req() adv_req_t alloc. fail. */
2350         ADV_DCNT adv_build_nosg;        /* # adv_build_req() adv_sgblk_t alloc. fail. */
2351         /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2352         ADV_DCNT exe_noerror;   /* # ASC_NOERROR returns. */
2353         ADV_DCNT exe_busy;      /* # ASC_BUSY returns. */
2354         ADV_DCNT exe_error;     /* # ASC_ERROR returns. */
2355         ADV_DCNT exe_unknown;   /* # unknown returns. */
2356         /* Data Transfer Statistics */
2357         ADV_DCNT xfer_cnt;      /* # I/O requests received */
2358         ADV_DCNT xfer_elem;     /* # scatter-gather elements */
2359         ADV_DCNT xfer_sect;     /* # 512-byte blocks */
2360 };
2361 #endif /* ADVANSYS_STATS */
2362
2363 /*
2364  * Structure allocated for each board.
2365  *
2366  * This structure is allocated by scsi_host_alloc() at the end
2367  * of the 'Scsi_Host' structure starting at the 'hostdata'
2368  * field. It is guaranteed to be allocated from DMA-able memory.
2369  */
2370 struct asc_board {
2371         struct device *dev;
2372         uint flags;             /* Board flags */
2373         unsigned int irq;
2374         union {
2375                 ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2376                 ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2377         } dvc_var;
2378         union {
2379                 ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2380                 ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2381         } dvc_cfg;
2382         ushort asc_n_io_port;   /* Number I/O ports. */
2383         ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2384         ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2385         ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2386         ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2387         union {
2388                 ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2389                 ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2390                 ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2391                 ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2392         } eep_config;
2393         ulong last_reset;       /* Saved last reset time */
2394         /* /proc/scsi/advansys/[0...] */
2395         char *prtbuf;           /* /proc print buffer */
2396 #ifdef ADVANSYS_STATS
2397         struct asc_stats asc_stats;     /* Board statistics */
2398 #endif                          /* ADVANSYS_STATS */
2399         /*
2400          * The following fields are used only for Narrow Boards.
2401          */
2402         uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2403         /*
2404          * The following fields are used only for Wide Boards.
2405          */
2406         void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2407         ushort ioport;          /* I/O Port address. */
2408         adv_req_t *adv_reqp;    /* Request structures. */
2409         adv_sgblk_t *adv_sgblkp;        /* Scatter-gather structures. */
2410         ushort bios_signature;  /* BIOS Signature. */
2411         ushort bios_version;    /* BIOS Version. */
2412         ushort bios_codeseg;    /* BIOS Code Segment. */
2413         ushort bios_codelen;    /* BIOS Code Segment Length. */
2414 };
2415
2416 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2417                                                         dvc_var.adv_dvc_var)
2418 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2419
2420 /* Overrun buffer used by all narrow boards. */
2421 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2422
2423 #ifdef ADVANSYS_DEBUG
2424 static int asc_dbglvl = 3;
2425
2426 /*
2427  * asc_prt_asc_dvc_var()
2428  */
2429 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2430 {
2431         printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2432
2433         printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2434                "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2435
2436         printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2437                 (unsigned)h->init_sdtr);
2438
2439         printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2440                "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2441                (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2442                (unsigned)h->chip_no);
2443
2444         printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2445                "%u,\n", (unsigned)h->queue_full_or_busy,
2446                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2447
2448         printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2449                "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2450                (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2451                (unsigned)h->in_critical_cnt);
2452
2453         printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2454                "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2455                (unsigned)h->init_state, (unsigned)h->no_scam,
2456                (unsigned)h->pci_fix_asyn_xfer);
2457
2458         printk(" cfg 0x%lx\n", (ulong)h->cfg);
2459 }
2460
2461 /*
2462  * asc_prt_asc_dvc_cfg()
2463  */
2464 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2465 {
2466         printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2467
2468         printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2469                h->can_tagged_qng, h->cmd_qng_enabled);
2470         printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2471                h->disc_enable, h->sdtr_enable);
2472
2473         printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2474                 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2475                 h->isa_dma_channel, h->chip_version);
2476
2477         printk(" mcode_date 0x%x, mcode_version %d, overrun_buf 0x%p\n",
2478                 h->mcode_date, h->mcode_version, h->overrun_buf);
2479 }
2480
2481 /*
2482  * asc_prt_adv_dvc_var()
2483  *
2484  * Display an ADV_DVC_VAR structure.
2485  */
2486 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2487 {
2488         printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2489
2490         printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2491                (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2492
2493         printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2494                (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2495
2496         printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2497                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2498
2499         printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2500                (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2501                (ulong)h->carr_freelist);
2502
2503         printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2504                (ulong)h->icq_sp, (ulong)h->irq_sp);
2505
2506         printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2507                (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2508
2509         printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2510                (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2511 }
2512
2513 /*
2514  * asc_prt_adv_dvc_cfg()
2515  *
2516  * Display an ADV_DVC_CFG structure.
2517  */
2518 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2519 {
2520         printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2521
2522         printk("  disc_enable 0x%x, termination 0x%x\n",
2523                h->disc_enable, h->termination);
2524
2525         printk("  chip_version 0x%x, mcode_date 0x%x\n",
2526                h->chip_version, h->mcode_date);
2527
2528         printk("  mcode_version 0x%x, control_flag 0x%x\n",
2529                h->mcode_version, h->control_flag);
2530 }
2531
2532 /*
2533  * asc_prt_scsi_host()
2534  */
2535 static void asc_prt_scsi_host(struct Scsi_Host *s)
2536 {
2537         struct asc_board *boardp = shost_priv(s);
2538
2539         printk("Scsi_Host at addr 0x%p, device %s\n", s, boardp->dev->bus_id);
2540         printk(" host_busy %u, host_no %d, last_reset %d,\n",
2541                s->host_busy, s->host_no, (unsigned)s->last_reset);
2542
2543         printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2544                (ulong)s->base, (ulong)s->io_port, boardp->irq);
2545
2546         printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2547                s->dma_channel, s->this_id, s->can_queue);
2548
2549         printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2550                s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2551
2552         if (ASC_NARROW_BOARD(boardp)) {
2553                 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2554                 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2555         } else {
2556                 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2557                 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2558         }
2559 }
2560
2561 /*
2562  * asc_prt_hex()
2563  *
2564  * Print hexadecimal output in 4 byte groupings 32 bytes
2565  * or 8 double-words per line.
2566  */
2567 static void asc_prt_hex(char *f, uchar *s, int l)
2568 {
2569         int i;
2570         int j;
2571         int k;
2572         int m;
2573
2574         printk("%s: (%d bytes)\n", f, l);
2575
2576         for (i = 0; i < l; i += 32) {
2577
2578                 /* Display a maximum of 8 double-words per line. */
2579                 if ((k = (l - i) / 4) >= 8) {
2580                         k = 8;
2581                         m = 0;
2582                 } else {
2583                         m = (l - i) % 4;
2584                 }
2585
2586                 for (j = 0; j < k; j++) {
2587                         printk(" %2.2X%2.2X%2.2X%2.2X",
2588                                (unsigned)s[i + (j * 4)],
2589                                (unsigned)s[i + (j * 4) + 1],
2590                                (unsigned)s[i + (j * 4) + 2],
2591                                (unsigned)s[i + (j * 4) + 3]);
2592                 }
2593
2594                 switch (m) {
2595                 case 0:
2596                 default:
2597                         break;
2598                 case 1:
2599                         printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2600                         break;
2601                 case 2:
2602                         printk(" %2.2X%2.2X",
2603                                (unsigned)s[i + (j * 4)],
2604                                (unsigned)s[i + (j * 4) + 1]);
2605                         break;
2606                 case 3:
2607                         printk(" %2.2X%2.2X%2.2X",
2608                                (unsigned)s[i + (j * 4) + 1],
2609                                (unsigned)s[i + (j * 4) + 2],
2610                                (unsigned)s[i + (j * 4) + 3]);
2611                         break;
2612                 }
2613
2614                 printk("\n");
2615         }
2616 }
2617
2618 /*
2619  * asc_prt_asc_scsi_q()
2620  */
2621 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2622 {
2623         ASC_SG_HEAD *sgp;
2624         int i;
2625
2626         printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2627
2628         printk
2629             (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2630              q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2631              q->q2.tag_code);
2632
2633         printk
2634             (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2635              (ulong)le32_to_cpu(q->q1.data_addr),
2636              (ulong)le32_to_cpu(q->q1.data_cnt),
2637              (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2638
2639         printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2640                (ulong)q->cdbptr, q->q2.cdb_len,
2641                (ulong)q->sg_head, q->q1.sg_queue_cnt);
2642
2643         if (q->sg_head) {
2644                 sgp = q->sg_head;
2645                 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2646                 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2647                        sgp->queue_cnt);
2648                 for (i = 0; i < sgp->entry_cnt; i++) {
2649                         printk(" [%u]: addr 0x%lx, bytes %lu\n",
2650                                i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2651                                (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2652                 }
2653
2654         }
2655 }
2656
2657 /*
2658  * asc_prt_asc_qdone_info()
2659  */
2660 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2661 {
2662         printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2663         printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2664                (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2665                q->d2.tag_code);
2666         printk
2667             (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2668              q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2669 }
2670
2671 /*
2672  * asc_prt_adv_sgblock()
2673  *
2674  * Display an ADV_SG_BLOCK structure.
2675  */
2676 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2677 {
2678         int i;
2679
2680         printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2681                (ulong)b, sgblockno);
2682         printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2683                b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2684         BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2685         if (b->sg_ptr != 0)
2686                 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2687         for (i = 0; i < b->sg_cnt; i++) {
2688                 printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2689                        i, (ulong)b->sg_list[i].sg_addr,
2690                        (ulong)b->sg_list[i].sg_count);
2691         }
2692 }
2693
2694 /*
2695  * asc_prt_adv_scsi_req_q()
2696  *
2697  * Display an ADV_SCSI_REQ_Q structure.
2698  */
2699 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2700 {
2701         int sg_blk_cnt;
2702         struct asc_sg_block *sg_ptr;
2703
2704         printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2705
2706         printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2707                q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2708
2709         printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2710                q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2711
2712         printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2713                (ulong)le32_to_cpu(q->data_cnt),
2714                (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2715
2716         printk
2717             ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2718              q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2719
2720         printk("  sg_working_ix 0x%x, target_cmd %u\n",
2721                q->sg_working_ix, q->target_cmd);
2722
2723         printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2724                (ulong)le32_to_cpu(q->scsiq_rptr),
2725                (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2726
2727         /* Display the request's ADV_SG_BLOCK structures. */
2728         if (q->sg_list_ptr != NULL) {
2729                 sg_blk_cnt = 0;
2730                 while (1) {
2731                         /*
2732                          * 'sg_ptr' is a physical address. Convert it to a virtual
2733                          * address by indexing 'sg_blk_cnt' into the virtual address
2734                          * array 'sg_list_ptr'.
2735                          *
2736                          * XXX - Assumes all SG physical blocks are virtually contiguous.
2737                          */
2738                         sg_ptr =
2739                             &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2740                         asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2741                         if (sg_ptr->sg_ptr == 0) {
2742                                 break;
2743                         }
2744                         sg_blk_cnt++;
2745                 }
2746         }
2747 }
2748 #endif /* ADVANSYS_DEBUG */
2749
2750 /*
2751  * advansys_info()
2752  *
2753  * Return suitable for printing on the console with the argument
2754  * adapter's configuration information.
2755  *
2756  * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2757  * otherwise the static 'info' array will be overrun.
2758  */
2759 static const char *advansys_info(struct Scsi_Host *shost)
2760 {
2761         static char info[ASC_INFO_SIZE];
2762         struct asc_board *boardp = shost_priv(shost);
2763         ASC_DVC_VAR *asc_dvc_varp;
2764         ADV_DVC_VAR *adv_dvc_varp;
2765         char *busname;
2766         char *widename = NULL;
2767
2768         if (ASC_NARROW_BOARD(boardp)) {
2769                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2770                 ASC_DBG(1, "begin\n");
2771                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2772                         if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2773                             ASC_IS_ISAPNP) {
2774                                 busname = "ISA PnP";
2775                         } else {
2776                                 busname = "ISA";
2777                         }
2778                         sprintf(info,
2779                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2780                                 ASC_VERSION, busname,
2781                                 (ulong)shost->io_port,
2782                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2783                                 boardp->irq, shost->dma_channel);
2784                 } else {
2785                         if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2786                                 busname = "VL";
2787                         } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2788                                 busname = "EISA";
2789                         } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2790                                 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2791                                     == ASC_IS_PCI_ULTRA) {
2792                                         busname = "PCI Ultra";
2793                                 } else {
2794                                         busname = "PCI";
2795                                 }
2796                         } else {
2797                                 busname = "?";
2798                                 shost_printk(KERN_ERR, shost, "unknown bus "
2799                                         "type %d\n", asc_dvc_varp->bus_type);
2800                         }
2801                         sprintf(info,
2802                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2803                                 ASC_VERSION, busname, (ulong)shost->io_port,
2804                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2805                                 boardp->irq);
2806                 }
2807         } else {
2808                 /*
2809                  * Wide Adapter Information
2810                  *
2811                  * Memory-mapped I/O is used instead of I/O space to access
2812                  * the adapter, but display the I/O Port range. The Memory
2813                  * I/O address is displayed through the driver /proc file.
2814                  */
2815                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2816                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2817                         widename = "Ultra-Wide";
2818                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2819                         widename = "Ultra2-Wide";
2820                 } else {
2821                         widename = "Ultra3-Wide";
2822                 }
2823                 sprintf(info,
2824                         "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2825                         ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2826                         (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2827         }
2828         BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2829         ASC_DBG(1, "end\n");
2830         return info;
2831 }
2832
2833 #ifdef CONFIG_PROC_FS
2834 /*
2835  * asc_prt_line()
2836  *
2837  * If 'cp' is NULL print to the console, otherwise print to a buffer.
2838  *
2839  * Return 0 if printing to the console, otherwise return the number of
2840  * bytes written to the buffer.
2841  *
2842  * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2843  * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2844  */
2845 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2846 {
2847         va_list args;
2848         int ret;
2849         char s[ASC_PRTLINE_SIZE];
2850
2851         va_start(args, fmt);
2852         ret = vsprintf(s, fmt, args);
2853         BUG_ON(ret >= ASC_PRTLINE_SIZE);
2854         if (buf == NULL) {
2855                 (void)printk(s);
2856                 ret = 0;
2857         } else {
2858                 ret = min(buflen, ret);
2859                 memcpy(buf, s, ret);
2860         }
2861         va_end(args);
2862         return ret;
2863 }
2864
2865 /*
2866  * asc_prt_board_devices()
2867  *
2868  * Print driver information for devices attached to the board.
2869  *
2870  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2871  * cf. asc_prt_line().
2872  *
2873  * Return the number of characters copied into 'cp'. No more than
2874  * 'cplen' characters will be copied to 'cp'.
2875  */
2876 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
2877 {
2878         struct asc_board *boardp = shost_priv(shost);
2879         int leftlen;
2880         int totlen;
2881         int len;
2882         int chip_scsi_id;
2883         int i;
2884
2885         leftlen = cplen;
2886         totlen = len = 0;
2887
2888         len = asc_prt_line(cp, leftlen,
2889                            "\nDevice Information for AdvanSys SCSI Host %d:\n",
2890                            shost->host_no);
2891         ASC_PRT_NEXT();
2892
2893         if (ASC_NARROW_BOARD(boardp)) {
2894                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2895         } else {
2896                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2897         }
2898
2899         len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
2900         ASC_PRT_NEXT();
2901         for (i = 0; i <= ADV_MAX_TID; i++) {
2902                 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
2903                         len = asc_prt_line(cp, leftlen, " %X,", i);
2904                         ASC_PRT_NEXT();
2905                 }
2906         }
2907         len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
2908         ASC_PRT_NEXT();
2909
2910         return totlen;
2911 }
2912
2913 /*
2914  * Display Wide Board BIOS Information.
2915  */
2916 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
2917 {
2918         struct asc_board *boardp = shost_priv(shost);
2919         int leftlen;
2920         int totlen;
2921         int len;
2922         ushort major, minor, letter;
2923
2924         leftlen = cplen;
2925         totlen = len = 0;
2926
2927         len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
2928         ASC_PRT_NEXT();
2929
2930         /*
2931          * If the BIOS saved a valid signature, then fill in
2932          * the BIOS code segment base address.
2933          */
2934         if (boardp->bios_signature != 0x55AA) {
2935                 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
2936                 ASC_PRT_NEXT();
2937                 len = asc_prt_line(cp, leftlen,
2938                                    "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2939                 ASC_PRT_NEXT();
2940                 len = asc_prt_line(cp, leftlen,
2941                                    "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2942                 ASC_PRT_NEXT();
2943         } else {
2944                 major = (boardp->bios_version >> 12) & 0xF;
2945                 minor = (boardp->bios_version >> 8) & 0xF;
2946                 letter = (boardp->bios_version & 0xFF);
2947
2948                 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
2949                                    major, minor,
2950                                    letter >= 26 ? '?' : letter + 'A');
2951                 ASC_PRT_NEXT();
2952
2953                 /*
2954                  * Current available ROM BIOS release is 3.1I for UW
2955                  * and 3.2I for U2W. This code doesn't differentiate
2956                  * UW and U2W boards.
2957                  */
2958                 if (major < 3 || (major <= 3 && minor < 1) ||
2959                     (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2960                         len = asc_prt_line(cp, leftlen,
2961                                            "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
2962                         ASC_PRT_NEXT();
2963                         len = asc_prt_line(cp, leftlen,
2964                                            "ftp://ftp.connectcom.net/pub\n");
2965                         ASC_PRT_NEXT();
2966                 }
2967         }
2968
2969         return totlen;
2970 }
2971
2972 /*
2973  * Add serial number to information bar if signature AAh
2974  * is found in at bit 15-9 (7 bits) of word 1.
2975  *
2976  * Serial Number consists fo 12 alpha-numeric digits.
2977  *
2978  *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
2979  *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
2980  *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
2981  *       5 - Product revision (A-J)    Word0:  "         "
2982  *
2983  *           Signature                 Word1: 15-9 (7 bits)
2984  *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2985  *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
2986  *
2987  *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2988  *
2989  * Note 1: Only production cards will have a serial number.
2990  *
2991  * Note 2: Signature is most significant 7 bits (0xFE).
2992  *
2993  * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2994  */
2995 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2996 {
2997         ushort w, num;
2998
2999         if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3000                 return ASC_FALSE;
3001         } else {
3002                 /*
3003                  * First word - 6 digits.
3004                  */
3005                 w = serialnum[0];
3006
3007                 /* Product type - 1st digit. */
3008                 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3009                         /* Product type is P=Prototype */
3010                         *cp += 0x8;
3011                 }
3012                 cp++;
3013
3014                 /* Manufacturing location - 2nd digit. */
3015                 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3016
3017                 /* Product ID - 3rd, 4th digits. */
3018                 num = w & 0x3FF;
3019                 *cp++ = '0' + (num / 100);
3020                 num %= 100;
3021                 *cp++ = '0' + (num / 10);
3022
3023                 /* Product revision - 5th digit. */
3024                 *cp++ = 'A' + (num % 10);
3025
3026                 /*
3027                  * Second word
3028                  */
3029                 w = serialnum[1];
3030
3031                 /*
3032                  * Year - 6th digit.
3033                  *
3034                  * If bit 15 of third word is set, then the
3035                  * last digit of the year is greater than 7.
3036                  */
3037                 if (serialnum[2] & 0x8000) {
3038                         *cp++ = '8' + ((w & 0x1C0) >> 6);
3039                 } else {
3040                         *cp++ = '0' + ((w & 0x1C0) >> 6);
3041                 }
3042
3043                 /* Week of year - 7th, 8th digits. */
3044                 num = w & 0x003F;
3045                 *cp++ = '0' + num / 10;
3046                 num %= 10;
3047                 *cp++ = '0' + num;
3048
3049                 /*
3050                  * Third word
3051                  */
3052                 w = serialnum[2] & 0x7FFF;
3053
3054                 /* Serial number - 9th digit. */
3055                 *cp++ = 'A' + (w / 1000);
3056
3057                 /* 10th, 11th, 12th digits. */
3058                 num = w % 1000;
3059                 *cp++ = '0' + num / 100;
3060                 num %= 100;
3061                 *cp++ = '0' + num / 10;
3062                 num %= 10;
3063                 *cp++ = '0' + num;
3064
3065                 *cp = '\0';     /* Null Terminate the string. */
3066                 return ASC_TRUE;
3067         }
3068 }
3069
3070 /*
3071  * asc_prt_asc_board_eeprom()
3072  *
3073  * Print board EEPROM configuration.
3074  *
3075  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3076  * cf. asc_prt_line().
3077  *
3078  * Return the number of characters copied into 'cp'. No more than
3079  * 'cplen' characters will be copied to 'cp'.
3080  */
3081 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3082 {
3083         struct asc_board *boardp = shost_priv(shost);
3084         ASC_DVC_VAR *asc_dvc_varp;
3085         int leftlen;
3086         int totlen;
3087         int len;
3088         ASCEEP_CONFIG *ep;
3089         int i;
3090 #ifdef CONFIG_ISA
3091         int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3092 #endif /* CONFIG_ISA */
3093         uchar serialstr[13];
3094
3095         asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3096         ep = &boardp->eep_config.asc_eep;
3097
3098         leftlen = cplen;
3099         totlen = len = 0;
3100
3101         len = asc_prt_line(cp, leftlen,
3102                            "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3103                            shost->host_no);
3104         ASC_PRT_NEXT();
3105
3106         if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3107             == ASC_TRUE) {
3108                 len =
3109                     asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3110                                  serialstr);
3111                 ASC_PRT_NEXT();
3112         } else {
3113                 if (ep->adapter_info[5] == 0xBB) {
3114                         len = asc_prt_line(cp, leftlen,
3115                                            " Default Settings Used for EEPROM-less Adapter.\n");
3116                         ASC_PRT_NEXT();
3117                 } else {
3118                         len = asc_prt_line(cp, leftlen,
3119                                            " Serial Number Signature Not Present.\n");
3120                         ASC_PRT_NEXT();
3121                 }
3122         }
3123
3124         len = asc_prt_line(cp, leftlen,
3125                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3126                            ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3127                            ep->max_tag_qng);
3128         ASC_PRT_NEXT();
3129
3130         len = asc_prt_line(cp, leftlen,
3131                            " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3132         ASC_PRT_NEXT();
3133
3134         len = asc_prt_line(cp, leftlen, " Target ID:           ");
3135         ASC_PRT_NEXT();
3136         for (i = 0; i <= ASC_MAX_TID; i++) {
3137                 len = asc_prt_line(cp, leftlen, " %d", i);
3138                 ASC_PRT_NEXT();
3139         }
3140         len = asc_prt_line(cp, leftlen, "\n");
3141         ASC_PRT_NEXT();
3142
3143         len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3144         ASC_PRT_NEXT();
3145         for (i = 0; i <= ASC_MAX_TID; i++) {
3146                 len = asc_prt_line(cp, leftlen, " %c",
3147                                    (ep->
3148                                     disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3149                                    'N');
3150                 ASC_PRT_NEXT();
3151         }
3152         len = asc_prt_line(cp, leftlen, "\n");
3153         ASC_PRT_NEXT();
3154
3155         len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3156         ASC_PRT_NEXT();
3157         for (i = 0; i <= ASC_MAX_TID; i++) {
3158                 len = asc_prt_line(cp, leftlen, " %c",
3159                                    (ep->
3160                                     use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3161                                    'N');
3162                 ASC_PRT_NEXT();
3163         }
3164         len = asc_prt_line(cp, leftlen, "\n");
3165         ASC_PRT_NEXT();
3166
3167         len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3168         ASC_PRT_NEXT();
3169         for (i = 0; i <= ASC_MAX_TID; i++) {
3170                 len = asc_prt_line(cp, leftlen, " %c",
3171                                    (ep->
3172                                     start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3173                                    'N');
3174                 ASC_PRT_NEXT();
3175         }
3176         len = asc_prt_line(cp, leftlen, "\n");
3177         ASC_PRT_NEXT();
3178
3179         len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3180         ASC_PRT_NEXT();
3181         for (i = 0; i <= ASC_MAX_TID; i++) {
3182                 len = asc_prt_line(cp, leftlen, " %c",
3183                                    (ep->
3184                                     init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3185                                    'N');
3186                 ASC_PRT_NEXT();
3187         }
3188         len = asc_prt_line(cp, leftlen, "\n");
3189         ASC_PRT_NEXT();
3190
3191 #ifdef CONFIG_ISA
3192         if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3193                 len = asc_prt_line(cp, leftlen,
3194                                    " Host ISA DMA speed:   %d MB/S\n",
3195                                    isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3196                 ASC_PRT_NEXT();
3197         }
3198 #endif /* CONFIG_ISA */
3199
3200         return totlen;
3201 }
3202
3203 /*
3204  * asc_prt_adv_board_eeprom()
3205  *
3206  * Print board EEPROM configuration.
3207  *
3208  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3209  * cf. asc_prt_line().
3210  *
3211  * Return the number of characters copied into 'cp'. No more than
3212  * 'cplen' characters will be copied to 'cp'.
3213  */
3214 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3215 {
3216         struct asc_board *boardp = shost_priv(shost);
3217         ADV_DVC_VAR *adv_dvc_varp;
3218         int leftlen;
3219         int totlen;
3220         int len;
3221         int i;
3222         char *termstr;
3223         uchar serialstr[13];
3224         ADVEEP_3550_CONFIG *ep_3550 = NULL;
3225         ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3226         ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3227         ushort word;
3228         ushort *wordp;
3229         ushort sdtr_speed = 0;
3230
3231         adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3232         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3233                 ep_3550 = &boardp->eep_config.adv_3550_eep;
3234         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3235                 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3236         } else {
3237                 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3238         }
3239
3240         leftlen = cplen;
3241         totlen = len = 0;
3242
3243         len = asc_prt_line(cp, leftlen,
3244                            "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3245                            shost->host_no);
3246         ASC_PRT_NEXT();
3247
3248         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3249                 wordp = &ep_3550->serial_number_word1;
3250         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3251                 wordp = &ep_38C0800->serial_number_word1;
3252         } else {
3253                 wordp = &ep_38C1600->serial_number_word1;
3254         }
3255
3256         if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3257                 len =
3258                     asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3259                                  serialstr);
3260                 ASC_PRT_NEXT();
3261         } else {
3262                 len = asc_prt_line(cp, leftlen,
3263                                    " Serial Number Signature Not Present.\n");
3264                 ASC_PRT_NEXT();
3265         }
3266
3267         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3268                 len = asc_prt_line(cp, leftlen,
3269                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3270                                    ep_3550->adapter_scsi_id,
3271                                    ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3272                 ASC_PRT_NEXT();
3273         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3274                 len = asc_prt_line(cp, leftlen,
3275                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3276                                    ep_38C0800->adapter_scsi_id,
3277                                    ep_38C0800->max_host_qng,
3278                                    ep_38C0800->max_dvc_qng);
3279                 ASC_PRT_NEXT();
3280         } else {
3281                 len = asc_prt_line(cp, leftlen,
3282                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3283                                    ep_38C1600->adapter_scsi_id,
3284                                    ep_38C1600->max_host_qng,
3285                                    ep_38C1600->max_dvc_qng);
3286                 ASC_PRT_NEXT();
3287         }
3288         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3289                 word = ep_3550->termination;
3290         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3291                 word = ep_38C0800->termination_lvd;
3292         } else {
3293                 word = ep_38C1600->termination_lvd;
3294         }
3295         switch (word) {
3296         case 1:
3297                 termstr = "Low Off/High Off";
3298                 break;
3299         case 2:
3300                 termstr = "Low Off/High On";
3301                 break;
3302         case 3:
3303                 termstr = "Low On/High On";
3304                 break;
3305         default:
3306         case 0:
3307                 termstr = "Automatic";
3308                 break;
3309         }
3310
3311         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3312                 len = asc_prt_line(cp, leftlen,
3313                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3314                                    ep_3550->termination, termstr,
3315                                    ep_3550->bios_ctrl);
3316                 ASC_PRT_NEXT();
3317         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3318                 len = asc_prt_line(cp, leftlen,
3319                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3320                                    ep_38C0800->termination_lvd, termstr,
3321                                    ep_38C0800->bios_ctrl);
3322                 ASC_PRT_NEXT();
3323         } else {
3324                 len = asc_prt_line(cp, leftlen,
3325                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3326                                    ep_38C1600->termination_lvd, termstr,
3327                                    ep_38C1600->bios_ctrl);
3328                 ASC_PRT_NEXT();
3329         }
3330
3331         len = asc_prt_line(cp, leftlen, " Target ID:           ");
3332         ASC_PRT_NEXT();
3333         for (i = 0; i <= ADV_MAX_TID; i++) {
3334                 len = asc_prt_line(cp, leftlen, " %X", i);
3335                 ASC_PRT_NEXT();
3336         }
3337         len = asc_prt_line(cp, leftlen, "\n");
3338         ASC_PRT_NEXT();
3339
3340         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3341                 word = ep_3550->disc_enable;
3342         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3343                 word = ep_38C0800->disc_enable;
3344         } else {
3345                 word = ep_38C1600->disc_enable;
3346         }
3347         len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3348         ASC_PRT_NEXT();
3349         for (i = 0; i <= ADV_MAX_TID; i++) {
3350                 len = asc_prt_line(cp, leftlen, " %c",
3351                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3352                 ASC_PRT_NEXT();
3353         }
3354         len = asc_prt_line(cp, leftlen, "\n");
3355         ASC_PRT_NEXT();
3356
3357         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3358                 word = ep_3550->tagqng_able;
3359         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3360                 word = ep_38C0800->tagqng_able;
3361         } else {
3362                 word = ep_38C1600->tagqng_able;
3363         }
3364         len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3365         ASC_PRT_NEXT();
3366         for (i = 0; i <= ADV_MAX_TID; i++) {
3367                 len = asc_prt_line(cp, leftlen, " %c",
3368                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3369                 ASC_PRT_NEXT();
3370         }
3371         len = asc_prt_line(cp, leftlen, "\n");
3372         ASC_PRT_NEXT();
3373
3374         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3375                 word = ep_3550->start_motor;
3376         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3377                 word = ep_38C0800->start_motor;
3378         } else {
3379                 word = ep_38C1600->start_motor;
3380         }
3381         len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3382         ASC_PRT_NEXT();
3383         for (i = 0; i <= ADV_MAX_TID; i++) {
3384                 len = asc_prt_line(cp, leftlen, " %c",
3385                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3386                 ASC_PRT_NEXT();
3387         }
3388         len = asc_prt_line(cp, leftlen, "\n");
3389         ASC_PRT_NEXT();
3390
3391         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3392                 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3393                 ASC_PRT_NEXT();
3394                 for (i = 0; i <= ADV_MAX_TID; i++) {
3395                         len = asc_prt_line(cp, leftlen, " %c",
3396                                            (ep_3550->
3397                                             sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3398                                            'Y' : 'N');
3399                         ASC_PRT_NEXT();
3400                 }
3401                 len = asc_prt_line(cp, leftlen, "\n");
3402                 ASC_PRT_NEXT();
3403         }
3404
3405         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3406                 len = asc_prt_line(cp, leftlen, " Ultra Transfer:      ");
3407                 ASC_PRT_NEXT();
3408                 for (i = 0; i <= ADV_MAX_TID; i++) {
3409                         len = asc_prt_line(cp, leftlen, " %c",
3410                                            (ep_3550->
3411                                             ultra_able & ADV_TID_TO_TIDMASK(i))
3412                                            ? 'Y' : 'N');
3413                         ASC_PRT_NEXT();
3414                 }
3415                 len = asc_prt_line(cp, leftlen, "\n");
3416                 ASC_PRT_NEXT();
3417         }
3418
3419         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3420                 word = ep_3550->wdtr_able;
3421         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3422                 word = ep_38C0800->wdtr_able;
3423         } else {
3424                 word = ep_38C1600->wdtr_able;
3425         }
3426         len = asc_prt_line(cp, leftlen, " Wide Transfer:       ");
3427         ASC_PRT_NEXT();
3428         for (i = 0; i <= ADV_MAX_TID; i++) {
3429                 len = asc_prt_line(cp, leftlen, " %c",
3430                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3431                 ASC_PRT_NEXT();
3432         }
3433         len = asc_prt_line(cp, leftlen, "\n");
3434         ASC_PRT_NEXT();
3435
3436         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3437             adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3438                 len = asc_prt_line(cp, leftlen,
3439                                    " Synchronous Transfer Speed (Mhz):\n  ");
3440                 ASC_PRT_NEXT();
3441                 for (i = 0; i <= ADV_MAX_TID; i++) {
3442                         char *speed_str;
3443
3444                         if (i == 0) {
3445                                 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3446                         } else if (i == 4) {
3447                                 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3448                         } else if (i == 8) {
3449                                 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3450                         } else if (i == 12) {
3451                                 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3452                         }
3453                         switch (sdtr_speed & ADV_MAX_TID) {
3454                         case 0:
3455                                 speed_str = "Off";
3456                                 break;
3457                         case 1:
3458                                 speed_str = "  5";
3459                                 break;
3460                         case 2:
3461                                 speed_str = " 10";
3462                                 break;
3463                         case 3:
3464                                 speed_str = " 20";
3465                                 break;
3466                         case 4:
3467                                 speed_str = " 40";
3468                                 break;
3469                         case 5:
3470                                 speed_str = " 80";
3471                                 break;
3472                         default:
3473                                 speed_str = "Unk";
3474                                 break;
3475                         }
3476                         len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3477                         ASC_PRT_NEXT();
3478                         if (i == 7) {
3479                                 len = asc_prt_line(cp, leftlen, "\n  ");
3480                                 ASC_PRT_NEXT();
3481                         }
3482                         sdtr_speed >>= 4;
3483                 }
3484                 len = asc_prt_line(cp, leftlen, "\n");
3485                 ASC_PRT_NEXT();
3486         }
3487
3488         return totlen;
3489 }
3490
3491 /*
3492  * asc_prt_driver_conf()
3493  *
3494  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3495  * cf. asc_prt_line().
3496  *
3497  * Return the number of characters copied into 'cp'. No more than
3498  * 'cplen' characters will be copied to 'cp'.
3499  */
3500 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3501 {
3502         struct asc_board *boardp = shost_priv(shost);
3503         int leftlen;
3504         int totlen;
3505         int len;
3506         int chip_scsi_id;
3507
3508         leftlen = cplen;
3509         totlen = len = 0;
3510
3511         len = asc_prt_line(cp, leftlen,
3512                            "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3513                            shost->host_no);
3514         ASC_PRT_NEXT();
3515
3516         len = asc_prt_line(cp, leftlen,
3517                            " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3518                            shost->host_busy, shost->last_reset, shost->max_id,
3519                            shost->max_lun, shost->max_channel);
3520         ASC_PRT_NEXT();
3521
3522         len = asc_prt_line(cp, leftlen,
3523                            " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3524                            shost->unique_id, shost->can_queue, shost->this_id,
3525                            shost->sg_tablesize, shost->cmd_per_lun);
3526         ASC_PRT_NEXT();
3527
3528         len = asc_prt_line(cp, leftlen,
3529                            " unchecked_isa_dma %d, use_clustering %d\n",
3530                            shost->unchecked_isa_dma, shost->use_clustering);
3531         ASC_PRT_NEXT();
3532
3533         len = asc_prt_line(cp, leftlen,
3534                            " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3535                            boardp->flags, boardp->last_reset, jiffies,
3536                            boardp->asc_n_io_port);
3537         ASC_PRT_NEXT();
3538
3539         len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3540         ASC_PRT_NEXT();
3541
3542         if (ASC_NARROW_BOARD(boardp)) {
3543                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3544         } else {
3545                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3546         }
3547
3548         return totlen;
3549 }
3550
3551 /*
3552  * asc_prt_asc_board_info()
3553  *
3554  * Print dynamic board configuration information.
3555  *
3556  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3557  * cf. asc_prt_line().
3558  *
3559  * Return the number of characters copied into 'cp'. No more than
3560  * 'cplen' characters will be copied to 'cp'.
3561  */
3562 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3563 {
3564         struct asc_board *boardp = shost_priv(shost);
3565         int chip_scsi_id;
3566         int leftlen;
3567         int totlen;
3568         int len;
3569         ASC_DVC_VAR *v;
3570         ASC_DVC_CFG *c;
3571         int i;
3572         int renegotiate = 0;
3573
3574         v = &boardp->dvc_var.asc_dvc_var;
3575         c = &boardp->dvc_cfg.asc_dvc_cfg;
3576         chip_scsi_id = c->chip_scsi_id;
3577
3578         leftlen = cplen;
3579         totlen = len = 0;
3580
3581         len = asc_prt_line(cp, leftlen,
3582                            "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3583                            shost->host_no);
3584         ASC_PRT_NEXT();
3585
3586         len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3587                            "mcode_version 0x%x, err_code %u\n",
3588                            c->chip_version, c->mcode_date, c->mcode_version,
3589                            v->err_code);
3590         ASC_PRT_NEXT();
3591
3592         /* Current number of commands waiting for the host. */
3593         len = asc_prt_line(cp, leftlen,
3594                            " Total Command Pending: %d\n", v->cur_total_qng);
3595         ASC_PRT_NEXT();
3596
3597         len = asc_prt_line(cp, leftlen, " Command Queuing:");
3598         ASC_PRT_NEXT();
3599         for (i = 0; i <= ASC_MAX_TID; i++) {
3600                 if ((chip_scsi_id == i) ||
3601                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3602                         continue;
3603                 }
3604                 len = asc_prt_line(cp, leftlen, " %X:%c",
3605                                    i,
3606                                    (v->
3607                                     use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3608                                    'Y' : 'N');
3609                 ASC_PRT_NEXT();
3610         }
3611         len = asc_prt_line(cp, leftlen, "\n");
3612         ASC_PRT_NEXT();
3613
3614         /* Current number of commands waiting for a device. */
3615         len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3616         ASC_PRT_NEXT();
3617         for (i = 0; i <= ASC_MAX_TID; i++) {
3618                 if ((chip_scsi_id == i) ||
3619                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3620                         continue;
3621                 }
3622                 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3623                 ASC_PRT_NEXT();
3624         }
3625         len = asc_prt_line(cp, leftlen, "\n");
3626         ASC_PRT_NEXT();
3627
3628         /* Current limit on number of commands that can be sent to a device. */
3629         len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3630         ASC_PRT_NEXT();
3631         for (i = 0; i <= ASC_MAX_TID; i++) {
3632                 if ((chip_scsi_id == i) ||
3633                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3634                         continue;
3635                 }
3636                 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3637                 ASC_PRT_NEXT();
3638         }
3639         len = asc_prt_line(cp, leftlen, "\n");
3640         ASC_PRT_NEXT();
3641
3642         /* Indicate whether the device has returned queue full status. */
3643         len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3644         ASC_PRT_NEXT();
3645         for (i = 0; i <= ASC_MAX_TID; i++) {
3646                 if ((chip_scsi_id == i) ||
3647                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3648                         continue;
3649                 }
3650                 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3651                         len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3652                                            i, boardp->queue_full_cnt[i]);
3653                 } else {
3654                         len = asc_prt_line(cp, leftlen, " %X:N", i);
3655                 }
3656                 ASC_PRT_NEXT();
3657         }
3658         len = asc_prt_line(cp, leftlen, "\n");
3659         ASC_PRT_NEXT();
3660
3661         len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3662         ASC_PRT_NEXT();
3663         for (i = 0; i <= ASC_MAX_TID; i++) {
3664                 if ((chip_scsi_id == i) ||
3665                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3666                         continue;
3667                 }
3668                 len = asc_prt_line(cp, leftlen, " %X:%c",
3669                                    i,
3670                                    (v->
3671                                     sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3672                                    'N');
3673                 ASC_PRT_NEXT();
3674         }
3675         len = asc_prt_line(cp, leftlen, "\n");
3676         ASC_PRT_NEXT();
3677
3678         for (i = 0; i <= ASC_MAX_TID; i++) {
3679                 uchar syn_period_ix;
3680
3681                 if ((chip_scsi_id == i) ||
3682                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3683                     ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3684                         continue;
3685                 }
3686
3687                 len = asc_prt_line(cp, leftlen, "  %X:", i);
3688                 ASC_PRT_NEXT();
3689
3690                 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3691                         len = asc_prt_line(cp, leftlen, " Asynchronous");
3692                         ASC_PRT_NEXT();
3693                 } else {
3694                         syn_period_ix =
3695                             (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3696                                                            1);
3697
3698                         len = asc_prt_line(cp, leftlen,
3699                                            " Transfer Period Factor: %d (%d.%d Mhz),",
3700                                            v->sdtr_period_tbl[syn_period_ix],
3701                                            250 /
3702                                            v->sdtr_period_tbl[syn_period_ix],
3703                                            ASC_TENTHS(250,
3704                                                       v->
3705                                                       sdtr_period_tbl
3706                                                       [syn_period_ix]));
3707                         ASC_PRT_NEXT();
3708
3709                         len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3710                                            boardp->
3711                                            sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3712                         ASC_PRT_NEXT();
3713                 }
3714
3715                 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3716                         len = asc_prt_line(cp, leftlen, "*\n");
3717                         renegotiate = 1;
3718                 } else {
3719                         len = asc_prt_line(cp, leftlen, "\n");
3720                 }
3721                 ASC_PRT_NEXT();
3722         }
3723
3724         if (renegotiate) {
3725                 len = asc_prt_line(cp, leftlen,
3726                                    " * = Re-negotiation pending before next command.\n");
3727                 ASC_PRT_NEXT();
3728         }
3729
3730         return totlen;
3731 }
3732
3733 /*
3734  * asc_prt_adv_board_info()
3735  *
3736  * Print dynamic board configuration information.
3737  *
3738  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3739  * cf. asc_prt_line().
3740  *
3741  * Return the number of characters copied into 'cp'. No more than
3742  * 'cplen' characters will be copied to 'cp'.
3743  */
3744 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3745 {
3746         struct asc_board *boardp = shost_priv(shost);
3747         int leftlen;
3748         int totlen;
3749         int len;
3750         int i;
3751         ADV_DVC_VAR *v;
3752         ADV_DVC_CFG *c;
3753         AdvPortAddr iop_base;
3754         ushort chip_scsi_id;
3755         ushort lramword;
3756         uchar lrambyte;
3757         ushort tagqng_able;
3758         ushort sdtr_able, wdtr_able;
3759         ushort wdtr_done, sdtr_done;
3760         ushort period = 0;
3761         int renegotiate = 0;
3762
3763         v = &boardp->dvc_var.adv_dvc_var;
3764         c = &boardp->dvc_cfg.adv_dvc_cfg;
3765         iop_base = v->iop_base;
3766         chip_scsi_id = v->chip_scsi_id;
3767
3768         leftlen = cplen;
3769         totlen = len = 0;
3770
3771         len = asc_prt_line(cp, leftlen,
3772                            "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3773                            shost->host_no);
3774         ASC_PRT_NEXT();
3775
3776         len = asc_prt_line(cp, leftlen,
3777                            " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3778                            v->iop_base,
3779                            AdvReadWordRegister(iop_base,
3780                                                IOPW_SCSI_CFG1) & CABLE_DETECT,
3781                            v->err_code);
3782         ASC_PRT_NEXT();
3783
3784         len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3785                            "mcode_version 0x%x\n", c->chip_version,
3786                            c->mcode_date, c->mcode_version);
3787         ASC_PRT_NEXT();
3788
3789         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3790         len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3791         ASC_PRT_NEXT();
3792         for (i = 0; i <= ADV_MAX_TID; i++) {
3793                 if ((chip_scsi_id == i) ||
3794                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3795                         continue;
3796                 }
3797
3798                 len = asc_prt_line(cp, leftlen, " %X:%c",
3799                                    i,
3800                                    (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3801                                    'N');
3802                 ASC_PRT_NEXT();
3803         }
3804         len = asc_prt_line(cp, leftlen, "\n");
3805         ASC_PRT_NEXT();
3806
3807         len = asc_prt_line(cp, leftlen, " Queue Limit:");
3808         ASC_PRT_NEXT();
3809         for (i = 0; i <= ADV_MAX_TID; i++) {
3810                 if ((chip_scsi_id == i) ||
3811                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3812                         continue;
3813                 }
3814
3815                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3816                                 lrambyte);
3817
3818                 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3819                 ASC_PRT_NEXT();
3820         }
3821         len = asc_prt_line(cp, leftlen, "\n");
3822         ASC_PRT_NEXT();
3823
3824         len = asc_prt_line(cp, leftlen, " Command Pending:");
3825         ASC_PRT_NEXT();
3826         for (i = 0; i <= ADV_MAX_TID; i++) {
3827                 if ((chip_scsi_id == i) ||
3828                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3829                         continue;
3830                 }
3831
3832                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3833                                 lrambyte);
3834
3835                 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3836                 ASC_PRT_NEXT();
3837         }
3838         len = asc_prt_line(cp, leftlen, "\n");
3839         ASC_PRT_NEXT();
3840
3841         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3842         len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3843         ASC_PRT_NEXT();
3844         for (i = 0; i <= ADV_MAX_TID; i++) {
3845                 if ((chip_scsi_id == i) ||
3846                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3847                         continue;
3848                 }
3849
3850                 len = asc_prt_line(cp, leftlen, " %X:%c",
3851                                    i,
3852                                    (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3853                                    'N');
3854                 ASC_PRT_NEXT();
3855         }
3856         len = asc_prt_line(cp, leftlen, "\n");
3857         ASC_PRT_NEXT();
3858
3859         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3860         len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3861         ASC_PRT_NEXT();
3862         for (i = 0; i <= ADV_MAX_TID; i++) {
3863                 if ((chip_scsi_id == i) ||
3864                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3865                         continue;
3866                 }
3867
3868                 AdvReadWordLram(iop_base,
3869                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3870                                 lramword);
3871
3872                 len = asc_prt_line(cp, leftlen, " %X:%d",
3873                                    i, (lramword & 0x8000) ? 16 : 8);
3874                 ASC_PRT_NEXT();
3875
3876                 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3877                     (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3878                         len = asc_prt_line(cp, leftlen, "*");
3879                         ASC_PRT_NEXT();
3880                         renegotiate = 1;
3881                 }
3882         }
3883         len = asc_prt_line(cp, leftlen, "\n");
3884         ASC_PRT_NEXT();
3885
3886         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3887         len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
3888         ASC_PRT_NEXT();
3889         for (i = 0; i <= ADV_MAX_TID; i++) {
3890                 if ((chip_scsi_id == i) ||
3891                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3892                         continue;
3893                 }
3894
3895                 len = asc_prt_line(cp, leftlen, " %X:%c",
3896                                    i,
3897                                    (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3898                                    'N');
3899                 ASC_PRT_NEXT();
3900         }
3901         len = asc_prt_line(cp, leftlen, "\n");
3902         ASC_PRT_NEXT();
3903
3904         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3905         for (i = 0; i <= ADV_MAX_TID; i++) {
3906
3907                 AdvReadWordLram(iop_base,
3908                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3909                                 lramword);
3910                 lramword &= ~0x8000;
3911
3912                 if ((chip_scsi_id == i) ||
3913                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3914                     ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3915                         continue;
3916                 }
3917
3918                 len = asc_prt_line(cp, leftlen, "  %X:", i);
3919                 ASC_PRT_NEXT();
3920
3921                 if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3922                         len = asc_prt_line(cp, leftlen, " Asynchronous");
3923                         ASC_PRT_NEXT();
3924                 } else {
3925                         len =
3926                             asc_prt_line(cp, leftlen,
3927                                          " Transfer Period Factor: ");
3928                         ASC_PRT_NEXT();
3929
3930                         if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3931                                 len =
3932                                     asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
3933                                 ASC_PRT_NEXT();
3934                         } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3935                                 len =
3936                                     asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
3937                                 ASC_PRT_NEXT();
3938                         } else {        /* 20 Mhz or below. */
3939
3940                                 period = (((lramword >> 8) * 25) + 50) / 4;
3941
3942                                 if (period == 0) {      /* Should never happen. */
3943                                         len =
3944                                             asc_prt_line(cp, leftlen,
3945                                                          "%d (? Mhz), ");
3946                                         ASC_PRT_NEXT();
3947                                 } else {
3948                                         len = asc_prt_line(cp, leftlen,
3949                                                            "%d (%d.%d Mhz),",
3950                                                            period, 250 / period,
3951                                                            ASC_TENTHS(250,
3952                                                                       period));
3953                                         ASC_PRT_NEXT();
3954                                 }
3955                         }
3956
3957                         len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3958                                            lramword & 0x1F);
3959                         ASC_PRT_NEXT();
3960                 }
3961
3962                 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3963                         len = asc_prt_line(cp, leftlen, "*\n");
3964                         renegotiate = 1;
3965                 } else {
3966                         len = asc_prt_line(cp, leftlen, "\n");
3967                 }
3968                 ASC_PRT_NEXT();
3969         }
3970
3971         if (renegotiate) {
3972                 len = asc_prt_line(cp, leftlen,
3973                                    " * = Re-negotiation pending before next command.\n");
3974                 ASC_PRT_NEXT();
3975         }
3976
3977         return totlen;
3978 }
3979
3980 /*
3981  * asc_proc_copy()
3982  *
3983  * Copy proc information to a read buffer taking into account the current
3984  * read offset in the file and the remaining space in the read buffer.
3985  */
3986 static int
3987 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
3988               char *cp, int cplen)
3989 {
3990         int cnt = 0;
3991
3992         ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
3993                  (unsigned)offset, (unsigned)advoffset, cplen);
3994         if (offset <= advoffset) {
3995                 /* Read offset below current offset, copy everything. */
3996                 cnt = min(cplen, leftlen);
3997                 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
3998                          (ulong)curbuf, (ulong)cp, cnt);
3999                 memcpy(curbuf, cp, cnt);
4000         } else if (offset < advoffset + cplen) {
4001                 /* Read offset within current range, partial copy. */
4002                 cnt = (advoffset + cplen) - offset;
4003                 cp = (cp + cplen) - cnt;
4004                 cnt = min(cnt, leftlen);
4005                 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4006                          (ulong)curbuf, (ulong)cp, cnt);
4007                 memcpy(curbuf, cp, cnt);
4008         }
4009         return cnt;
4010 }
4011
4012 #ifdef ADVANSYS_STATS
4013 /*
4014  * asc_prt_board_stats()
4015  *
4016  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4017  * cf. asc_prt_line().
4018  *
4019  * Return the number of characters copied into 'cp'. No more than
4020  * 'cplen' characters will be copied to 'cp'.
4021  */
4022 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4023 {
4024         struct asc_board *boardp = shost_priv(shost);
4025         struct asc_stats *s = &boardp->asc_stats;
4026
4027         int leftlen = cplen;
4028         int len, totlen = 0;
4029
4030         len = asc_prt_line(cp, leftlen,
4031                            "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4032                            shost->host_no);
4033         ASC_PRT_NEXT();
4034
4035         len = asc_prt_line(cp, leftlen,
4036                            " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4037                            s->queuecommand, s->reset, s->biosparam,
4038                            s->interrupt);
4039         ASC_PRT_NEXT();
4040
4041         len = asc_prt_line(cp, leftlen,
4042                            " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4043                            s->callback, s->done, s->build_error,
4044                            s->adv_build_noreq, s->adv_build_nosg);
4045         ASC_PRT_NEXT();
4046
4047         len = asc_prt_line(cp, leftlen,
4048                            " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4049                            s->exe_noerror, s->exe_busy, s->exe_error,
4050                            s->exe_unknown);
4051         ASC_PRT_NEXT();
4052
4053         /*
4054          * Display data transfer statistics.
4055          */
4056         if (s->xfer_cnt > 0) {
4057                 len = asc_prt_line(cp, leftlen, " xfer_cnt %lu, xfer_elem %lu, ",
4058                                    s->xfer_cnt, s->xfer_elem);
4059                 ASC_PRT_NEXT();
4060
4061                 len = asc_prt_line(cp, leftlen, "xfer_bytes %lu.%01lu kb\n",
4062                                    s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
4063                 ASC_PRT_NEXT();
4064
4065                 /* Scatter gather transfer statistics */
4066                 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4067                                    s->xfer_elem / s->xfer_cnt,
4068                                    ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
4069                 ASC_PRT_NEXT();
4070
4071                 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4072                                    (s->xfer_sect / 2) / s->xfer_elem,
4073                                    ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
4074                 ASC_PRT_NEXT();
4075
4076                 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4077                                    (s->xfer_sect / 2) / s->xfer_cnt,
4078                                    ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
4079                 ASC_PRT_NEXT();
4080         }
4081
4082         return totlen;
4083 }
4084 #endif /* ADVANSYS_STATS */
4085
4086 /*
4087  * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4088  *
4089  * *buffer: I/O buffer
4090  * **start: if inout == FALSE pointer into buffer where user read should start
4091  * offset: current offset into a /proc/scsi/advansys/[0...] file
4092  * length: length of buffer
4093  * hostno: Scsi_Host host_no
4094  * inout: TRUE - user is writing; FALSE - user is reading
4095  *
4096  * Return the number of bytes read from or written to a
4097  * /proc/scsi/advansys/[0...] file.
4098  *
4099  * Note: This function uses the per board buffer 'prtbuf' which is
4100  * allocated when the board is initialized in advansys_detect(). The
4101  * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4102  * used to write to the buffer. The way asc_proc_copy() is written
4103  * if 'prtbuf' is too small it will not be overwritten. Instead the
4104  * user just won't get all the available statistics.
4105  */
4106 static int
4107 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4108                    off_t offset, int length, int inout)
4109 {
4110         struct asc_board *boardp = shost_priv(shost);
4111         char *cp;
4112         int cplen;
4113         int cnt;
4114         int totcnt;
4115         int leftlen;
4116         char *curbuf;
4117         off_t advoffset;
4118
4119         ASC_DBG(1, "begin\n");
4120
4121         /*
4122          * User write not supported.
4123          */
4124         if (inout == TRUE)
4125                 return -ENOSYS;
4126
4127         /*
4128          * User read of /proc/scsi/advansys/[0...] file.
4129          */
4130
4131         /* Copy read data starting at the beginning of the buffer. */
4132         *start = buffer;
4133         curbuf = buffer;
4134         advoffset = 0;
4135         totcnt = 0;
4136         leftlen = length;
4137
4138         /*
4139          * Get board configuration information.
4140          *
4141          * advansys_info() returns the board string from its own static buffer.
4142          */
4143         cp = (char *)advansys_info(shost);
4144         strcat(cp, "\n");
4145         cplen = strlen(cp);
4146         /* Copy board information. */
4147         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4148         totcnt += cnt;
4149         leftlen -= cnt;
4150         if (leftlen == 0) {
4151                 ASC_DBG(1, "totcnt %d\n", totcnt);
4152                 return totcnt;
4153         }
4154         advoffset += cplen;
4155         curbuf += cnt;
4156
4157         /*
4158          * Display Wide Board BIOS Information.
4159          */
4160         if (!ASC_NARROW_BOARD(boardp)) {
4161                 cp = boardp->prtbuf;
4162                 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4163                 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4164                 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4165                                   cplen);
4166                 totcnt += cnt;
4167                 leftlen -= cnt;
4168                 if (leftlen == 0) {
4169                         ASC_DBG(1, "totcnt %d\n", totcnt);
4170                         return totcnt;
4171                 }
4172                 advoffset += cplen;
4173                 curbuf += cnt;
4174         }
4175
4176         /*
4177          * Display driver information for each device attached to the board.
4178          */
4179         cp = boardp->prtbuf;
4180         cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4181         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4182         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4183         totcnt += cnt;
4184         leftlen -= cnt;
4185         if (leftlen == 0) {
4186                 ASC_DBG(1, "totcnt %d\n", totcnt);
4187                 return totcnt;
4188         }
4189         advoffset += cplen;
4190         curbuf += cnt;
4191
4192         /*
4193          * Display EEPROM configuration for the board.
4194          */
4195         cp = boardp->prtbuf;
4196         if (ASC_NARROW_BOARD(boardp)) {
4197                 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4198         } else {
4199                 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4200         }
4201         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4202         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4203         totcnt += cnt;
4204         leftlen -= cnt;
4205         if (leftlen == 0) {
4206                 ASC_DBG(1, "totcnt %d\n", totcnt);
4207                 return totcnt;
4208         }
4209         advoffset += cplen;
4210         curbuf += cnt;
4211
4212         /*
4213          * Display driver configuration and information for the board.
4214          */
4215         cp = boardp->prtbuf;
4216         cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4217         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4218         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4219         totcnt += cnt;
4220         leftlen -= cnt;
4221         if (leftlen == 0) {
4222                 ASC_DBG(1, "totcnt %d\n", totcnt);
4223                 return totcnt;
4224         }
4225         advoffset += cplen;
4226         curbuf += cnt;
4227
4228 #ifdef ADVANSYS_STATS
4229         /*
4230          * Display driver statistics for the board.
4231          */
4232         cp = boardp->prtbuf;
4233         cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4234         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4235         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4236         totcnt += cnt;
4237         leftlen -= cnt;
4238         if (leftlen == 0) {
4239                 ASC_DBG(1, "totcnt %d\n", totcnt);
4240                 return totcnt;
4241         }
4242         advoffset += cplen;
4243         curbuf += cnt;
4244 #endif /* ADVANSYS_STATS */
4245
4246         /*
4247          * Display Asc Library dynamic configuration information
4248          * for the board.
4249          */
4250         cp = boardp->prtbuf;
4251         if (ASC_NARROW_BOARD(boardp)) {
4252                 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4253         } else {
4254                 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4255         }
4256         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4257         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4258         totcnt += cnt;
4259         leftlen -= cnt;
4260         if (leftlen == 0) {
4261                 ASC_DBG(1, "totcnt %d\n", totcnt);
4262                 return totcnt;
4263         }
4264         advoffset += cplen;
4265         curbuf += cnt;
4266
4267         ASC_DBG(1, "totcnt %d\n", totcnt);
4268
4269         return totcnt;
4270 }
4271 #endif /* CONFIG_PROC_FS */
4272
4273 static void asc_scsi_done(struct scsi_cmnd *scp)
4274 {
4275         scsi_dma_unmap(scp);
4276         ASC_STATS(scp->device->host, done);
4277         scp->scsi_done(scp);
4278 }
4279
4280 static void AscSetBank(PortAddr iop_base, uchar bank)
4281 {
4282         uchar val;
4283
4284         val = AscGetChipControl(iop_base) &
4285             (~
4286              (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4287               CC_CHIP_RESET));
4288         if (bank == 1) {
4289                 val |= CC_BANK_ONE;
4290         } else if (bank == 2) {
4291                 val |= CC_DIAG | CC_BANK_ONE;
4292         } else {
4293                 val &= ~CC_BANK_ONE;
4294         }
4295         AscSetChipControl(iop_base, val);
4296 }
4297
4298 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4299 {
4300         AscSetBank(iop_base, 1);
4301         AscWriteChipIH(iop_base, ins_code);
4302         AscSetBank(iop_base, 0);
4303 }
4304
4305 static int AscStartChip(PortAddr iop_base)
4306 {
4307         AscSetChipControl(iop_base, 0);
4308         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4309                 return (0);
4310         }
4311         return (1);
4312 }
4313
4314 static int AscStopChip(PortAddr iop_base)
4315 {
4316         uchar cc_val;
4317
4318         cc_val =
4319             AscGetChipControl(iop_base) &
4320             (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4321         AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4322         AscSetChipIH(iop_base, INS_HALT);
4323         AscSetChipIH(iop_base, INS_RFLAG_WTM);
4324         if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4325                 return (0);
4326         }
4327         return (1);
4328 }
4329
4330 static int AscIsChipHalted(PortAddr iop_base)
4331 {
4332         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4333                 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4334                         return (1);
4335                 }
4336         }
4337         return (0);
4338 }
4339
4340 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4341 {
4342         PortAddr iop_base;
4343         int i = 10;
4344
4345         iop_base = asc_dvc->iop_base;
4346         while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4347                && (i-- > 0)) {
4348                 mdelay(100);
4349         }
4350         AscStopChip(iop_base);
4351         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4352         udelay(60);
4353         AscSetChipIH(iop_base, INS_RFLAG_WTM);
4354         AscSetChipIH(iop_base, INS_HALT);
4355         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4356         AscSetChipControl(iop_base, CC_HALT);
4357         mdelay(200);
4358         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4359         AscSetChipStatus(iop_base, 0);
4360         return (AscIsChipHalted(iop_base));
4361 }
4362
4363 static int AscFindSignature(PortAddr iop_base)
4364 {
4365         ushort sig_word;
4366
4367         ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4368                  iop_base, AscGetChipSignatureByte(iop_base));
4369         if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4370                 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4371                          iop_base, AscGetChipSignatureWord(iop_base));
4372                 sig_word = AscGetChipSignatureWord(iop_base);
4373                 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4374                     (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4375                         return (1);
4376                 }
4377         }
4378         return (0);
4379 }
4380
4381 static void AscEnableInterrupt(PortAddr iop_base)
4382 {
4383         ushort cfg;
4384
4385         cfg = AscGetChipCfgLsw(iop_base);
4386         AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4387 }
4388
4389 static void AscDisableInterrupt(PortAddr iop_base)
4390 {
4391         ushort cfg;
4392
4393         cfg = AscGetChipCfgLsw(iop_base);
4394         AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4395 }
4396
4397 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4398 {
4399         unsigned char byte_data;
4400         unsigned short word_data;
4401
4402         if (isodd_word(addr)) {
4403                 AscSetChipLramAddr(iop_base, addr - 1);
4404                 word_data = AscGetChipLramData(iop_base);
4405                 byte_data = (word_data >> 8) & 0xFF;
4406         } else {
4407                 AscSetChipLramAddr(iop_base, addr);
4408                 word_data = AscGetChipLramData(iop_base);
4409                 byte_data = word_data & 0xFF;
4410         }
4411         return byte_data;
4412 }
4413
4414 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4415 {
4416         ushort word_data;
4417
4418         AscSetChipLramAddr(iop_base, addr);
4419         word_data = AscGetChipLramData(iop_base);
4420         return (word_data);
4421 }
4422
4423 #if CC_VERY_LONG_SG_LIST
4424 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4425 {
4426         ushort val_low, val_high;
4427         ASC_DCNT dword_data;
4428
4429         AscSetChipLramAddr(iop_base, addr);
4430         val_low = AscGetChipLramData(iop_base);
4431         val_high = AscGetChipLramData(iop_base);
4432         dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4433         return (dword_data);
4434 }
4435 #endif /* CC_VERY_LONG_SG_LIST */
4436
4437 static void
4438 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4439 {
4440         int i;
4441
4442         AscSetChipLramAddr(iop_base, s_addr);
4443         for (i = 0; i < words; i++) {
4444                 AscSetChipLramData(iop_base, set_wval);
4445         }
4446 }
4447
4448 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4449 {
4450         AscSetChipLramAddr(iop_base, addr);
4451         AscSetChipLramData(iop_base, word_val);
4452 }
4453
4454 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4455 {
4456         ushort word_data;
4457
4458         if (isodd_word(addr)) {
4459                 addr--;
4460                 word_data = AscReadLramWord(iop_base, addr);
4461                 word_data &= 0x00FF;
4462                 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4463         } else {
4464                 word_data = AscReadLramWord(iop_base, addr);
4465                 word_data &= 0xFF00;
4466                 word_data |= ((ushort)byte_val & 0x00FF);
4467         }
4468         AscWriteLramWord(iop_base, addr, word_data);
4469 }
4470
4471 /*
4472  * Copy 2 bytes to LRAM.
4473  *
4474  * The source data is assumed to be in little-endian order in memory
4475  * and is maintained in little-endian order when written to LRAM.
4476  */
4477 static void
4478 AscMemWordCopyPtrToLram(PortAddr iop_base,
4479                         ushort s_addr, uchar *s_buffer, int words)
4480 {
4481         int i;
4482
4483         AscSetChipLramAddr(iop_base, s_addr);
4484         for (i = 0; i < 2 * words; i += 2) {
4485                 /*
4486                  * On a little-endian system the second argument below
4487                  * produces a little-endian ushort which is written to
4488                  * LRAM in little-endian order. On a big-endian system
4489                  * the second argument produces a big-endian ushort which
4490                  * is "transparently" byte-swapped by outpw() and written
4491                  * in little-endian order to LRAM.
4492                  */
4493                 outpw(iop_base + IOP_RAM_DATA,
4494                       ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4495         }
4496 }
4497
4498 /*
4499  * Copy 4 bytes to LRAM.
4500  *
4501  * The source data is assumed to be in little-endian order in memory
4502  * and is maintained in little-endian order when writen to LRAM.
4503  */
4504 static void
4505 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4506                          ushort s_addr, uchar *s_buffer, int dwords)
4507 {
4508         int i;
4509
4510         AscSetChipLramAddr(iop_base, s_addr);
4511         for (i = 0; i < 4 * dwords; i += 4) {
4512                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
4513                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
4514         }
4515 }
4516
4517 /*
4518  * Copy 2 bytes from LRAM.
4519  *
4520  * The source data is assumed to be in little-endian order in LRAM
4521  * and is maintained in little-endian order when written to memory.
4522  */
4523 static void
4524 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4525                           ushort s_addr, uchar *d_buffer, int words)
4526 {
4527         int i;
4528         ushort word;
4529
4530         AscSetChipLramAddr(iop_base, s_addr);
4531         for (i = 0; i < 2 * words; i += 2) {
4532                 word = inpw(iop_base + IOP_RAM_DATA);
4533                 d_buffer[i] = word & 0xff;
4534                 d_buffer[i + 1] = (word >> 8) & 0xff;
4535         }
4536 }
4537
4538 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4539 {
4540         ASC_DCNT sum;
4541         int i;
4542
4543         sum = 0L;
4544         for (i = 0; i < words; i++, s_addr += 2) {
4545                 sum += AscReadLramWord(iop_base, s_addr);
4546         }
4547         return (sum);
4548 }
4549
4550 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4551 {
4552         uchar i;
4553         ushort s_addr;
4554         PortAddr iop_base;
4555         ushort warn_code;
4556
4557         iop_base = asc_dvc->iop_base;
4558         warn_code = 0;
4559         AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4560                           (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4561                                     64) >> 1));
4562         i = ASC_MIN_ACTIVE_QNO;
4563         s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4564         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4565                          (uchar)(i + 1));
4566         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4567                          (uchar)(asc_dvc->max_total_qng));
4568         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4569                          (uchar)i);
4570         i++;
4571         s_addr += ASC_QBLK_SIZE;
4572         for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4573                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4574                                  (uchar)(i + 1));
4575                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4576                                  (uchar)(i - 1));
4577                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4578                                  (uchar)i);
4579         }
4580         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4581                          (uchar)ASC_QLINK_END);
4582         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4583                          (uchar)(asc_dvc->max_total_qng - 1));
4584         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4585                          (uchar)asc_dvc->max_total_qng);
4586         i++;
4587         s_addr += ASC_QBLK_SIZE;
4588         for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4589              i++, s_addr += ASC_QBLK_SIZE) {
4590                 AscWriteLramByte(iop_base,
4591                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4592                 AscWriteLramByte(iop_base,
4593                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4594                 AscWriteLramByte(iop_base,
4595                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4596         }
4597         return warn_code;
4598 }
4599
4600 static ASC_DCNT
4601 AscLoadMicroCode(PortAddr iop_base,
4602                  ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4603 {
4604         ASC_DCNT chksum;
4605         ushort mcode_word_size;
4606         ushort mcode_chksum;
4607
4608         /* Write the microcode buffer starting at LRAM address 0. */
4609         mcode_word_size = (ushort)(mcode_size >> 1);
4610         AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4611         AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4612
4613         chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4614         ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4615         mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4616                                                  (ushort)ASC_CODE_SEC_BEG,
4617                                                  (ushort)((mcode_size -
4618                                                            s_addr - (ushort)
4619                                                            ASC_CODE_SEC_BEG) /
4620                                                           2));
4621         ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4622         AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4623         AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4624         return chksum;
4625 }
4626
4627 /* Microcode buffer is kept after initialization for error recovery. */
4628 static uchar _asc_mcode_buf[] = {
4629         0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4630         0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4631         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4632         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4633         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4634         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4635         0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4636         0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4637         0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4638         0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4639         0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4640         0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4641         0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4642         0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4643         0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4644         0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4645         0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4646         0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4647         0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4648         0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4649         0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4650         0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4651         0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4652         0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4653         0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4654         0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4655         0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4656         0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4657         0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4658         0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4659         0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4660         0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4661         0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4662         0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4663         0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4664         0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4665         0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4666         0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4667         0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4668         0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4669         0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4670         0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4671         0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4672         0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4673         0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4674         0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4675         0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4676         0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4677         0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4678         0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4679         0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4680         0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4681         0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4682         0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4683         0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4684         0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4685         0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4686         0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4687         0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4688         0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4689         0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4690         0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4691         0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4692         0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4693         0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4694         0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4695         0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4696         0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4697         0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4698         0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4699         0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4700         0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4701         0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4702         0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4703         0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4704         0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4705         0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4706         0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4707         0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4708         0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4709         0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4710         0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4711         0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4712         0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4713         0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4714         0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4715         0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4716         0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4717         0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4718         0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4719         0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4720         0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4721         0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4722         0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4723         0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4724         0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4725         0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4726         0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4727         0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4728         0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4729         0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4730         0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4731         0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4732         0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4733         0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4734         0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4735         0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4736         0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4737         0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4738         0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4739         0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4740         0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4741         0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4742         0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4743         0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4744         0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4745         0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4746         0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4747         0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4748         0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4749         0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4750         0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
4751         0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
4752         0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
4753         0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
4754         0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
4755         0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
4756         0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
4757         0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
4758         0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
4759         0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
4760         0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
4761         0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
4762         0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
4763         0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
4764         0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
4765         0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
4766         0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
4767         0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
4768         0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
4769         0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
4770         0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
4771         0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
4772         0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
4773         0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
4774         0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
4775         0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
4776         0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
4777         0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
4778         0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
4779         0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
4780         0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
4781         0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
4782         0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
4783         0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
4784         0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
4785         0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
4786         0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
4787         0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
4788         0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
4789         0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
4790         0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
4791         0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
4792         0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
4793         0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
4794         0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
4795         0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
4796         0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
4797         0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
4798         0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
4799         0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
4800         0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
4801         0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
4802         0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
4803         0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
4804         0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
4805         0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
4806         0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
4807         0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
4808         0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
4809         0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
4810         0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
4811         0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
4812         0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
4813         0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
4814         0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
4815         0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
4816         0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
4817         0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
4818         0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
4819         0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
4820         0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
4821 };
4822
4823 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
4824 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
4825
4826 /* Microcode buffer is kept after initialization for error recovery. */
4827 static unsigned char _adv_asc3550_buf[] = {
4828         0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
4829         0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
4830         0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
4831         0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
4832         0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
4833         0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
4834         0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
4835         0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
4836         0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
4837         0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
4838         0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
4839         0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
4840         0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
4841         0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
4842         0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
4843         0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
4844         0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
4845         0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
4846         0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
4847         0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
4848         0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
4849         0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
4850         0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
4851         0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
4852         0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
4853         0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
4854         0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
4855         0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
4856         0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
4857         0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
4858         0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
4859         0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
4860         0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
4861         0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
4862         0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
4863         0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
4864         0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
4865         0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
4866         0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
4867         0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
4868         0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
4869         0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
4870         0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
4871         0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
4872         0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
4873         0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
4874         0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
4875         0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
4876         0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
4877         0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
4878         0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
4879         0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
4880         0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
4881         0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
4882         0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
4883         0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
4884         0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
4885         0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02,
4886         0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02,
4887         0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
4888         0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
4889         0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10,
4890         0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e, 0x02, 0x29, 0x14, 0x4d,
4891         0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd,
4892         0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
4893         0x58, 0x1c, 0x17, 0x06, 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0,
4894         0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe, 0x5a, 0x1c, 0xea, 0xfe,
4895         0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f,
4896         0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe,
4897         0x69, 0x10, 0x17, 0x06, 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d,
4898         0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe, 0x52, 0x16, 0x09, 0x4a,
4899         0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40,
4900         0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41,
4901         0x58, 0x0a, 0x99, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03,
4902         0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02, 0xe8, 0x27, 0xf8, 0xfe,
4903         0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b,
4904         0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0,
4905         0xfe, 0x56, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0,
4906         0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x64, 0x03, 0xeb, 0x0f,
4907         0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04,
4908         0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40,
4909         0x01, 0x0e, 0xac, 0x75, 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2,
4910         0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe, 0x92, 0x03, 0xec, 0x11,
4911         0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4,
4912         0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe,
4913         0x0a, 0xf0, 0xfe, 0x7a, 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe,
4914         0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, 0xd1,
4915         0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c,
4916         0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3,
4917         0x0a, 0xca, 0x01, 0x0e, 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28,
4918         0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02,
4919         0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f,
4920         0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
4921         0x12, 0x2b, 0xff, 0x02, 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04,
4922         0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5, 0xfe, 0x4c, 0x44, 0xfe,
4923         0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
4924         0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d,
4925         0xfe, 0x2a, 0x13, 0x2f, 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c,
4926         0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86, 0x09, 0x04, 0x1d, 0xfe,
4927         0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12,
4928         0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe,
4929         0x70, 0x0c, 0x02, 0x22, 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90,
4930         0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29, 0xfe, 0x42, 0x5b, 0x67,
4931         0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4,
4932         0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a,
4933         0xfe, 0x70, 0x12, 0x49, 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2,
4934         0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31, 0xe4, 0x6a, 0x49, 0x04,
4935         0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12,
4936         0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05,
4937         0x11, 0xfe, 0xe3, 0x00, 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05,
4938         0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24, 0xfe, 0x21, 0x00, 0xa1,
4939         0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08,
4940         0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01,
4941         0x86, 0x24, 0x06, 0x12, 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d,
4942         0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b,
4943         0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe,
4944         0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13,
4945         0x47, 0x01, 0xa7, 0x26, 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19,
4946         0xfe, 0x02, 0x12, 0x5f, 0x01, 0xfe, 0xaa, 0x14, 0x1f, 0xfe, 0xfe, 0x05,
4947         0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x50, 0xb4, 0x0c,
4948         0x50, 0x05, 0xc6, 0x28, 0xfe, 0x62, 0x12, 0x05, 0x3f, 0x28, 0xfe, 0x5a,
4949         0x13, 0x01, 0xfe, 0x14, 0x18, 0x01, 0xfe, 0x66, 0x18, 0xfe, 0x43, 0x48,
4950         0xb7, 0x19, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d,
4951         0x85, 0xb7, 0x69, 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x72, 0x06, 0x49, 0x04,
4952         0x1b, 0xdf, 0x89, 0x0a, 0x4d, 0x01, 0xfe, 0xd8, 0x14, 0x1f, 0xfe, 0x68,
4953         0x06, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x3f, 0xb4,
4954         0x0c, 0x3f, 0x17, 0x06, 0x01, 0xa7, 0xec, 0x72, 0x70, 0x01, 0x6e, 0x87,
4955         0x11, 0xfe, 0xe2, 0x00, 0x01, 0x08, 0x25, 0x32, 0xfe, 0x0a, 0xf0, 0xfe,
4956         0xa6, 0x06, 0x8c, 0xfe, 0x5c, 0x07, 0xfe, 0x06, 0xf0, 0xfe, 0x64, 0x07,
4957         0x8d, 0x81, 0x02, 0x22, 0x09, 0x04, 0x0b, 0xfe, 0x2e, 0x12, 0x15, 0x1a,
4958         0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00,
4959         0x01, 0x08, 0xfe, 0x99, 0xa4, 0x01, 0x08, 0x15, 0x00, 0x02, 0xfe, 0x32,
4960         0x08, 0x61, 0x04, 0x1b, 0xfe, 0x38, 0x12, 0x09, 0x04, 0x1b, 0x6e, 0x15,
4961         0xfe, 0x1b, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01,
4962         0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x06, 0x01, 0x08, 0x15, 0x00, 0x02,
4963         0xd9, 0x66, 0x4c, 0xfe, 0x3a, 0x55, 0x5f, 0xfe, 0x9a, 0x81, 0x4b, 0x1d,
4964         0xba, 0xfe, 0x32, 0x07, 0x0a, 0x1d, 0xfe, 0x09, 0x6f, 0xaf, 0xfe, 0xca,
4965         0x45, 0xfe, 0x32, 0x12, 0x62, 0x2c, 0x85, 0x66, 0x7b, 0x01, 0x08, 0x25,
4966         0x32, 0xfe, 0x0a, 0xf0, 0xfe, 0x32, 0x07, 0x8d, 0x81, 0x8c, 0xfe, 0x5c,
4967         0x07, 0x02, 0x22, 0x01, 0x43, 0x02, 0xfe, 0x8a, 0x06, 0x15, 0x19, 0x02,
4968         0xfe, 0x8a, 0x06, 0xfe, 0x9c, 0xf7, 0xd4, 0xfe, 0x2c, 0x90, 0xfe, 0xae,
4969         0x90, 0x77, 0xfe, 0xca, 0x07, 0x0c, 0x54, 0x18, 0x55, 0x09, 0x4a, 0x6a,
4970         0x35, 0x1e, 0x20, 0x07, 0x10, 0xfe, 0x0e, 0x12, 0x74, 0xfe, 0x80, 0x80,
4971         0x37, 0x20, 0x63, 0x27, 0xfe, 0x06, 0x10, 0xfe, 0x83, 0xe7, 0xc4, 0xa1,
4972         0xfe, 0x03, 0x40, 0x09, 0x4a, 0x4f, 0x35, 0x01, 0xa8, 0xad, 0xfe, 0x1f,
4973         0x40, 0x12, 0x58, 0x01, 0xa5, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe,
4974         0x44, 0x51, 0xfe, 0xc6, 0x51, 0x83, 0xfb, 0xfe, 0x8a, 0x90, 0x0c, 0x52,
4975         0x18, 0x53, 0xfe, 0x0c, 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe,
4976         0xc2, 0x50, 0x0c, 0x39, 0x18, 0x3a, 0xfe, 0x4a, 0x10, 0x09, 0x04, 0x6a,
4977         0xfe, 0x2a, 0x12, 0xfe, 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x54, 0x18,
4978         0x55, 0x09, 0x04, 0x4f, 0x85, 0x01, 0xa8, 0xfe, 0x1f, 0x80, 0x12, 0x58,
4979         0xfe, 0x44, 0x90, 0xfe, 0xc6, 0x90, 0x0c, 0x56, 0x18, 0x57, 0xfb, 0xfe,
4980         0x8a, 0x90, 0x0c, 0x52, 0x18, 0x53, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90,
4981         0x0c, 0x39, 0x18, 0x3a, 0x0c, 0x38, 0x18, 0x4e, 0x09, 0x4a, 0x19, 0x35,
4982         0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x48, 0x08, 0xfe, 0x9e, 0xf0,
4983         0xfe, 0x5c, 0x08, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0xfe, 0x80,
4984         0x08, 0xb9, 0xfe, 0x9e, 0x08, 0x8c, 0xfe, 0x74, 0x08, 0xfe, 0x06, 0xf0,
4985         0xfe, 0x7a, 0x08, 0x8d, 0x81, 0x02, 0x22, 0x01, 0x43, 0xfe, 0xc9, 0x10,
4986         0x15, 0x19, 0xfe, 0xc9, 0x10, 0x61, 0x04, 0x06, 0xfe, 0x10, 0x12, 0x61,
4987         0x04, 0x0b, 0x45, 0x09, 0x04, 0x0b, 0xfe, 0x68, 0x12, 0xfe, 0x2e, 0x1c,
4988         0x02, 0xfe, 0x24, 0x0a, 0x61, 0x04, 0x06, 0x45, 0x61, 0x04, 0x0b, 0xfe,
4989         0x52, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0x1e, 0x09, 0xfe,
4990         0xac, 0xf0, 0xfe, 0xbe, 0x08, 0xfe, 0x8a, 0x10, 0xaa, 0xfe, 0xf3, 0x10,
4991         0xfe, 0xad, 0xf0, 0xfe, 0xca, 0x08, 0x02, 0xfe, 0x24, 0x0a, 0xab, 0xfe,
4992         0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0x9d, 0xe9, 0x1c, 0xfe, 0x00, 0xfe, 0xfe,
4993         0x1c, 0x12, 0xb5, 0xfe, 0xd2, 0xf0, 0x9d, 0xfe, 0x76, 0x18, 0x1c, 0x1a,
4994         0x16, 0x9d, 0x05, 0xcb, 0x1c, 0x06, 0x16, 0x9d, 0xb8, 0x6d, 0xb9, 0x6d,
4995         0xaa, 0xab, 0xfe, 0xb1, 0x10, 0x70, 0x5e, 0x2b, 0x14, 0x92, 0x01, 0x33,
4996         0x0f, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x5a, 0x0f, 0x7c, 0x02, 0x5a,
4997         0xfe, 0x74, 0x18, 0x1c, 0xfe, 0x00, 0xf8, 0x16, 0x6d, 0x67, 0x1b, 0x01,
4998         0xfe, 0x44, 0x0d, 0x3b, 0x01, 0xe6, 0x1e, 0x27, 0x74, 0x67, 0x1a, 0x02,
4999         0x6d, 0x09, 0x04, 0x0b, 0x21, 0xfe, 0x06, 0x0a, 0x09, 0x04, 0x6a, 0xfe,
5000         0x82, 0x12, 0x09, 0x04, 0x19, 0xfe, 0x66, 0x13, 0x1e, 0x58, 0xac, 0xfc,
5001         0xfe, 0x83, 0x80, 0xfe, 0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91,
5002         0xfe, 0x86, 0x91, 0x63, 0x27, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x77,
5003         0xd7, 0x05, 0x54, 0x31, 0x55, 0x0c, 0x7b, 0x18, 0x7c, 0xbe, 0x54, 0xbf,
5004         0x55, 0x01, 0xa8, 0xad, 0x63, 0x27, 0x12, 0x58, 0xc0, 0x38, 0xc1, 0x4e,
5005         0x79, 0x56, 0x68, 0x57, 0xf4, 0xf5, 0xfe, 0x04, 0xfa, 0x38, 0xfe, 0x05,
5006         0xfa, 0x4e, 0x01, 0xa5, 0xa2, 0x23, 0x0c, 0x7b, 0x0c, 0x7c, 0x79, 0x56,
5007         0x68, 0x57, 0xfe, 0x12, 0x10, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x79, 0x39,
5008         0x68, 0x3a, 0x09, 0x04, 0xfe, 0xf7, 0x00, 0x35, 0x05, 0x52, 0x31, 0x53,
5009         0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59,
5010         0x02, 0x6d, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x09, 0x04, 0xfe, 0xf7, 0x00,
5011         0x35, 0xfe, 0x3a, 0x55, 0xfe, 0x19, 0x81, 0x5f, 0xfe, 0x10, 0x90, 0xfe,
5012         0x92, 0x90, 0xfe, 0xd7, 0x10, 0x2f, 0x07, 0x9b, 0x16, 0xfe, 0xc6, 0x08,
5013         0x11, 0x9b, 0x09, 0x04, 0x0b, 0xfe, 0x14, 0x13, 0x05, 0x39, 0x31, 0x3a,
5014         0x77, 0xfe, 0xc6, 0x08, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x02, 0x6d,
5015         0x23, 0x47, 0xfe, 0x19, 0x80, 0xde, 0x09, 0x04, 0x0b, 0xfe, 0x1a, 0x12,
5016         0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41, 0xe9, 0xb5, 0xfe, 0xd1, 0xf0, 0xd9,
5017         0x14, 0x7a, 0x01, 0x33, 0x0f, 0xfe, 0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe,
5018         0x6c, 0x19, 0xbe, 0x39, 0xfe, 0xed, 0x19, 0xbf, 0x3a, 0xfe, 0x0c, 0x51,
5019         0xfe, 0x8e, 0x51, 0xe9, 0x1c, 0xfe, 0x00, 0xff, 0x34, 0xfe, 0x74, 0x10,
5020         0xb5, 0xfe, 0xd2, 0xf0, 0xfe, 0xb2, 0x0a, 0xfe, 0x76, 0x18, 0x1c, 0x1a,
5021         0x84, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0x08, 0x13, 0x0f, 0xfe, 0x16, 0x00,
5022         0x02, 0x5a, 0xfe, 0xd1, 0xf0, 0xfe, 0xc4, 0x0a, 0x14, 0x7a, 0x01, 0x33,
5023         0x0f, 0xfe, 0x17, 0x00, 0xfe, 0x42, 0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xca,
5024         0x0a, 0xfe, 0x3c, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xd6, 0x0a, 0x0f, 0xfe,
5025         0x22, 0x00, 0x02, 0x5a, 0xfe, 0xcb, 0xf0, 0xfe, 0xe2, 0x0a, 0x0f, 0xfe,
5026         0x24, 0x00, 0x02, 0x5a, 0xfe, 0xd0, 0xf0, 0xfe, 0xec, 0x0a, 0x0f, 0x93,
5027         0xdc, 0xfe, 0xcf, 0xf0, 0xfe, 0xf6, 0x0a, 0x0f, 0x4c, 0xfe, 0x10, 0x10,
5028         0xfe, 0xcc, 0xf0, 0xd9, 0x61, 0x04, 0x19, 0x3b, 0x0f, 0xfe, 0x12, 0x00,
5029         0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x0c, 0x0b, 0xfe, 0x9e, 0xf0,
5030         0xfe, 0x20, 0x0b, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0x22, 0xb9,
5031         0x22, 0x2a, 0xec, 0x65, 0xfe, 0x2c, 0x0b, 0x25, 0x32, 0x8c, 0xfe, 0x48,
5032         0x0b, 0x8d, 0x81, 0xb8, 0xd4, 0xb9, 0xd4, 0x02, 0x22, 0x01, 0x43, 0xfe,
5033         0xdb, 0x10, 0x11, 0xfe, 0xe8, 0x00, 0xaa, 0xab, 0x70, 0xbc, 0x7d, 0xbd,
5034         0x7f, 0xfe, 0x89, 0xf0, 0x22, 0x30, 0x2e, 0xd8, 0xbc, 0x7d, 0xbd, 0x7f,
5035         0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd6, 0xb1, 0x45, 0x0f, 0xfe, 0x42,
5036         0x00, 0x02, 0x5a, 0x78, 0x06, 0xfe, 0x81, 0x49, 0x16, 0xfe, 0x38, 0x0c,
5037         0x09, 0x04, 0x0b, 0xfe, 0x44, 0x13, 0x0f, 0x00, 0x4b, 0x0b, 0xfe, 0x54,
5038         0x12, 0x4b, 0xfe, 0x28, 0x00, 0x21, 0xfe, 0xa6, 0x0c, 0x0a, 0x40, 0x01,
5039         0x0e, 0x07, 0x00, 0x5d, 0x3e, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01,
5040         0xe7, 0x01, 0xe8, 0x0a, 0x99, 0x01, 0xfe, 0x32, 0x0e, 0x59, 0x11, 0x2d,
5041         0x01, 0x6f, 0x02, 0x29, 0x0f, 0xfe, 0x44, 0x00, 0x4b, 0x0b, 0xdf, 0x3e,
5042         0x0b, 0xfe, 0xb4, 0x10, 0x01, 0x86, 0x3e, 0x0b, 0xfe, 0xaa, 0x10, 0x01,
5043         0x86, 0xfe, 0x19, 0x82, 0xfe, 0x34, 0x46, 0xa3, 0x3e, 0x0b, 0x0f, 0xfe,
5044         0x43, 0x00, 0xfe, 0x96, 0x10, 0x09, 0x4a, 0x0b, 0x35, 0x01, 0xe7, 0x01,
5045         0xe8, 0x59, 0x11, 0x2d, 0x01, 0x6f, 0x67, 0x0b, 0x59, 0x3c, 0x8a, 0x02,
5046         0xfe, 0x2a, 0x03, 0x09, 0x04, 0x0b, 0x84, 0x3e, 0x0b, 0x0f, 0x00, 0xfe,
5047         0x5c, 0x10, 0x61, 0x04, 0x1b, 0xfe, 0x58, 0x12, 0x09, 0x04, 0x1b, 0xfe,
5048         0x50, 0x13, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x5c, 0x0c, 0xfe,
5049         0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x62, 0x0c, 0x09, 0x4a, 0x1b, 0x35,
5050         0xfe, 0xa9, 0x10, 0x0f, 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0b, 0x5f,
5051         0x5c, 0x0f, 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x0f, 0xfe, 0x47, 0x00,
5052         0xa1, 0x0f, 0xfe, 0x41, 0x00, 0xa0, 0x0f, 0xfe, 0x24, 0x00, 0x87, 0xaa,
5053         0xab, 0x70, 0x05, 0x6b, 0x28, 0x21, 0xd1, 0x5f, 0xfe, 0x04, 0xe6, 0x1b,
5054         0xfe, 0x9d, 0x41, 0xfe, 0x1c, 0x42, 0x59, 0x01, 0xda, 0x02, 0x29, 0xea,
5055         0x14, 0x0b, 0x37, 0x95, 0xa9, 0x14, 0xfe, 0x31, 0x00, 0x37, 0x97, 0x01,
5056         0xfe, 0x54, 0x0f, 0x02, 0xd0, 0x3c, 0xfe, 0x06, 0xec, 0xc9, 0xee, 0x3e,
5057         0x1d, 0xfe, 0xce, 0x45, 0x34, 0x3c, 0xfe, 0x06, 0xea, 0xc9, 0xfe, 0x47,
5058         0x4b, 0x89, 0xfe, 0x75, 0x57, 0x05, 0x51, 0xfe, 0x98, 0x56, 0xfe, 0x38,
5059         0x12, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x44, 0x48, 0x46, 0x09, 0x04, 0x1d,
5060         0xfe, 0x1a, 0x13, 0x0a, 0x40, 0x01, 0x0e, 0x47, 0xfe, 0x41, 0x58, 0x0a,
5061         0x99, 0x01, 0x0e, 0xfe, 0x49, 0x54, 0x8e, 0xfe, 0x2a, 0x0d, 0x02, 0xfe,
5062         0x2a, 0x03, 0x0a, 0x51, 0xfe, 0xee, 0x14, 0xee, 0x3e, 0x1d, 0xfe, 0xce,
5063         0x45, 0x34, 0x3c, 0xfe, 0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x29, 0x1e,
5064         0x20, 0x07, 0x10, 0xfe, 0x9e, 0x12, 0x23, 0x12, 0x4d, 0x12, 0x94, 0x12,
5065         0xce, 0x1e, 0x2d, 0x47, 0x37, 0x2d, 0xb1, 0xe0, 0xfe, 0xbc, 0xf0, 0xfe,
5066         0xec, 0x0d, 0x13, 0x06, 0x12, 0x4d, 0x01, 0xfe, 0xe2, 0x15, 0x05, 0xfe,
5067         0x38, 0x01, 0x31, 0xfe, 0x3a, 0x01, 0x77, 0xfe, 0xf0, 0x0d, 0xfe, 0x02,
5068         0xec, 0xce, 0x62, 0x00, 0x5d, 0xfe, 0x04, 0xec, 0x20, 0x46, 0xfe, 0x05,
5069         0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x52, 0x16, 0xfb, 0xfe, 0x48, 0xf4,
5070         0x0d, 0xfe, 0x18, 0x13, 0xaf, 0xfe, 0x02, 0xea, 0xce, 0x62, 0x7a, 0xfe,
5071         0xc5, 0x13, 0x14, 0x1b, 0x37, 0x95, 0xa9, 0x5c, 0x05, 0xfe, 0x38, 0x01,
5072         0x1c, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x05, 0xfe, 0x3a, 0x01,
5073         0x0c, 0xfe, 0x62, 0x01, 0x3d, 0x12, 0x20, 0x24, 0x06, 0x12, 0x2d, 0x11,
5074         0x2d, 0x8a, 0x13, 0x06, 0x03, 0x23, 0x03, 0x1e, 0x4d, 0xfe, 0xf7, 0x12,
5075         0x1e, 0x94, 0xac, 0x12, 0x94, 0x07, 0x7a, 0xfe, 0x71, 0x13, 0xfe, 0x24,
5076         0x1c, 0x14, 0x1a, 0x37, 0x95, 0xa9, 0xfe, 0xd9, 0x10, 0xb6, 0xfe, 0x03,
5077         0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xb6, 0xfe, 0x03, 0xdc,
5078         0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x23,
5079         0xfe, 0x00, 0xcc, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x75, 0x03, 0x09, 0x04,
5080         0x4c, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13,
5081         0xfe, 0x1e, 0x80, 0xe1, 0xfe, 0x1d, 0x80, 0xa4, 0xfe, 0x0c, 0x90, 0xfe,
5082         0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xa3, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
5083         0x0b, 0xfe, 0x3c, 0x50, 0xa0, 0x01, 0xfe, 0x82, 0x16, 0x2f, 0x07, 0x2d,
5084         0xe0, 0x01, 0xfe, 0xbc, 0x15, 0x09, 0x04, 0x1d, 0x45, 0x01, 0xe7, 0x01,
5085         0xe8, 0x11, 0xfe, 0xe9, 0x00, 0x09, 0x04, 0x4c, 0xfe, 0x2c, 0x13, 0x01,
5086         0xfe, 0x14, 0x16, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90,
5087         0x0c, 0xfe, 0x64, 0x01, 0x18, 0xfe, 0x66, 0x01, 0x09, 0x04, 0x4f, 0xfe,
5088         0x12, 0x12, 0xfe, 0x03, 0x80, 0x74, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80,
5089         0x40, 0x12, 0x20, 0x63, 0x27, 0x11, 0xc8, 0x59, 0x1e, 0x20, 0xed, 0x76,
5090         0x20, 0x03, 0xfe, 0x08, 0x1c, 0x05, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58,
5091         0x05, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x05, 0xfe, 0xb0, 0x00, 0xfe,
5092         0x08, 0x58, 0x05, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
5093         0x24, 0x69, 0x12, 0xc9, 0x23, 0x0c, 0x50, 0x0c, 0x3f, 0x13, 0x40, 0x48,
5094         0x5f, 0x17, 0x1d, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x21, 0xfe, 0x08,
5095         0x0f, 0x3e, 0x10, 0x13, 0x42, 0x48, 0x17, 0x4c, 0xfe, 0x90, 0x4d, 0xfe,
5096         0x91, 0x54, 0x21, 0xfe, 0x1e, 0x0f, 0x24, 0x10, 0x12, 0x20, 0x78, 0x2c,
5097         0x46, 0x1e, 0x20, 0xed, 0x76, 0x20, 0x11, 0xc8, 0xf6, 0xfe, 0xd6, 0xf0,
5098         0xfe, 0x32, 0x0f, 0xea, 0x70, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
5099         0x18, 0x1c, 0x03, 0x3c, 0xfe, 0x0c, 0x14, 0xee, 0xfe, 0x07, 0xe6, 0x1d,
5100         0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x03, 0x01, 0x86, 0x78, 0x2c, 0x46,
5101         0xfa, 0xef, 0xfe, 0x42, 0x13, 0x2f, 0x07, 0x2d, 0xfe, 0x34, 0x13, 0x0a,
5102         0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x36, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01,
5103         0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10,
5104         0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xfe, 0x80, 0x5c, 0x01, 0x6f, 0xfe, 0x0e,
5105         0x10, 0x07, 0x7e, 0x45, 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x6c, 0x0f, 0x03,
5106         0xfe, 0x44, 0x58, 0x74, 0xfe, 0x01, 0xec, 0x97, 0xfe, 0x9e, 0x40, 0xfe,
5107         0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x1b, 0x76, 0x27, 0x01, 0xda, 0xfe,
5108         0xdd, 0x10, 0x2a, 0xbc, 0x7d, 0xbd, 0x7f, 0x30, 0x2e, 0xd5, 0x07, 0x1b,
5109         0xfe, 0x48, 0x12, 0x07, 0x0b, 0xfe, 0x56, 0x12, 0x07, 0x1a, 0xfe, 0x30,
5110         0x12, 0x07, 0xc2, 0x16, 0xfe, 0x3e, 0x11, 0x07, 0xfe, 0x23, 0x00, 0x16,
5111         0xfe, 0x4a, 0x11, 0x07, 0x06, 0x16, 0xfe, 0xa8, 0x11, 0x07, 0x19, 0xfe,
5112         0x12, 0x12, 0x07, 0x00, 0x16, 0x22, 0x14, 0xc2, 0x01, 0x33, 0x9f, 0x2b,
5113         0x01, 0x08, 0x8c, 0x43, 0x03, 0x2b, 0xfe, 0x62, 0x08, 0x0a, 0xca, 0x01,
5114         0xfe, 0x32, 0x0e, 0x11, 0x7e, 0x02, 0x29, 0x2b, 0x2f, 0x07, 0x9b, 0xfe,
5115         0xd9, 0x13, 0x79, 0x39, 0x68, 0x3a, 0x77, 0xfe, 0xfc, 0x10, 0x09, 0x04,
5116         0x6a, 0xfe, 0x72, 0x12, 0xc0, 0x38, 0xc1, 0x4e, 0xf4, 0xf5, 0x8e, 0xfe,
5117         0xc6, 0x10, 0x1e, 0x58, 0xfe, 0x26, 0x13, 0x05, 0x7b, 0x31, 0x7c, 0x77,
5118         0xfe, 0x82, 0x0c, 0x0c, 0x54, 0x18, 0x55, 0x23, 0x0c, 0x7b, 0x0c, 0x7c,
5119         0x01, 0xa8, 0x24, 0x69, 0x73, 0x12, 0x58, 0x01, 0xa5, 0xc0, 0x38, 0xc1,
5120         0x4e, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x38, 0xfe,
5121         0x05, 0xfa, 0x4e, 0xfe, 0x91, 0x10, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x40,
5122         0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x56, 0x18, 0x57, 0x83, 0xc0, 0x38, 0xc1,
5123         0x4e, 0xf4, 0xf5, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x00, 0x56, 0xfe, 0xa1,
5124         0x56, 0x0c, 0x52, 0x18, 0x53, 0x09, 0x04, 0x6a, 0xfe, 0x1e, 0x12, 0x1e,
5125         0x58, 0xfe, 0x1f, 0x40, 0x05, 0x54, 0x31, 0x55, 0xfe, 0x2c, 0x50, 0xfe,
5126         0xae, 0x50, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x44, 0x50, 0xfe, 0xc6, 0x50,
5127         0x05, 0x52, 0x31, 0x53, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x05, 0x39,
5128         0x31, 0x3a, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x5c, 0x24, 0x06,
5129         0x12, 0xcd, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x1f, 0x44, 0x30, 0x2e, 0xd5,
5130         0x07, 0x06, 0x21, 0x44, 0x2f, 0x07, 0x9b, 0x21, 0x5b, 0x01, 0x6e, 0x1c,
5131         0x3d, 0x16, 0x44, 0x09, 0x04, 0x0b, 0xe2, 0x79, 0x39, 0x68, 0x3a, 0xfe,
5132         0x0a, 0x55, 0x34, 0xfe, 0x8b, 0x55, 0xbe, 0x39, 0xbf, 0x3a, 0xfe, 0x0c,
5133         0x51, 0xfe, 0x8e, 0x51, 0x02, 0x5b, 0xfe, 0x19, 0x81, 0xaf, 0xfe, 0x19,
5134         0x41, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e,
5135         0xd8, 0x4b, 0x1a, 0xfe, 0xa6, 0x12, 0x4b, 0x0b, 0x3b, 0x02, 0x44, 0x01,
5136         0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, 0xd6, 0x07, 0x1a, 0x21, 0x44,
5137         0x01, 0x08, 0x1f, 0xa2, 0x30, 0x2e, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49,
5138         0x60, 0x05, 0xfe, 0x9c, 0x00, 0x28, 0x84, 0x49, 0x04, 0x19, 0x34, 0x9f,
5139         0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda,
5140         0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1,
5141         0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
5142         0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
5143         0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
5144         0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
5145         0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
5146         0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
5147         0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
5148         0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
5149         0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
5150         0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
5151         0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
5152         0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5153         0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
5154         0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
5155         0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5156         0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
5157         0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
5158         0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
5159         0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
5160         0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
5161         0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
5162         0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
5163         0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
5164         0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
5165         0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
5166         0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
5167         0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
5168         0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
5169         0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
5170         0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
5171         0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
5172         0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
5173         0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
5174         0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
5175         0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
5176         0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
5177         0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
5178         0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5179         0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5180         0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5181         0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5182         0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5183         0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5184         0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5185         0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5186         0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5187         0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5188         0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5189         0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5190         0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5191         0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5192         0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5193         0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5194         0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5195         0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5196         0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5197         0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5198         0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5199         0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5200         0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5201         0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5202         0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5203         0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5204         0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5205         0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5206         0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5207         0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5208         0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5209         0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5210         0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5211         0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5212         0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5213         0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5214         0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5215         0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5216         0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5217         0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5218         0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5219         0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5220         0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5221         0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5222         0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5223         0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5224         0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5225         0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5226         0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5227         0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5228         0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5229         0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5230         0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5231         0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5232         0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5233         0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5234         0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5235         0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5236         0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5237         0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5238         0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5239         0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5240         0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5241         0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5242         0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5243         0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5244         0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5245         0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5246         0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5247 };
5248
5249 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf);     /* 0x13AD */
5250 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL;     /* Expanded little-endian checksum. */
5251
5252 /* Microcode buffer is kept after initialization for error recovery. */
5253 static unsigned char _adv_asc38C0800_buf[] = {
5254         0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5255         0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5256         0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5257         0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5258         0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5259         0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5260         0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5261         0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5262         0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5263         0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5264         0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5265         0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5266         0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5267         0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5268         0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5269         0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5270         0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5271         0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5272         0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5273         0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5274         0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5275         0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5276         0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5277         0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5278         0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5279         0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5280         0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5281         0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5282         0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5283         0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5284         0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5285         0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5286         0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5287         0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5288         0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5289         0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5290         0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5291         0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5292         0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5293         0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5294         0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5295         0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5296         0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5297         0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
5298         0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5299         0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
5300         0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5301         0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
5302         0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5303         0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
5304         0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
5305         0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
5306         0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
5307         0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
5308         0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
5309         0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
5310         0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
5311         0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
5312         0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
5313         0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
5314         0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
5315         0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10,
5316         0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59,
5317         0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd,
5318         0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
5319         0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0,
5320         0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe,
5321         0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10,
5322         0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
5323         0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43,
5324         0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54,
5325         0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b,
5326         0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
5327         0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe,
5328         0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02,
5329         0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe,
5330         0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
5331         0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe,
5332         0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10,
5333         0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02,
5334         0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
5335         0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78,
5336         0x01, 0xfe, 0xb4, 0x16, 0x12, 0xd1, 0x1c, 0xd9, 0xfe, 0x01, 0xf0, 0xd9,
5337         0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27,
5338         0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
5339         0x06, 0xf0, 0xfe, 0xc8, 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a,
5340         0x06, 0x02, 0x24, 0x03, 0x70, 0x28, 0x17, 0xfe, 0xfa, 0x04, 0x15, 0x6d,
5341         0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8, 0xf9, 0x2c, 0x99, 0x19,
5342         0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c,
5343         0x74, 0x01, 0xaf, 0x8c, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x17, 0xda,
5344         0x09, 0xd1, 0x01, 0x0e, 0x8d, 0x51, 0x64, 0x79, 0x2a, 0x03, 0x70, 0x28,
5345         0xfe, 0x10, 0x12, 0x15, 0x6d, 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02,
5346         0xd8, 0xc7, 0x81, 0xc8, 0x83, 0x1c, 0x24, 0x27, 0xfe, 0x40, 0x04, 0x1d,
5347         0xfe, 0x3c, 0x04, 0x3b, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
5348         0x12, 0x2d, 0xff, 0x02, 0x00, 0x10, 0x01, 0x0b, 0x1d, 0xfe, 0xe4, 0x04,
5349         0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde, 0xfe, 0x4c, 0x44, 0xfe,
5350         0x4c, 0x12, 0x51, 0xfe, 0x44, 0x48, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b,
5351         0xda, 0x4f, 0x79, 0x2a, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62,
5352         0x13, 0x08, 0x05, 0x1b, 0xfe, 0x2a, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x52,
5353         0x13, 0xfe, 0x20, 0x10, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b, 0xda, 0xfe,
5354         0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x40, 0x13, 0x08, 0x05, 0x1b, 0xfe,
5355         0x08, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe,
5356         0x1c, 0x12, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00,
5357         0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x2d, 0x12, 0xfe, 0xe6,
5358         0x00, 0xfe, 0x1c, 0x90, 0xfe, 0x40, 0x5c, 0x04, 0x15, 0x9d, 0x01, 0x36,
5359         0x02, 0x2b, 0xfe, 0x42, 0x5b, 0x99, 0x19, 0xfe, 0x46, 0x59, 0xfe, 0xbf,
5360         0x57, 0xfe, 0x77, 0x57, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4, 0x5b, 0x08,
5361         0x05, 0x0a, 0xfe, 0x84, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x19, 0xfe, 0x7c,
5362         0x12, 0x53, 0x05, 0x06, 0xfe, 0x6c, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x28,
5363         0x17, 0xfe, 0x90, 0x05, 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe,
5364         0x56, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x4e, 0x12, 0x67, 0xff,
5365         0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c, 0x34, 0xfe, 0x89, 0x48,
5366         0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05,
5367         0x12, 0xfe, 0xe3, 0x00, 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05,
5368         0xfe, 0x49, 0xf0, 0xfe, 0x70, 0x05, 0x88, 0x25, 0xfe, 0x21, 0x00, 0xab,
5369         0x25, 0xfe, 0x22, 0x00, 0xaa, 0x25, 0x58, 0xfe, 0x09, 0x48, 0xff, 0x02,
5370         0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2,
5371         0x08, 0x53, 0x05, 0xcb, 0x4d, 0x01, 0xb0, 0x25, 0x06, 0x13, 0xd3, 0x39,
5372         0xfe, 0x27, 0x01, 0x08, 0x05, 0x1b, 0xfe, 0x22, 0x12, 0x41, 0x01, 0xb2,
5373         0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36,
5374         0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb,
5375         0x03, 0x5c, 0x28, 0xfe, 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18,
5376         0x06, 0x09, 0x06, 0x53, 0x05, 0x1f, 0xfe, 0x02, 0x12, 0x50, 0x01, 0xfe,
5377         0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe,
5378         0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62,
5379         0x12, 0x03, 0x45, 0x28, 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01,
5380         0xfe, 0x76, 0x19, 0xfe, 0x43, 0x48, 0xc4, 0xcc, 0x0f, 0x71, 0xff, 0x02,
5381         0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4, 0x6e, 0x41, 0x01, 0xb2,
5382         0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01,
5383         0xfe, 0xcc, 0x15, 0x1d, 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12,
5384         0xfe, 0xe5, 0x00, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x18, 0x06, 0x01, 0xb2,
5385         0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe, 0xe2, 0x00, 0x27, 0xdb,
5386         0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07,
5387         0xfe, 0x06, 0xf0, 0xfe, 0x74, 0x07, 0x95, 0x86, 0x02, 0x24, 0x08, 0x05,
5388         0x0a, 0xfe, 0x2e, 0x12, 0x16, 0x19, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b,
5389         0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0xfe, 0x99, 0xa4, 0x01,
5390         0x0b, 0x16, 0x00, 0x02, 0xfe, 0x42, 0x08, 0x68, 0x05, 0x1a, 0xfe, 0x38,
5391         0x12, 0x08, 0x05, 0x1a, 0xfe, 0x30, 0x13, 0x16, 0xfe, 0x1b, 0x00, 0x01,
5392         0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01,
5393         0x0b, 0x16, 0x06, 0x01, 0x0b, 0x16, 0x00, 0x02, 0xe2, 0x6c, 0x58, 0xbe,
5394         0x50, 0xfe, 0x9a, 0x81, 0x55, 0x1b, 0x7a, 0xfe, 0x42, 0x07, 0x09, 0x1b,
5395         0xfe, 0x09, 0x6f, 0xba, 0xfe, 0xca, 0x45, 0xfe, 0x32, 0x12, 0x69, 0x6d,
5396         0x8b, 0x6c, 0x7f, 0x27, 0xfe, 0x54, 0x07, 0x1c, 0x34, 0xfe, 0x0a, 0xf0,
5397         0xfe, 0x42, 0x07, 0x95, 0x86, 0x94, 0xfe, 0x6c, 0x07, 0x02, 0x24, 0x01,
5398         0x4b, 0x02, 0xdb, 0x16, 0x1f, 0x02, 0xdb, 0xfe, 0x9c, 0xf7, 0xdc, 0xfe,
5399         0x2c, 0x90, 0xfe, 0xae, 0x90, 0x56, 0xfe, 0xda, 0x07, 0x0c, 0x60, 0x14,
5400         0x61, 0x08, 0x54, 0x5a, 0x37, 0x22, 0x20, 0x07, 0x11, 0xfe, 0x0e, 0x12,
5401         0x8d, 0xfe, 0x80, 0x80, 0x39, 0x20, 0x6a, 0x2a, 0xfe, 0x06, 0x10, 0xfe,
5402         0x83, 0xe7, 0xfe, 0x48, 0x00, 0xab, 0xfe, 0x03, 0x40, 0x08, 0x54, 0x5b,
5403         0x37, 0x01, 0xb3, 0xb8, 0xfe, 0x1f, 0x40, 0x13, 0x62, 0x01, 0xef, 0xfe,
5404         0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x88,
5405         0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90, 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x0c,
5406         0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x0c, 0x3d,
5407         0x14, 0x3e, 0xfe, 0x4a, 0x10, 0x08, 0x05, 0x5a, 0xfe, 0x2a, 0x12, 0xfe,
5408         0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x60, 0x14, 0x61, 0x08, 0x05, 0x5b,
5409         0x8b, 0x01, 0xb3, 0xfe, 0x1f, 0x80, 0x13, 0x62, 0xfe, 0x44, 0x90, 0xfe,
5410         0xc6, 0x90, 0x0c, 0x3f, 0x14, 0x40, 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90,
5411         0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90, 0x0c, 0x3d,
5412         0x14, 0x3e, 0x0c, 0x2e, 0x14, 0x3c, 0x21, 0x0c, 0x49, 0x0c, 0x63, 0x08,
5413         0x54, 0x1f, 0x37, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27, 0xdd, 0xfe, 0x9e,
5414         0xf0, 0xfe, 0x76, 0x08, 0xbc, 0x17, 0x34, 0x2c, 0x77, 0xe6, 0xc5, 0xfe,
5415         0x9a, 0x08, 0xc6, 0xfe, 0xb8, 0x08, 0x94, 0xfe, 0x8e, 0x08, 0xfe, 0x06,
5416         0xf0, 0xfe, 0x94, 0x08, 0x95, 0x86, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xc9,
5417         0x10, 0x16, 0x1f, 0xfe, 0xc9, 0x10, 0x68, 0x05, 0x06, 0xfe, 0x10, 0x12,
5418         0x68, 0x05, 0x0a, 0x4e, 0x08, 0x05, 0x0a, 0xfe, 0x90, 0x12, 0xfe, 0x2e,
5419         0x1c, 0x02, 0xfe, 0x18, 0x0b, 0x68, 0x05, 0x06, 0x4e, 0x68, 0x05, 0x0a,
5420         0xfe, 0x7a, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0xd2, 0x09,
5421         0xfe, 0xac, 0xf0, 0xfe, 0x00, 0x09, 0x02, 0xfe, 0xde, 0x09, 0xfe, 0xb7,
5422         0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0x02, 0xf6, 0x1a, 0x50, 0xfe, 0x70, 0x18,
5423         0xfe, 0xf1, 0x18, 0xfe, 0x40, 0x55, 0xfe, 0xe1, 0x55, 0xfe, 0x10, 0x58,
5424         0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x1c, 0x85, 0xfe,
5425         0x8c, 0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0xac, 0xf0, 0xfe, 0xf0, 0x08, 0xb5,
5426         0xfe, 0xcb, 0x10, 0xfe, 0xad, 0xf0, 0xfe, 0x0c, 0x09, 0x02, 0xfe, 0x18,
5427         0x0b, 0xb6, 0xfe, 0xbf, 0x10, 0xfe, 0x2b, 0xf0, 0x85, 0xf4, 0x1e, 0xfe,
5428         0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xc2, 0xfe, 0xd2, 0xf0, 0x85, 0xfe, 0x76,
5429         0x18, 0x1e, 0x19, 0x17, 0x85, 0x03, 0xd2, 0x1e, 0x06, 0x17, 0x85, 0xc5,
5430         0x4a, 0xc6, 0x4a, 0xb5, 0xb6, 0xfe, 0x89, 0x10, 0x74, 0x67, 0x2d, 0x15,
5431         0x9d, 0x01, 0x36, 0x10, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x65, 0x10,
5432         0x80, 0x02, 0x65, 0xfe, 0x98, 0x80, 0xfe, 0x19, 0xe4, 0x0a, 0xfe, 0x1a,
5433         0x12, 0x51, 0xfe, 0x19, 0x82, 0xfe, 0x6c, 0x18, 0xfe, 0x44, 0x54, 0xbe,
5434         0xfe, 0x19, 0x81, 0xfe, 0x74, 0x18, 0x8f, 0x90, 0x17, 0xfe, 0xce, 0x08,
5435         0x02, 0x4a, 0x08, 0x05, 0x5a, 0xec, 0x03, 0x2e, 0x29, 0x3c, 0x0c, 0x3f,
5436         0x14, 0x40, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x6c, 0x18, 0xfe, 0xed, 0x18,
5437         0xfe, 0x44, 0x54, 0xfe, 0xe5, 0x54, 0x3a, 0x3f, 0x3b, 0x40, 0x03, 0x49,
5438         0x29, 0x63, 0x8f, 0xfe, 0xe3, 0x54, 0xfe, 0x74, 0x18, 0xfe, 0xf5, 0x18,
5439         0x8f, 0xfe, 0xe3, 0x54, 0x90, 0xc0, 0x56, 0xfe, 0xce, 0x08, 0x02, 0x4a,
5440         0xfe, 0x37, 0xf0, 0xfe, 0xda, 0x09, 0xfe, 0x8b, 0xf0, 0xfe, 0x60, 0x09,
5441         0x02, 0x4a, 0x08, 0x05, 0x0a, 0x23, 0xfe, 0xfa, 0x0a, 0x3a, 0x49, 0x3b,
5442         0x63, 0x56, 0xfe, 0x3e, 0x0a, 0x0f, 0xfe, 0xc0, 0x07, 0x41, 0x98, 0x00,
5443         0xad, 0xfe, 0x01, 0x59, 0xfe, 0x52, 0xf0, 0xfe, 0x0c, 0x0a, 0x8f, 0x7a,
5444         0xfe, 0x24, 0x0a, 0x3a, 0x49, 0x8f, 0xfe, 0xe3, 0x54, 0x57, 0x49, 0x7d,
5445         0x63, 0xfe, 0x14, 0x58, 0xfe, 0x95, 0x58, 0x02, 0x4a, 0x3a, 0x49, 0x3b,
5446         0x63, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0xbe, 0x57, 0x49, 0x57, 0x63,
5447         0x02, 0x4a, 0x08, 0x05, 0x5a, 0xfe, 0x82, 0x12, 0x08, 0x05, 0x1f, 0xfe,
5448         0x66, 0x13, 0x22, 0x62, 0xb7, 0xfe, 0x03, 0xa1, 0xfe, 0x83, 0x80, 0xfe,
5449         0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91, 0xfe, 0x86, 0x91, 0x6a,
5450         0x2a, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x56, 0xe0, 0x03, 0x60, 0x29,
5451         0x61, 0x0c, 0x7f, 0x14, 0x80, 0x57, 0x60, 0x7d, 0x61, 0x01, 0xb3, 0xb8,
5452         0x6a, 0x2a, 0x13, 0x62, 0x9b, 0x2e, 0x9c, 0x3c, 0x3a, 0x3f, 0x3b, 0x40,
5453         0x90, 0xc0, 0xfe, 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0x01, 0xef,
5454         0xfe, 0x36, 0x10, 0x21, 0x0c, 0x7f, 0x0c, 0x80, 0x3a, 0x3f, 0x3b, 0x40,
5455         0xe4, 0x08, 0x05, 0x1f, 0x17, 0xe0, 0x3a, 0x3d, 0x3b, 0x3e, 0x08, 0x05,
5456         0xfe, 0xf7, 0x00, 0x37, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x10, 0x58, 0xfe,
5457         0x91, 0x58, 0x57, 0x49, 0x7d, 0x63, 0x02, 0xfe, 0xf4, 0x09, 0x08, 0x05,
5458         0x1f, 0x17, 0xe0, 0x08, 0x05, 0xfe, 0xf7, 0x00, 0x37, 0xbe, 0xfe, 0x19,
5459         0x81, 0x50, 0xfe, 0x10, 0x90, 0xfe, 0x92, 0x90, 0xfe, 0xd3, 0x10, 0x32,
5460         0x07, 0xa6, 0x17, 0xfe, 0x08, 0x09, 0x12, 0xa6, 0x08, 0x05, 0x0a, 0xfe,
5461         0x14, 0x13, 0x03, 0x3d, 0x29, 0x3e, 0x56, 0xfe, 0x08, 0x09, 0xfe, 0x0c,
5462         0x58, 0xfe, 0x8d, 0x58, 0x02, 0x4a, 0x21, 0x41, 0xfe, 0x19, 0x80, 0xe7,
5463         0x08, 0x05, 0x0a, 0xfe, 0x1a, 0x12, 0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41,
5464         0xf4, 0xc2, 0xfe, 0xd1, 0xf0, 0xe2, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe,
5465         0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe, 0x6c, 0x19, 0x57, 0x3d, 0xfe, 0xed,
5466         0x19, 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0xf4, 0x1e, 0xfe,
5467         0x00, 0xff, 0x35, 0xfe, 0x74, 0x10, 0xc2, 0xfe, 0xd2, 0xf0, 0xfe, 0xa6,
5468         0x0b, 0xfe, 0x76, 0x18, 0x1e, 0x19, 0x8a, 0x03, 0xd2, 0x1e, 0x06, 0xfe,
5469         0x08, 0x13, 0x10, 0xfe, 0x16, 0x00, 0x02, 0x65, 0xfe, 0xd1, 0xf0, 0xfe,
5470         0xb8, 0x0b, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe, 0x17, 0x00, 0xfe, 0x42,
5471         0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xbe, 0x0b, 0xfe, 0x3c, 0x10, 0xfe, 0xcd,
5472         0xf0, 0xfe, 0xca, 0x0b, 0x10, 0xfe, 0x22, 0x00, 0x02, 0x65, 0xfe, 0xcb,
5473         0xf0, 0xfe, 0xd6, 0x0b, 0x10, 0xfe, 0x24, 0x00, 0x02, 0x65, 0xfe, 0xd0,
5474         0xf0, 0xfe, 0xe0, 0x0b, 0x10, 0x9e, 0xe5, 0xfe, 0xcf, 0xf0, 0xfe, 0xea,
5475         0x0b, 0x10, 0x58, 0xfe, 0x10, 0x10, 0xfe, 0xcc, 0xf0, 0xe2, 0x68, 0x05,
5476         0x1f, 0x4d, 0x10, 0xfe, 0x12, 0x00, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27,
5477         0xfe, 0x00, 0x0c, 0xfe, 0x9e, 0xf0, 0xfe, 0x14, 0x0c, 0xbc, 0x17, 0x34,
5478         0x2c, 0x77, 0xe6, 0xc5, 0x24, 0xc6, 0x24, 0x2c, 0xfa, 0x27, 0xfe, 0x20,
5479         0x0c, 0x1c, 0x34, 0x94, 0xfe, 0x3c, 0x0c, 0x95, 0x86, 0xc5, 0xdc, 0xc6,
5480         0xdc, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xdb, 0x10, 0x12, 0xfe, 0xe8, 0x00,
5481         0xb5, 0xb6, 0x74, 0xc7, 0x81, 0xc8, 0x83, 0xfe, 0x89, 0xf0, 0x24, 0x33,
5482         0x31, 0xe1, 0xc7, 0x81, 0xc8, 0x83, 0x27, 0xfe, 0x66, 0x0c, 0x1d, 0x24,
5483         0x33, 0x31, 0xdf, 0xbc, 0x4e, 0x10, 0xfe, 0x42, 0x00, 0x02, 0x65, 0x7c,
5484         0x06, 0xfe, 0x81, 0x49, 0x17, 0xfe, 0x2c, 0x0d, 0x08, 0x05, 0x0a, 0xfe,
5485         0x44, 0x13, 0x10, 0x00, 0x55, 0x0a, 0xfe, 0x54, 0x12, 0x55, 0xfe, 0x28,
5486         0x00, 0x23, 0xfe, 0x9a, 0x0d, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66,
5487         0x44, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01, 0xf5, 0x01, 0xf6, 0x09,
5488         0xa4, 0x01, 0xfe, 0x26, 0x0f, 0x64, 0x12, 0x2f, 0x01, 0x73, 0x02, 0x2b,
5489         0x10, 0xfe, 0x44, 0x00, 0x55, 0x0a, 0xe9, 0x44, 0x0a, 0xfe, 0xb4, 0x10,
5490         0x01, 0xb0, 0x44, 0x0a, 0xfe, 0xaa, 0x10, 0x01, 0xb0, 0xfe, 0x19, 0x82,
5491         0xfe, 0x34, 0x46, 0xac, 0x44, 0x0a, 0x10, 0xfe, 0x43, 0x00, 0xfe, 0x96,
5492         0x10, 0x08, 0x54, 0x0a, 0x37, 0x01, 0xf5, 0x01, 0xf6, 0x64, 0x12, 0x2f,
5493         0x01, 0x73, 0x99, 0x0a, 0x64, 0x42, 0x92, 0x02, 0xfe, 0x2e, 0x03, 0x08,
5494         0x05, 0x0a, 0x8a, 0x44, 0x0a, 0x10, 0x00, 0xfe, 0x5c, 0x10, 0x68, 0x05,
5495         0x1a, 0xfe, 0x58, 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x50, 0x13, 0xfe, 0x1c,
5496         0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x50, 0x0d, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d,
5497         0xf0, 0xfe, 0x56, 0x0d, 0x08, 0x54, 0x1a, 0x37, 0xfe, 0xa9, 0x10, 0x10,
5498         0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0a, 0x50, 0xfe, 0x2e, 0x10, 0x10,
5499         0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x10, 0x6f, 0xab, 0x10, 0xfe, 0x41,
5500         0x00, 0xaa, 0x10, 0xfe, 0x24, 0x00, 0x8c, 0xb5, 0xb6, 0x74, 0x03, 0x70,
5501         0x28, 0x23, 0xd8, 0x50, 0xfe, 0x04, 0xe6, 0x1a, 0xfe, 0x9d, 0x41, 0xfe,
5502         0x1c, 0x42, 0x64, 0x01, 0xe3, 0x02, 0x2b, 0xf8, 0x15, 0x0a, 0x39, 0xa0,
5503         0xb4, 0x15, 0xfe, 0x31, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10, 0x02,
5504         0xd7, 0x42, 0xfe, 0x06, 0xec, 0xd0, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45,
5505         0x35, 0x42, 0xfe, 0x06, 0xea, 0xd0, 0xfe, 0x47, 0x4b, 0x91, 0xfe, 0x75,
5506         0x57, 0x03, 0x5d, 0xfe, 0x98, 0x56, 0xfe, 0x38, 0x12, 0x09, 0x48, 0x01,
5507         0x0e, 0xfe, 0x44, 0x48, 0x4f, 0x08, 0x05, 0x1b, 0xfe, 0x1a, 0x13, 0x09,
5508         0x46, 0x01, 0x0e, 0x41, 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe,
5509         0x49, 0x54, 0x96, 0xfe, 0x1e, 0x0e, 0x02, 0xfe, 0x2e, 0x03, 0x09, 0x5d,
5510         0xfe, 0xee, 0x14, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45, 0x35, 0x42, 0xfe,
5511         0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x2b, 0x22, 0x20, 0x07, 0x11, 0xfe,
5512         0x9e, 0x12, 0x21, 0x13, 0x59, 0x13, 0x9f, 0x13, 0xd5, 0x22, 0x2f, 0x41,
5513         0x39, 0x2f, 0xbc, 0xad, 0xfe, 0xbc, 0xf0, 0xfe, 0xe0, 0x0e, 0x0f, 0x06,
5514         0x13, 0x59, 0x01, 0xfe, 0xda, 0x16, 0x03, 0xfe, 0x38, 0x01, 0x29, 0xfe,
5515         0x3a, 0x01, 0x56, 0xfe, 0xe4, 0x0e, 0xfe, 0x02, 0xec, 0xd5, 0x69, 0x00,
5516         0x66, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01,
5517         0x01, 0xfe, 0x4a, 0x17, 0xfe, 0x08, 0x90, 0xfe, 0x48, 0xf4, 0x0d, 0xfe,
5518         0x18, 0x13, 0xba, 0xfe, 0x02, 0xea, 0xd5, 0x69, 0x7e, 0xfe, 0xc5, 0x13,
5519         0x15, 0x1a, 0x39, 0xa0, 0xb4, 0xfe, 0x2e, 0x10, 0x03, 0xfe, 0x38, 0x01,
5520         0x1e, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x03, 0xfe, 0x3a, 0x01,
5521         0x0c, 0xfe, 0x62, 0x01, 0x43, 0x13, 0x20, 0x25, 0x06, 0x13, 0x2f, 0x12,
5522         0x2f, 0x92, 0x0f, 0x06, 0x04, 0x21, 0x04, 0x22, 0x59, 0xfe, 0xf7, 0x12,
5523         0x22, 0x9f, 0xb7, 0x13, 0x9f, 0x07, 0x7e, 0xfe, 0x71, 0x13, 0xfe, 0x24,
5524         0x1c, 0x15, 0x19, 0x39, 0xa0, 0xb4, 0xfe, 0xd9, 0x10, 0xc3, 0xfe, 0x03,
5525         0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xc3, 0xfe, 0x03, 0xdc,
5526         0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x21,
5527         0xfe, 0x00, 0xcc, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x78, 0x04, 0x08, 0x05,
5528         0x58, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13,
5529         0xfe, 0x1e, 0x80, 0xed, 0xfe, 0x1d, 0x80, 0xae, 0xfe, 0x0c, 0x90, 0xfe,
5530         0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xac, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
5531         0x0a, 0xfe, 0x3c, 0x50, 0xaa, 0x01, 0xfe, 0x7a, 0x17, 0x32, 0x07, 0x2f,
5532         0xad, 0x01, 0xfe, 0xb4, 0x16, 0x08, 0x05, 0x1b, 0x4e, 0x01, 0xf5, 0x01,
5533         0xf6, 0x12, 0xfe, 0xe9, 0x00, 0x08, 0x05, 0x58, 0xfe, 0x2c, 0x13, 0x01,
5534         0xfe, 0x0c, 0x17, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90,
5535         0x0c, 0xfe, 0x64, 0x01, 0x14, 0xfe, 0x66, 0x01, 0x08, 0x05, 0x5b, 0xfe,
5536         0x12, 0x12, 0xfe, 0x03, 0x80, 0x8d, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80,
5537         0x40, 0x13, 0x20, 0x6a, 0x2a, 0x12, 0xcf, 0x64, 0x22, 0x20, 0xfb, 0x79,
5538         0x20, 0x04, 0xfe, 0x08, 0x1c, 0x03, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58,
5539         0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe,
5540         0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
5541         0x25, 0x6e, 0x13, 0xd0, 0x21, 0x0c, 0x5c, 0x0c, 0x45, 0x0f, 0x46, 0x52,
5542         0x50, 0x18, 0x1b, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x23, 0xfe, 0xfc,
5543         0x0f, 0x44, 0x11, 0x0f, 0x48, 0x52, 0x18, 0x58, 0xfe, 0x90, 0x4d, 0xfe,
5544         0x91, 0x54, 0x23, 0xe4, 0x25, 0x11, 0x13, 0x20, 0x7c, 0x6f, 0x4f, 0x22,
5545         0x20, 0xfb, 0x79, 0x20, 0x12, 0xcf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
5546         0xfe, 0x26, 0x10, 0xf8, 0x74, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
5547         0x18, 0x1c, 0x04, 0x42, 0xfe, 0x0c, 0x14, 0xfc, 0xfe, 0x07, 0xe6, 0x1b,
5548         0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x04, 0x01, 0xb0, 0x7c, 0x6f, 0x4f,
5549         0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42, 0x13, 0x32, 0x07, 0x2f,
5550         0xfe, 0x34, 0x13, 0x09, 0x48, 0x01, 0x0e, 0xbb, 0xfe, 0x36, 0x12, 0xfe,
5551         0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe,
5552         0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe,
5553         0x80, 0x5c, 0x01, 0x73, 0xfe, 0x0e, 0x10, 0x07, 0x82, 0x4e, 0xfe, 0x14,
5554         0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x60, 0x10, 0x04, 0xfe, 0x44, 0x58, 0x8d,
5555         0xfe, 0x01, 0xec, 0xa2, 0xfe, 0x9e, 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe,
5556         0x9c, 0xe7, 0x1a, 0x79, 0x2a, 0x01, 0xe3, 0xfe, 0xdd, 0x10, 0x2c, 0xc7,
5557         0x81, 0xc8, 0x83, 0x33, 0x31, 0xde, 0x07, 0x1a, 0xfe, 0x48, 0x12, 0x07,
5558         0x0a, 0xfe, 0x56, 0x12, 0x07, 0x19, 0xfe, 0x30, 0x12, 0x07, 0xc9, 0x17,
5559         0xfe, 0x32, 0x12, 0x07, 0xfe, 0x23, 0x00, 0x17, 0xeb, 0x07, 0x06, 0x17,
5560         0xfe, 0x9c, 0x12, 0x07, 0x1f, 0xfe, 0x12, 0x12, 0x07, 0x00, 0x17, 0x24,
5561         0x15, 0xc9, 0x01, 0x36, 0xa9, 0x2d, 0x01, 0x0b, 0x94, 0x4b, 0x04, 0x2d,
5562         0xdd, 0x09, 0xd1, 0x01, 0xfe, 0x26, 0x0f, 0x12, 0x82, 0x02, 0x2b, 0x2d,
5563         0x32, 0x07, 0xa6, 0xfe, 0xd9, 0x13, 0x3a, 0x3d, 0x3b, 0x3e, 0x56, 0xfe,
5564         0xf0, 0x11, 0x08, 0x05, 0x5a, 0xfe, 0x72, 0x12, 0x9b, 0x2e, 0x9c, 0x3c,
5565         0x90, 0xc0, 0x96, 0xfe, 0xba, 0x11, 0x22, 0x62, 0xfe, 0x26, 0x13, 0x03,
5566         0x7f, 0x29, 0x80, 0x56, 0xfe, 0x76, 0x0d, 0x0c, 0x60, 0x14, 0x61, 0x21,
5567         0x0c, 0x7f, 0x0c, 0x80, 0x01, 0xb3, 0x25, 0x6e, 0x77, 0x13, 0x62, 0x01,
5568         0xef, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe,
5569         0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0xfe, 0x91, 0x10, 0x03, 0x3f,
5570         0x29, 0x40, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x3f, 0x14, 0x40,
5571         0x88, 0x9b, 0x2e, 0x9c, 0x3c, 0x90, 0xc0, 0x03, 0x5e, 0x29, 0x5f, 0xfe,
5572         0x00, 0x56, 0xfe, 0xa1, 0x56, 0x0c, 0x5e, 0x14, 0x5f, 0x08, 0x05, 0x5a,
5573         0xfe, 0x1e, 0x12, 0x22, 0x62, 0xfe, 0x1f, 0x40, 0x03, 0x60, 0x29, 0x61,
5574         0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x03, 0x3f, 0x29, 0x40, 0xfe, 0x44,
5575         0x50, 0xfe, 0xc6, 0x50, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x08, 0x50, 0xfe,
5576         0x8a, 0x50, 0x03, 0x3d, 0x29, 0x3e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50,
5577         0x02, 0x89, 0x25, 0x06, 0x13, 0xd4, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1d,
5578         0x4c, 0x33, 0x31, 0xde, 0x07, 0x06, 0x23, 0x4c, 0x32, 0x07, 0xa6, 0x23,
5579         0x72, 0x01, 0xaf, 0x1e, 0x43, 0x17, 0x4c, 0x08, 0x05, 0x0a, 0xee, 0x3a,
5580         0x3d, 0x3b, 0x3e, 0xfe, 0x0a, 0x55, 0x35, 0xfe, 0x8b, 0x55, 0x57, 0x3d,
5581         0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x72, 0xfe, 0x19,
5582         0x81, 0xba, 0xfe, 0x19, 0x41, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1c, 0x34,
5583         0x1d, 0xe8, 0x33, 0x31, 0xe1, 0x55, 0x19, 0xfe, 0xa6, 0x12, 0x55, 0x0a,
5584         0x4d, 0x02, 0x4c, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0xe8, 0x33, 0x31, 0xdf,
5585         0x07, 0x19, 0x23, 0x4c, 0x01, 0x0b, 0x1d, 0xe8, 0x33, 0x31, 0xfe, 0xe8,
5586         0x09, 0xfe, 0xc2, 0x49, 0x51, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0x8a, 0x53,
5587         0x05, 0x1f, 0x35, 0xa9, 0xfe, 0xbb, 0x45, 0x55, 0x00, 0x4e, 0x44, 0x06,
5588         0x7c, 0x43, 0xfe, 0xda, 0x14, 0x01, 0xaf, 0x8c, 0xfe, 0x4b, 0x45, 0xee,
5589         0x32, 0x07, 0xa5, 0xed, 0x03, 0xcd, 0x28, 0x8a, 0x03, 0x45, 0x28, 0x35,
5590         0x67, 0x02, 0x72, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17,
5591         0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01,
5592         0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0x4c, 0x33,
5593         0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
5594         0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
5595         0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
5596         0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
5597         0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
5598         0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
5599         0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
5600         0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5601         0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
5602         0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
5603         0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5604         0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
5605         0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
5606         0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
5607         0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
5608         0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
5609         0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
5610         0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
5611         0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
5612         0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
5613         0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
5614         0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
5615         0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
5616         0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
5617         0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
5618         0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
5619         0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
5620         0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
5621         0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
5622         0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
5623         0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
5624         0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
5625         0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
5626         0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
5627         0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
5628         0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
5629         0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
5630         0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5631         0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5632         0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5633         0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5634         0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5635         0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5636         0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5637         0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5638         0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5639         0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5640         0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5641         0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5642         0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5643         0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5644         0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5645         0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5646         0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5647         0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5648         0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5649         0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5650         0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5651         0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5652         0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5653         0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5654         0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5655         0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5656         0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5657         0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5658         0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5659         0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5660         0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5661         0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5662         0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5663         0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5664         0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5665         0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5666         0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5667         0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5668         0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5669         0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5670         0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5671         0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5672         0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5673         0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5674         0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5675         0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5676         0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5677         0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5678         0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5679         0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5680         0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5681         0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5682         0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5683         0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5684         0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5685         0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5686         0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5687         0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5688         0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5689         0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5690         0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5691         0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5692         0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5693         0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5694         0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5695         0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5696         0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5697         0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5698         0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5699 };
5700
5701 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf);       /* 0x14E1 */
5702 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL;  /* Expanded little-endian checksum. */
5703
5704 /* Microcode buffer is kept after initialization for error recovery. */
5705 static unsigned char _adv_asc38C1600_buf[] = {
5706         0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5707         0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5708         0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5709         0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5710         0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5711         0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5712         0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5713         0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5714         0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5715         0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5716         0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5717         0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5718         0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5719         0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5720         0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5721         0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5722         0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5723         0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5724         0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5725         0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5726         0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5727         0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5728         0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5729         0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5730         0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5731         0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5732         0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5733         0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5734         0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5735         0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5736         0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5737         0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5738         0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5739         0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5740         0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5741         0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5742         0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5743         0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5744         0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5745         0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5746         0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5747         0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5748         0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
5749         0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
5750         0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5751         0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
5752         0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5753         0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
5754         0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5755         0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
5756         0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
5757         0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
5758         0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
5759         0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
5760         0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
5761         0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
5762         0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
5763         0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
5764         0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
5765         0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
5766         0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
5767         0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
5768         0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
5769         0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
5770         0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
5771         0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
5772         0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
5773         0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
5774         0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
5775         0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
5776         0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
5777         0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
5778         0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
5779         0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
5780         0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
5781         0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
5782         0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
5783         0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
5784         0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
5785         0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
5786         0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
5787         0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
5788         0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
5789         0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe,
5790         0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
5791         0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe,
5792         0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0,
5793         0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b,
5794         0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
5795         0xea, 0xfe, 0x46, 0x1c, 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf,
5796         0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, 0x75, 0x01, 0xa6, 0x86, 0x0a,
5797         0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a, 0xe1, 0x01, 0x18, 0x77,
5798         0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42,
5799         0x8f, 0xfe, 0x70, 0x02, 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29,
5800         0x2f, 0xfe, 0x4e, 0x04, 0x16, 0xfe, 0x4a, 0x04, 0x7e, 0xfe, 0xa0, 0x00,
5801         0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff, 0x02, 0x00, 0x10, 0x01,
5802         0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25,
5803         0xee, 0xfe, 0x4c, 0x44, 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13,
5804         0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x60, 0x8d, 0x30, 0x01, 0xfe, 0x4e,
5805         0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xfe,
5806         0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10,
5807         0x13, 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe,
5808         0x48, 0x47, 0xfe, 0x54, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xa5, 0x01, 0x43,
5809         0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xf9, 0x1f, 0x7f,
5810         0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f,
5811         0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe,
5812         0x1c, 0x90, 0x04, 0xfe, 0x9c, 0x93, 0x3a, 0x0b, 0x0e, 0x8b, 0x02, 0x1f,
5813         0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b, 0x7d, 0x1d, 0xfe, 0x46,
5814         0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04,
5815         0xfe, 0x87, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c,
5816         0x06, 0x0d, 0xfe, 0x98, 0x13, 0x0f, 0xfe, 0x20, 0x80, 0x04, 0xfe, 0xa0,
5817         0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84, 0x12, 0x01, 0x38, 0x06,
5818         0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda,
5819         0x05, 0xd0, 0x54, 0x01, 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe,
5820         0xa0, 0x00, 0x1e, 0xfe, 0x50, 0x12, 0x5e, 0xff, 0x02, 0x00, 0x10, 0x2f,
5821         0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe,
5822         0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01,
5823         0x38, 0xfe, 0x4a, 0xf0, 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba,
5824         0x05, 0x71, 0x2e, 0xfe, 0x21, 0x00, 0xf1, 0x2e, 0xfe, 0x22, 0x00, 0xa2,
5825         0x2e, 0x4a, 0xfe, 0x09, 0x48, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, 0xd0,
5826         0x05, 0x17, 0xfe, 0xf4, 0x05, 0xfe, 0xe2, 0x08, 0x01, 0x38, 0x06, 0xfe,
5827         0x1c, 0x00, 0x4d, 0x01, 0xa7, 0x2e, 0x07, 0x20, 0xe4, 0x47, 0xfe, 0x27,
5828         0x01, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x24, 0x12, 0x3e, 0x01, 0x84, 0x1f,
5829         0x7f, 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42,
5830         0x8f, 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x03, 0xe6, 0x1e, 0xfe, 0xca, 0x13,
5831         0x03, 0xb6, 0x1e, 0xfe, 0x40, 0x12, 0x03, 0x66, 0x1e, 0xfe, 0x38, 0x13,
5832         0x3e, 0x01, 0x84, 0x17, 0xfe, 0x72, 0x06, 0x0a, 0x07, 0x01, 0x38, 0x06,
5833         0x24, 0xfe, 0x02, 0x12, 0x4f, 0x01, 0xfe, 0x56, 0x19, 0x16, 0xfe, 0x68,
5834         0x06, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x03, 0x66, 0x8a, 0x10, 0x66,
5835         0x03, 0x9a, 0x1e, 0xfe, 0x70, 0x12, 0x03, 0x55, 0x1e, 0xfe, 0x68, 0x13,
5836         0x01, 0xc6, 0x09, 0x12, 0x48, 0xfe, 0x92, 0x06, 0x2e, 0x12, 0x01, 0xfe,
5837         0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0x13, 0x58, 0xff, 0x02, 0x00,
5838         0x57, 0x52, 0xad, 0x23, 0x3f, 0x4e, 0x62, 0x49, 0x3e, 0x01, 0x84, 0x17,
5839         0xfe, 0xea, 0x06, 0x01, 0x38, 0x06, 0x12, 0xf7, 0x45, 0x0a, 0x95, 0x01,
5840         0xfe, 0x84, 0x19, 0x16, 0xfe, 0xe0, 0x06, 0x15, 0x82, 0x01, 0x41, 0x15,
5841         0xe2, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x1c, 0x07, 0x01, 0x84, 0xfe, 0xae,
5842         0x10, 0x03, 0x6f, 0x1e, 0xfe, 0x9e, 0x13, 0x3e, 0x01, 0x84, 0x03, 0x9a,
5843         0x1e, 0xfe, 0x1a, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfc, 0x01, 0xc6, 0x01,
5844         0xfe, 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0xf0, 0x45, 0x0a, 0x95,
5845         0x03, 0xb6, 0x1e, 0xf8, 0x01, 0x38, 0x06, 0x24, 0x36, 0xfe, 0x02, 0xf6,
5846         0x07, 0x71, 0x78, 0x8c, 0x00, 0x4d, 0x62, 0x49, 0x3e, 0x2d, 0x93, 0x4e,
5847         0xd0, 0x0d, 0x17, 0xfe, 0x9a, 0x07, 0x01, 0xfe, 0xc0, 0x19, 0x16, 0xfe,
5848         0x90, 0x07, 0x26, 0x20, 0x9e, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x21,
5849         0x9e, 0x09, 0x07, 0xfb, 0x03, 0xe6, 0xfe, 0x58, 0x57, 0x10, 0xe6, 0x05,
5850         0xfe, 0x2a, 0x06, 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x1c, 0x07, 0x01, 0x84,
5851         0xfe, 0x9c, 0x32, 0x5f, 0x75, 0x01, 0xa6, 0x86, 0x15, 0xfe, 0xe2, 0x00,
5852         0x2f, 0xed, 0x2a, 0x3c, 0xfe, 0x0a, 0xf0, 0xfe, 0xce, 0x07, 0xae, 0xfe,
5853         0x96, 0x08, 0xfe, 0x06, 0xf0, 0xfe, 0x9e, 0x08, 0xaf, 0xa0, 0x05, 0x29,
5854         0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x2e, 0x12, 0x14, 0x1d, 0x01, 0x08, 0x14,
5855         0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0xfe,
5856         0x99, 0xa4, 0x01, 0x08, 0x14, 0x00, 0x05, 0xfe, 0xc6, 0x09, 0x01, 0x76,
5857         0x06, 0x12, 0xfe, 0x3a, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x30, 0x13,
5858         0x14, 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00,
5859         0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x07, 0x01, 0x08, 0x14, 0x00,
5860         0x05, 0xef, 0x7c, 0x4a, 0x78, 0x4f, 0x0f, 0xfe, 0x9a, 0x81, 0x04, 0xfe,
5861         0x9a, 0x83, 0xfe, 0xcb, 0x47, 0x0b, 0x0e, 0x2d, 0x28, 0x48, 0xfe, 0x6c,
5862         0x08, 0x0a, 0x28, 0xfe, 0x09, 0x6f, 0xca, 0xfe, 0xca, 0x45, 0xfe, 0x32,
5863         0x12, 0x53, 0x63, 0x4e, 0x7c, 0x97, 0x2f, 0xfe, 0x7e, 0x08, 0x2a, 0x3c,
5864         0xfe, 0x0a, 0xf0, 0xfe, 0x6c, 0x08, 0xaf, 0xa0, 0xae, 0xfe, 0x96, 0x08,
5865         0x05, 0x29, 0x01, 0x41, 0x05, 0xed, 0x14, 0x24, 0x05, 0xed, 0xfe, 0x9c,
5866         0xf7, 0x9f, 0x01, 0xfe, 0xae, 0x1e, 0xfe, 0x18, 0x58, 0x01, 0xfe, 0xbe,
5867         0x1e, 0xfe, 0x99, 0x58, 0xfe, 0x78, 0x18, 0xfe, 0xf9, 0x18, 0x8e, 0xfe,
5868         0x16, 0x09, 0x10, 0x6a, 0x22, 0x6b, 0x01, 0x0c, 0x61, 0x54, 0x44, 0x21,
5869         0x2c, 0x09, 0x1a, 0xf8, 0x77, 0x01, 0xfe, 0x7e, 0x1e, 0x47, 0x2c, 0x7a,
5870         0x30, 0xf0, 0xfe, 0x83, 0xe7, 0xfe, 0x3f, 0x00, 0x71, 0xfe, 0x03, 0x40,
5871         0x01, 0x0c, 0x61, 0x65, 0x44, 0x01, 0xc2, 0xc8, 0xfe, 0x1f, 0x40, 0x20,
5872         0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe,
5873         0x44, 0x51, 0xfe, 0xc6, 0x51, 0xfe, 0x10, 0x10, 0x01, 0xfe, 0xce, 0x1e,
5874         0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x01, 0xfe, 0xee, 0x1e,
5875         0x01, 0xfe, 0xfe, 0x1e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x10, 0x4b,
5876         0x22, 0x4c, 0xfe, 0x8a, 0x10, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x50, 0x12,
5877         0x01, 0xfe, 0xae, 0x1e, 0x01, 0xfe, 0xbe, 0x1e, 0x10, 0x6a, 0x22, 0x6b,
5878         0x01, 0x0c, 0x06, 0x65, 0x4e, 0x01, 0xc2, 0x0f, 0xfe, 0x1f, 0x80, 0x04,
5879         0xfe, 0x9f, 0x83, 0x33, 0x0b, 0x0e, 0x20, 0x6e, 0x0f, 0xfe, 0x44, 0x90,
5880         0x04, 0xfe, 0xc4, 0x93, 0x3a, 0x0b, 0xfe, 0xc6, 0x90, 0x04, 0xfe, 0xc6,
5881         0x93, 0x79, 0x0b, 0x0e, 0x10, 0x6c, 0x22, 0x6d, 0x01, 0xfe, 0xce, 0x1e,
5882         0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x0f, 0xfe, 0x40, 0x90,
5883         0x04, 0xfe, 0xc0, 0x93, 0x3a, 0x0b, 0xfe, 0xc2, 0x90, 0x04, 0xfe, 0xc2,
5884         0x93, 0x79, 0x0b, 0x0e, 0x10, 0x4b, 0x22, 0x4c, 0x10, 0x64, 0x22, 0x34,
5885         0x01, 0x0c, 0x61, 0x24, 0x44, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe,
5886         0xde, 0x09, 0xfe, 0x9e, 0xf0, 0xfe, 0xf2, 0x09, 0xfe, 0x01, 0x48, 0x1b,
5887         0x3c, 0x37, 0x88, 0xf5, 0xd4, 0xfe, 0x1e, 0x0a, 0xd5, 0xfe, 0x42, 0x0a,
5888         0xd2, 0xfe, 0x1e, 0x0a, 0xd3, 0xfe, 0x42, 0x0a, 0xae, 0xfe, 0x12, 0x0a,
5889         0xfe, 0x06, 0xf0, 0xfe, 0x18, 0x0a, 0xaf, 0xa0, 0x05, 0x29, 0x01, 0x41,
5890         0xfe, 0xc1, 0x10, 0x14, 0x24, 0xfe, 0xc1, 0x10, 0x01, 0x76, 0x06, 0x07,
5891         0xfe, 0x14, 0x12, 0x01, 0x76, 0x06, 0x0d, 0x5d, 0x01, 0x0c, 0x06, 0x0d,
5892         0xfe, 0x74, 0x12, 0xfe, 0x2e, 0x1c, 0x05, 0xfe, 0x1a, 0x0c, 0x01, 0x76,
5893         0x06, 0x07, 0x5d, 0x01, 0x76, 0x06, 0x0d, 0x41, 0xfe, 0x2c, 0x1c, 0xfe,
5894         0xaa, 0xf0, 0xfe, 0xce, 0x0a, 0xfe, 0xac, 0xf0, 0xfe, 0x66, 0x0a, 0xfe,
5895         0x92, 0x10, 0xc4, 0xf6, 0xfe, 0xad, 0xf0, 0xfe, 0x72, 0x0a, 0x05, 0xfe,
5896         0x1a, 0x0c, 0xc5, 0xfe, 0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0xbf, 0xfe, 0x6b,
5897         0x18, 0x23, 0xfe, 0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xac, 0xfe, 0xd2, 0xf0,
5898         0xbf, 0xfe, 0x76, 0x18, 0x23, 0x1d, 0x1b, 0xbf, 0x03, 0xe3, 0x23, 0x07,
5899         0x1b, 0xbf, 0xd4, 0x5b, 0xd5, 0x5b, 0xd2, 0x5b, 0xd3, 0x5b, 0xc4, 0xc5,
5900         0xfe, 0xa9, 0x10, 0x75, 0x5e, 0x32, 0x1f, 0x7f, 0x01, 0x42, 0x19, 0xfe,
5901         0x35, 0x00, 0xfe, 0x01, 0xf0, 0x70, 0x19, 0x98, 0x05, 0x70, 0xfe, 0x74,
5902         0x18, 0x23, 0xfe, 0x00, 0xf8, 0x1b, 0x5b, 0x7d, 0x12, 0x01, 0xfe, 0x78,
5903         0x0f, 0x4d, 0x01, 0xfe, 0x96, 0x1a, 0x21, 0x30, 0x77, 0x7d, 0x1d, 0x05,
5904         0x5b, 0x01, 0x0c, 0x06, 0x0d, 0x2b, 0xfe, 0xe2, 0x0b, 0x01, 0x0c, 0x06,
5905         0x54, 0xfe, 0xa6, 0x12, 0x01, 0x0c, 0x06, 0x24, 0xfe, 0x88, 0x13, 0x21,
5906         0x6e, 0xc7, 0x01, 0xfe, 0x1e, 0x1f, 0x0f, 0xfe, 0x83, 0x80, 0x04, 0xfe,
5907         0x83, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xfe, 0xc8, 0x44, 0xfe, 0x42,
5908         0x13, 0x0f, 0xfe, 0x04, 0x91, 0x04, 0xfe, 0x84, 0x93, 0xfe, 0xca, 0x57,
5909         0x0b, 0xfe, 0x86, 0x91, 0x04, 0xfe, 0x86, 0x93, 0xfe, 0xcb, 0x57, 0x0b,
5910         0x0e, 0x7a, 0x30, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x8e, 0x40, 0x03,
5911         0x6a, 0x3b, 0x6b, 0x10, 0x97, 0x22, 0x98, 0xd9, 0x6a, 0xda, 0x6b, 0x01,
5912         0xc2, 0xc8, 0x7a, 0x30, 0x20, 0x6e, 0xdb, 0x64, 0xdc, 0x34, 0x91, 0x6c,
5913         0x7e, 0x6d, 0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xfe, 0x04, 0xfa, 0x64,
5914         0xfe, 0x05, 0xfa, 0x34, 0x01, 0xfe, 0x6a, 0x16, 0xa3, 0x26, 0x10, 0x97,
5915         0x10, 0x98, 0x91, 0x6c, 0x7e, 0x6d, 0xfe, 0x14, 0x10, 0x01, 0x0c, 0x06,
5916         0x24, 0x1b, 0x40, 0x91, 0x4b, 0x7e, 0x4c, 0x01, 0x0c, 0x06, 0xfe, 0xf7,
5917         0x00, 0x44, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58,
5918         0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x05, 0x5b, 0x01, 0x0c, 0x06, 0x24,
5919         0x1b, 0x40, 0x01, 0x0c, 0x06, 0xfe, 0xf7, 0x00, 0x44, 0x78, 0x01, 0xfe,
5920         0x8e, 0x1e, 0x4f, 0x0f, 0xfe, 0x10, 0x90, 0x04, 0xfe, 0x90, 0x93, 0x3a,
5921         0x0b, 0xfe, 0x92, 0x90, 0x04, 0xfe, 0x92, 0x93, 0x79, 0x0b, 0x0e, 0xfe,
5922         0xbd, 0x10, 0x01, 0x43, 0x09, 0xbb, 0x1b, 0xfe, 0x6e, 0x0a, 0x15, 0xbb,
5923         0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x14, 0x13, 0x03, 0x4b, 0x3b, 0x4c, 0x8e,
5924         0xfe, 0x6e, 0x0a, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x05, 0x5b, 0x26,
5925         0x3e, 0x0f, 0xfe, 0x19, 0x80, 0x04, 0xfe, 0x99, 0x83, 0x33, 0x0b, 0x0e,
5926         0xfe, 0xe5, 0x10, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1a, 0x12, 0xfe, 0x6c,
5927         0x19, 0xfe, 0x19, 0x41, 0xfe, 0x6b, 0x18, 0xac, 0xfe, 0xd1, 0xf0, 0xef,
5928         0x1f, 0x92, 0x01, 0x42, 0x19, 0xfe, 0x44, 0x00, 0xfe, 0x90, 0x10, 0xfe,
5929         0x6c, 0x19, 0xd9, 0x4b, 0xfe, 0xed, 0x19, 0xda, 0x4c, 0xfe, 0x0c, 0x51,
5930         0xfe, 0x8e, 0x51, 0xfe, 0x6b, 0x18, 0x23, 0xfe, 0x00, 0xff, 0x31, 0xfe,
5931         0x76, 0x10, 0xac, 0xfe, 0xd2, 0xf0, 0xfe, 0xba, 0x0c, 0xfe, 0x76, 0x18,
5932         0x23, 0x1d, 0x5d, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0x08, 0x13, 0x19, 0xfe,
5933         0x16, 0x00, 0x05, 0x70, 0xfe, 0xd1, 0xf0, 0xfe, 0xcc, 0x0c, 0x1f, 0x92,
5934         0x01, 0x42, 0x19, 0xfe, 0x17, 0x00, 0x5c, 0xfe, 0xce, 0xf0, 0xfe, 0xd2,
5935         0x0c, 0xfe, 0x3e, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xde, 0x0c, 0x19, 0xfe,
5936         0x22, 0x00, 0x05, 0x70, 0xfe, 0xcb, 0xf0, 0xfe, 0xea, 0x0c, 0x19, 0xfe,
5937         0x24, 0x00, 0x05, 0x70, 0xfe, 0xd0, 0xf0, 0xfe, 0xf4, 0x0c, 0x19, 0x94,
5938         0xfe, 0x1c, 0x10, 0xfe, 0xcf, 0xf0, 0xfe, 0xfe, 0x0c, 0x19, 0x4a, 0xf3,
5939         0xfe, 0xcc, 0xf0, 0xef, 0x01, 0x76, 0x06, 0x24, 0x4d, 0x19, 0xfe, 0x12,
5940         0x00, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe, 0x16, 0x0d, 0xfe, 0x9e,
5941         0xf0, 0xfe, 0x2a, 0x0d, 0xfe, 0x01, 0x48, 0x1b, 0x3c, 0x37, 0x88, 0xf5,
5942         0xd4, 0x29, 0xd5, 0x29, 0xd2, 0x29, 0xd3, 0x29, 0x37, 0xfe, 0x9c, 0x32,
5943         0x2f, 0xfe, 0x3e, 0x0d, 0x2a, 0x3c, 0xae, 0xfe, 0x62, 0x0d, 0xaf, 0xa0,
5944         0xd4, 0x9f, 0xd5, 0x9f, 0xd2, 0x9f, 0xd3, 0x9f, 0x05, 0x29, 0x01, 0x41,
5945         0xfe, 0xd3, 0x10, 0x15, 0xfe, 0xe8, 0x00, 0xc4, 0xc5, 0x75, 0xd7, 0x99,
5946         0xd8, 0x9c, 0xfe, 0x89, 0xf0, 0x29, 0x27, 0x25, 0xbe, 0xd7, 0x99, 0xd8,
5947         0x9c, 0x2f, 0xfe, 0x8c, 0x0d, 0x16, 0x29, 0x27, 0x25, 0xbd, 0xfe, 0x01,
5948         0x48, 0xa4, 0x19, 0xfe, 0x42, 0x00, 0x05, 0x70, 0x90, 0x07, 0xfe, 0x81,
5949         0x49, 0x1b, 0xfe, 0x64, 0x0e, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x44, 0x13,
5950         0x19, 0x00, 0x2d, 0x0d, 0xfe, 0x54, 0x12, 0x2d, 0xfe, 0x28, 0x00, 0x2b,
5951         0xfe, 0xda, 0x0e, 0x0a, 0x57, 0x01, 0x18, 0x09, 0x00, 0x36, 0x46, 0xfe,
5952         0x28, 0x00, 0xfe, 0xfa, 0x10, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00,
5953         0x1d, 0x0a, 0xba, 0x01, 0xfe, 0x58, 0x10, 0x40, 0x15, 0x56, 0x01, 0x85,
5954         0x05, 0x35, 0x19, 0xfe, 0x44, 0x00, 0x2d, 0x0d, 0xf7, 0x46, 0x0d, 0xfe,
5955         0xcc, 0x10, 0x01, 0xa7, 0x46, 0x0d, 0xfe, 0xc2, 0x10, 0x01, 0xa7, 0x0f,
5956         0xfe, 0x19, 0x82, 0x04, 0xfe, 0x99, 0x83, 0xfe, 0xcc, 0x47, 0x0b, 0x0e,
5957         0xfe, 0x34, 0x46, 0xa5, 0x46, 0x0d, 0x19, 0xfe, 0x43, 0x00, 0xfe, 0xa2,
5958         0x10, 0x01, 0x0c, 0x61, 0x0d, 0x44, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe,
5959         0x00, 0x1d, 0x40, 0x15, 0x56, 0x01, 0x85, 0x7d, 0x0d, 0x40, 0x51, 0x01,
5960         0xfe, 0x9e, 0x1e, 0x05, 0xfe, 0x3a, 0x03, 0x01, 0x0c, 0x06, 0x0d, 0x5d,
5961         0x46, 0x0d, 0x19, 0x00, 0xfe, 0x62, 0x10, 0x01, 0x76, 0x06, 0x12, 0xfe,
5962         0x5c, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x52, 0x13, 0xfe, 0x1c, 0x1c,
5963         0xfe, 0x9d, 0xf0, 0xfe, 0x8e, 0x0e, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0,
5964         0xfe, 0x94, 0x0e, 0x01, 0x0c, 0x61, 0x12, 0x44, 0xfe, 0x9f, 0x10, 0x19,
5965         0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0d, 0x4f, 0xfe, 0x2e, 0x10, 0x19,
5966         0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x19, 0xfe, 0x47, 0x00, 0xf1, 0x19,
5967         0xfe, 0x41, 0x00, 0xa2, 0x19, 0xfe, 0x24, 0x00, 0x86, 0xc4, 0xc5, 0x75,
5968         0x03, 0x81, 0x1e, 0x2b, 0xea, 0x4f, 0xfe, 0x04, 0xe6, 0x12, 0xfe, 0x9d,
5969         0x41, 0xfe, 0x1c, 0x42, 0x40, 0x01, 0xf4, 0x05, 0x35, 0xfe, 0x12, 0x1c,
5970         0x1f, 0x0d, 0x47, 0xb5, 0xc3, 0x1f, 0xfe, 0x31, 0x00, 0x47, 0xb8, 0x01,
5971         0xfe, 0xd4, 0x11, 0x05, 0xe9, 0x51, 0xfe, 0x06, 0xec, 0xe0, 0xfe, 0x0e,
5972         0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0x06, 0xea, 0xe0,
5973         0xfe, 0x47, 0x4b, 0x45, 0xfe, 0x75, 0x57, 0x03, 0x67, 0xfe, 0x98, 0x56,
5974         0xfe, 0x38, 0x12, 0x0a, 0x5a, 0x01, 0x18, 0xfe, 0x44, 0x48, 0x60, 0x01,
5975         0x0c, 0x06, 0x28, 0xfe, 0x18, 0x13, 0x0a, 0x57, 0x01, 0x18, 0x3e, 0xfe,
5976         0x41, 0x58, 0x0a, 0xba, 0xfe, 0xfa, 0x14, 0xfe, 0x49, 0x54, 0xb0, 0xfe,
5977         0x5e, 0x0f, 0x05, 0xfe, 0x3a, 0x03, 0x0a, 0x67, 0xfe, 0xe0, 0x14, 0xfe,
5978         0x0e, 0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0xce, 0x47,
5979         0xfe, 0xad, 0x13, 0x05, 0x35, 0x21, 0x2c, 0x09, 0x1a, 0xfe, 0x98, 0x12,
5980         0x26, 0x20, 0x96, 0x20, 0xe7, 0xfe, 0x08, 0x1c, 0xfe, 0x7c, 0x19, 0xfe,
5981         0xfd, 0x19, 0xfe, 0x0a, 0x1c, 0x03, 0xe5, 0xfe, 0x48, 0x55, 0xa5, 0x3b,
5982         0xfe, 0x62, 0x01, 0xfe, 0xc9, 0x55, 0x31, 0xfe, 0x74, 0x10, 0x01, 0xfe,
5983         0xf0, 0x1a, 0x03, 0xfe, 0x38, 0x01, 0x3b, 0xfe, 0x3a, 0x01, 0x8e, 0xfe,
5984         0x1e, 0x10, 0xfe, 0x02, 0xec, 0xe7, 0x53, 0x00, 0x36, 0xfe, 0x04, 0xec,
5985         0x2c, 0x60, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x62, 0x1b,
5986         0x01, 0xfe, 0xce, 0x1e, 0xb2, 0x11, 0xfe, 0x18, 0x13, 0xca, 0xfe, 0x02,
5987         0xea, 0xe7, 0x53, 0x92, 0xfe, 0xc3, 0x13, 0x1f, 0x12, 0x47, 0xb5, 0xc3,
5988         0xfe, 0x2a, 0x10, 0x03, 0xfe, 0x38, 0x01, 0x23, 0xfe, 0xf0, 0xff, 0x10,
5989         0xe5, 0x03, 0xfe, 0x3a, 0x01, 0x10, 0xfe, 0x62, 0x01, 0x01, 0xfe, 0x1e,
5990         0x1e, 0x20, 0x2c, 0x15, 0x56, 0x01, 0xfe, 0x9e, 0x1e, 0x13, 0x07, 0x02,
5991         0x26, 0x02, 0x21, 0x96, 0xc7, 0x20, 0x96, 0x09, 0x92, 0xfe, 0x79, 0x13,
5992         0x1f, 0x1d, 0x47, 0xb5, 0xc3, 0xfe, 0xe1, 0x10, 0xcf, 0xfe, 0x03, 0xdc,
5993         0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xcf, 0xfe, 0x03, 0xdc, 0xfe,
5994         0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x26, 0xfe,
5995         0x00, 0xcc, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x89, 0x02, 0x01, 0x0c, 0x06,
5996         0x4a, 0xfe, 0x4e, 0x13, 0x0f, 0xfe, 0x1c, 0x80, 0x04, 0xfe, 0x9c, 0x83,
5997         0x33, 0x0b, 0x0e, 0x09, 0x07, 0xfe, 0x3a, 0x13, 0x0f, 0xfe, 0x1e, 0x80,
5998         0x04, 0xfe, 0x9e, 0x83, 0x33, 0x0b, 0x0e, 0xfe, 0x2a, 0x13, 0x0f, 0xfe,
5999         0x1d, 0x80, 0x04, 0xfe, 0x9d, 0x83, 0xfe, 0xf9, 0x13, 0x0e, 0xfe, 0x1c,
6000         0x13, 0x01, 0xfe, 0xee, 0x1e, 0xac, 0xfe, 0x14, 0x13, 0x01, 0xfe, 0xfe,
6001         0x1e, 0xfe, 0x81, 0x58, 0xfa, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4,
6002         0x0d, 0xfe, 0x3c, 0x50, 0xa2, 0x01, 0xfe, 0x92, 0x1b, 0x01, 0x43, 0x09,
6003         0x56, 0xfb, 0x01, 0xfe, 0xc8, 0x1a, 0x01, 0x0c, 0x06, 0x28, 0xa4, 0x01,
6004         0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00, 0x1d, 0x15, 0xfe, 0xe9, 0x00, 0x01,
6005         0x0c, 0x06, 0x4a, 0xfe, 0x4e, 0x13, 0x01, 0xfe, 0x22, 0x1b, 0xfe, 0x1e,
6006         0x1c, 0x0f, 0xfe, 0x14, 0x90, 0x04, 0xfe, 0x94, 0x93, 0x3a, 0x0b, 0xfe,
6007         0x96, 0x90, 0x04, 0xfe, 0x96, 0x93, 0x79, 0x0b, 0x0e, 0x10, 0xfe, 0x64,
6008         0x01, 0x22, 0xfe, 0x66, 0x01, 0x01, 0x0c, 0x06, 0x65, 0xf9, 0x0f, 0xfe,
6009         0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x0e, 0x77, 0xfe, 0x01,
6010         0xec, 0x2c, 0xfe, 0x80, 0x40, 0x20, 0x2c, 0x7a, 0x30, 0x15, 0xdf, 0x40,
6011         0x21, 0x2c, 0xfe, 0x00, 0x40, 0x8d, 0x2c, 0x02, 0xfe, 0x08, 0x1c, 0x03,
6012         0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58, 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07,
6013         0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe, 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00,
6014         0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c, 0x2e, 0x49, 0x20, 0xe0, 0x26, 0x10,
6015         0x66, 0x10, 0x55, 0x10, 0x6f, 0x13, 0x57, 0x52, 0x4f, 0x1c, 0x28, 0xfe,
6016         0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe, 0x88, 0x11, 0x46, 0x1a, 0x13,
6017         0x5a, 0x52, 0x1c, 0x4a, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe,
6018         0x9e, 0x11, 0x2e, 0x1a, 0x20, 0x2c, 0x90, 0x34, 0x60, 0x21, 0x2c, 0xfe,
6019         0x00, 0x40, 0x8d, 0x2c, 0x15, 0xdf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
6020         0xfe, 0xb2, 0x11, 0xfe, 0x12, 0x1c, 0x75, 0xfe, 0x14, 0x1c, 0xfe, 0x10,
6021         0x1c, 0xfe, 0x18, 0x1c, 0x02, 0x51, 0xfe, 0x0c, 0x14, 0xfe, 0x0e, 0x47,
6022         0xfe, 0x07, 0xe6, 0x28, 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x02, 0x01,
6023         0xa7, 0x90, 0x34, 0x60, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42,
6024         0x13, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x34, 0x13, 0x0a, 0x5a, 0x01,
6025         0x18, 0xcb, 0xfe, 0x36, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
6026         0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f, 0x89,
6027         0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x5c, 0x01, 0x85,
6028         0xf2, 0x09, 0x9b, 0xa4, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0xec,
6029         0x11, 0x02, 0xfe, 0x44, 0x58, 0x77, 0xfe, 0x01, 0xec, 0xb8, 0xfe, 0x9e,
6030         0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x12, 0x8d, 0x30, 0x01,
6031         0xf4, 0xfe, 0xdd, 0x10, 0x37, 0xd7, 0x99, 0xd8, 0x9c, 0x27, 0x25, 0xee,
6032         0x09, 0x12, 0xfe, 0x48, 0x12, 0x09, 0x0d, 0xfe, 0x56, 0x12, 0x09, 0x1d,
6033         0xfe, 0x30, 0x12, 0x09, 0xdd, 0x1b, 0xfe, 0xc4, 0x13, 0x09, 0xfe, 0x23,
6034         0x00, 0x1b, 0xfe, 0xd0, 0x13, 0x09, 0x07, 0x1b, 0xfe, 0x34, 0x14, 0x09,
6035         0x24, 0xfe, 0x12, 0x12, 0x09, 0x00, 0x1b, 0x29, 0x1f, 0xdd, 0x01, 0x42,
6036         0xa1, 0x32, 0x01, 0x08, 0xae, 0x41, 0x02, 0x32, 0xfe, 0x62, 0x08, 0x0a,
6037         0xe1, 0x01, 0xfe, 0x58, 0x10, 0x15, 0x9b, 0x05, 0x35, 0x32, 0x01, 0x43,
6038         0x09, 0xbb, 0xfe, 0xd7, 0x13, 0x91, 0x4b, 0x7e, 0x4c, 0x8e, 0xfe, 0x80,
6039         0x13, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x72, 0x12, 0xdb, 0x64, 0xdc, 0x34,
6040         0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xb0, 0xfe, 0x4a, 0x13, 0x21, 0x6e,
6041         0xfe, 0x26, 0x13, 0x03, 0x97, 0x3b, 0x98, 0x8e, 0xfe, 0xb6, 0x0e, 0x10,
6042         0x6a, 0x22, 0x6b, 0x26, 0x10, 0x97, 0x10, 0x98, 0x01, 0xc2, 0x2e, 0x49,
6043         0x88, 0x20, 0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xdb, 0x64, 0xdc, 0x34, 0xfe,
6044         0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x64, 0xfe, 0x05, 0xfa,
6045         0x34, 0xfe, 0x8f, 0x10, 0x03, 0x6c, 0x3b, 0x6d, 0xfe, 0x40, 0x56, 0xfe,
6046         0xe1, 0x56, 0x10, 0x6c, 0x22, 0x6d, 0x71, 0xdb, 0x64, 0xdc, 0x34, 0xfe,
6047         0x44, 0x55, 0xfe, 0xe5, 0x55, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x00, 0x56,
6048         0xfe, 0xa1, 0x56, 0x10, 0x68, 0x22, 0x69, 0x01, 0x0c, 0x06, 0x54, 0xf9,
6049         0x21, 0x6e, 0xfe, 0x1f, 0x40, 0x03, 0x6a, 0x3b, 0x6b, 0xfe, 0x2c, 0x50,
6050         0xfe, 0xae, 0x50, 0x03, 0x6c, 0x3b, 0x6d, 0xfe, 0x44, 0x50, 0xfe, 0xc6,
6051         0x50, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x03,
6052         0x4b, 0x3b, 0x4c, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x05, 0x73, 0x2e,
6053         0x07, 0x20, 0x9e, 0x05, 0x72, 0x32, 0x01, 0x08, 0x16, 0x3d, 0x27, 0x25,
6054         0xee, 0x09, 0x07, 0x2b, 0x3d, 0x01, 0x43, 0x09, 0xbb, 0x2b, 0x72, 0x01,
6055         0xa6, 0x23, 0x3f, 0x1b, 0x3d, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1e, 0x13,
6056         0x91, 0x4b, 0x7e, 0x4c, 0xfe, 0x0a, 0x55, 0x31, 0xfe, 0x8b, 0x55, 0xd9,
6057         0x4b, 0xda, 0x4c, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x05, 0x72, 0x01,
6058         0xfe, 0x8e, 0x1e, 0xca, 0xfe, 0x19, 0x41, 0x05, 0x72, 0x32, 0x01, 0x08,
6059         0x2a, 0x3c, 0x16, 0xc0, 0x27, 0x25, 0xbe, 0x2d, 0x1d, 0xc0, 0x2d, 0x0d,
6060         0x83, 0x2d, 0x7f, 0x1b, 0xfe, 0x66, 0x15, 0x05, 0x3d, 0x01, 0x08, 0x2a,
6061         0x3c, 0x16, 0xc0, 0x27, 0x25, 0xbd, 0x09, 0x1d, 0x2b, 0x3d, 0x01, 0x08,
6062         0x16, 0xc0, 0x27, 0x25, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49, 0x50, 0x03,
6063         0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa1, 0xfe, 0xbb, 0x45,
6064         0x2d, 0x00, 0xa4, 0x46, 0x07, 0x90, 0x3f, 0x01, 0xfe, 0xf8, 0x15, 0x01,
6065         0xa6, 0x86, 0xfe, 0x4b, 0x45, 0xfe, 0x20, 0x13, 0x01, 0x43, 0x09, 0x82,
6066         0xfe, 0x16, 0x13, 0x03, 0x9a, 0x1e, 0x5d, 0x03, 0x55, 0x1e, 0x31, 0x5e,
6067         0x05, 0x72, 0xfe, 0xc0, 0x5d, 0x01, 0xa7, 0xfe, 0x03, 0x17, 0x03, 0x66,
6068         0x8a, 0x10, 0x66, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, 0x01, 0xfe, 0x56,
6069         0x19, 0x05, 0x73, 0x01, 0x08, 0x2a, 0x3c, 0x16, 0x3d, 0x27, 0x25, 0xbd,
6070         0x09, 0x07, 0x2b, 0x3d, 0x01, 0xfe, 0xbe, 0x16, 0xfe, 0x42, 0x58, 0xfe,
6071         0xe8, 0x14, 0x01, 0xa6, 0x86, 0xfe, 0x4a, 0xf4, 0x0d, 0x1b, 0x3d, 0xfe,
6072         0x4a, 0xf4, 0x07, 0xfe, 0x0e, 0x12, 0x01, 0x43, 0x09, 0x82, 0x4e, 0x05,
6073         0x72, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73,
6074         0x01, 0xfe, 0x84, 0x19, 0x05, 0x73, 0x01, 0x08, 0x2a, 0x3c, 0x16, 0x3d,
6075         0x27, 0x25, 0xbd, 0x09, 0x12, 0x2b, 0x3d, 0x01, 0xfe, 0xe8, 0x17, 0x8b,
6076         0xfe, 0xaa, 0x14, 0xfe, 0xb6, 0x14, 0x86, 0xa8, 0xb2, 0x0d, 0x1b, 0x3d,
6077         0xb2, 0x07, 0xfe, 0x0e, 0x12, 0x01, 0x43, 0x09, 0x82, 0x4e, 0x05, 0x72,
6078         0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, 0x01,
6079         0xfe, 0xc0, 0x19, 0x05, 0x73, 0x13, 0x07, 0x2f, 0xfe, 0xcc, 0x15, 0x17,
6080         0xfe, 0xe2, 0x15, 0x5f, 0xcc, 0x01, 0x08, 0x26, 0x5f, 0x02, 0x8f, 0xfe,
6081         0xde, 0x15, 0x2a, 0xfe, 0xde, 0x15, 0x16, 0xfe, 0xcc, 0x15, 0x5e, 0x32,
6082         0x01, 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52,
6083         0xad, 0x23, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x02,
6084         0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xad, 0x23, 0x3f, 0xfe, 0x30,
6085         0x56, 0xfe, 0x00, 0x5c, 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52,
6086         0xad, 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xfe, 0x00, 0x5e,
6087         0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xad, 0xfe, 0x0b, 0x58,
6088         0x02, 0x0a, 0x66, 0x01, 0x5c, 0x0a, 0x55, 0x01, 0x5c, 0x0a, 0x6f, 0x01,
6089         0x5c, 0x02, 0x01, 0xfe, 0x1e, 0x1f, 0x23, 0x1a, 0xff, 0x03, 0x00, 0x54,
6090         0xfe, 0x00, 0xf4, 0x24, 0x52, 0x0f, 0xfe, 0x00, 0x7c, 0x04, 0xfe, 0x07,
6091         0x7c, 0x3a, 0x0b, 0x0e, 0xfe, 0x00, 0x71, 0xfe, 0xf9, 0x18, 0xfe, 0x7a,
6092         0x19, 0xfe, 0xfb, 0x19, 0xfe, 0x1a, 0xf7, 0x00, 0xfe, 0x1b, 0xf7, 0x00,
6093         0x7a, 0x30, 0x10, 0x68, 0x22, 0x69, 0xd9, 0x6c, 0xda, 0x6d, 0x02, 0xfe,
6094         0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x77,
6095         0x02, 0x01, 0xc6, 0xfe, 0x42, 0x48, 0x4f, 0x50, 0x45, 0x01, 0x08, 0x16,
6096         0xfe, 0xe0, 0x17, 0x27, 0x25, 0xbe, 0x01, 0x08, 0x16, 0xfe, 0xe0, 0x17,
6097         0x27, 0x25, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0x9a, 0x1e, 0xfe,
6098         0xda, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfe, 0xd0, 0x13, 0x26, 0x53, 0x12,
6099         0x48, 0xfe, 0x08, 0x17, 0xd1, 0x12, 0x53, 0x12, 0xfe, 0x1e, 0x13, 0x2d,
6100         0xb4, 0x7b, 0xfe, 0x26, 0x17, 0x4d, 0x13, 0x07, 0x1c, 0xb4, 0x90, 0x04,
6101         0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xf1, 0xff, 0x02, 0x83, 0x55,
6102         0x53, 0x1d, 0xfe, 0x12, 0x13, 0xd6, 0xfe, 0x30, 0x00, 0xb0, 0xfe, 0x80,
6103         0x17, 0x1c, 0x63, 0x13, 0x07, 0xfe, 0x56, 0x10, 0x53, 0x0d, 0xfe, 0x16,
6104         0x13, 0xd6, 0xfe, 0x64, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0x64,
6105         0x00, 0x1c, 0x94, 0x13, 0x07, 0xfe, 0x28, 0x10, 0x53, 0x07, 0xfe, 0x60,
6106         0x13, 0xd6, 0xfe, 0xc8, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0xc8,
6107         0x00, 0x1c, 0x95, 0x13, 0x07, 0x71, 0xd6, 0xfe, 0x90, 0x01, 0x48, 0xfe,
6108         0x8c, 0x17, 0x45, 0xf3, 0xfe, 0x43, 0xf4, 0x96, 0xfe, 0x56, 0xf0, 0xfe,
6109         0x9e, 0x17, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x43, 0xf4, 0x94, 0xf6, 0x8b,
6110         0x01, 0xfe, 0x24, 0x16, 0x23, 0x3f, 0xfc, 0xa8, 0x8c, 0x49, 0x48, 0xfe,
6111         0xda, 0x17, 0x62, 0x49, 0xfe, 0x1c, 0x10, 0xa8, 0x8c, 0x80, 0x48, 0xfe,
6112         0xda, 0x17, 0x62, 0x80, 0x71, 0x50, 0x26, 0xfe, 0x4d, 0xf4, 0x00, 0xf7,
6113         0x45, 0x13, 0x07, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x02, 0x50, 0x13,
6114         0x0d, 0x02, 0x50, 0x3e, 0x78, 0x4f, 0x45, 0x01, 0x08, 0x16, 0xa9, 0x27,
6115         0x25, 0xbe, 0xfe, 0x03, 0xea, 0xfe, 0x7e, 0x01, 0x01, 0x08, 0x16, 0xa9,
6116         0x27, 0x25, 0xfe, 0xe9, 0x0a, 0x01, 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe,
6117         0xe9, 0x0a, 0xfe, 0x05, 0xea, 0xfe, 0x7f, 0x01, 0x01, 0x08, 0x16, 0xa9,
6118         0x27, 0x25, 0xfe, 0x69, 0x09, 0xfe, 0x02, 0xea, 0xfe, 0x80, 0x01, 0x01,
6119         0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, 0xe8, 0x08, 0x47, 0xfe, 0x81, 0x01,
6120         0x03, 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa2, 0x78, 0xf2,
6121         0x53, 0x07, 0x36, 0xfe, 0x34, 0xf4, 0x3f, 0xa1, 0x78, 0x03, 0x9a, 0x1e,
6122         0x83, 0x01, 0x38, 0x06, 0x12, 0x31, 0xf0, 0x4f, 0x45, 0xfe, 0x90, 0x10,
6123         0xfe, 0x40, 0x5a, 0x23, 0x3f, 0xfb, 0x8c, 0x49, 0x48, 0xfe, 0xaa, 0x18,
6124         0x62, 0x49, 0x71, 0x8c, 0x80, 0x48, 0xfe, 0xaa, 0x18, 0x62, 0x80, 0xfe,
6125         0xb4, 0x56, 0xfe, 0x40, 0x5d, 0x01, 0xc6, 0x01, 0xfe, 0xac, 0x1d, 0xfe,
6126         0x02, 0x17, 0xfe, 0xc8, 0x45, 0xfe, 0x5a, 0xf0, 0xfe, 0xc0, 0x18, 0xfe,
6127         0x43, 0x48, 0x2d, 0x93, 0x36, 0xfe, 0x34, 0xf4, 0xfe, 0x00, 0x11, 0xfe,
6128         0x40, 0x10, 0x2d, 0xb4, 0x36, 0xfe, 0x34, 0xf4, 0x04, 0xfe, 0x34, 0x10,
6129         0x2d, 0xfe, 0x0b, 0x00, 0x36, 0x46, 0x63, 0xfe, 0x28, 0x10, 0xfe, 0xc0,
6130         0x49, 0xff, 0x02, 0x00, 0x54, 0xb2, 0xfe, 0x90, 0x01, 0x48, 0xfe, 0xfa,
6131         0x18, 0x45, 0xfe, 0x1c, 0xf4, 0x3f, 0xf3, 0xfe, 0x40, 0xf4, 0x96, 0xfe,
6132         0x56, 0xf0, 0xfe, 0x0c, 0x19, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x40, 0xf4,
6133         0x94, 0xf6, 0x3e, 0x2d, 0x93, 0x4e, 0xd0, 0x0d, 0x21, 0xfe, 0x7f, 0x01,
6134         0xfe, 0xc8, 0x46, 0xfe, 0x24, 0x13, 0x8c, 0x00, 0x5d, 0x26, 0x21, 0xfe,
6135         0x7e, 0x01, 0xfe, 0xc8, 0x45, 0xfe, 0x14, 0x13, 0x21, 0xfe, 0x80, 0x01,
6136         0xfe, 0x48, 0x45, 0xfa, 0x21, 0xfe, 0x81, 0x01, 0xfe, 0xc8, 0x44, 0x4e,
6137         0x26, 0x02, 0x13, 0x07, 0x02, 0x78, 0x45, 0x50, 0x13, 0x0d, 0x02, 0x14,
6138         0x07, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x14, 0x0d, 0x01, 0x08, 0x17,
6139         0xfe, 0x82, 0x19, 0x14, 0x1d, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x5f,
6140         0xfe, 0x89, 0x49, 0x01, 0x08, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
6141         0x14, 0x1d, 0x01, 0x08, 0x17, 0xc1, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
6142         0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0xc1, 0x5f, 0xfe, 0x89, 0x4a, 0x01,
6143         0x08, 0x02, 0x50, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f,
6144         0x01, 0x08, 0x17, 0x74, 0x14, 0x12, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x89,
6145         0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01, 0x08, 0x17, 0x74, 0xfe,
6146         0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17,
6147         0x74, 0x5f, 0xcc, 0x01, 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c,
6148         0x13, 0xc8, 0x20, 0xe4, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x5f, 0xa1, 0x5e,
6149         0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f,
6150         0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13,
6151         0x16, 0xfe, 0x64, 0x1a, 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09,
6152         0x07, 0x5d, 0x01, 0x0c, 0x61, 0x07, 0x44, 0x02, 0x0a, 0x5a, 0x01, 0x18,
6153         0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01,
6154         0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa,
6155         0xfe, 0x80, 0xe7, 0x1a, 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe,
6156         0xb2, 0x16, 0xaa, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0xaa, 0x0a, 0x67, 0x01,
6157         0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe, 0x7e, 0x1e, 0xfe, 0x80,
6158         0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18,
6159         0xfe, 0x80, 0x4c, 0x0a, 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c,
6160         0xe5, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe, 0x1d,
6161         0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe, 0x2a, 0x1c, 0xfa, 0xb3,
6162         0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe,
6163         0xf4, 0x1a, 0xfe, 0xfa, 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01,
6164         0xfe, 0x00, 0xf4, 0x24, 0xfe, 0x18, 0x58, 0x03, 0xfe, 0x66, 0x01, 0xfe,
6165         0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, 0x07,
6166         0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c,
6167         0xf7, 0x24, 0xb1, 0xfe, 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9,
6168         0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c, 0x1a, 0x87, 0xfe, 0x83,
6169         0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
6170         0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
6171         0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b,
6172         0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04,
6173         0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
6174         0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
6175         0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6,
6176         0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c,
6177         0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
6178         0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
6179         0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83,
6180         0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a,
6181         0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
6182         0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
6183         0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13,
6184         0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1,
6185         0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
6186         0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
6187         0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48,
6188         0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f,
6189         0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
6190         0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
6191         0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
6192         0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
6193         0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
6194         0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6195         0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6196         0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6197         0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6198         0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6199         0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6200         0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6201         0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6202         0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6203         0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6204         0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6205         0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6206         0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6207         0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6208         0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6209         0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6210         0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6211         0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6212         0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6213         0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6214         0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6215         0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6216         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6217         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6218         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6219         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6220         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6221         0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6222         0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6223         0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6224         0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6225         0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6226         0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6227         0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6228         0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6229         0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6230         0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6231         0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6232         0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6233         0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6234 };
6235
6236 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf);       /* 0x1673 */
6237 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL;  /* Expanded little-endian checksum. */
6238
6239 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6240 {
6241         PortAddr iop_base;
6242         int i;
6243         ushort lram_addr;
6244
6245         iop_base = asc_dvc->iop_base;
6246         AscPutRiscVarFreeQHead(iop_base, 1);
6247         AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6248         AscPutVarFreeQHead(iop_base, 1);
6249         AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6250         AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6251                          (uchar)((int)asc_dvc->max_total_qng + 1));
6252         AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6253                          (uchar)((int)asc_dvc->max_total_qng + 2));
6254         AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6255                          asc_dvc->max_total_qng);
6256         AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6257         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6258         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6259         AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6260         AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6261         AscPutQDoneInProgress(iop_base, 0);
6262         lram_addr = ASC_QADR_BEG;
6263         for (i = 0; i < 32; i++, lram_addr += 2) {
6264                 AscWriteLramWord(iop_base, lram_addr, 0);
6265         }
6266 }
6267
6268 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6269 {
6270         int i;
6271         ushort warn_code;
6272         PortAddr iop_base;
6273         ASC_PADDR phy_addr;
6274         ASC_DCNT phy_size;
6275
6276         iop_base = asc_dvc->iop_base;
6277         warn_code = 0;
6278         for (i = 0; i <= ASC_MAX_TID; i++) {
6279                 AscPutMCodeInitSDTRAtID(iop_base, i,
6280                                         asc_dvc->cfg->sdtr_period_offset[i]);
6281         }
6282
6283         AscInitQLinkVar(asc_dvc);
6284         AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6285                          asc_dvc->cfg->disc_enable);
6286         AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6287                          ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6288
6289         /* Align overrun buffer on an 8 byte boundary. */
6290         phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6291         phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6292         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6293                                  (uchar *)&phy_addr, 1);
6294         phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6295         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6296                                  (uchar *)&phy_size, 1);
6297
6298         asc_dvc->cfg->mcode_date =
6299             AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6300         asc_dvc->cfg->mcode_version =
6301             AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6302
6303         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6304         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6305                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6306                 return warn_code;
6307         }
6308         if (AscStartChip(iop_base) != 1) {
6309                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6310                 return warn_code;
6311         }
6312
6313         return warn_code;
6314 }
6315
6316 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6317 {
6318         ushort warn_code;
6319         PortAddr iop_base;
6320
6321         iop_base = asc_dvc->iop_base;
6322         warn_code = 0;
6323         if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6324             !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6325                 AscResetChipAndScsiBus(asc_dvc);
6326                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6327         }
6328         asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6329         if (asc_dvc->err_code != 0)
6330                 return UW_ERR;
6331         if (!AscFindSignature(asc_dvc->iop_base)) {
6332                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6333                 return warn_code;
6334         }
6335         AscDisableInterrupt(iop_base);
6336         warn_code |= AscInitLram(asc_dvc);
6337         if (asc_dvc->err_code != 0)
6338                 return UW_ERR;
6339         ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)_asc_mcode_chksum);
6340         if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6341                              _asc_mcode_size) != _asc_mcode_chksum) {
6342                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6343                 return warn_code;
6344         }
6345         warn_code |= AscInitMicroCodeVar(asc_dvc);
6346         asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6347         AscEnableInterrupt(iop_base);
6348         return warn_code;
6349 }
6350
6351 /*
6352  * Load the Microcode
6353  *
6354  * Write the microcode image to RISC memory starting at address 0.
6355  *
6356  * The microcode is stored compressed in the following format:
6357  *
6358  *  254 word (508 byte) table indexed by byte code followed
6359  *  by the following byte codes:
6360  *
6361  *    1-Byte Code:
6362  *      00: Emit word 0 in table.
6363  *      01: Emit word 1 in table.
6364  *      .
6365  *      FD: Emit word 253 in table.
6366  *
6367  *    Multi-Byte Code:
6368  *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6369  *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6370  *
6371  * Returns 0 or an error if the checksum doesn't match
6372  */
6373 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6374                             int memsize, int chksum)
6375 {
6376         int i, j, end, len = 0;
6377         ADV_DCNT sum;
6378
6379         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6380
6381         for (i = 253 * 2; i < size; i++) {
6382                 if (buf[i] == 0xff) {
6383                         unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6384                         for (j = 0; j < buf[i + 1]; j++) {
6385                                 AdvWriteWordAutoIncLram(iop_base, word);
6386                                 len += 2;
6387                         }
6388                         i += 3;
6389                 } else if (buf[i] == 0xfe) {
6390                         unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6391                         AdvWriteWordAutoIncLram(iop_base, word);
6392                         i += 2;
6393                         len += 2;
6394                 } else {
6395                         unsigned char off = buf[i] * 2;
6396                         unsigned short word = (buf[off + 1] << 8) | buf[off];
6397                         AdvWriteWordAutoIncLram(iop_base, word);
6398                         len += 2;
6399                 }
6400         }
6401
6402         end = len;
6403
6404         while (len < memsize) {
6405                 AdvWriteWordAutoIncLram(iop_base, 0);
6406                 len += 2;
6407         }
6408
6409         /* Verify the microcode checksum. */
6410         sum = 0;
6411         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6412
6413         for (len = 0; len < end; len += 2) {
6414                 sum += AdvReadWordAutoIncLram(iop_base);
6415         }
6416
6417         if (sum != chksum)
6418                 return ASC_IERR_MCODE_CHKSUM;
6419
6420         return 0;
6421 }
6422
6423 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6424 {
6425         ADV_CARR_T *carrp;
6426         ADV_SDCNT buf_size;
6427         ADV_PADDR carr_paddr;
6428
6429         carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6430         asc_dvc->carr_freelist = NULL;
6431         if (carrp == asc_dvc->carrier_buf) {
6432                 buf_size = ADV_CARRIER_BUFSIZE;
6433         } else {
6434                 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6435         }
6436
6437         do {
6438                 /* Get physical address of the carrier 'carrp'. */
6439                 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
6440
6441                 buf_size -= sizeof(ADV_CARR_T);
6442
6443                 carrp->carr_pa = carr_paddr;
6444                 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6445
6446                 /*
6447                  * Insert the carrier at the beginning of the freelist.
6448                  */
6449                 carrp->next_vpa =
6450                         cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6451                 asc_dvc->carr_freelist = carrp;
6452
6453                 carrp++;
6454         } while (buf_size > 0);
6455 }
6456
6457 /*
6458  * Send an idle command to the chip and wait for completion.
6459  *
6460  * Command completion is polled for once per microsecond.
6461  *
6462  * The function can be called from anywhere including an interrupt handler.
6463  * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6464  * functions to prevent reentrancy.
6465  *
6466  * Return Values:
6467  *   ADV_TRUE - command completed successfully
6468  *   ADV_FALSE - command failed
6469  *   ADV_ERROR - command timed out
6470  */
6471 static int
6472 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6473                ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6474 {
6475         int result;
6476         ADV_DCNT i, j;
6477         AdvPortAddr iop_base;
6478
6479         iop_base = asc_dvc->iop_base;
6480
6481         /*
6482          * Clear the idle command status which is set by the microcode
6483          * to a non-zero value to indicate when the command is completed.
6484          * The non-zero result is one of the IDLE_CMD_STATUS_* values
6485          */
6486         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6487
6488         /*
6489          * Write the idle command value after the idle command parameter
6490          * has been written to avoid a race condition. If the order is not
6491          * followed, the microcode may process the idle command before the
6492          * parameters have been written to LRAM.
6493          */
6494         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6495                                 cpu_to_le32(idle_cmd_parameter));
6496         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6497
6498         /*
6499          * Tickle the RISC to tell it to process the idle command.
6500          */
6501         AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6502         if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6503                 /*
6504                  * Clear the tickle value. In the ASC-3550 the RISC flag
6505                  * command 'clr_tickle_b' does not work unless the host
6506                  * value is cleared.
6507                  */
6508                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6509         }
6510
6511         /* Wait for up to 100 millisecond for the idle command to timeout. */
6512         for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6513                 /* Poll once each microsecond for command completion. */
6514                 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6515                         AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6516                                         result);
6517                         if (result != 0)
6518                                 return result;
6519                         udelay(1);
6520                 }
6521         }
6522
6523         BUG();          /* The idle command should never timeout. */
6524         return ADV_ERROR;
6525 }
6526
6527 /*
6528  * Reset SCSI Bus and purge all outstanding requests.
6529  *
6530  * Return Value:
6531  *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
6532  *      ADV_FALSE(0) -  Microcode command failed.
6533  *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6534  *                      may be hung which requires driver recovery.
6535  */
6536 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6537 {
6538         int status;
6539
6540         /*
6541          * Send the SCSI Bus Reset idle start idle command which asserts
6542          * the SCSI Bus Reset signal.
6543          */
6544         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6545         if (status != ADV_TRUE) {
6546                 return status;
6547         }
6548
6549         /*
6550          * Delay for the specified SCSI Bus Reset hold time.
6551          *
6552          * The hold time delay is done on the host because the RISC has no
6553          * microsecond accurate timer.
6554          */
6555         udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6556
6557         /*
6558          * Send the SCSI Bus Reset end idle command which de-asserts
6559          * the SCSI Bus Reset signal and purges any pending requests.
6560          */
6561         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6562         if (status != ADV_TRUE) {
6563                 return status;
6564         }
6565
6566         mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
6567
6568         return status;
6569 }
6570
6571 /*
6572  * Initialize the ASC-3550.
6573  *
6574  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6575  *
6576  * For a non-fatal error return a warning code. If there are no warnings
6577  * then 0 is returned.
6578  *
6579  * Needed after initialization for error recovery.
6580  */
6581 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6582 {
6583         AdvPortAddr iop_base;
6584         ushort warn_code;
6585         int begin_addr;
6586         int end_addr;
6587         ushort code_sum;
6588         int word;
6589         int i;
6590         ushort scsi_cfg1;
6591         uchar tid;
6592         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
6593         ushort wdtr_able = 0, sdtr_able, tagqng_able;
6594         uchar max_cmd[ADV_MAX_TID + 1];
6595
6596         /* If there is already an error, don't continue. */
6597         if (asc_dvc->err_code != 0)
6598                 return ADV_ERROR;
6599
6600         /*
6601          * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6602          */
6603         if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6604                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6605                 return ADV_ERROR;
6606         }
6607
6608         warn_code = 0;
6609         iop_base = asc_dvc->iop_base;
6610
6611         /*
6612          * Save the RISC memory BIOS region before writing the microcode.
6613          * The BIOS may already be loaded and using its RISC LRAM region
6614          * so its region must be saved and restored.
6615          *
6616          * Note: This code makes the assumption, which is currently true,
6617          * that a chip reset does not clear RISC LRAM.
6618          */
6619         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6620                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6621                                 bios_mem[i]);
6622         }
6623
6624         /*
6625          * Save current per TID negotiated values.
6626          */
6627         if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6628                 ushort bios_version, major, minor;
6629
6630                 bios_version =
6631                     bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6632                 major = (bios_version >> 12) & 0xF;
6633                 minor = (bios_version >> 8) & 0xF;
6634                 if (major < 3 || (major == 3 && minor == 1)) {
6635                         /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6636                         AdvReadWordLram(iop_base, 0x120, wdtr_able);
6637                 } else {
6638                         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6639                 }
6640         }
6641         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6642         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6643         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6644                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6645                                 max_cmd[tid]);
6646         }
6647
6648         asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6649                                         _adv_asc3550_size, ADV_3550_MEMSIZE,
6650                                         _adv_asc3550_chksum);
6651         if (asc_dvc->err_code)
6652                 return ADV_ERROR;
6653
6654         /*
6655          * Restore the RISC memory BIOS region.
6656          */
6657         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6658                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6659                                  bios_mem[i]);
6660         }
6661
6662         /*
6663          * Calculate and write the microcode code checksum to the microcode
6664          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6665          */
6666         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6667         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6668         code_sum = 0;
6669         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6670         for (word = begin_addr; word < end_addr; word += 2) {
6671                 code_sum += AdvReadWordAutoIncLram(iop_base);
6672         }
6673         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6674
6675         /*
6676          * Read and save microcode version and date.
6677          */
6678         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6679                         asc_dvc->cfg->mcode_date);
6680         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6681                         asc_dvc->cfg->mcode_version);
6682
6683         /*
6684          * Set the chip type to indicate the ASC3550.
6685          */
6686         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6687
6688         /*
6689          * If the PCI Configuration Command Register "Parity Error Response
6690          * Control" Bit was clear (0), then set the microcode variable
6691          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6692          * to ignore DMA parity errors.
6693          */
6694         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6695                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6696                 word |= CONTROL_FLAG_IGNORE_PERR;
6697                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6698         }
6699
6700         /*
6701          * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6702          * threshold of 128 bytes. This register is only accessible to the host.
6703          */
6704         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6705                              START_CTL_EMFU | READ_CMD_MRM);
6706
6707         /*
6708          * Microcode operating variables for WDTR, SDTR, and command tag
6709          * queuing will be set in slave_configure() based on what a
6710          * device reports it is capable of in Inquiry byte 7.
6711          *
6712          * If SCSI Bus Resets have been disabled, then directly set
6713          * SDTR and WDTR from the EEPROM configuration. This will allow
6714          * the BIOS and warm boot to work without a SCSI bus hang on
6715          * the Inquiry caused by host and target mismatched DTR values.
6716          * Without the SCSI Bus Reset, before an Inquiry a device can't
6717          * be assumed to be in Asynchronous, Narrow mode.
6718          */
6719         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
6720                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
6721                                  asc_dvc->wdtr_able);
6722                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
6723                                  asc_dvc->sdtr_able);
6724         }
6725
6726         /*
6727          * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
6728          * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
6729          * bitmask. These values determine the maximum SDTR speed negotiated
6730          * with a device.
6731          *
6732          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6733          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6734          * without determining here whether the device supports SDTR.
6735          *
6736          * 4-bit speed  SDTR speed name
6737          * ===========  ===============
6738          * 0000b (0x0)  SDTR disabled
6739          * 0001b (0x1)  5 Mhz
6740          * 0010b (0x2)  10 Mhz
6741          * 0011b (0x3)  20 Mhz (Ultra)
6742          * 0100b (0x4)  40 Mhz (LVD/Ultra2)
6743          * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
6744          * 0110b (0x6)  Undefined
6745          * .
6746          * 1111b (0xF)  Undefined
6747          */
6748         word = 0;
6749         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6750                 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
6751                         /* Set Ultra speed for TID 'tid'. */
6752                         word |= (0x3 << (4 * (tid % 4)));
6753                 } else {
6754                         /* Set Fast speed for TID 'tid'. */
6755                         word |= (0x2 << (4 * (tid % 4)));
6756                 }
6757                 if (tid == 3) { /* Check if done with sdtr_speed1. */
6758                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
6759                         word = 0;
6760                 } else if (tid == 7) {  /* Check if done with sdtr_speed2. */
6761                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
6762                         word = 0;
6763                 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
6764                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
6765                         word = 0;
6766                 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
6767                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
6768                         /* End of loop. */
6769                 }
6770         }
6771
6772         /*
6773          * Set microcode operating variable for the disconnect per TID bitmask.
6774          */
6775         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
6776                          asc_dvc->cfg->disc_enable);
6777
6778         /*
6779          * Set SCSI_CFG0 Microcode Default Value.
6780          *
6781          * The microcode will set the SCSI_CFG0 register using this value
6782          * after it is started below.
6783          */
6784         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
6785                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
6786                          asc_dvc->chip_scsi_id);
6787
6788         /*
6789          * Determine SCSI_CFG1 Microcode Default Value.
6790          *
6791          * The microcode will set the SCSI_CFG1 register using this value
6792          * after it is started below.
6793          */
6794
6795         /* Read current SCSI_CFG1 Register value. */
6796         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
6797
6798         /*
6799          * If all three connectors are in use, return an error.
6800          */
6801         if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
6802             (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
6803                 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
6804                 return ADV_ERROR;
6805         }
6806
6807         /*
6808          * If the internal narrow cable is reversed all of the SCSI_CTRL
6809          * register signals will be set. Check for and return an error if
6810          * this condition is found.
6811          */
6812         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
6813                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
6814                 return ADV_ERROR;
6815         }
6816
6817         /*
6818          * If this is a differential board and a single-ended device
6819          * is attached to one of the connectors, return an error.
6820          */
6821         if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
6822                 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
6823                 return ADV_ERROR;
6824         }
6825
6826         /*
6827          * If automatic termination control is enabled, then set the
6828          * termination value based on a table listed in a_condor.h.
6829          *
6830          * If manual termination was specified with an EEPROM setting
6831          * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
6832          * is ready to be 'ored' into SCSI_CFG1.
6833          */
6834         if (asc_dvc->cfg->termination == 0) {
6835                 /*
6836                  * The software always controls termination by setting TERM_CTL_SEL.
6837                  * If TERM_CTL_SEL were set to 0, the hardware would set termination.
6838                  */
6839                 asc_dvc->cfg->termination |= TERM_CTL_SEL;
6840
6841                 switch (scsi_cfg1 & CABLE_DETECT) {
6842                         /* TERM_CTL_H: on, TERM_CTL_L: on */
6843                 case 0x3:
6844                 case 0x7:
6845                 case 0xB:
6846                 case 0xD:
6847                 case 0xE:
6848                 case 0xF:
6849                         asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
6850                         break;
6851
6852                         /* TERM_CTL_H: on, TERM_CTL_L: off */
6853                 case 0x1:
6854                 case 0x5:
6855                 case 0x9:
6856                 case 0xA:
6857                 case 0xC:
6858                         asc_dvc->cfg->termination |= TERM_CTL_H;
6859                         break;
6860
6861                         /* TERM_CTL_H: off, TERM_CTL_L: off */
6862                 case 0x2:
6863                 case 0x6:
6864                         break;
6865                 }
6866         }
6867
6868         /*
6869          * Clear any set TERM_CTL_H and TERM_CTL_L bits.
6870          */
6871         scsi_cfg1 &= ~TERM_CTL;
6872
6873         /*
6874          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
6875          * set 'scsi_cfg1'. The TERM_POL bit does not need to be
6876          * referenced, because the hardware internally inverts
6877          * the Termination High and Low bits if TERM_POL is set.
6878          */
6879         scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
6880
6881         /*
6882          * Set SCSI_CFG1 Microcode Default Value
6883          *
6884          * Set filter value and possibly modified termination control
6885          * bits in the Microcode SCSI_CFG1 Register Value.
6886          *
6887          * The microcode will set the SCSI_CFG1 register using this value
6888          * after it is started below.
6889          */
6890         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
6891                          FLTR_DISABLE | scsi_cfg1);
6892
6893         /*
6894          * Set MEM_CFG Microcode Default Value
6895          *
6896          * The microcode will set the MEM_CFG register using this value
6897          * after it is started below.
6898          *
6899          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
6900          * are defined.
6901          *
6902          * ASC-3550 has 8KB internal memory.
6903          */
6904         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
6905                          BIOS_EN | RAM_SZ_8KB);
6906
6907         /*
6908          * Set SEL_MASK Microcode Default Value
6909          *
6910          * The microcode will set the SEL_MASK register using this value
6911          * after it is started below.
6912          */
6913         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
6914                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
6915
6916         AdvBuildCarrierFreelist(asc_dvc);
6917
6918         /*
6919          * Set-up the Host->RISC Initiator Command Queue (ICQ).
6920          */
6921
6922         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
6923                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
6924                 return ADV_ERROR;
6925         }
6926         asc_dvc->carr_freelist = (ADV_CARR_T *)
6927             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
6928
6929         /*
6930          * The first command issued will be placed in the stopper carrier.
6931          */
6932         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
6933
6934         /*
6935          * Set RISC ICQ physical address start value.
6936          */
6937         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
6938
6939         /*
6940          * Set-up the RISC->Host Initiator Response Queue (IRQ).
6941          */
6942         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
6943                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
6944                 return ADV_ERROR;
6945         }
6946         asc_dvc->carr_freelist = (ADV_CARR_T *)
6947             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
6948
6949         /*
6950          * The first command completed by the RISC will be placed in
6951          * the stopper.
6952          *
6953          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
6954          * completed the RISC will set the ASC_RQ_STOPPER bit.
6955          */
6956         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
6957
6958         /*
6959          * Set RISC IRQ physical address start value.
6960          */
6961         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
6962         asc_dvc->carr_pending_cnt = 0;
6963
6964         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
6965                              (ADV_INTR_ENABLE_HOST_INTR |
6966                               ADV_INTR_ENABLE_GLOBAL_INTR));
6967
6968         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
6969         AdvWriteWordRegister(iop_base, IOPW_PC, word);
6970
6971         /* finally, finally, gentlemen, start your engine */
6972         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
6973
6974         /*
6975          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
6976          * Resets should be performed. The RISC has to be running
6977          * to issue a SCSI Bus Reset.
6978          */
6979         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
6980                 /*
6981                  * If the BIOS Signature is present in memory, restore the
6982                  * BIOS Handshake Configuration Table and do not perform
6983                  * a SCSI Bus Reset.
6984                  */
6985                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
6986                     0x55AA) {
6987                         /*
6988                          * Restore per TID negotiated values.
6989                          */
6990                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6991                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6992                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
6993                                          tagqng_able);
6994                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6995                                 AdvWriteByteLram(iop_base,
6996                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
6997                                                  max_cmd[tid]);
6998                         }
6999                 } else {
7000                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7001                                 warn_code = ASC_WARN_BUSRESET_ERROR;
7002                         }
7003                 }
7004         }
7005
7006         return warn_code;
7007 }
7008
7009 /*
7010  * Initialize the ASC-38C0800.
7011  *
7012  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7013  *
7014  * For a non-fatal error return a warning code. If there are no warnings
7015  * then 0 is returned.
7016  *
7017  * Needed after initialization for error recovery.
7018  */
7019 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7020 {
7021         AdvPortAddr iop_base;
7022         ushort warn_code;
7023         int begin_addr;
7024         int end_addr;
7025         ushort code_sum;
7026         int word;
7027         int i;
7028         ushort scsi_cfg1;
7029         uchar byte;
7030         uchar tid;
7031         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
7032         ushort wdtr_able, sdtr_able, tagqng_able;
7033         uchar max_cmd[ADV_MAX_TID + 1];
7034
7035         /* If there is already an error, don't continue. */
7036         if (asc_dvc->err_code != 0)
7037                 return ADV_ERROR;
7038
7039         /*
7040          * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7041          */
7042         if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7043                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7044                 return ADV_ERROR;
7045         }
7046
7047         warn_code = 0;
7048         iop_base = asc_dvc->iop_base;
7049
7050         /*
7051          * Save the RISC memory BIOS region before writing the microcode.
7052          * The BIOS may already be loaded and using its RISC LRAM region
7053          * so its region must be saved and restored.
7054          *
7055          * Note: This code makes the assumption, which is currently true,
7056          * that a chip reset does not clear RISC LRAM.
7057          */
7058         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7059                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7060                                 bios_mem[i]);
7061         }
7062
7063         /*
7064          * Save current per TID negotiated values.
7065          */
7066         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7067         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7068         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7069         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7070                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7071                                 max_cmd[tid]);
7072         }
7073
7074         /*
7075          * RAM BIST (RAM Built-In Self Test)
7076          *
7077          * Address : I/O base + offset 0x38h register (byte).
7078          * Function: Bit 7-6(RW) : RAM mode
7079          *                          Normal Mode   : 0x00
7080          *                          Pre-test Mode : 0x40
7081          *                          RAM Test Mode : 0x80
7082          *           Bit 5       : unused
7083          *           Bit 4(RO)   : Done bit
7084          *           Bit 3-0(RO) : Status
7085          *                          Host Error    : 0x08
7086          *                          Int_RAM Error : 0x04
7087          *                          RISC Error    : 0x02
7088          *                          SCSI Error    : 0x01
7089          *                          No Error      : 0x00
7090          *
7091          * Note: RAM BIST code should be put right here, before loading the
7092          * microcode and after saving the RISC memory BIOS region.
7093          */
7094
7095         /*
7096          * LRAM Pre-test
7097          *
7098          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7099          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7100          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7101          * to NORMAL_MODE, return an error too.
7102          */
7103         for (i = 0; i < 2; i++) {
7104                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7105                 mdelay(10);     /* Wait for 10ms before reading back. */
7106                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7107                 if ((byte & RAM_TEST_DONE) == 0
7108                     || (byte & 0x0F) != PRE_TEST_VALUE) {
7109                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7110                         return ADV_ERROR;
7111                 }
7112
7113                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7114                 mdelay(10);     /* Wait for 10ms before reading back. */
7115                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7116                     != NORMAL_VALUE) {
7117                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7118                         return ADV_ERROR;
7119                 }
7120         }
7121
7122         /*
7123          * LRAM Test - It takes about 1.5 ms to run through the test.
7124          *
7125          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7126          * If Done bit not set or Status not 0, save register byte, set the
7127          * err_code, and return an error.
7128          */
7129         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7130         mdelay(10);     /* Wait for 10ms before checking status. */
7131
7132         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7133         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7134                 /* Get here if Done bit not set or Status not 0. */
7135                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
7136                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7137                 return ADV_ERROR;
7138         }
7139
7140         /* We need to reset back to normal mode after LRAM test passes. */
7141         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7142
7143         asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7144                                  _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7145                                  _adv_asc38C0800_chksum);
7146         if (asc_dvc->err_code)
7147                 return ADV_ERROR;
7148
7149         /*
7150          * Restore the RISC memory BIOS region.
7151          */
7152         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7153                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7154                                  bios_mem[i]);
7155         }
7156
7157         /*
7158          * Calculate and write the microcode code checksum to the microcode
7159          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7160          */
7161         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7162         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7163         code_sum = 0;
7164         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7165         for (word = begin_addr; word < end_addr; word += 2) {
7166                 code_sum += AdvReadWordAutoIncLram(iop_base);
7167         }
7168         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7169
7170         /*
7171          * Read microcode version and date.
7172          */
7173         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7174                         asc_dvc->cfg->mcode_date);
7175         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7176                         asc_dvc->cfg->mcode_version);
7177
7178         /*
7179          * Set the chip type to indicate the ASC38C0800.
7180          */
7181         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7182
7183         /*
7184          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7185          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7186          * cable detection and then we are able to read C_DET[3:0].
7187          *
7188          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7189          * Microcode Default Value' section below.
7190          */
7191         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7192         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7193                              scsi_cfg1 | DIS_TERM_DRV);
7194
7195         /*
7196          * If the PCI Configuration Command Register "Parity Error Response
7197          * Control" Bit was clear (0), then set the microcode variable
7198          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7199          * to ignore DMA parity errors.
7200          */
7201         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7202                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7203                 word |= CONTROL_FLAG_IGNORE_PERR;
7204                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7205         }
7206
7207         /*
7208          * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7209          * bits for the default FIFO threshold.
7210          *
7211          * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7212          *
7213          * For DMA Errata #4 set the BC_THRESH_ENB bit.
7214          */
7215         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7216                              BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7217                              READ_CMD_MRM);
7218
7219         /*
7220          * Microcode operating variables for WDTR, SDTR, and command tag
7221          * queuing will be set in slave_configure() based on what a
7222          * device reports it is capable of in Inquiry byte 7.
7223          *
7224          * If SCSI Bus Resets have been disabled, then directly set
7225          * SDTR and WDTR from the EEPROM configuration. This will allow
7226          * the BIOS and warm boot to work without a SCSI bus hang on
7227          * the Inquiry caused by host and target mismatched DTR values.
7228          * Without the SCSI Bus Reset, before an Inquiry a device can't
7229          * be assumed to be in Asynchronous, Narrow mode.
7230          */
7231         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7232                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7233                                  asc_dvc->wdtr_able);
7234                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7235                                  asc_dvc->sdtr_able);
7236         }
7237
7238         /*
7239          * Set microcode operating variables for DISC and SDTR_SPEED1,
7240          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7241          * configuration values.
7242          *
7243          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7244          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7245          * without determining here whether the device supports SDTR.
7246          */
7247         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7248                          asc_dvc->cfg->disc_enable);
7249         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7250         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7251         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7252         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7253
7254         /*
7255          * Set SCSI_CFG0 Microcode Default Value.
7256          *
7257          * The microcode will set the SCSI_CFG0 register using this value
7258          * after it is started below.
7259          */
7260         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7261                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7262                          asc_dvc->chip_scsi_id);
7263
7264         /*
7265          * Determine SCSI_CFG1 Microcode Default Value.
7266          *
7267          * The microcode will set the SCSI_CFG1 register using this value
7268          * after it is started below.
7269          */
7270
7271         /* Read current SCSI_CFG1 Register value. */
7272         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7273
7274         /*
7275          * If the internal narrow cable is reversed all of the SCSI_CTRL
7276          * register signals will be set. Check for and return an error if
7277          * this condition is found.
7278          */
7279         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7280                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7281                 return ADV_ERROR;
7282         }
7283
7284         /*
7285          * All kind of combinations of devices attached to one of four
7286          * connectors are acceptable except HVD device attached. For example,
7287          * LVD device can be attached to SE connector while SE device attached
7288          * to LVD connector.  If LVD device attached to SE connector, it only
7289          * runs up to Ultra speed.
7290          *
7291          * If an HVD device is attached to one of LVD connectors, return an
7292          * error.  However, there is no way to detect HVD device attached to
7293          * SE connectors.
7294          */
7295         if (scsi_cfg1 & HVD) {
7296                 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7297                 return ADV_ERROR;
7298         }
7299
7300         /*
7301          * If either SE or LVD automatic termination control is enabled, then
7302          * set the termination value based on a table listed in a_condor.h.
7303          *
7304          * If manual termination was specified with an EEPROM setting then
7305          * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7306          * to be 'ored' into SCSI_CFG1.
7307          */
7308         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7309                 /* SE automatic termination control is enabled. */
7310                 switch (scsi_cfg1 & C_DET_SE) {
7311                         /* TERM_SE_HI: on, TERM_SE_LO: on */
7312                 case 0x1:
7313                 case 0x2:
7314                 case 0x3:
7315                         asc_dvc->cfg->termination |= TERM_SE;
7316                         break;
7317
7318                         /* TERM_SE_HI: on, TERM_SE_LO: off */
7319                 case 0x0:
7320                         asc_dvc->cfg->termination |= TERM_SE_HI;
7321                         break;
7322                 }
7323         }
7324
7325         if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7326                 /* LVD automatic termination control is enabled. */
7327                 switch (scsi_cfg1 & C_DET_LVD) {
7328                         /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7329                 case 0x4:
7330                 case 0x8:
7331                 case 0xC:
7332                         asc_dvc->cfg->termination |= TERM_LVD;
7333                         break;
7334
7335                         /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7336                 case 0x0:
7337                         break;
7338                 }
7339         }
7340
7341         /*
7342          * Clear any set TERM_SE and TERM_LVD bits.
7343          */
7344         scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7345
7346         /*
7347          * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7348          */
7349         scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7350
7351         /*
7352          * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7353          * bits and set possibly modified termination control bits in the
7354          * Microcode SCSI_CFG1 Register Value.
7355          */
7356         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7357
7358         /*
7359          * Set SCSI_CFG1 Microcode Default Value
7360          *
7361          * Set possibly modified termination control and reset DIS_TERM_DRV
7362          * bits in the Microcode SCSI_CFG1 Register Value.
7363          *
7364          * The microcode will set the SCSI_CFG1 register using this value
7365          * after it is started below.
7366          */
7367         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7368
7369         /*
7370          * Set MEM_CFG Microcode Default Value
7371          *
7372          * The microcode will set the MEM_CFG register using this value
7373          * after it is started below.
7374          *
7375          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7376          * are defined.
7377          *
7378          * ASC-38C0800 has 16KB internal memory.
7379          */
7380         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7381                          BIOS_EN | RAM_SZ_16KB);
7382
7383         /*
7384          * Set SEL_MASK Microcode Default Value
7385          *
7386          * The microcode will set the SEL_MASK register using this value
7387          * after it is started below.
7388          */
7389         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7390                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7391
7392         AdvBuildCarrierFreelist(asc_dvc);
7393
7394         /*
7395          * Set-up the Host->RISC Initiator Command Queue (ICQ).
7396          */
7397
7398         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7399                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7400                 return ADV_ERROR;
7401         }
7402         asc_dvc->carr_freelist = (ADV_CARR_T *)
7403             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7404
7405         /*
7406          * The first command issued will be placed in the stopper carrier.
7407          */
7408         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7409
7410         /*
7411          * Set RISC ICQ physical address start value.
7412          * carr_pa is LE, must be native before write
7413          */
7414         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7415
7416         /*
7417          * Set-up the RISC->Host Initiator Response Queue (IRQ).
7418          */
7419         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7420                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7421                 return ADV_ERROR;
7422         }
7423         asc_dvc->carr_freelist = (ADV_CARR_T *)
7424             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7425
7426         /*
7427          * The first command completed by the RISC will be placed in
7428          * the stopper.
7429          *
7430          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7431          * completed the RISC will set the ASC_RQ_STOPPER bit.
7432          */
7433         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7434
7435         /*
7436          * Set RISC IRQ physical address start value.
7437          *
7438          * carr_pa is LE, must be native before write *
7439          */
7440         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7441         asc_dvc->carr_pending_cnt = 0;
7442
7443         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7444                              (ADV_INTR_ENABLE_HOST_INTR |
7445                               ADV_INTR_ENABLE_GLOBAL_INTR));
7446
7447         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7448         AdvWriteWordRegister(iop_base, IOPW_PC, word);
7449
7450         /* finally, finally, gentlemen, start your engine */
7451         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7452
7453         /*
7454          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7455          * Resets should be performed. The RISC has to be running
7456          * to issue a SCSI Bus Reset.
7457          */
7458         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7459                 /*
7460                  * If the BIOS Signature is present in memory, restore the
7461                  * BIOS Handshake Configuration Table and do not perform
7462                  * a SCSI Bus Reset.
7463                  */
7464                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7465                     0x55AA) {
7466                         /*
7467                          * Restore per TID negotiated values.
7468                          */
7469                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7470                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7471                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7472                                          tagqng_able);
7473                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7474                                 AdvWriteByteLram(iop_base,
7475                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
7476                                                  max_cmd[tid]);
7477                         }
7478                 } else {
7479                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7480                                 warn_code = ASC_WARN_BUSRESET_ERROR;
7481                         }
7482                 }
7483         }
7484
7485         return warn_code;
7486 }
7487
7488 /*
7489  * Initialize the ASC-38C1600.
7490  *
7491  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7492  *
7493  * For a non-fatal error return a warning code. If there are no warnings
7494  * then 0 is returned.
7495  *
7496  * Needed after initialization for error recovery.
7497  */
7498 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7499 {
7500         AdvPortAddr iop_base;
7501         ushort warn_code;
7502         int begin_addr;
7503         int end_addr;
7504         ushort code_sum;
7505         long word;
7506         int i;
7507         ushort scsi_cfg1;
7508         uchar byte;
7509         uchar tid;
7510         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
7511         ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7512         uchar max_cmd[ASC_MAX_TID + 1];
7513
7514         /* If there is already an error, don't continue. */
7515         if (asc_dvc->err_code != 0) {
7516                 return ADV_ERROR;
7517         }
7518
7519         /*
7520          * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7521          */
7522         if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7523                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7524                 return ADV_ERROR;
7525         }
7526
7527         warn_code = 0;
7528         iop_base = asc_dvc->iop_base;
7529
7530         /*
7531          * Save the RISC memory BIOS region before writing the microcode.
7532          * The BIOS may already be loaded and using its RISC LRAM region
7533          * so its region must be saved and restored.
7534          *
7535          * Note: This code makes the assumption, which is currently true,
7536          * that a chip reset does not clear RISC LRAM.
7537          */
7538         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7539                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7540                                 bios_mem[i]);
7541         }
7542
7543         /*
7544          * Save current per TID negotiated values.
7545          */
7546         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7547         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7548         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7549         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7550         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7551                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7552                                 max_cmd[tid]);
7553         }
7554
7555         /*
7556          * RAM BIST (Built-In Self Test)
7557          *
7558          * Address : I/O base + offset 0x38h register (byte).
7559          * Function: Bit 7-6(RW) : RAM mode
7560          *                          Normal Mode   : 0x00
7561          *                          Pre-test Mode : 0x40
7562          *                          RAM Test Mode : 0x80
7563          *           Bit 5       : unused
7564          *           Bit 4(RO)   : Done bit
7565          *           Bit 3-0(RO) : Status
7566          *                          Host Error    : 0x08
7567          *                          Int_RAM Error : 0x04
7568          *                          RISC Error    : 0x02
7569          *                          SCSI Error    : 0x01
7570          *                          No Error      : 0x00
7571          *
7572          * Note: RAM BIST code should be put right here, before loading the
7573          * microcode and after saving the RISC memory BIOS region.
7574          */
7575
7576         /*
7577          * LRAM Pre-test
7578          *
7579          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7580          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7581          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7582          * to NORMAL_MODE, return an error too.
7583          */
7584         for (i = 0; i < 2; i++) {
7585                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7586                 mdelay(10);     /* Wait for 10ms before reading back. */
7587                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7588                 if ((byte & RAM_TEST_DONE) == 0
7589                     || (byte & 0x0F) != PRE_TEST_VALUE) {
7590                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7591                         return ADV_ERROR;
7592                 }
7593
7594                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7595                 mdelay(10);     /* Wait for 10ms before reading back. */
7596                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7597                     != NORMAL_VALUE) {
7598                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7599                         return ADV_ERROR;
7600                 }
7601         }
7602
7603         /*
7604          * LRAM Test - It takes about 1.5 ms to run through the test.
7605          *
7606          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7607          * If Done bit not set or Status not 0, save register byte, set the
7608          * err_code, and return an error.
7609          */
7610         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7611         mdelay(10);     /* Wait for 10ms before checking status. */
7612
7613         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7614         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7615                 /* Get here if Done bit not set or Status not 0. */
7616                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
7617                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7618                 return ADV_ERROR;
7619         }
7620
7621         /* We need to reset back to normal mode after LRAM test passes. */
7622         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7623
7624         asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7625                                  _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7626                                  _adv_asc38C1600_chksum);
7627         if (asc_dvc->err_code)
7628                 return ADV_ERROR;
7629
7630         /*
7631          * Restore the RISC memory BIOS region.
7632          */
7633         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7634                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7635                                  bios_mem[i]);
7636         }
7637
7638         /*
7639          * Calculate and write the microcode code checksum to the microcode
7640          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7641          */
7642         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7643         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7644         code_sum = 0;
7645         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7646         for (word = begin_addr; word < end_addr; word += 2) {
7647                 code_sum += AdvReadWordAutoIncLram(iop_base);
7648         }
7649         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7650
7651         /*
7652          * Read microcode version and date.
7653          */
7654         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7655                         asc_dvc->cfg->mcode_date);
7656         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7657                         asc_dvc->cfg->mcode_version);
7658
7659         /*
7660          * Set the chip type to indicate the ASC38C1600.
7661          */
7662         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7663
7664         /*
7665          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7666          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7667          * cable detection and then we are able to read C_DET[3:0].
7668          *
7669          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7670          * Microcode Default Value' section below.
7671          */
7672         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7673         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7674                              scsi_cfg1 | DIS_TERM_DRV);
7675
7676         /*
7677          * If the PCI Configuration Command Register "Parity Error Response
7678          * Control" Bit was clear (0), then set the microcode variable
7679          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7680          * to ignore DMA parity errors.
7681          */
7682         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7683                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7684                 word |= CONTROL_FLAG_IGNORE_PERR;
7685                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7686         }
7687
7688         /*
7689          * If the BIOS control flag AIPP (Asynchronous Information
7690          * Phase Protection) disable bit is not set, then set the firmware
7691          * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7692          * AIPP checking and encoding.
7693          */
7694         if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7695                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7696                 word |= CONTROL_FLAG_ENABLE_AIPP;
7697                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7698         }
7699
7700         /*
7701          * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7702          * and START_CTL_TH [3:2].
7703          */
7704         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7705                              FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7706
7707         /*
7708          * Microcode operating variables for WDTR, SDTR, and command tag
7709          * queuing will be set in slave_configure() based on what a
7710          * device reports it is capable of in Inquiry byte 7.
7711          *
7712          * If SCSI Bus Resets have been disabled, then directly set
7713          * SDTR and WDTR from the EEPROM configuration. This will allow
7714          * the BIOS and warm boot to work without a SCSI bus hang on
7715          * the Inquiry caused by host and target mismatched DTR values.
7716          * Without the SCSI Bus Reset, before an Inquiry a device can't
7717          * be assumed to be in Asynchronous, Narrow mode.
7718          */
7719         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7720                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7721                                  asc_dvc->wdtr_able);
7722                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7723                                  asc_dvc->sdtr_able);
7724         }
7725
7726         /*
7727          * Set microcode operating variables for DISC and SDTR_SPEED1,
7728          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7729          * configuration values.
7730          *
7731          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7732          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7733          * without determining here whether the device supports SDTR.
7734          */
7735         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7736                          asc_dvc->cfg->disc_enable);
7737         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7738         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7739         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7740         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7741
7742         /*
7743          * Set SCSI_CFG0 Microcode Default Value.
7744          *
7745          * The microcode will set the SCSI_CFG0 register using this value
7746          * after it is started below.
7747          */
7748         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7749                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7750                          asc_dvc->chip_scsi_id);
7751
7752         /*
7753          * Calculate SCSI_CFG1 Microcode Default Value.
7754          *
7755          * The microcode will set the SCSI_CFG1 register using this value
7756          * after it is started below.
7757          *
7758          * Each ASC-38C1600 function has only two cable detect bits.
7759          * The bus mode override bits are in IOPB_SOFT_OVER_WR.
7760          */
7761         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7762
7763         /*
7764          * If the cable is reversed all of the SCSI_CTRL register signals
7765          * will be set. Check for and return an error if this condition is
7766          * found.
7767          */
7768         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7769                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7770                 return ADV_ERROR;
7771         }
7772
7773         /*
7774          * Each ASC-38C1600 function has two connectors. Only an HVD device
7775          * can not be connected to either connector. An LVD device or SE device
7776          * may be connected to either connecor. If an SE device is connected,
7777          * then at most Ultra speed (20 Mhz) can be used on both connectors.
7778          *
7779          * If an HVD device is attached, return an error.
7780          */
7781         if (scsi_cfg1 & HVD) {
7782                 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
7783                 return ADV_ERROR;
7784         }
7785
7786         /*
7787          * Each function in the ASC-38C1600 uses only the SE cable detect and
7788          * termination because there are two connectors for each function. Each
7789          * function may use either LVD or SE mode. Corresponding the SE automatic
7790          * termination control EEPROM bits are used for each function. Each
7791          * function has its own EEPROM. If SE automatic control is enabled for
7792          * the function, then set the termination value based on a table listed
7793          * in a_condor.h.
7794          *
7795          * If manual termination is specified in the EEPROM for the function,
7796          * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
7797          * ready to be 'ored' into SCSI_CFG1.
7798          */
7799         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7800                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
7801                 /* SE automatic termination control is enabled. */
7802                 switch (scsi_cfg1 & C_DET_SE) {
7803                         /* TERM_SE_HI: on, TERM_SE_LO: on */
7804                 case 0x1:
7805                 case 0x2:
7806                 case 0x3:
7807                         asc_dvc->cfg->termination |= TERM_SE;
7808                         break;
7809
7810                 case 0x0:
7811                         if (PCI_FUNC(pdev->devfn) == 0) {
7812                                 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
7813                         } else {
7814                                 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
7815                                 asc_dvc->cfg->termination |= TERM_SE_HI;
7816                         }
7817                         break;
7818                 }
7819         }
7820
7821         /*
7822          * Clear any set TERM_SE bits.
7823          */
7824         scsi_cfg1 &= ~TERM_SE;
7825
7826         /*
7827          * Invert the TERM_SE bits and then set 'scsi_cfg1'.
7828          */
7829         scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
7830
7831         /*
7832          * Clear Big Endian and Terminator Polarity bits and set possibly
7833          * modified termination control bits in the Microcode SCSI_CFG1
7834          * Register Value.
7835          *
7836          * Big Endian bit is not used even on big endian machines.
7837          */
7838         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
7839
7840         /*
7841          * Set SCSI_CFG1 Microcode Default Value
7842          *
7843          * Set possibly modified termination control bits in the Microcode
7844          * SCSI_CFG1 Register Value.
7845          *
7846          * The microcode will set the SCSI_CFG1 register using this value
7847          * after it is started below.
7848          */
7849         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7850
7851         /*
7852          * Set MEM_CFG Microcode Default Value
7853          *
7854          * The microcode will set the MEM_CFG register using this value
7855          * after it is started below.
7856          *
7857          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7858          * are defined.
7859          *
7860          * ASC-38C1600 has 32KB internal memory.
7861          *
7862          * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
7863          * out a special 16K Adv Library and Microcode version. After the issue
7864          * resolved, we should turn back to the 32K support. Both a_condor.h and
7865          * mcode.sas files also need to be updated.
7866          *
7867          * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7868          *  BIOS_EN | RAM_SZ_32KB);
7869          */
7870         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7871                          BIOS_EN | RAM_SZ_16KB);
7872
7873         /*
7874          * Set SEL_MASK Microcode Default Value
7875          *
7876          * The microcode will set the SEL_MASK register using this value
7877          * after it is started below.
7878          */
7879         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7880                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7881
7882         AdvBuildCarrierFreelist(asc_dvc);
7883
7884         /*
7885          * Set-up the Host->RISC Initiator Command Queue (ICQ).
7886          */
7887         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7888                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7889                 return ADV_ERROR;
7890         }
7891         asc_dvc->carr_freelist = (ADV_CARR_T *)
7892             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7893
7894         /*
7895          * The first command issued will be placed in the stopper carrier.
7896          */
7897         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7898
7899         /*
7900          * Set RISC ICQ physical address start value. Initialize the
7901          * COMMA register to the same value otherwise the RISC will
7902          * prematurely detect a command is available.
7903          */
7904         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7905         AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
7906                               le32_to_cpu(asc_dvc->icq_sp->carr_pa));
7907
7908         /*
7909          * Set-up the RISC->Host Initiator Response Queue (IRQ).
7910          */
7911         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7912                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7913                 return ADV_ERROR;
7914         }
7915         asc_dvc->carr_freelist = (ADV_CARR_T *)
7916             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7917
7918         /*
7919          * The first command completed by the RISC will be placed in
7920          * the stopper.
7921          *
7922          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7923          * completed the RISC will set the ASC_RQ_STOPPER bit.
7924          */
7925         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7926
7927         /*
7928          * Set RISC IRQ physical address start value.
7929          */
7930         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7931         asc_dvc->carr_pending_cnt = 0;
7932
7933         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7934                              (ADV_INTR_ENABLE_HOST_INTR |
7935                               ADV_INTR_ENABLE_GLOBAL_INTR));
7936         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7937         AdvWriteWordRegister(iop_base, IOPW_PC, word);
7938
7939         /* finally, finally, gentlemen, start your engine */
7940         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7941
7942         /*
7943          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7944          * Resets should be performed. The RISC has to be running
7945          * to issue a SCSI Bus Reset.
7946          */
7947         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7948                 /*
7949                  * If the BIOS Signature is present in memory, restore the
7950                  * per TID microcode operating variables.
7951                  */
7952                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7953                     0x55AA) {
7954                         /*
7955                          * Restore per TID negotiated values.
7956                          */
7957                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7958                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7959                         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7960                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7961                                          tagqng_able);
7962                         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7963                                 AdvWriteByteLram(iop_base,
7964                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
7965                                                  max_cmd[tid]);
7966                         }
7967                 } else {
7968                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7969                                 warn_code = ASC_WARN_BUSRESET_ERROR;
7970                         }
7971                 }
7972         }
7973
7974         return warn_code;
7975 }
7976
7977 /*
7978  * Reset chip and SCSI Bus.
7979  *
7980  * Return Value:
7981  *      ADV_TRUE(1) -   Chip re-initialization and SCSI Bus Reset successful.
7982  *      ADV_FALSE(0) -  Chip re-initialization and SCSI Bus Reset failure.
7983  */
7984 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
7985 {
7986         int status;
7987         ushort wdtr_able, sdtr_able, tagqng_able;
7988         ushort ppr_able = 0;
7989         uchar tid, max_cmd[ADV_MAX_TID + 1];
7990         AdvPortAddr iop_base;
7991         ushort bios_sig;
7992
7993         iop_base = asc_dvc->iop_base;
7994
7995         /*
7996          * Save current per TID negotiated values.
7997          */
7998         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7999         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8000         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8001                 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8002         }
8003         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8004         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8005                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8006                                 max_cmd[tid]);
8007         }
8008
8009         /*
8010          * Force the AdvInitAsc3550/38C0800Driver() function to
8011          * perform a SCSI Bus Reset by clearing the BIOS signature word.
8012          * The initialization functions assumes a SCSI Bus Reset is not
8013          * needed if the BIOS signature word is present.
8014          */
8015         AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8016         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8017
8018         /*
8019          * Stop chip and reset it.
8020          */
8021         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8022         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8023         mdelay(100);
8024         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8025                              ADV_CTRL_REG_CMD_WR_IO_REG);
8026
8027         /*
8028          * Reset Adv Library error code, if any, and try
8029          * re-initializing the chip.
8030          */
8031         asc_dvc->err_code = 0;
8032         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8033                 status = AdvInitAsc38C1600Driver(asc_dvc);
8034         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8035                 status = AdvInitAsc38C0800Driver(asc_dvc);
8036         } else {
8037                 status = AdvInitAsc3550Driver(asc_dvc);
8038         }
8039
8040         /* Translate initialization return value to status value. */
8041         if (status == 0) {
8042                 status = ADV_TRUE;
8043         } else {
8044                 status = ADV_FALSE;
8045         }
8046
8047         /*
8048          * Restore the BIOS signature word.
8049          */
8050         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8051
8052         /*
8053          * Restore per TID negotiated values.
8054          */
8055         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8056         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8057         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8058                 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8059         }
8060         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8061         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8062                 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8063                                  max_cmd[tid]);
8064         }
8065
8066         return status;
8067 }
8068
8069 /*
8070  * adv_async_callback() - Adv Library asynchronous event callback function.
8071  */
8072 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8073 {
8074         switch (code) {
8075         case ADV_ASYNC_SCSI_BUS_RESET_DET:
8076                 /*
8077                  * The firmware detected a SCSI Bus reset.
8078                  */
8079                 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8080                 break;
8081
8082         case ADV_ASYNC_RDMA_FAILURE:
8083                 /*
8084                  * Handle RDMA failure by resetting the SCSI Bus and
8085                  * possibly the chip if it is unresponsive. Log the error
8086                  * with a unique code.
8087                  */
8088                 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
8089                 AdvResetChipAndSB(adv_dvc_varp);
8090                 break;
8091
8092         case ADV_HOST_SCSI_BUS_RESET:
8093                 /*
8094                  * Host generated SCSI bus reset occurred.
8095                  */
8096                 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
8097                 break;
8098
8099         default:
8100                 ASC_DBG(0, "unknown code 0x%x\n", code);
8101                 break;
8102         }
8103 }
8104
8105 /*
8106  * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8107  *
8108  * Callback function for the Wide SCSI Adv Library.
8109  */
8110 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8111 {
8112         struct asc_board *boardp;
8113         adv_req_t *reqp;
8114         adv_sgblk_t *sgblkp;
8115         struct scsi_cmnd *scp;
8116         struct Scsi_Host *shost;
8117         ADV_DCNT resid_cnt;
8118
8119         ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8120                  (ulong)adv_dvc_varp, (ulong)scsiqp);
8121         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8122
8123         /*
8124          * Get the adv_req_t structure for the command that has been
8125          * completed. The adv_req_t structure actually contains the
8126          * completed ADV_SCSI_REQ_Q structure.
8127          */
8128         reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8129         ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
8130         if (reqp == NULL) {
8131                 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8132                 return;
8133         }
8134
8135         /*
8136          * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8137          * command that has been completed.
8138          *
8139          * Note: The adv_req_t request structure and adv_sgblk_t structure,
8140          * if any, are dropped, because a board structure pointer can not be
8141          * determined.
8142          */
8143         scp = reqp->cmndp;
8144         ASC_DBG(1, "scp 0x%p\n", scp);
8145         if (scp == NULL) {
8146                 ASC_PRINT
8147                     ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8148                 return;
8149         }
8150         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8151
8152         shost = scp->device->host;
8153         ASC_STATS(shost, callback);
8154         ASC_DBG(1, "shost 0x%p\n", shost);
8155
8156         boardp = shost_priv(shost);
8157         BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8158
8159         /*
8160          * 'done_status' contains the command's ending status.
8161          */
8162         switch (scsiqp->done_status) {
8163         case QD_NO_ERROR:
8164                 ASC_DBG(2, "QD_NO_ERROR\n");
8165                 scp->result = 0;
8166
8167                 /*
8168                  * Check for an underrun condition.
8169                  *
8170                  * If there was no error and an underrun condition, then
8171                  * then return the number of underrun bytes.
8172                  */
8173                 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8174                 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
8175                     resid_cnt <= scsi_bufflen(scp)) {
8176                         ASC_DBG(1, "underrun condition %lu bytes\n",
8177                                  (ulong)resid_cnt);
8178                         scsi_set_resid(scp, resid_cnt);
8179                 }
8180                 break;
8181
8182         case QD_WITH_ERROR:
8183                 ASC_DBG(2, "QD_WITH_ERROR\n");
8184                 switch (scsiqp->host_status) {
8185                 case QHSTA_NO_ERROR:
8186                         if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8187                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
8188                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8189                                                   sizeof(scp->sense_buffer));
8190                                 /*
8191                                  * Note: The 'status_byte()' macro used by
8192                                  * target drivers defined in scsi.h shifts the
8193                                  * status byte returned by host drivers right
8194                                  * by 1 bit.  This is why target drivers also
8195                                  * use right shifted status byte definitions.
8196                                  * For instance target drivers use
8197                                  * CHECK_CONDITION, defined to 0x1, instead of
8198                                  * the SCSI defined check condition value of
8199                                  * 0x2. Host drivers are supposed to return
8200                                  * the status byte as it is defined by SCSI.
8201                                  */
8202                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8203                                     STATUS_BYTE(scsiqp->scsi_status);
8204                         } else {
8205                                 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8206                         }
8207                         break;
8208
8209                 default:
8210                         /* Some other QHSTA error occurred. */
8211                         ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
8212                         scp->result = HOST_BYTE(DID_BAD_TARGET);
8213                         break;
8214                 }
8215                 break;
8216
8217         case QD_ABORTED_BY_HOST:
8218                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
8219                 scp->result =
8220                     HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8221                 break;
8222
8223         default:
8224                 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
8225                 scp->result =
8226                     HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8227                 break;
8228         }
8229
8230         /*
8231          * If the 'init_tidmask' bit isn't already set for the target and the
8232          * current request finished normally, then set the bit for the target
8233          * to indicate that a device is present.
8234          */
8235         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8236             scsiqp->done_status == QD_NO_ERROR &&
8237             scsiqp->host_status == QHSTA_NO_ERROR) {
8238                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8239         }
8240
8241         asc_scsi_done(scp);
8242
8243         /*
8244          * Free all 'adv_sgblk_t' structures allocated for the request.
8245          */
8246         while ((sgblkp = reqp->sgblkp) != NULL) {
8247                 /* Remove 'sgblkp' from the request list. */
8248                 reqp->sgblkp = sgblkp->next_sgblkp;
8249
8250                 /* Add 'sgblkp' to the board free list. */
8251                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8252                 boardp->adv_sgblkp = sgblkp;
8253         }
8254
8255         /*
8256          * Free the adv_req_t structure used with the command by adding
8257          * it back to the board free list.
8258          */
8259         reqp->next_reqp = boardp->adv_reqp;
8260         boardp->adv_reqp = reqp;
8261
8262         ASC_DBG(1, "done\n");
8263 }
8264
8265 /*
8266  * Adv Library Interrupt Service Routine
8267  *
8268  *  This function is called by a driver's interrupt service routine.
8269  *  The function disables and re-enables interrupts.
8270  *
8271  *  When a microcode idle command is completed, the ADV_DVC_VAR
8272  *  'idle_cmd_done' field is set to ADV_TRUE.
8273  *
8274  *  Note: AdvISR() can be called when interrupts are disabled or even
8275  *  when there is no hardware interrupt condition present. It will
8276  *  always check for completed idle commands and microcode requests.
8277  *  This is an important feature that shouldn't be changed because it
8278  *  allows commands to be completed from polling mode loops.
8279  *
8280  * Return:
8281  *   ADV_TRUE(1) - interrupt was pending
8282  *   ADV_FALSE(0) - no interrupt was pending
8283  */
8284 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8285 {
8286         AdvPortAddr iop_base;
8287         uchar int_stat;
8288         ushort target_bit;
8289         ADV_CARR_T *free_carrp;
8290         ADV_VADDR irq_next_vpa;
8291         ADV_SCSI_REQ_Q *scsiq;
8292
8293         iop_base = asc_dvc->iop_base;
8294
8295         /* Reading the register clears the interrupt. */
8296         int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8297
8298         if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8299                          ADV_INTR_STATUS_INTRC)) == 0) {
8300                 return ADV_FALSE;
8301         }
8302
8303         /*
8304          * Notify the driver of an asynchronous microcode condition by
8305          * calling the adv_async_callback function. The function
8306          * is passed the microcode ASC_MC_INTRB_CODE byte value.
8307          */
8308         if (int_stat & ADV_INTR_STATUS_INTRB) {
8309                 uchar intrb_code;
8310
8311                 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8312
8313                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8314                     asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8315                         if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8316                             asc_dvc->carr_pending_cnt != 0) {
8317                                 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8318                                                      ADV_TICKLE_A);
8319                                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8320                                         AdvWriteByteRegister(iop_base,
8321                                                              IOPB_TICKLE,
8322                                                              ADV_TICKLE_NOP);
8323                                 }
8324                         }
8325                 }
8326
8327                 adv_async_callback(asc_dvc, intrb_code);
8328         }
8329
8330         /*
8331          * Check if the IRQ stopper carrier contains a completed request.
8332          */
8333         while (((irq_next_vpa =
8334                  le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8335                 /*
8336                  * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8337                  * The RISC will have set 'areq_vpa' to a virtual address.
8338                  *
8339                  * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8340                  * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8341                  * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8342                  * in AdvExeScsiQueue().
8343                  */
8344                 scsiq = (ADV_SCSI_REQ_Q *)
8345                     ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8346
8347                 /*
8348                  * Request finished with good status and the queue was not
8349                  * DMAed to host memory by the firmware. Set all status fields
8350                  * to indicate good status.
8351                  */
8352                 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8353                         scsiq->done_status = QD_NO_ERROR;
8354                         scsiq->host_status = scsiq->scsi_status = 0;
8355                         scsiq->data_cnt = 0L;
8356                 }
8357
8358                 /*
8359                  * Advance the stopper pointer to the next carrier
8360                  * ignoring the lower four bits. Free the previous
8361                  * stopper carrier.
8362                  */
8363                 free_carrp = asc_dvc->irq_sp;
8364                 asc_dvc->irq_sp = (ADV_CARR_T *)
8365                     ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8366
8367                 free_carrp->next_vpa =
8368                     cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8369                 asc_dvc->carr_freelist = free_carrp;
8370                 asc_dvc->carr_pending_cnt--;
8371
8372                 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8373
8374                 /*
8375                  * Clear request microcode control flag.
8376                  */
8377                 scsiq->cntl = 0;
8378
8379                 /*
8380                  * Notify the driver of the completed request by passing
8381                  * the ADV_SCSI_REQ_Q pointer to its callback function.
8382                  */
8383                 scsiq->a_flag |= ADV_SCSIQ_DONE;
8384                 adv_isr_callback(asc_dvc, scsiq);
8385                 /*
8386                  * Note: After the driver callback function is called, 'scsiq'
8387                  * can no longer be referenced.
8388                  *
8389                  * Fall through and continue processing other completed
8390                  * requests...
8391                  */
8392         }
8393         return ADV_TRUE;
8394 }
8395
8396 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8397 {
8398         if (asc_dvc->err_code == 0) {
8399                 asc_dvc->err_code = err_code;
8400                 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8401                                  err_code);
8402         }
8403         return err_code;
8404 }
8405
8406 static void AscAckInterrupt(PortAddr iop_base)
8407 {
8408         uchar host_flag;
8409         uchar risc_flag;
8410         ushort loop;
8411
8412         loop = 0;
8413         do {
8414                 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8415                 if (loop++ > 0x7FFF) {
8416                         break;
8417                 }
8418         } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8419         host_flag =
8420             AscReadLramByte(iop_base,
8421                             ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8422         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8423                          (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8424         AscSetChipStatus(iop_base, CIW_INT_ACK);
8425         loop = 0;
8426         while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8427                 AscSetChipStatus(iop_base, CIW_INT_ACK);
8428                 if (loop++ > 3) {
8429                         break;
8430                 }
8431         }
8432         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8433 }
8434
8435 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8436 {
8437         const uchar *period_table;
8438         int max_index;
8439         int min_index;
8440         int i;
8441
8442         period_table = asc_dvc->sdtr_period_tbl;
8443         max_index = (int)asc_dvc->max_sdtr_index;
8444         min_index = (int)asc_dvc->min_sdtr_index;
8445         if ((syn_time <= period_table[max_index])) {
8446                 for (i = min_index; i < (max_index - 1); i++) {
8447                         if (syn_time <= period_table[i]) {
8448                                 return (uchar)i;
8449                         }
8450                 }
8451                 return (uchar)max_index;
8452         } else {
8453                 return (uchar)(max_index + 1);
8454         }
8455 }
8456
8457 static uchar
8458 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8459 {
8460         EXT_MSG sdtr_buf;
8461         uchar sdtr_period_index;
8462         PortAddr iop_base;
8463
8464         iop_base = asc_dvc->iop_base;
8465         sdtr_buf.msg_type = EXTENDED_MESSAGE;
8466         sdtr_buf.msg_len = MS_SDTR_LEN;
8467         sdtr_buf.msg_req = EXTENDED_SDTR;
8468         sdtr_buf.xfer_period = sdtr_period;
8469         sdtr_offset &= ASC_SYN_MAX_OFFSET;
8470         sdtr_buf.req_ack_offset = sdtr_offset;
8471         sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8472         if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8473                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8474                                         (uchar *)&sdtr_buf,
8475                                         sizeof(EXT_MSG) >> 1);
8476                 return ((sdtr_period_index << 4) | sdtr_offset);
8477         } else {
8478                 sdtr_buf.req_ack_offset = 0;
8479                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8480                                         (uchar *)&sdtr_buf,
8481                                         sizeof(EXT_MSG) >> 1);
8482                 return 0;
8483         }
8484 }
8485
8486 static uchar
8487 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8488 {
8489         uchar byte;
8490         uchar sdtr_period_ix;
8491
8492         sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8493         if (sdtr_period_ix > asc_dvc->max_sdtr_index)
8494                 return 0xFF;
8495         byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8496         return byte;
8497 }
8498
8499 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8500 {
8501         ASC_SCSI_BIT_ID_TYPE org_id;
8502         int i;
8503         int sta = TRUE;
8504
8505         AscSetBank(iop_base, 1);
8506         org_id = AscReadChipDvcID(iop_base);
8507         for (i = 0; i <= ASC_MAX_TID; i++) {
8508                 if (org_id == (0x01 << i))
8509                         break;
8510         }
8511         org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8512         AscWriteChipDvcID(iop_base, id);
8513         if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8514                 AscSetBank(iop_base, 0);
8515                 AscSetChipSyn(iop_base, sdtr_data);
8516                 if (AscGetChipSyn(iop_base) != sdtr_data) {
8517                         sta = FALSE;
8518                 }
8519         } else {
8520                 sta = FALSE;
8521         }
8522         AscSetBank(iop_base, 1);
8523         AscWriteChipDvcID(iop_base, org_id);
8524         AscSetBank(iop_base, 0);
8525         return (sta);
8526 }
8527
8528 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8529 {
8530         AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8531         AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8532 }
8533
8534 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8535 {
8536         EXT_MSG ext_msg;
8537         EXT_MSG out_msg;
8538         ushort halt_q_addr;
8539         int sdtr_accept;
8540         ushort int_halt_code;
8541         ASC_SCSI_BIT_ID_TYPE scsi_busy;
8542         ASC_SCSI_BIT_ID_TYPE target_id;
8543         PortAddr iop_base;
8544         uchar tag_code;
8545         uchar q_status;
8546         uchar halt_qp;
8547         uchar sdtr_data;
8548         uchar target_ix;
8549         uchar q_cntl, tid_no;
8550         uchar cur_dvc_qng;
8551         uchar asyn_sdtr;
8552         uchar scsi_status;
8553         struct asc_board *boardp;
8554
8555         BUG_ON(!asc_dvc->drv_ptr);
8556         boardp = asc_dvc->drv_ptr;
8557
8558         iop_base = asc_dvc->iop_base;
8559         int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8560
8561         halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8562         halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8563         target_ix = AscReadLramByte(iop_base,
8564                                     (ushort)(halt_q_addr +
8565                                              (ushort)ASC_SCSIQ_B_TARGET_IX));
8566         q_cntl = AscReadLramByte(iop_base,
8567                             (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8568         tid_no = ASC_TIX_TO_TID(target_ix);
8569         target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8570         if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8571                 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8572         } else {
8573                 asyn_sdtr = 0;
8574         }
8575         if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8576                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8577                         AscSetChipSDTR(iop_base, 0, tid_no);
8578                         boardp->sdtr_data[tid_no] = 0;
8579                 }
8580                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8581                 return (0);
8582         } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8583                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8584                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8585                         boardp->sdtr_data[tid_no] = asyn_sdtr;
8586                 }
8587                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8588                 return (0);
8589         } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8590                 AscMemWordCopyPtrFromLram(iop_base,
8591                                           ASCV_MSGIN_BEG,
8592                                           (uchar *)&ext_msg,
8593                                           sizeof(EXT_MSG) >> 1);
8594
8595                 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8596                     ext_msg.msg_req == EXTENDED_SDTR &&
8597                     ext_msg.msg_len == MS_SDTR_LEN) {
8598                         sdtr_accept = TRUE;
8599                         if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8600
8601                                 sdtr_accept = FALSE;
8602                                 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8603                         }
8604                         if ((ext_msg.xfer_period <
8605                              asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
8606                             || (ext_msg.xfer_period >
8607                                 asc_dvc->sdtr_period_tbl[asc_dvc->
8608                                                          max_sdtr_index])) {
8609                                 sdtr_accept = FALSE;
8610                                 ext_msg.xfer_period =
8611                                     asc_dvc->sdtr_period_tbl[asc_dvc->
8612                                                              min_sdtr_index];
8613                         }
8614                         if (sdtr_accept) {
8615                                 sdtr_data =
8616                                     AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8617                                                    ext_msg.req_ack_offset);
8618                                 if ((sdtr_data == 0xFF)) {
8619
8620                                         q_cntl |= QC_MSG_OUT;
8621                                         asc_dvc->init_sdtr &= ~target_id;
8622                                         asc_dvc->sdtr_done &= ~target_id;
8623                                         AscSetChipSDTR(iop_base, asyn_sdtr,
8624                                                        tid_no);
8625                                         boardp->sdtr_data[tid_no] = asyn_sdtr;
8626                                 }
8627                         }
8628                         if (ext_msg.req_ack_offset == 0) {
8629
8630                                 q_cntl &= ~QC_MSG_OUT;
8631                                 asc_dvc->init_sdtr &= ~target_id;
8632                                 asc_dvc->sdtr_done &= ~target_id;
8633                                 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8634                         } else {
8635                                 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8636                                         q_cntl &= ~QC_MSG_OUT;
8637                                         asc_dvc->sdtr_done |= target_id;
8638                                         asc_dvc->init_sdtr |= target_id;
8639                                         asc_dvc->pci_fix_asyn_xfer &=
8640                                             ~target_id;
8641                                         sdtr_data =
8642                                             AscCalSDTRData(asc_dvc,
8643                                                            ext_msg.xfer_period,
8644                                                            ext_msg.
8645                                                            req_ack_offset);
8646                                         AscSetChipSDTR(iop_base, sdtr_data,
8647                                                        tid_no);
8648                                         boardp->sdtr_data[tid_no] = sdtr_data;
8649                                 } else {
8650                                         q_cntl |= QC_MSG_OUT;
8651                                         AscMsgOutSDTR(asc_dvc,
8652                                                       ext_msg.xfer_period,
8653                                                       ext_msg.req_ack_offset);
8654                                         asc_dvc->pci_fix_asyn_xfer &=
8655                                             ~target_id;
8656                                         sdtr_data =
8657                                             AscCalSDTRData(asc_dvc,
8658                                                            ext_msg.xfer_period,
8659                                                            ext_msg.
8660                                                            req_ack_offset);
8661                                         AscSetChipSDTR(iop_base, sdtr_data,
8662                                                        tid_no);
8663                                         boardp->sdtr_data[tid_no] = sdtr_data;
8664                                         asc_dvc->sdtr_done |= target_id;
8665                                         asc_dvc->init_sdtr |= target_id;
8666                                 }
8667                         }
8668
8669                         AscWriteLramByte(iop_base,
8670                                          (ushort)(halt_q_addr +
8671                                                   (ushort)ASC_SCSIQ_B_CNTL),
8672                                          q_cntl);
8673                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8674                         return (0);
8675                 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8676                            ext_msg.msg_req == EXTENDED_WDTR &&
8677                            ext_msg.msg_len == MS_WDTR_LEN) {
8678
8679                         ext_msg.wdtr_width = 0;
8680                         AscMemWordCopyPtrToLram(iop_base,
8681                                                 ASCV_MSGOUT_BEG,
8682                                                 (uchar *)&ext_msg,
8683                                                 sizeof(EXT_MSG) >> 1);
8684                         q_cntl |= QC_MSG_OUT;
8685                         AscWriteLramByte(iop_base,
8686                                          (ushort)(halt_q_addr +
8687                                                   (ushort)ASC_SCSIQ_B_CNTL),
8688                                          q_cntl);
8689                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8690                         return (0);
8691                 } else {
8692
8693                         ext_msg.msg_type = MESSAGE_REJECT;
8694                         AscMemWordCopyPtrToLram(iop_base,
8695                                                 ASCV_MSGOUT_BEG,
8696                                                 (uchar *)&ext_msg,
8697                                                 sizeof(EXT_MSG) >> 1);
8698                         q_cntl |= QC_MSG_OUT;
8699                         AscWriteLramByte(iop_base,
8700                                          (ushort)(halt_q_addr +
8701                                                   (ushort)ASC_SCSIQ_B_CNTL),
8702                                          q_cntl);
8703                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8704                         return (0);
8705                 }
8706         } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
8707
8708                 q_cntl |= QC_REQ_SENSE;
8709
8710                 if ((asc_dvc->init_sdtr & target_id) != 0) {
8711
8712                         asc_dvc->sdtr_done &= ~target_id;
8713
8714                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8715                         q_cntl |= QC_MSG_OUT;
8716                         AscMsgOutSDTR(asc_dvc,
8717                                       asc_dvc->
8718                                       sdtr_period_tbl[(sdtr_data >> 4) &
8719                                                       (uchar)(asc_dvc->
8720                                                               max_sdtr_index -
8721                                                               1)],
8722                                       (uchar)(sdtr_data & (uchar)
8723                                               ASC_SYN_MAX_OFFSET));
8724                 }
8725
8726                 AscWriteLramByte(iop_base,
8727                                  (ushort)(halt_q_addr +
8728                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8729
8730                 tag_code = AscReadLramByte(iop_base,
8731                                            (ushort)(halt_q_addr + (ushort)
8732                                                     ASC_SCSIQ_B_TAG_CODE));
8733                 tag_code &= 0xDC;
8734                 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
8735                     && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
8736                     ) {
8737
8738                         tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8739                                      | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
8740
8741                 }
8742                 AscWriteLramByte(iop_base,
8743                                  (ushort)(halt_q_addr +
8744                                           (ushort)ASC_SCSIQ_B_TAG_CODE),
8745                                  tag_code);
8746
8747                 q_status = AscReadLramByte(iop_base,
8748                                            (ushort)(halt_q_addr + (ushort)
8749                                                     ASC_SCSIQ_B_STATUS));
8750                 q_status |= (QS_READY | QS_BUSY);
8751                 AscWriteLramByte(iop_base,
8752                                  (ushort)(halt_q_addr +
8753                                           (ushort)ASC_SCSIQ_B_STATUS),
8754                                  q_status);
8755
8756                 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
8757                 scsi_busy &= ~target_id;
8758                 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8759
8760                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8761                 return (0);
8762         } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
8763
8764                 AscMemWordCopyPtrFromLram(iop_base,
8765                                           ASCV_MSGOUT_BEG,
8766                                           (uchar *)&out_msg,
8767                                           sizeof(EXT_MSG) >> 1);
8768
8769                 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
8770                     (out_msg.msg_len == MS_SDTR_LEN) &&
8771                     (out_msg.msg_req == EXTENDED_SDTR)) {
8772
8773                         asc_dvc->init_sdtr &= ~target_id;
8774                         asc_dvc->sdtr_done &= ~target_id;
8775                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8776                         boardp->sdtr_data[tid_no] = asyn_sdtr;
8777                 }
8778                 q_cntl &= ~QC_MSG_OUT;
8779                 AscWriteLramByte(iop_base,
8780                                  (ushort)(halt_q_addr +
8781                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8782                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8783                 return (0);
8784         } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
8785
8786                 scsi_status = AscReadLramByte(iop_base,
8787                                               (ushort)((ushort)halt_q_addr +
8788                                                        (ushort)
8789                                                        ASC_SCSIQ_SCSI_STATUS));
8790                 cur_dvc_qng =
8791                     AscReadLramByte(iop_base,
8792                                     (ushort)((ushort)ASC_QADR_BEG +
8793                                              (ushort)target_ix));
8794                 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
8795
8796                         scsi_busy = AscReadLramByte(iop_base,
8797                                                     (ushort)ASCV_SCSIBUSY_B);
8798                         scsi_busy |= target_id;
8799                         AscWriteLramByte(iop_base,
8800                                          (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8801                         asc_dvc->queue_full_or_busy |= target_id;
8802
8803                         if (scsi_status == SAM_STAT_TASK_SET_FULL) {
8804                                 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
8805                                         cur_dvc_qng -= 1;
8806                                         asc_dvc->max_dvc_qng[tid_no] =
8807                                             cur_dvc_qng;
8808
8809                                         AscWriteLramByte(iop_base,
8810                                                          (ushort)((ushort)
8811                                                                   ASCV_MAX_DVC_QNG_BEG
8812                                                                   + (ushort)
8813                                                                   tid_no),
8814                                                          cur_dvc_qng);
8815
8816                                         /*
8817                                          * Set the device queue depth to the
8818                                          * number of active requests when the
8819                                          * QUEUE FULL condition was encountered.
8820                                          */
8821                                         boardp->queue_full |= target_id;
8822                                         boardp->queue_full_cnt[tid_no] =
8823                                             cur_dvc_qng;
8824                                 }
8825                         }
8826                 }
8827                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8828                 return (0);
8829         }
8830 #if CC_VERY_LONG_SG_LIST
8831         else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
8832                 uchar q_no;
8833                 ushort q_addr;
8834                 uchar sg_wk_q_no;
8835                 uchar first_sg_wk_q_no;
8836                 ASC_SCSI_Q *scsiq;      /* Ptr to driver request. */
8837                 ASC_SG_HEAD *sg_head;   /* Ptr to driver SG request. */
8838                 ASC_SG_LIST_Q scsi_sg_q;        /* Structure written to queue. */
8839                 ushort sg_list_dwords;
8840                 ushort sg_entry_cnt;
8841                 uchar next_qp;
8842                 int i;
8843
8844                 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
8845                 if (q_no == ASC_QLINK_END)
8846                         return 0;
8847
8848                 q_addr = ASC_QNO_TO_QADDR(q_no);
8849
8850                 /*
8851                  * Convert the request's SRB pointer to a host ASC_SCSI_REQ
8852                  * structure pointer using a macro provided by the driver.
8853                  * The ASC_SCSI_REQ pointer provides a pointer to the
8854                  * host ASC_SG_HEAD structure.
8855                  */
8856                 /* Read request's SRB pointer. */
8857                 scsiq = (ASC_SCSI_Q *)
8858                     ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
8859                                                                     (ushort)
8860                                                                     (q_addr +
8861                                                                      ASC_SCSIQ_D_SRBPTR))));
8862
8863                 /*
8864                  * Get request's first and working SG queue.
8865                  */
8866                 sg_wk_q_no = AscReadLramByte(iop_base,
8867                                              (ushort)(q_addr +
8868                                                       ASC_SCSIQ_B_SG_WK_QP));
8869
8870                 first_sg_wk_q_no = AscReadLramByte(iop_base,
8871                                                    (ushort)(q_addr +
8872                                                             ASC_SCSIQ_B_FIRST_SG_WK_QP));
8873
8874                 /*
8875                  * Reset request's working SG queue back to the
8876                  * first SG queue.
8877                  */
8878                 AscWriteLramByte(iop_base,
8879                                  (ushort)(q_addr +
8880                                           (ushort)ASC_SCSIQ_B_SG_WK_QP),
8881                                  first_sg_wk_q_no);
8882
8883                 sg_head = scsiq->sg_head;
8884
8885                 /*
8886                  * Set sg_entry_cnt to the number of SG elements
8887                  * that will be completed on this interrupt.
8888                  *
8889                  * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
8890                  * SG elements. The data_cnt and data_addr fields which
8891                  * add 1 to the SG element capacity are not used when
8892                  * restarting SG handling after a halt.
8893                  */
8894                 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
8895                         sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8896
8897                         /*
8898                          * Keep track of remaining number of SG elements that
8899                          * will need to be handled on the next interrupt.
8900                          */
8901                         scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
8902                 } else {
8903                         sg_entry_cnt = scsiq->remain_sg_entry_cnt;
8904                         scsiq->remain_sg_entry_cnt = 0;
8905                 }
8906
8907                 /*
8908                  * Copy SG elements into the list of allocated SG queues.
8909                  *
8910                  * Last index completed is saved in scsiq->next_sg_index.
8911                  */
8912                 next_qp = first_sg_wk_q_no;
8913                 q_addr = ASC_QNO_TO_QADDR(next_qp);
8914                 scsi_sg_q.sg_head_qp = q_no;
8915                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8916                 for (i = 0; i < sg_head->queue_cnt; i++) {
8917                         scsi_sg_q.seq_no = i + 1;
8918                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8919                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8920                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8921                                 /*
8922                                  * After very first SG queue RISC FW uses next
8923                                  * SG queue first element then checks sg_list_cnt
8924                                  * against zero and then decrements, so set
8925                                  * sg_list_cnt 1 less than number of SG elements
8926                                  * in each SG queue.
8927                                  */
8928                                 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
8929                                 scsi_sg_q.sg_cur_list_cnt =
8930                                     ASC_SG_LIST_PER_Q - 1;
8931                         } else {
8932                                 /*
8933                                  * This is the last SG queue in the list of
8934                                  * allocated SG queues. If there are more
8935                                  * SG elements than will fit in the allocated
8936                                  * queues, then set the QCSG_SG_XFER_MORE flag.
8937                                  */
8938                                 if (scsiq->remain_sg_entry_cnt != 0) {
8939                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8940                                 } else {
8941                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8942                                 }
8943                                 /* equals sg_entry_cnt * 2 */
8944                                 sg_list_dwords = sg_entry_cnt << 1;
8945                                 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
8946                                 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
8947                                 sg_entry_cnt = 0;
8948                         }
8949
8950                         scsi_sg_q.q_no = next_qp;
8951                         AscMemWordCopyPtrToLram(iop_base,
8952                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8953                                                 (uchar *)&scsi_sg_q,
8954                                                 sizeof(ASC_SG_LIST_Q) >> 1);
8955
8956                         AscMemDWordCopyPtrToLram(iop_base,
8957                                                  q_addr + ASC_SGQ_LIST_BEG,
8958                                                  (uchar *)&sg_head->
8959                                                  sg_list[scsiq->next_sg_index],
8960                                                  sg_list_dwords);
8961
8962                         scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
8963
8964                         /*
8965                          * If the just completed SG queue contained the
8966                          * last SG element, then no more SG queues need
8967                          * to be written.
8968                          */
8969                         if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
8970                                 break;
8971                         }
8972
8973                         next_qp = AscReadLramByte(iop_base,
8974                                                   (ushort)(q_addr +
8975                                                            ASC_SCSIQ_B_FWD));
8976                         q_addr = ASC_QNO_TO_QADDR(next_qp);
8977                 }
8978
8979                 /*
8980                  * Clear the halt condition so the RISC will be restarted
8981                  * after the return.
8982                  */
8983                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8984                 return (0);
8985         }
8986 #endif /* CC_VERY_LONG_SG_LIST */
8987         return (0);
8988 }
8989
8990 /*
8991  * void
8992  * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8993  *
8994  * Calling/Exit State:
8995  *    none
8996  *
8997  * Description:
8998  *     Input an ASC_QDONE_INFO structure from the chip
8999  */
9000 static void
9001 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9002 {
9003         int i;
9004         ushort word;
9005
9006         AscSetChipLramAddr(iop_base, s_addr);
9007         for (i = 0; i < 2 * words; i += 2) {
9008                 if (i == 10) {
9009                         continue;
9010                 }
9011                 word = inpw(iop_base + IOP_RAM_DATA);
9012                 inbuf[i] = word & 0xff;
9013                 inbuf[i + 1] = (word >> 8) & 0xff;
9014         }
9015         ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9016 }
9017
9018 static uchar
9019 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9020                       ushort q_addr,
9021                       ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9022 {
9023         ushort _val;
9024         uchar sg_queue_cnt;
9025
9026         DvcGetQinfo(iop_base,
9027                     q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9028                     (uchar *)scsiq,
9029                     (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9030
9031         _val = AscReadLramWord(iop_base,
9032                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9033         scsiq->q_status = (uchar)_val;
9034         scsiq->q_no = (uchar)(_val >> 8);
9035         _val = AscReadLramWord(iop_base,
9036                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9037         scsiq->cntl = (uchar)_val;
9038         sg_queue_cnt = (uchar)(_val >> 8);
9039         _val = AscReadLramWord(iop_base,
9040                                (ushort)(q_addr +
9041                                         (ushort)ASC_SCSIQ_B_SENSE_LEN));
9042         scsiq->sense_len = (uchar)_val;
9043         scsiq->extra_bytes = (uchar)(_val >> 8);
9044
9045         /*
9046          * Read high word of remain bytes from alternate location.
9047          */
9048         scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9049                                                           (ushort)(q_addr +
9050                                                                    (ushort)
9051                                                                    ASC_SCSIQ_W_ALT_DC1)))
9052                                << 16);
9053         /*
9054          * Read low word of remain bytes from original location.
9055          */
9056         scsiq->remain_bytes += AscReadLramWord(iop_base,
9057                                                (ushort)(q_addr + (ushort)
9058                                                         ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9059
9060         scsiq->remain_bytes &= max_dma_count;
9061         return sg_queue_cnt;
9062 }
9063
9064 /*
9065  * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9066  *
9067  * Interrupt callback function for the Narrow SCSI Asc Library.
9068  */
9069 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9070 {
9071         struct asc_board *boardp;
9072         struct scsi_cmnd *scp;
9073         struct Scsi_Host *shost;
9074
9075         ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
9076         ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9077
9078         /*
9079          * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9080          * command that has been completed.
9081          */
9082         scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9083         ASC_DBG(1, "scp 0x%p\n", scp);
9084
9085         if (scp == NULL) {
9086                 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9087                 return;
9088         }
9089         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9090
9091         shost = scp->device->host;
9092         ASC_STATS(shost, callback);
9093         ASC_DBG(1, "shost 0x%p\n", shost);
9094
9095         boardp = shost_priv(shost);
9096         BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9097
9098         /*
9099          * 'qdonep' contains the command's ending status.
9100          */
9101         switch (qdonep->d3.done_stat) {
9102         case QD_NO_ERROR:
9103                 ASC_DBG(2, "QD_NO_ERROR\n");
9104                 scp->result = 0;
9105
9106                 /*
9107                  * Check for an underrun condition.
9108                  *
9109                  * If there was no error and an underrun condition, then
9110                  * return the number of underrun bytes.
9111                  */
9112                 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
9113                     qdonep->remain_bytes <= scsi_bufflen(scp)) {
9114                         ASC_DBG(1, "underrun condition %u bytes\n",
9115                                  (unsigned)qdonep->remain_bytes);
9116                         scsi_set_resid(scp, qdonep->remain_bytes);
9117                 }
9118                 break;
9119
9120         case QD_WITH_ERROR:
9121                 ASC_DBG(2, "QD_WITH_ERROR\n");
9122                 switch (qdonep->d3.host_stat) {
9123                 case QHSTA_NO_ERROR:
9124                         if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9125                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
9126                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9127                                                   sizeof(scp->sense_buffer));
9128                                 /*
9129                                  * Note: The 'status_byte()' macro used by
9130                                  * target drivers defined in scsi.h shifts the
9131                                  * status byte returned by host drivers right
9132                                  * by 1 bit.  This is why target drivers also
9133                                  * use right shifted status byte definitions.
9134                                  * For instance target drivers use
9135                                  * CHECK_CONDITION, defined to 0x1, instead of
9136                                  * the SCSI defined check condition value of
9137                                  * 0x2. Host drivers are supposed to return
9138                                  * the status byte as it is defined by SCSI.
9139                                  */
9140                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9141                                     STATUS_BYTE(qdonep->d3.scsi_stat);
9142                         } else {
9143                                 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9144                         }
9145                         break;
9146
9147                 default:
9148                         /* QHSTA error occurred */
9149                         ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
9150                         scp->result = HOST_BYTE(DID_BAD_TARGET);
9151                         break;
9152                 }
9153                 break;
9154
9155         case QD_ABORTED_BY_HOST:
9156                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
9157                 scp->result =
9158                     HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9159                                                     scsi_msg) |
9160                     STATUS_BYTE(qdonep->d3.scsi_stat);
9161                 break;
9162
9163         default:
9164                 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
9165                 scp->result =
9166                     HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9167                                                     scsi_msg) |
9168                     STATUS_BYTE(qdonep->d3.scsi_stat);
9169                 break;
9170         }
9171
9172         /*
9173          * If the 'init_tidmask' bit isn't already set for the target and the
9174          * current request finished normally, then set the bit for the target
9175          * to indicate that a device is present.
9176          */
9177         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9178             qdonep->d3.done_stat == QD_NO_ERROR &&
9179             qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9180                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9181         }
9182
9183         asc_scsi_done(scp);
9184 }
9185
9186 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9187 {
9188         uchar next_qp;
9189         uchar n_q_used;
9190         uchar sg_list_qp;
9191         uchar sg_queue_cnt;
9192         uchar q_cnt;
9193         uchar done_q_tail;
9194         uchar tid_no;
9195         ASC_SCSI_BIT_ID_TYPE scsi_busy;
9196         ASC_SCSI_BIT_ID_TYPE target_id;
9197         PortAddr iop_base;
9198         ushort q_addr;
9199         ushort sg_q_addr;
9200         uchar cur_target_qng;
9201         ASC_QDONE_INFO scsiq_buf;
9202         ASC_QDONE_INFO *scsiq;
9203         int false_overrun;
9204
9205         iop_base = asc_dvc->iop_base;
9206         n_q_used = 1;
9207         scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9208         done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9209         q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9210         next_qp = AscReadLramByte(iop_base,
9211                                   (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9212         if (next_qp != ASC_QLINK_END) {
9213                 AscPutVarDoneQTail(iop_base, next_qp);
9214                 q_addr = ASC_QNO_TO_QADDR(next_qp);
9215                 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9216                                                      asc_dvc->max_dma_count);
9217                 AscWriteLramByte(iop_base,
9218                                  (ushort)(q_addr +
9219                                           (ushort)ASC_SCSIQ_B_STATUS),
9220                                  (uchar)(scsiq->
9221                                          q_status & (uchar)~(QS_READY |
9222                                                              QS_ABORTED)));
9223                 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9224                 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9225                 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9226                         sg_q_addr = q_addr;
9227                         sg_list_qp = next_qp;
9228                         for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9229                                 sg_list_qp = AscReadLramByte(iop_base,
9230                                                              (ushort)(sg_q_addr
9231                                                                       + (ushort)
9232                                                                       ASC_SCSIQ_B_FWD));
9233                                 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9234                                 if (sg_list_qp == ASC_QLINK_END) {
9235                                         AscSetLibErrorCode(asc_dvc,
9236                                                            ASCQ_ERR_SG_Q_LINKS);
9237                                         scsiq->d3.done_stat = QD_WITH_ERROR;
9238                                         scsiq->d3.host_stat =
9239                                             QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9240                                         goto FATAL_ERR_QDONE;
9241                                 }
9242                                 AscWriteLramByte(iop_base,
9243                                                  (ushort)(sg_q_addr + (ushort)
9244                                                           ASC_SCSIQ_B_STATUS),
9245                                                  QS_FREE);
9246                         }
9247                         n_q_used = sg_queue_cnt + 1;
9248                         AscPutVarDoneQTail(iop_base, sg_list_qp);
9249                 }
9250                 if (asc_dvc->queue_full_or_busy & target_id) {
9251                         cur_target_qng = AscReadLramByte(iop_base,
9252                                                          (ushort)((ushort)
9253                                                                   ASC_QADR_BEG
9254                                                                   + (ushort)
9255                                                                   scsiq->d2.
9256                                                                   target_ix));
9257                         if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9258                                 scsi_busy = AscReadLramByte(iop_base, (ushort)
9259                                                             ASCV_SCSIBUSY_B);
9260                                 scsi_busy &= ~target_id;
9261                                 AscWriteLramByte(iop_base,
9262                                                  (ushort)ASCV_SCSIBUSY_B,
9263                                                  scsi_busy);
9264                                 asc_dvc->queue_full_or_busy &= ~target_id;
9265                         }
9266                 }
9267                 if (asc_dvc->cur_total_qng >= n_q_used) {
9268                         asc_dvc->cur_total_qng -= n_q_used;
9269                         if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9270                                 asc_dvc->cur_dvc_qng[tid_no]--;
9271                         }
9272                 } else {
9273                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9274                         scsiq->d3.done_stat = QD_WITH_ERROR;
9275                         goto FATAL_ERR_QDONE;
9276                 }
9277                 if ((scsiq->d2.srb_ptr == 0UL) ||
9278                     ((scsiq->q_status & QS_ABORTED) != 0)) {
9279                         return (0x11);
9280                 } else if (scsiq->q_status == QS_DONE) {
9281                         false_overrun = FALSE;
9282                         if (scsiq->extra_bytes != 0) {
9283                                 scsiq->remain_bytes +=
9284                                     (ADV_DCNT)scsiq->extra_bytes;
9285                         }
9286                         if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9287                                 if (scsiq->d3.host_stat ==
9288                                     QHSTA_M_DATA_OVER_RUN) {
9289                                         if ((scsiq->
9290                                              cntl & (QC_DATA_IN | QC_DATA_OUT))
9291                                             == 0) {
9292                                                 scsiq->d3.done_stat =
9293                                                     QD_NO_ERROR;
9294                                                 scsiq->d3.host_stat =
9295                                                     QHSTA_NO_ERROR;
9296                                         } else if (false_overrun) {
9297                                                 scsiq->d3.done_stat =
9298                                                     QD_NO_ERROR;
9299                                                 scsiq->d3.host_stat =
9300                                                     QHSTA_NO_ERROR;
9301                                         }
9302                                 } else if (scsiq->d3.host_stat ==
9303                                            QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9304                                         AscStopChip(iop_base);
9305                                         AscSetChipControl(iop_base,
9306                                                           (uchar)(CC_SCSI_RESET
9307                                                                   | CC_HALT));
9308                                         udelay(60);
9309                                         AscSetChipControl(iop_base, CC_HALT);
9310                                         AscSetChipStatus(iop_base,
9311                                                          CIW_CLR_SCSI_RESET_INT);
9312                                         AscSetChipStatus(iop_base, 0);
9313                                         AscSetChipControl(iop_base, 0);
9314                                 }
9315                         }
9316                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9317                                 asc_isr_callback(asc_dvc, scsiq);
9318                         } else {
9319                                 if ((AscReadLramByte(iop_base,
9320                                                      (ushort)(q_addr + (ushort)
9321                                                               ASC_SCSIQ_CDB_BEG))
9322                                      == START_STOP)) {
9323                                         asc_dvc->unit_not_ready &= ~target_id;
9324                                         if (scsiq->d3.done_stat != QD_NO_ERROR) {
9325                                                 asc_dvc->start_motor &=
9326                                                     ~target_id;
9327                                         }
9328                                 }
9329                         }
9330                         return (1);
9331                 } else {
9332                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9333  FATAL_ERR_QDONE:
9334                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9335                                 asc_isr_callback(asc_dvc, scsiq);
9336                         }
9337                         return (0x80);
9338                 }
9339         }
9340         return (0);
9341 }
9342
9343 static int AscISR(ASC_DVC_VAR *asc_dvc)
9344 {
9345         ASC_CS_TYPE chipstat;
9346         PortAddr iop_base;
9347         ushort saved_ram_addr;
9348         uchar ctrl_reg;
9349         uchar saved_ctrl_reg;
9350         int int_pending;
9351         int status;
9352         uchar host_flag;
9353
9354         iop_base = asc_dvc->iop_base;
9355         int_pending = FALSE;
9356
9357         if (AscIsIntPending(iop_base) == 0)
9358                 return int_pending;
9359
9360         if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9361                 return ERR;
9362         }
9363         if (asc_dvc->in_critical_cnt != 0) {
9364                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9365                 return ERR;
9366         }
9367         if (asc_dvc->is_in_int) {
9368                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9369                 return ERR;
9370         }
9371         asc_dvc->is_in_int = TRUE;
9372         ctrl_reg = AscGetChipControl(iop_base);
9373         saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9374                                        CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9375         chipstat = AscGetChipStatus(iop_base);
9376         if (chipstat & CSW_SCSI_RESET_LATCH) {
9377                 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9378                         int i = 10;
9379                         int_pending = TRUE;
9380                         asc_dvc->sdtr_done = 0;
9381                         saved_ctrl_reg &= (uchar)(~CC_HALT);
9382                         while ((AscGetChipStatus(iop_base) &
9383                                 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9384                                 mdelay(100);
9385                         }
9386                         AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9387                         AscSetChipControl(iop_base, CC_HALT);
9388                         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9389                         AscSetChipStatus(iop_base, 0);
9390                         chipstat = AscGetChipStatus(iop_base);
9391                 }
9392         }
9393         saved_ram_addr = AscGetChipLramAddr(iop_base);
9394         host_flag = AscReadLramByte(iop_base,
9395                                     ASCV_HOST_FLAG_B) &
9396             (uchar)(~ASC_HOST_FLAG_IN_ISR);
9397         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9398                          (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9399         if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9400                 AscAckInterrupt(iop_base);
9401                 int_pending = TRUE;
9402                 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9403                         if (AscIsrChipHalted(asc_dvc) == ERR) {
9404                                 goto ISR_REPORT_QDONE_FATAL_ERROR;
9405                         } else {
9406                                 saved_ctrl_reg &= (uchar)(~CC_HALT);
9407                         }
9408                 } else {
9409  ISR_REPORT_QDONE_FATAL_ERROR:
9410                         if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9411                                 while (((status =
9412                                          AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9413                                 }
9414                         } else {
9415                                 do {
9416                                         if ((status =
9417                                              AscIsrQDone(asc_dvc)) == 1) {
9418                                                 break;
9419                                         }
9420                                 } while (status == 0x11);
9421                         }
9422                         if ((status & 0x80) != 0)
9423                                 int_pending = ERR;
9424                 }
9425         }
9426         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9427         AscSetChipLramAddr(iop_base, saved_ram_addr);
9428         AscSetChipControl(iop_base, saved_ctrl_reg);
9429         asc_dvc->is_in_int = FALSE;
9430         return int_pending;
9431 }
9432
9433 /*
9434  * advansys_reset()
9435  *
9436  * Reset the bus associated with the command 'scp'.
9437  *
9438  * This function runs its own thread. Interrupts must be blocked but
9439  * sleeping is allowed and no locking other than for host structures is
9440  * required. Returns SUCCESS or FAILED.
9441  */
9442 static int advansys_reset(struct scsi_cmnd *scp)
9443 {
9444         struct Scsi_Host *shost = scp->device->host;
9445         struct asc_board *boardp = shost_priv(shost);
9446         unsigned long flags;
9447         int status;
9448         int ret = SUCCESS;
9449
9450         ASC_DBG(1, "0x%p\n", scp);
9451
9452         ASC_STATS(shost, reset);
9453
9454         scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9455
9456         if (ASC_NARROW_BOARD(boardp)) {
9457                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9458
9459                 /* Reset the chip and SCSI bus. */
9460                 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
9461                 status = AscInitAsc1000Driver(asc_dvc);
9462
9463                 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9464                 if (asc_dvc->err_code) {
9465                         scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9466                                     "0x%x\n", asc_dvc->err_code);
9467                         ret = FAILED;
9468                 } else if (status) {
9469                         scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9470                                     "0x%x\n", status);
9471                 } else {
9472                         scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9473                                     "successful\n");
9474                 }
9475
9476                 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
9477                 spin_lock_irqsave(shost->host_lock, flags);
9478         } else {
9479                 /*
9480                  * If the suggest reset bus flags are set, then reset the bus.
9481                  * Otherwise only reset the device.
9482                  */
9483                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9484
9485                 /*
9486                  * Reset the target's SCSI bus.
9487                  */
9488                 ASC_DBG(1, "before AdvResetChipAndSB()\n");
9489                 switch (AdvResetChipAndSB(adv_dvc)) {
9490                 case ASC_TRUE:
9491                         scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9492                                     "successful\n");
9493                         break;
9494                 case ASC_FALSE:
9495                 default:
9496                         scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9497                         ret = FAILED;
9498                         break;
9499                 }
9500                 spin_lock_irqsave(shost->host_lock, flags);
9501                 AdvISR(adv_dvc);
9502         }
9503
9504         /* Save the time of the most recently completed reset. */
9505         boardp->last_reset = jiffies;
9506         spin_unlock_irqrestore(shost->host_lock, flags);
9507
9508         ASC_DBG(1, "ret %d\n", ret);
9509
9510         return ret;
9511 }
9512
9513 /*
9514  * advansys_biosparam()
9515  *
9516  * Translate disk drive geometry if the "BIOS greater than 1 GB"
9517  * support is enabled for a drive.
9518  *
9519  * ip (information pointer) is an int array with the following definition:
9520  * ip[0]: heads
9521  * ip[1]: sectors
9522  * ip[2]: cylinders
9523  */
9524 static int
9525 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9526                    sector_t capacity, int ip[])
9527 {
9528         struct asc_board *boardp = shost_priv(sdev->host);
9529
9530         ASC_DBG(1, "begin\n");
9531         ASC_STATS(sdev->host, biosparam);
9532         if (ASC_NARROW_BOARD(boardp)) {
9533                 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9534                      ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9535                         ip[0] = 255;
9536                         ip[1] = 63;
9537                 } else {
9538                         ip[0] = 64;
9539                         ip[1] = 32;
9540                 }
9541         } else {
9542                 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9543                      BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9544                         ip[0] = 255;
9545                         ip[1] = 63;
9546                 } else {
9547                         ip[0] = 64;
9548                         ip[1] = 32;
9549                 }
9550         }
9551         ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9552         ASC_DBG(1, "end\n");
9553         return 0;
9554 }
9555
9556 /*
9557  * First-level interrupt handler.
9558  *
9559  * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9560  */
9561 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9562 {
9563         struct Scsi_Host *shost = dev_id;
9564         struct asc_board *boardp = shost_priv(shost);
9565         irqreturn_t result = IRQ_NONE;
9566
9567         ASC_DBG(2, "boardp 0x%p\n", boardp);
9568         spin_lock(shost->host_lock);
9569         if (ASC_NARROW_BOARD(boardp)) {
9570                 if (AscIsIntPending(shost->io_port)) {
9571                         result = IRQ_HANDLED;
9572                         ASC_STATS(shost, interrupt);
9573                         ASC_DBG(1, "before AscISR()\n");
9574                         AscISR(&boardp->dvc_var.asc_dvc_var);
9575                 }
9576         } else {
9577                 ASC_DBG(1, "before AdvISR()\n");
9578                 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9579                         result = IRQ_HANDLED;
9580                         ASC_STATS(shost, interrupt);
9581                 }
9582         }
9583         spin_unlock(shost->host_lock);
9584
9585         ASC_DBG(1, "end\n");
9586         return result;
9587 }
9588
9589 static int AscHostReqRiscHalt(PortAddr iop_base)
9590 {
9591         int count = 0;
9592         int sta = 0;
9593         uchar saved_stop_code;
9594
9595         if (AscIsChipHalted(iop_base))
9596                 return (1);
9597         saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9598         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9599                          ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9600         do {
9601                 if (AscIsChipHalted(iop_base)) {
9602                         sta = 1;
9603                         break;
9604                 }
9605                 mdelay(100);
9606         } while (count++ < 20);
9607         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9608         return (sta);
9609 }
9610
9611 static int
9612 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9613 {
9614         int sta = FALSE;
9615
9616         if (AscHostReqRiscHalt(iop_base)) {
9617                 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9618                 AscStartChip(iop_base);
9619         }
9620         return sta;
9621 }
9622
9623 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9624 {
9625         char type = sdev->type;
9626         ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9627
9628         if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9629                 return;
9630         if (asc_dvc->init_sdtr & tid_bits)
9631                 return;
9632
9633         if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9634                 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9635
9636         asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9637         if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9638             (type == TYPE_ROM) || (type == TYPE_TAPE))
9639                 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9640
9641         if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9642                 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9643                                         ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9644 }
9645
9646 static void
9647 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9648 {
9649         ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9650         ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9651
9652         if (sdev->lun == 0) {
9653                 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9654                 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9655                         asc_dvc->init_sdtr |= tid_bit;
9656                 } else {
9657                         asc_dvc->init_sdtr &= ~tid_bit;
9658                 }
9659
9660                 if (orig_init_sdtr != asc_dvc->init_sdtr)
9661                         AscAsyncFix(asc_dvc, sdev);
9662         }
9663
9664         if (sdev->tagged_supported) {
9665                 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9666                         if (sdev->lun == 0) {
9667                                 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9668                                 asc_dvc->use_tagged_qng |= tid_bit;
9669                         }
9670                         scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9671                                                 asc_dvc->max_dvc_qng[sdev->id]);
9672                 }
9673         } else {
9674                 if (sdev->lun == 0) {
9675                         asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9676                         asc_dvc->use_tagged_qng &= ~tid_bit;
9677                 }
9678                 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9679         }
9680
9681         if ((sdev->lun == 0) &&
9682             (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9683                 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9684                                  asc_dvc->cfg->disc_enable);
9685                 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9686                                  asc_dvc->use_tagged_qng);
9687                 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9688                                  asc_dvc->cfg->can_tagged_qng);
9689
9690                 asc_dvc->max_dvc_qng[sdev->id] =
9691                                         asc_dvc->cfg->max_tag_qng[sdev->id];
9692                 AscWriteLramByte(asc_dvc->iop_base,
9693                                  (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
9694                                  asc_dvc->max_dvc_qng[sdev->id]);
9695         }
9696 }
9697
9698 /*
9699  * Wide Transfers
9700  *
9701  * If the EEPROM enabled WDTR for the device and the device supports wide
9702  * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
9703  * write the new value to the microcode.
9704  */
9705 static void
9706 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
9707 {
9708         unsigned short cfg_word;
9709         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9710         if ((cfg_word & tidmask) != 0)
9711                 return;
9712
9713         cfg_word |= tidmask;
9714         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9715
9716         /*
9717          * Clear the microcode SDTR and WDTR negotiation done indicators for
9718          * the target to cause it to negotiate with the new setting set above.
9719          * WDTR when accepted causes the target to enter asynchronous mode, so
9720          * SDTR must be negotiated.
9721          */
9722         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9723         cfg_word &= ~tidmask;
9724         AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9725         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9726         cfg_word &= ~tidmask;
9727         AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9728 }
9729
9730 /*
9731  * Synchronous Transfers
9732  *
9733  * If the EEPROM enabled SDTR for the device and the device
9734  * supports synchronous transfers, then turn on the device's
9735  * 'sdtr_able' bit. Write the new value to the microcode.
9736  */
9737 static void
9738 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
9739 {
9740         unsigned short cfg_word;
9741         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9742         if ((cfg_word & tidmask) != 0)
9743                 return;
9744
9745         cfg_word |= tidmask;
9746         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9747
9748         /*
9749          * Clear the microcode "SDTR negotiation" done indicator for the
9750          * target to cause it to negotiate with the new setting set above.
9751          */
9752         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9753         cfg_word &= ~tidmask;
9754         AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9755 }
9756
9757 /*
9758  * PPR (Parallel Protocol Request) Capable
9759  *
9760  * If the device supports DT mode, then it must be PPR capable.
9761  * The PPR message will be used in place of the SDTR and WDTR
9762  * messages to negotiate synchronous speed and offset, transfer
9763  * width, and protocol options.
9764  */
9765 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
9766                                 AdvPortAddr iop_base, unsigned short tidmask)
9767 {
9768         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9769         adv_dvc->ppr_able |= tidmask;
9770         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9771 }
9772
9773 static void
9774 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
9775 {
9776         AdvPortAddr iop_base = adv_dvc->iop_base;
9777         unsigned short tidmask = 1 << sdev->id;
9778
9779         if (sdev->lun == 0) {
9780                 /*
9781                  * Handle WDTR, SDTR, and Tag Queuing. If the feature
9782                  * is enabled in the EEPROM and the device supports the
9783                  * feature, then enable it in the microcode.
9784                  */
9785
9786                 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
9787                         advansys_wide_enable_wdtr(iop_base, tidmask);
9788                 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
9789                         advansys_wide_enable_sdtr(iop_base, tidmask);
9790                 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
9791                         advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
9792
9793                 /*
9794                  * Tag Queuing is disabled for the BIOS which runs in polled
9795                  * mode and would see no benefit from Tag Queuing. Also by
9796                  * disabling Tag Queuing in the BIOS devices with Tag Queuing
9797                  * bugs will at least work with the BIOS.
9798                  */
9799                 if ((adv_dvc->tagqng_able & tidmask) &&
9800                     sdev->tagged_supported) {
9801                         unsigned short cfg_word;
9802                         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
9803                         cfg_word |= tidmask;
9804                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
9805                                          cfg_word);
9806                         AdvWriteByteLram(iop_base,
9807                                          ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
9808                                          adv_dvc->max_dvc_qng);
9809                 }
9810         }
9811
9812         if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
9813                 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9814                                         adv_dvc->max_dvc_qng);
9815         } else {
9816                 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9817         }
9818 }
9819
9820 /*
9821  * Set the number of commands to queue per device for the
9822  * specified host adapter.
9823  */
9824 static int advansys_slave_configure(struct scsi_device *sdev)
9825 {
9826         struct asc_board *boardp = shost_priv(sdev->host);
9827
9828         if (ASC_NARROW_BOARD(boardp))
9829                 advansys_narrow_slave_configure(sdev,
9830                                                 &boardp->dvc_var.asc_dvc_var);
9831         else
9832                 advansys_wide_slave_configure(sdev,
9833                                                 &boardp->dvc_var.adv_dvc_var);
9834
9835         return 0;
9836 }
9837
9838 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
9839                         struct asc_scsi_q *asc_scsi_q)
9840 {
9841         int use_sg;
9842
9843         memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
9844
9845         /*
9846          * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
9847          */
9848         asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
9849
9850         /*
9851          * Build the ASC_SCSI_Q request.
9852          */
9853         asc_scsi_q->cdbptr = &scp->cmnd[0];
9854         asc_scsi_q->q2.cdb_len = scp->cmd_len;
9855         asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
9856         asc_scsi_q->q1.target_lun = scp->device->lun;
9857         asc_scsi_q->q2.target_ix =
9858             ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
9859         asc_scsi_q->q1.sense_addr =
9860             cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
9861         asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
9862
9863         /*
9864          * If there are any outstanding requests for the current target,
9865          * then every 255th request send an ORDERED request. This heuristic
9866          * tries to retain the benefit of request sorting while preventing
9867          * request starvation. 255 is the max number of tags or pending commands
9868          * a device may have outstanding.
9869          *
9870          * The request count is incremented below for every successfully
9871          * started request.
9872          *
9873          */
9874         if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
9875             (boardp->reqcnt[scp->device->id] % 255) == 0) {
9876                 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
9877         } else {
9878                 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
9879         }
9880
9881         /* Build ASC_SCSI_Q */
9882         use_sg = scsi_dma_map(scp);
9883         if (use_sg != 0) {
9884                 int sgcnt;
9885                 struct scatterlist *slp;
9886                 struct asc_sg_head *asc_sg_head;
9887
9888                 if (use_sg > scp->device->host->sg_tablesize) {
9889                         scmd_printk(KERN_ERR, scp, "use_sg %d > "
9890                                 "sg_tablesize %d\n", use_sg,
9891                                 scp->device->host->sg_tablesize);
9892                         scsi_dma_unmap(scp);
9893                         scp->result = HOST_BYTE(DID_ERROR);
9894                         return ASC_ERROR;
9895                 }
9896
9897                 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
9898                         use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
9899                 if (!asc_sg_head) {
9900                         scsi_dma_unmap(scp);
9901                         scp->result = HOST_BYTE(DID_SOFT_ERROR);
9902                         return ASC_ERROR;
9903                 }
9904
9905                 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
9906                 asc_scsi_q->sg_head = asc_sg_head;
9907                 asc_scsi_q->q1.data_cnt = 0;
9908                 asc_scsi_q->q1.data_addr = 0;
9909                 /* This is a byte value, otherwise it would need to be swapped. */
9910                 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
9911                 ASC_STATS_ADD(scp->device->host, xfer_elem,
9912                               asc_sg_head->entry_cnt);
9913
9914                 /*
9915                  * Convert scatter-gather list into ASC_SG_HEAD list.
9916                  */
9917                 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
9918                         asc_sg_head->sg_list[sgcnt].addr =
9919                             cpu_to_le32(sg_dma_address(slp));
9920                         asc_sg_head->sg_list[sgcnt].bytes =
9921                             cpu_to_le32(sg_dma_len(slp));
9922                         ASC_STATS_ADD(scp->device->host, xfer_sect,
9923                                       DIV_ROUND_UP(sg_dma_len(slp), 512));
9924                 }
9925         }
9926
9927         ASC_STATS(scp->device->host, xfer_cnt);
9928
9929         ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
9930         ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
9931
9932         return ASC_NOERROR;
9933 }
9934
9935 /*
9936  * Build scatter-gather list for Adv Library (Wide Board).
9937  *
9938  * Additional ADV_SG_BLOCK structures will need to be allocated
9939  * if the total number of scatter-gather elements exceeds
9940  * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
9941  * assumed to be physically contiguous.
9942  *
9943  * Return:
9944  *      ADV_SUCCESS(1) - SG List successfully created
9945  *      ADV_ERROR(-1) - SG List creation failed
9946  */
9947 static int
9948 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
9949                int use_sg)
9950 {
9951         adv_sgblk_t *sgblkp;
9952         ADV_SCSI_REQ_Q *scsiqp;
9953         struct scatterlist *slp;
9954         int sg_elem_cnt;
9955         ADV_SG_BLOCK *sg_block, *prev_sg_block;
9956         ADV_PADDR sg_block_paddr;
9957         int i;
9958
9959         scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
9960         slp = scsi_sglist(scp);
9961         sg_elem_cnt = use_sg;
9962         prev_sg_block = NULL;
9963         reqp->sgblkp = NULL;
9964
9965         for (;;) {
9966                 /*
9967                  * Allocate a 'adv_sgblk_t' structure from the board free
9968                  * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
9969                  * (15) scatter-gather elements.
9970                  */
9971                 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
9972                         ASC_DBG(1, "no free adv_sgblk_t\n");
9973                         ASC_STATS(scp->device->host, adv_build_nosg);
9974
9975                         /*
9976                          * Allocation failed. Free 'adv_sgblk_t' structures
9977                          * already allocated for the request.
9978                          */
9979                         while ((sgblkp = reqp->sgblkp) != NULL) {
9980                                 /* Remove 'sgblkp' from the request list. */
9981                                 reqp->sgblkp = sgblkp->next_sgblkp;
9982
9983                                 /* Add 'sgblkp' to the board free list. */
9984                                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
9985                                 boardp->adv_sgblkp = sgblkp;
9986                         }
9987                         return ASC_BUSY;
9988                 }
9989
9990                 /* Complete 'adv_sgblk_t' board allocation. */
9991                 boardp->adv_sgblkp = sgblkp->next_sgblkp;
9992                 sgblkp->next_sgblkp = NULL;
9993
9994                 /*
9995                  * Get 8 byte aligned virtual and physical addresses
9996                  * for the allocated ADV_SG_BLOCK structure.
9997                  */
9998                 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
9999                 sg_block_paddr = virt_to_bus(sg_block);
10000
10001                 /*
10002                  * Check if this is the first 'adv_sgblk_t' for the
10003                  * request.
10004                  */
10005                 if (reqp->sgblkp == NULL) {
10006                         /* Request's first scatter-gather block. */
10007                         reqp->sgblkp = sgblkp;
10008
10009                         /*
10010                          * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10011                          * address pointers.
10012                          */
10013                         scsiqp->sg_list_ptr = sg_block;
10014                         scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10015                 } else {
10016                         /* Request's second or later scatter-gather block. */
10017                         sgblkp->next_sgblkp = reqp->sgblkp;
10018                         reqp->sgblkp = sgblkp;
10019
10020                         /*
10021                          * Point the previous ADV_SG_BLOCK structure to
10022                          * the newly allocated ADV_SG_BLOCK structure.
10023                          */
10024                         prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10025                 }
10026
10027                 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10028                         sg_block->sg_list[i].sg_addr =
10029                                         cpu_to_le32(sg_dma_address(slp));
10030                         sg_block->sg_list[i].sg_count =
10031                                         cpu_to_le32(sg_dma_len(slp));
10032                         ASC_STATS_ADD(scp->device->host, xfer_sect,
10033                                       DIV_ROUND_UP(sg_dma_len(slp), 512));
10034
10035                         if (--sg_elem_cnt == 0) {       /* Last ADV_SG_BLOCK and scatter-gather entry. */
10036                                 sg_block->sg_cnt = i + 1;
10037                                 sg_block->sg_ptr = 0L;  /* Last ADV_SG_BLOCK in list. */
10038                                 return ADV_SUCCESS;
10039                         }
10040                         slp++;
10041                 }
10042                 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10043                 prev_sg_block = sg_block;
10044         }
10045 }
10046
10047 /*
10048  * Build a request structure for the Adv Library (Wide Board).
10049  *
10050  * If an adv_req_t can not be allocated to issue the request,
10051  * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10052  *
10053  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10054  * microcode for DMA addresses or math operations are byte swapped
10055  * to little-endian order.
10056  */
10057 static int
10058 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
10059               ADV_SCSI_REQ_Q **adv_scsiqpp)
10060 {
10061         adv_req_t *reqp;
10062         ADV_SCSI_REQ_Q *scsiqp;
10063         int i;
10064         int ret;
10065         int use_sg;
10066
10067         /*
10068          * Allocate an adv_req_t structure from the board to execute
10069          * the command.
10070          */
10071         if (boardp->adv_reqp == NULL) {
10072                 ASC_DBG(1, "no free adv_req_t\n");
10073                 ASC_STATS(scp->device->host, adv_build_noreq);
10074                 return ASC_BUSY;
10075         } else {
10076                 reqp = boardp->adv_reqp;
10077                 boardp->adv_reqp = reqp->next_reqp;
10078                 reqp->next_reqp = NULL;
10079         }
10080
10081         /*
10082          * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10083          */
10084         scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10085
10086         /*
10087          * Initialize the structure.
10088          */
10089         scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10090
10091         /*
10092          * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10093          */
10094         scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10095
10096         /*
10097          * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10098          */
10099         reqp->cmndp = scp;
10100
10101         /*
10102          * Build the ADV_SCSI_REQ_Q request.
10103          */
10104
10105         /* Set CDB length and copy it to the request structure.  */
10106         scsiqp->cdb_len = scp->cmd_len;
10107         /* Copy first 12 CDB bytes to cdb[]. */
10108         for (i = 0; i < scp->cmd_len && i < 12; i++) {
10109                 scsiqp->cdb[i] = scp->cmnd[i];
10110         }
10111         /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10112         for (; i < scp->cmd_len; i++) {
10113                 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10114         }
10115
10116         scsiqp->target_id = scp->device->id;
10117         scsiqp->target_lun = scp->device->lun;
10118
10119         scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10120         scsiqp->sense_len = sizeof(scp->sense_buffer);
10121
10122         /* Build ADV_SCSI_REQ_Q */
10123
10124         use_sg = scsi_dma_map(scp);
10125         if (use_sg == 0) {
10126                 /* Zero-length transfer */
10127                 reqp->sgblkp = NULL;
10128                 scsiqp->data_cnt = 0;
10129                 scsiqp->vdata_addr = NULL;
10130
10131                 scsiqp->data_addr = 0;
10132                 scsiqp->sg_list_ptr = NULL;
10133                 scsiqp->sg_real_addr = 0;
10134         } else {
10135                 if (use_sg > ADV_MAX_SG_LIST) {
10136                         scmd_printk(KERN_ERR, scp, "use_sg %d > "
10137                                    "ADV_MAX_SG_LIST %d\n", use_sg,
10138                                    scp->device->host->sg_tablesize);
10139                         scsi_dma_unmap(scp);
10140                         scp->result = HOST_BYTE(DID_ERROR);
10141
10142                         /*
10143                          * Free the 'adv_req_t' structure by adding it back
10144                          * to the board free list.
10145                          */
10146                         reqp->next_reqp = boardp->adv_reqp;
10147                         boardp->adv_reqp = reqp;
10148
10149                         return ASC_ERROR;
10150                 }
10151
10152                 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
10153
10154                 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10155                 if (ret != ADV_SUCCESS) {
10156                         /*
10157                          * Free the adv_req_t structure by adding it back to
10158                          * the board free list.
10159                          */
10160                         reqp->next_reqp = boardp->adv_reqp;
10161                         boardp->adv_reqp = reqp;
10162
10163                         return ret;
10164                 }
10165
10166                 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
10167         }
10168
10169         ASC_STATS(scp->device->host, xfer_cnt);
10170
10171         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10172         ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10173
10174         *adv_scsiqpp = scsiqp;
10175
10176         return ASC_NOERROR;
10177 }
10178
10179 static int AscSgListToQueue(int sg_list)
10180 {
10181         int n_sg_list_qs;
10182
10183         n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10184         if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10185                 n_sg_list_qs++;
10186         return n_sg_list_qs + 1;
10187 }
10188
10189 static uint
10190 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10191 {
10192         uint cur_used_qs;
10193         uint cur_free_qs;
10194         ASC_SCSI_BIT_ID_TYPE target_id;
10195         uchar tid_no;
10196
10197         target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10198         tid_no = ASC_TIX_TO_TID(target_ix);
10199         if ((asc_dvc->unit_not_ready & target_id) ||
10200             (asc_dvc->queue_full_or_busy & target_id)) {
10201                 return 0;
10202         }
10203         if (n_qs == 1) {
10204                 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10205                     (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10206         } else {
10207                 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10208                     (uint) ASC_MIN_FREE_Q;
10209         }
10210         if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10211                 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10212                 if (asc_dvc->cur_dvc_qng[tid_no] >=
10213                     asc_dvc->max_dvc_qng[tid_no]) {
10214                         return 0;
10215                 }
10216                 return cur_free_qs;
10217         }
10218         if (n_qs > 1) {
10219                 if ((n_qs > asc_dvc->last_q_shortage)
10220                     && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10221                         asc_dvc->last_q_shortage = n_qs;
10222                 }
10223         }
10224         return 0;
10225 }
10226
10227 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10228 {
10229         ushort q_addr;
10230         uchar next_qp;
10231         uchar q_status;
10232
10233         q_addr = ASC_QNO_TO_QADDR(free_q_head);
10234         q_status = (uchar)AscReadLramByte(iop_base,
10235                                           (ushort)(q_addr +
10236                                                    ASC_SCSIQ_B_STATUS));
10237         next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10238         if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10239                 return next_qp;
10240         return ASC_QLINK_END;
10241 }
10242
10243 static uchar
10244 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10245 {
10246         uchar i;
10247
10248         for (i = 0; i < n_free_q; i++) {
10249                 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10250                 if (free_q_head == ASC_QLINK_END)
10251                         break;
10252         }
10253         return free_q_head;
10254 }
10255
10256 /*
10257  * void
10258  * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10259  *
10260  * Calling/Exit State:
10261  *    none
10262  *
10263  * Description:
10264  *     Output an ASC_SCSI_Q structure to the chip
10265  */
10266 static void
10267 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10268 {
10269         int i;
10270
10271         ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10272         AscSetChipLramAddr(iop_base, s_addr);
10273         for (i = 0; i < 2 * words; i += 2) {
10274                 if (i == 4 || i == 20) {
10275                         continue;
10276                 }
10277                 outpw(iop_base + IOP_RAM_DATA,
10278                       ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10279         }
10280 }
10281
10282 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10283 {
10284         ushort q_addr;
10285         uchar tid_no;
10286         uchar sdtr_data;
10287         uchar syn_period_ix;
10288         uchar syn_offset;
10289         PortAddr iop_base;
10290
10291         iop_base = asc_dvc->iop_base;
10292         if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10293             ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10294                 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10295                 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10296                 syn_period_ix =
10297                     (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10298                 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10299                 AscMsgOutSDTR(asc_dvc,
10300                               asc_dvc->sdtr_period_tbl[syn_period_ix],
10301                               syn_offset);
10302                 scsiq->q1.cntl |= QC_MSG_OUT;
10303         }
10304         q_addr = ASC_QNO_TO_QADDR(q_no);
10305         if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10306                 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10307         }
10308         scsiq->q1.status = QS_FREE;
10309         AscMemWordCopyPtrToLram(iop_base,
10310                                 q_addr + ASC_SCSIQ_CDB_BEG,
10311                                 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10312
10313         DvcPutScsiQ(iop_base,
10314                     q_addr + ASC_SCSIQ_CPY_BEG,
10315                     (uchar *)&scsiq->q1.cntl,
10316                     ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10317         AscWriteLramWord(iop_base,
10318                          (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10319                          (ushort)(((ushort)scsiq->q1.
10320                                    q_no << 8) | (ushort)QS_READY));
10321         return 1;
10322 }
10323
10324 static int
10325 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10326 {
10327         int sta;
10328         int i;
10329         ASC_SG_HEAD *sg_head;
10330         ASC_SG_LIST_Q scsi_sg_q;
10331         ASC_DCNT saved_data_addr;
10332         ASC_DCNT saved_data_cnt;
10333         PortAddr iop_base;
10334         ushort sg_list_dwords;
10335         ushort sg_index;
10336         ushort sg_entry_cnt;
10337         ushort q_addr;
10338         uchar next_qp;
10339
10340         iop_base = asc_dvc->iop_base;
10341         sg_head = scsiq->sg_head;
10342         saved_data_addr = scsiq->q1.data_addr;
10343         saved_data_cnt = scsiq->q1.data_cnt;
10344         scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10345         scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10346 #if CC_VERY_LONG_SG_LIST
10347         /*
10348          * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10349          * then not all SG elements will fit in the allocated queues.
10350          * The rest of the SG elements will be copied when the RISC
10351          * completes the SG elements that fit and halts.
10352          */
10353         if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10354                 /*
10355                  * Set sg_entry_cnt to be the number of SG elements that
10356                  * will fit in the allocated SG queues. It is minus 1, because
10357                  * the first SG element is handled above. ASC_MAX_SG_LIST is
10358                  * already inflated by 1 to account for this. For example it
10359                  * may be 50 which is 1 + 7 queues * 7 SG elements.
10360                  */
10361                 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10362
10363                 /*
10364                  * Keep track of remaining number of SG elements that will
10365                  * need to be handled from a_isr.c.
10366                  */
10367                 scsiq->remain_sg_entry_cnt =
10368                     sg_head->entry_cnt - ASC_MAX_SG_LIST;
10369         } else {
10370 #endif /* CC_VERY_LONG_SG_LIST */
10371                 /*
10372                  * Set sg_entry_cnt to be the number of SG elements that
10373                  * will fit in the allocated SG queues. It is minus 1, because
10374                  * the first SG element is handled above.
10375                  */
10376                 sg_entry_cnt = sg_head->entry_cnt - 1;
10377 #if CC_VERY_LONG_SG_LIST
10378         }
10379 #endif /* CC_VERY_LONG_SG_LIST */
10380         if (sg_entry_cnt != 0) {
10381                 scsiq->q1.cntl |= QC_SG_HEAD;
10382                 q_addr = ASC_QNO_TO_QADDR(q_no);
10383                 sg_index = 1;
10384                 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10385                 scsi_sg_q.sg_head_qp = q_no;
10386                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10387                 for (i = 0; i < sg_head->queue_cnt; i++) {
10388                         scsi_sg_q.seq_no = i + 1;
10389                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10390                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10391                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10392                                 if (i == 0) {
10393                                         scsi_sg_q.sg_list_cnt =
10394                                             ASC_SG_LIST_PER_Q;
10395                                         scsi_sg_q.sg_cur_list_cnt =
10396                                             ASC_SG_LIST_PER_Q;
10397                                 } else {
10398                                         scsi_sg_q.sg_list_cnt =
10399                                             ASC_SG_LIST_PER_Q - 1;
10400                                         scsi_sg_q.sg_cur_list_cnt =
10401                                             ASC_SG_LIST_PER_Q - 1;
10402                                 }
10403                         } else {
10404 #if CC_VERY_LONG_SG_LIST
10405                                 /*
10406                                  * This is the last SG queue in the list of
10407                                  * allocated SG queues. If there are more
10408                                  * SG elements than will fit in the allocated
10409                                  * queues, then set the QCSG_SG_XFER_MORE flag.
10410                                  */
10411                                 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10412                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10413                                 } else {
10414 #endif /* CC_VERY_LONG_SG_LIST */
10415                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10416 #if CC_VERY_LONG_SG_LIST
10417                                 }
10418 #endif /* CC_VERY_LONG_SG_LIST */
10419                                 sg_list_dwords = sg_entry_cnt << 1;
10420                                 if (i == 0) {
10421                                         scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10422                                         scsi_sg_q.sg_cur_list_cnt =
10423                                             sg_entry_cnt;
10424                                 } else {
10425                                         scsi_sg_q.sg_list_cnt =
10426                                             sg_entry_cnt - 1;
10427                                         scsi_sg_q.sg_cur_list_cnt =
10428                                             sg_entry_cnt - 1;
10429                                 }
10430                                 sg_entry_cnt = 0;
10431                         }
10432                         next_qp = AscReadLramByte(iop_base,
10433                                                   (ushort)(q_addr +
10434                                                            ASC_SCSIQ_B_FWD));
10435                         scsi_sg_q.q_no = next_qp;
10436                         q_addr = ASC_QNO_TO_QADDR(next_qp);
10437                         AscMemWordCopyPtrToLram(iop_base,
10438                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10439                                                 (uchar *)&scsi_sg_q,
10440                                                 sizeof(ASC_SG_LIST_Q) >> 1);
10441                         AscMemDWordCopyPtrToLram(iop_base,
10442                                                  q_addr + ASC_SGQ_LIST_BEG,
10443                                                  (uchar *)&sg_head->
10444                                                  sg_list[sg_index],
10445                                                  sg_list_dwords);
10446                         sg_index += ASC_SG_LIST_PER_Q;
10447                         scsiq->next_sg_index = sg_index;
10448                 }
10449         } else {
10450                 scsiq->q1.cntl &= ~QC_SG_HEAD;
10451         }
10452         sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10453         scsiq->q1.data_addr = saved_data_addr;
10454         scsiq->q1.data_cnt = saved_data_cnt;
10455         return (sta);
10456 }
10457
10458 static int
10459 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10460 {
10461         PortAddr iop_base;
10462         uchar free_q_head;
10463         uchar next_qp;
10464         uchar tid_no;
10465         uchar target_ix;
10466         int sta;
10467
10468         iop_base = asc_dvc->iop_base;
10469         target_ix = scsiq->q2.target_ix;
10470         tid_no = ASC_TIX_TO_TID(target_ix);
10471         sta = 0;
10472         free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10473         if (n_q_required > 1) {
10474                 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10475                                                     (uchar)n_q_required);
10476                 if (next_qp != ASC_QLINK_END) {
10477                         asc_dvc->last_q_shortage = 0;
10478                         scsiq->sg_head->queue_cnt = n_q_required - 1;
10479                         scsiq->q1.q_no = free_q_head;
10480                         sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10481                                                      free_q_head);
10482                 }
10483         } else if (n_q_required == 1) {
10484                 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10485                 if (next_qp != ASC_QLINK_END) {
10486                         scsiq->q1.q_no = free_q_head;
10487                         sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10488                 }
10489         }
10490         if (sta == 1) {
10491                 AscPutVarFreeQHead(iop_base, next_qp);
10492                 asc_dvc->cur_total_qng += n_q_required;
10493                 asc_dvc->cur_dvc_qng[tid_no]++;
10494         }
10495         return sta;
10496 }
10497
10498 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST  16
10499 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10500         INQUIRY,
10501         REQUEST_SENSE,
10502         READ_CAPACITY,
10503         READ_TOC,
10504         MODE_SELECT,
10505         MODE_SENSE,
10506         MODE_SELECT_10,
10507         MODE_SENSE_10,
10508         0xFF,
10509         0xFF,
10510         0xFF,
10511         0xFF,
10512         0xFF,
10513         0xFF,
10514         0xFF,
10515         0xFF
10516 };
10517
10518 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10519 {
10520         PortAddr iop_base;
10521         int sta;
10522         int n_q_required;
10523         int disable_syn_offset_one_fix;
10524         int i;
10525         ASC_PADDR addr;
10526         ushort sg_entry_cnt = 0;
10527         ushort sg_entry_cnt_minus_one = 0;
10528         uchar target_ix;
10529         uchar tid_no;
10530         uchar sdtr_data;
10531         uchar extra_bytes;
10532         uchar scsi_cmd;
10533         uchar disable_cmd;
10534         ASC_SG_HEAD *sg_head;
10535         ASC_DCNT data_cnt;
10536
10537         iop_base = asc_dvc->iop_base;
10538         sg_head = scsiq->sg_head;
10539         if (asc_dvc->err_code != 0)
10540                 return (ERR);
10541         scsiq->q1.q_no = 0;
10542         if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10543                 scsiq->q1.extra_bytes = 0;
10544         }
10545         sta = 0;
10546         target_ix = scsiq->q2.target_ix;
10547         tid_no = ASC_TIX_TO_TID(target_ix);
10548         n_q_required = 1;
10549         if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10550                 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10551                         asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10552                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10553                         AscMsgOutSDTR(asc_dvc,
10554                                       asc_dvc->
10555                                       sdtr_period_tbl[(sdtr_data >> 4) &
10556                                                       (uchar)(asc_dvc->
10557                                                               max_sdtr_index -
10558                                                               1)],
10559                                       (uchar)(sdtr_data & (uchar)
10560                                               ASC_SYN_MAX_OFFSET));
10561                         scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10562                 }
10563         }
10564         if (asc_dvc->in_critical_cnt != 0) {
10565                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10566                 return (ERR);
10567         }
10568         asc_dvc->in_critical_cnt++;
10569         if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10570                 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10571                         asc_dvc->in_critical_cnt--;
10572                         return (ERR);
10573                 }
10574 #if !CC_VERY_LONG_SG_LIST
10575                 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10576                         asc_dvc->in_critical_cnt--;
10577                         return (ERR);
10578                 }
10579 #endif /* !CC_VERY_LONG_SG_LIST */
10580                 if (sg_entry_cnt == 1) {
10581                         scsiq->q1.data_addr =
10582                             (ADV_PADDR)sg_head->sg_list[0].addr;
10583                         scsiq->q1.data_cnt =
10584                             (ADV_DCNT)sg_head->sg_list[0].bytes;
10585                         scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10586                 }
10587                 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10588         }
10589         scsi_cmd = scsiq->cdbptr[0];
10590         disable_syn_offset_one_fix = FALSE;
10591         if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10592             !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10593                 if (scsiq->q1.cntl & QC_SG_HEAD) {
10594                         data_cnt = 0;
10595                         for (i = 0; i < sg_entry_cnt; i++) {
10596                                 data_cnt +=
10597                                     (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10598                                                           bytes);
10599                         }
10600                 } else {
10601                         data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10602                 }
10603                 if (data_cnt != 0UL) {
10604                         if (data_cnt < 512UL) {
10605                                 disable_syn_offset_one_fix = TRUE;
10606                         } else {
10607                                 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10608                                      i++) {
10609                                         disable_cmd =
10610                                             _syn_offset_one_disable_cmd[i];
10611                                         if (disable_cmd == 0xFF) {
10612                                                 break;
10613                                         }
10614                                         if (scsi_cmd == disable_cmd) {
10615                                                 disable_syn_offset_one_fix =
10616                                                     TRUE;
10617                                                 break;
10618                                         }
10619                                 }
10620                         }
10621                 }
10622         }
10623         if (disable_syn_offset_one_fix) {
10624                 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10625                 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10626                                        ASC_TAG_FLAG_DISABLE_DISCONNECT);
10627         } else {
10628                 scsiq->q2.tag_code &= 0x27;
10629         }
10630         if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10631                 if (asc_dvc->bug_fix_cntl) {
10632                         if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10633                                 if ((scsi_cmd == READ_6) ||
10634                                     (scsi_cmd == READ_10)) {
10635                                         addr =
10636                                             (ADV_PADDR)le32_to_cpu(sg_head->
10637                                                                    sg_list
10638                                                                    [sg_entry_cnt_minus_one].
10639                                                                    addr) +
10640                                             (ADV_DCNT)le32_to_cpu(sg_head->
10641                                                                   sg_list
10642                                                                   [sg_entry_cnt_minus_one].
10643                                                                   bytes);
10644                                         extra_bytes =
10645                                             (uchar)((ushort)addr & 0x0003);
10646                                         if ((extra_bytes != 0)
10647                                             &&
10648                                             ((scsiq->q2.
10649                                               tag_code &
10650                                               ASC_TAG_FLAG_EXTRA_BYTES)
10651                                              == 0)) {
10652                                                 scsiq->q2.tag_code |=
10653                                                     ASC_TAG_FLAG_EXTRA_BYTES;
10654                                                 scsiq->q1.extra_bytes =
10655                                                     extra_bytes;
10656                                                 data_cnt =
10657                                                     le32_to_cpu(sg_head->
10658                                                                 sg_list
10659                                                                 [sg_entry_cnt_minus_one].
10660                                                                 bytes);
10661                                                 data_cnt -=
10662                                                     (ASC_DCNT) extra_bytes;
10663                                                 sg_head->
10664                                                     sg_list
10665                                                     [sg_entry_cnt_minus_one].
10666                                                     bytes =
10667                                                     cpu_to_le32(data_cnt);
10668                                         }
10669                                 }
10670                         }
10671                 }
10672                 sg_head->entry_to_copy = sg_head->entry_cnt;
10673 #if CC_VERY_LONG_SG_LIST
10674                 /*
10675                  * Set the sg_entry_cnt to the maximum possible. The rest of
10676                  * the SG elements will be copied when the RISC completes the
10677                  * SG elements that fit and halts.
10678                  */
10679                 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10680                         sg_entry_cnt = ASC_MAX_SG_LIST;
10681                 }
10682 #endif /* CC_VERY_LONG_SG_LIST */
10683                 n_q_required = AscSgListToQueue(sg_entry_cnt);
10684                 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10685                      (uint) n_q_required)
10686                     || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10687                         if ((sta =
10688                              AscSendScsiQueue(asc_dvc, scsiq,
10689                                               n_q_required)) == 1) {
10690                                 asc_dvc->in_critical_cnt--;
10691                                 return (sta);
10692                         }
10693                 }
10694         } else {
10695                 if (asc_dvc->bug_fix_cntl) {
10696                         if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10697                                 if ((scsi_cmd == READ_6) ||
10698                                     (scsi_cmd == READ_10)) {
10699                                         addr =
10700                                             le32_to_cpu(scsiq->q1.data_addr) +
10701                                             le32_to_cpu(scsiq->q1.data_cnt);
10702                                         extra_bytes =
10703                                             (uchar)((ushort)addr & 0x0003);
10704                                         if ((extra_bytes != 0)
10705                                             &&
10706                                             ((scsiq->q2.
10707                                               tag_code &
10708                                               ASC_TAG_FLAG_EXTRA_BYTES)
10709                                              == 0)) {
10710                                                 data_cnt =
10711                                                     le32_to_cpu(scsiq->q1.
10712                                                                 data_cnt);
10713                                                 if (((ushort)data_cnt & 0x01FF)
10714                                                     == 0) {
10715                                                         scsiq->q2.tag_code |=
10716                                                             ASC_TAG_FLAG_EXTRA_BYTES;
10717                                                         data_cnt -= (ASC_DCNT)
10718                                                             extra_bytes;
10719                                                         scsiq->q1.data_cnt =
10720                                                             cpu_to_le32
10721                                                             (data_cnt);
10722                                                         scsiq->q1.extra_bytes =
10723                                                             extra_bytes;
10724                                                 }
10725                                         }
10726                                 }
10727                         }
10728                 }
10729                 n_q_required = 1;
10730                 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10731                     ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10732                         if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10733                                                     n_q_required)) == 1) {
10734                                 asc_dvc->in_critical_cnt--;
10735                                 return (sta);
10736                         }
10737                 }
10738         }
10739         asc_dvc->in_critical_cnt--;
10740         return (sta);
10741 }
10742
10743 /*
10744  * AdvExeScsiQueue() - Send a request to the RISC microcode program.
10745  *
10746  *   Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
10747  *   add the carrier to the ICQ (Initiator Command Queue), and tickle the
10748  *   RISC to notify it a new command is ready to be executed.
10749  *
10750  * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
10751  * set to SCSI_MAX_RETRY.
10752  *
10753  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
10754  * for DMA addresses or math operations are byte swapped to little-endian
10755  * order.
10756  *
10757  * Return:
10758  *      ADV_SUCCESS(1) - The request was successfully queued.
10759  *      ADV_BUSY(0) -    Resource unavailable; Retry again after pending
10760  *                       request completes.
10761  *      ADV_ERROR(-1) -  Invalid ADV_SCSI_REQ_Q request structure
10762  *                       host IC error.
10763  */
10764 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
10765 {
10766         AdvPortAddr iop_base;
10767         ADV_PADDR req_paddr;
10768         ADV_CARR_T *new_carrp;
10769
10770         /*
10771          * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
10772          */
10773         if (scsiq->target_id > ADV_MAX_TID) {
10774                 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
10775                 scsiq->done_status = QD_WITH_ERROR;
10776                 return ADV_ERROR;
10777         }
10778
10779         iop_base = asc_dvc->iop_base;
10780
10781         /*
10782          * Allocate a carrier ensuring at least one carrier always
10783          * remains on the freelist and initialize fields.
10784          */
10785         if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
10786                 return ADV_BUSY;
10787         }
10788         asc_dvc->carr_freelist = (ADV_CARR_T *)
10789             ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
10790         asc_dvc->carr_pending_cnt++;
10791
10792         /*
10793          * Set the carrier to be a stopper by setting 'next_vpa'
10794          * to the stopper value. The current stopper will be changed
10795          * below to point to the new stopper.
10796          */
10797         new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
10798
10799         /*
10800          * Clear the ADV_SCSI_REQ_Q done flag.
10801          */
10802         scsiq->a_flag &= ~ADV_SCSIQ_DONE;
10803
10804         req_paddr = virt_to_bus(scsiq);
10805         BUG_ON(req_paddr & 31);
10806         /* Wait for assertion before making little-endian */
10807         req_paddr = cpu_to_le32(req_paddr);
10808
10809         /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
10810         scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
10811         scsiq->scsiq_rptr = req_paddr;
10812
10813         scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
10814         /*
10815          * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
10816          * order during initialization.
10817          */
10818         scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
10819
10820         /*
10821          * Use the current stopper to send the ADV_SCSI_REQ_Q command to
10822          * the microcode. The newly allocated stopper will become the new
10823          * stopper.
10824          */
10825         asc_dvc->icq_sp->areq_vpa = req_paddr;
10826
10827         /*
10828          * Set the 'next_vpa' pointer for the old stopper to be the
10829          * physical address of the new stopper. The RISC can only
10830          * follow physical addresses.
10831          */
10832         asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
10833
10834         /*
10835          * Set the host adapter stopper pointer to point to the new carrier.
10836          */
10837         asc_dvc->icq_sp = new_carrp;
10838
10839         if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
10840             asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10841                 /*
10842                  * Tickle the RISC to tell it to read its Command Queue Head pointer.
10843                  */
10844                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
10845                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
10846                         /*
10847                          * Clear the tickle value. In the ASC-3550 the RISC flag
10848                          * command 'clr_tickle_a' does not work unless the host
10849                          * value is cleared.
10850                          */
10851                         AdvWriteByteRegister(iop_base, IOPB_TICKLE,
10852                                              ADV_TICKLE_NOP);
10853                 }
10854         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
10855                 /*
10856                  * Notify the RISC a carrier is ready by writing the physical
10857                  * address of the new carrier stopper to the COMMA register.
10858                  */
10859                 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
10860                                       le32_to_cpu(new_carrp->carr_pa));
10861         }
10862
10863         return ADV_SUCCESS;
10864 }
10865
10866 /*
10867  * Execute a single 'Scsi_Cmnd'.
10868  */
10869 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
10870 {
10871         int ret, err_code;
10872         struct asc_board *boardp = shost_priv(scp->device->host);
10873
10874         ASC_DBG(1, "scp 0x%p\n", scp);
10875
10876         if (ASC_NARROW_BOARD(boardp)) {
10877                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
10878                 struct asc_scsi_q asc_scsi_q;
10879
10880                 /* asc_build_req() can not return ASC_BUSY. */
10881                 ret = asc_build_req(boardp, scp, &asc_scsi_q);
10882                 if (ret == ASC_ERROR) {
10883                         ASC_STATS(scp->device->host, build_error);
10884                         return ASC_ERROR;
10885                 }
10886
10887                 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
10888                 kfree(asc_scsi_q.sg_head);
10889                 err_code = asc_dvc->err_code;
10890         } else {
10891                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
10892                 ADV_SCSI_REQ_Q *adv_scsiqp;
10893
10894                 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
10895                 case ASC_NOERROR:
10896                         ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
10897                         break;
10898                 case ASC_BUSY:
10899                         ASC_DBG(1, "adv_build_req ASC_BUSY\n");
10900                         /*
10901                          * The asc_stats fields 'adv_build_noreq' and
10902                          * 'adv_build_nosg' count wide board busy conditions.
10903                          * They are updated in adv_build_req and
10904                          * adv_get_sglist, respectively.
10905                          */
10906                         return ASC_BUSY;
10907                 case ASC_ERROR:
10908                 default:
10909                         ASC_DBG(1, "adv_build_req ASC_ERROR\n");
10910                         ASC_STATS(scp->device->host, build_error);
10911                         return ASC_ERROR;
10912                 }
10913
10914                 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
10915                 err_code = adv_dvc->err_code;
10916         }
10917
10918         switch (ret) {
10919         case ASC_NOERROR:
10920                 ASC_STATS(scp->device->host, exe_noerror);
10921                 /*
10922                  * Increment monotonically increasing per device
10923                  * successful request counter. Wrapping doesn't matter.
10924                  */
10925                 boardp->reqcnt[scp->device->id]++;
10926                 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
10927                 break;
10928         case ASC_BUSY:
10929                 ASC_STATS(scp->device->host, exe_busy);
10930                 break;
10931         case ASC_ERROR:
10932                 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
10933                         "err_code 0x%x\n", err_code);
10934                 ASC_STATS(scp->device->host, exe_error);
10935                 scp->result = HOST_BYTE(DID_ERROR);
10936                 break;
10937         default:
10938                 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
10939                         "err_code 0x%x\n", err_code);
10940                 ASC_STATS(scp->device->host, exe_unknown);
10941                 scp->result = HOST_BYTE(DID_ERROR);
10942                 break;
10943         }
10944
10945         ASC_DBG(1, "end\n");
10946         return ret;
10947 }
10948
10949 /*
10950  * advansys_queuecommand() - interrupt-driven I/O entrypoint.
10951  *
10952  * This function always returns 0. Command return status is saved
10953  * in the 'scp' result field.
10954  */
10955 static int
10956 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
10957 {
10958         struct Scsi_Host *shost = scp->device->host;
10959         int asc_res, result = 0;
10960
10961         ASC_STATS(shost, queuecommand);
10962         scp->scsi_done = done;
10963
10964         asc_res = asc_execute_scsi_cmnd(scp);
10965
10966         switch (asc_res) {
10967         case ASC_NOERROR:
10968                 break;
10969         case ASC_BUSY:
10970                 result = SCSI_MLQUEUE_HOST_BUSY;
10971                 break;
10972         case ASC_ERROR:
10973         default:
10974                 asc_scsi_done(scp);
10975                 break;
10976         }
10977
10978         return result;
10979 }
10980
10981 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
10982 {
10983         PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
10984             (PortAddr) (ASC_EISA_CFG_IOP_MASK);
10985         return inpw(eisa_cfg_iop);
10986 }
10987
10988 /*
10989  * Return the BIOS address of the adapter at the specified
10990  * I/O port and with the specified bus type.
10991  */
10992 static unsigned short __devinit
10993 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
10994 {
10995         unsigned short cfg_lsw;
10996         unsigned short bios_addr;
10997
10998         /*
10999          * The PCI BIOS is re-located by the motherboard BIOS. Because
11000          * of this the driver can not determine where a PCI BIOS is
11001          * loaded and executes.
11002          */
11003         if (bus_type & ASC_IS_PCI)
11004                 return 0;
11005
11006         if ((bus_type & ASC_IS_EISA) != 0) {
11007                 cfg_lsw = AscGetEisaChipCfg(iop_base);
11008                 cfg_lsw &= 0x000F;
11009                 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11010                 return bios_addr;
11011         }
11012
11013         cfg_lsw = AscGetChipCfgLsw(iop_base);
11014
11015         /*
11016          *  ISA PnP uses the top bit as the 32K BIOS flag
11017          */
11018         if (bus_type == ASC_IS_ISAPNP)
11019                 cfg_lsw &= 0x7FFF;
11020         bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11021         return bios_addr;
11022 }
11023
11024 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11025 {
11026         ushort cfg_lsw;
11027
11028         if (AscGetChipScsiID(iop_base) == new_host_id) {
11029                 return (new_host_id);
11030         }
11031         cfg_lsw = AscGetChipCfgLsw(iop_base);
11032         cfg_lsw &= 0xF8FF;
11033         cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11034         AscSetChipCfgLsw(iop_base, cfg_lsw);
11035         return (AscGetChipScsiID(iop_base));
11036 }
11037
11038 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11039 {
11040         unsigned char sc;
11041
11042         AscSetBank(iop_base, 1);
11043         sc = inp(iop_base + IOP_REG_SC);
11044         AscSetBank(iop_base, 0);
11045         return sc;
11046 }
11047
11048 static unsigned char __devinit
11049 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11050 {
11051         if (bus_type & ASC_IS_EISA) {
11052                 PortAddr eisa_iop;
11053                 unsigned char revision;
11054                 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11055                     (PortAddr) ASC_EISA_REV_IOP_MASK;
11056                 revision = inp(eisa_iop);
11057                 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11058         }
11059         return AscGetChipVerNo(iop_base);
11060 }
11061
11062 #ifdef CONFIG_ISA
11063 static void __devinit AscEnableIsaDma(uchar dma_channel)
11064 {
11065         if (dma_channel < 4) {
11066                 outp(0x000B, (ushort)(0xC0 | dma_channel));
11067                 outp(0x000A, dma_channel);
11068         } else if (dma_channel < 8) {
11069                 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11070                 outp(0x00D4, (ushort)(dma_channel - 4));
11071         }
11072 }
11073 #endif /* CONFIG_ISA */
11074
11075 static int AscStopQueueExe(PortAddr iop_base)
11076 {
11077         int count = 0;
11078
11079         if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11080                 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11081                                  ASC_STOP_REQ_RISC_STOP);
11082                 do {
11083                         if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11084                             ASC_STOP_ACK_RISC_STOP) {
11085                                 return (1);
11086                         }
11087                         mdelay(100);
11088                 } while (count++ < 20);
11089         }
11090         return (0);
11091 }
11092
11093 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11094 {
11095         if (bus_type & ASC_IS_ISA)
11096                 return ASC_MAX_ISA_DMA_COUNT;
11097         else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11098                 return ASC_MAX_VL_DMA_COUNT;
11099         return ASC_MAX_PCI_DMA_COUNT;
11100 }
11101
11102 #ifdef CONFIG_ISA
11103 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11104 {
11105         ushort channel;
11106
11107         channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11108         if (channel == 0x03)
11109                 return (0);
11110         else if (channel == 0x00)
11111                 return (7);
11112         return (channel + 4);
11113 }
11114
11115 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11116 {
11117         ushort cfg_lsw;
11118         uchar value;
11119
11120         if ((dma_channel >= 5) && (dma_channel <= 7)) {
11121                 if (dma_channel == 7)
11122                         value = 0x00;
11123                 else
11124                         value = dma_channel - 4;
11125                 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11126                 cfg_lsw |= value;
11127                 AscSetChipCfgLsw(iop_base, cfg_lsw);
11128                 return (AscGetIsaDmaChannel(iop_base));
11129         }
11130         return 0;
11131 }
11132
11133 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11134 {
11135         uchar speed_value;
11136
11137         AscSetBank(iop_base, 1);
11138         speed_value = AscReadChipDmaSpeed(iop_base);
11139         speed_value &= 0x07;
11140         AscSetBank(iop_base, 0);
11141         return speed_value;
11142 }
11143
11144 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11145 {
11146         speed_value &= 0x07;
11147         AscSetBank(iop_base, 1);
11148         AscWriteChipDmaSpeed(iop_base, speed_value);
11149         AscSetBank(iop_base, 0);
11150         return AscGetIsaDmaSpeed(iop_base);
11151 }
11152 #endif /* CONFIG_ISA */
11153
11154 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11155 {
11156         int i;
11157         PortAddr iop_base;
11158         ushort warn_code;
11159         uchar chip_version;
11160
11161         iop_base = asc_dvc->iop_base;
11162         warn_code = 0;
11163         asc_dvc->err_code = 0;
11164         if ((asc_dvc->bus_type &
11165              (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11166                 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11167         }
11168         AscSetChipControl(iop_base, CC_HALT);
11169         AscSetChipStatus(iop_base, 0);
11170         asc_dvc->bug_fix_cntl = 0;
11171         asc_dvc->pci_fix_asyn_xfer = 0;
11172         asc_dvc->pci_fix_asyn_xfer_always = 0;
11173         /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11174         asc_dvc->sdtr_done = 0;
11175         asc_dvc->cur_total_qng = 0;
11176         asc_dvc->is_in_int = 0;
11177         asc_dvc->in_critical_cnt = 0;
11178         asc_dvc->last_q_shortage = 0;
11179         asc_dvc->use_tagged_qng = 0;
11180         asc_dvc->no_scam = 0;
11181         asc_dvc->unit_not_ready = 0;
11182         asc_dvc->queue_full_or_busy = 0;
11183         asc_dvc->redo_scam = 0;
11184         asc_dvc->res2 = 0;
11185         asc_dvc->min_sdtr_index = 0;
11186         asc_dvc->cfg->can_tagged_qng = 0;
11187         asc_dvc->cfg->cmd_qng_enabled = 0;
11188         asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11189         asc_dvc->init_sdtr = 0;
11190         asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11191         asc_dvc->scsi_reset_wait = 3;
11192         asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11193         asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11194         asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11195         asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11196         asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11197         chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11198         asc_dvc->cfg->chip_version = chip_version;
11199         asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
11200         asc_dvc->max_sdtr_index = 7;
11201         if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11202             (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11203                 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11204                 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
11205                 asc_dvc->max_sdtr_index = 15;
11206                 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11207                         AscSetExtraControl(iop_base,
11208                                            (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11209                 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11210                         AscSetExtraControl(iop_base,
11211                                            (SEC_ACTIVE_NEGATE |
11212                                             SEC_ENABLE_FILTER));
11213                 }
11214         }
11215         if (asc_dvc->bus_type == ASC_IS_PCI) {
11216                 AscSetExtraControl(iop_base,
11217                                    (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11218         }
11219
11220         asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11221 #ifdef CONFIG_ISA
11222         if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11223                 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11224                         AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11225                         asc_dvc->bus_type = ASC_IS_ISAPNP;
11226                 }
11227                 asc_dvc->cfg->isa_dma_channel =
11228                     (uchar)AscGetIsaDmaChannel(iop_base);
11229         }
11230 #endif /* CONFIG_ISA */
11231         for (i = 0; i <= ASC_MAX_TID; i++) {
11232                 asc_dvc->cur_dvc_qng[i] = 0;
11233                 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11234                 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11235                 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11236                 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11237         }
11238         return warn_code;
11239 }
11240
11241 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11242 {
11243         int retry;
11244
11245         for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11246                 unsigned char read_back;
11247                 AscSetChipEEPCmd(iop_base, cmd_reg);
11248                 mdelay(1);
11249                 read_back = AscGetChipEEPCmd(iop_base);
11250                 if (read_back == cmd_reg)
11251                         return 1;
11252         }
11253         return 0;
11254 }
11255
11256 static void __devinit AscWaitEEPRead(void)
11257 {
11258         mdelay(1);
11259 }
11260
11261 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11262 {
11263         ushort read_wval;
11264         uchar cmd_reg;
11265
11266         AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11267         AscWaitEEPRead();
11268         cmd_reg = addr | ASC_EEP_CMD_READ;
11269         AscWriteEEPCmdReg(iop_base, cmd_reg);
11270         AscWaitEEPRead();
11271         read_wval = AscGetChipEEPData(iop_base);
11272         AscWaitEEPRead();
11273         return read_wval;
11274 }
11275
11276 static ushort __devinit
11277 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11278 {
11279         ushort wval;
11280         ushort sum;
11281         ushort *wbuf;
11282         int cfg_beg;
11283         int cfg_end;
11284         int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11285         int s_addr;
11286
11287         wbuf = (ushort *)cfg_buf;
11288         sum = 0;
11289         /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11290         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11291                 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11292                 sum += *wbuf;
11293         }
11294         if (bus_type & ASC_IS_VL) {
11295                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11296                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11297         } else {
11298                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11299                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11300         }
11301         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11302                 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11303                 if (s_addr <= uchar_end_in_config) {
11304                         /*
11305                          * Swap all char fields - must unswap bytes already swapped
11306                          * by AscReadEEPWord().
11307                          */
11308                         *wbuf = le16_to_cpu(wval);
11309                 } else {
11310                         /* Don't swap word field at the end - cntl field. */
11311                         *wbuf = wval;
11312                 }
11313                 sum += wval;    /* Checksum treats all EEPROM data as words. */
11314         }
11315         /*
11316          * Read the checksum word which will be compared against 'sum'
11317          * by the caller. Word field already swapped.
11318          */
11319         *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11320         return sum;
11321 }
11322
11323 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11324 {
11325         PortAddr iop_base;
11326         ushort q_addr;
11327         ushort saved_word;
11328         int sta;
11329
11330         iop_base = asc_dvc->iop_base;
11331         sta = 0;
11332         q_addr = ASC_QNO_TO_QADDR(241);
11333         saved_word = AscReadLramWord(iop_base, q_addr);
11334         AscSetChipLramAddr(iop_base, q_addr);
11335         AscSetChipLramData(iop_base, 0x55AA);
11336         mdelay(10);
11337         AscSetChipLramAddr(iop_base, q_addr);
11338         if (AscGetChipLramData(iop_base) == 0x55AA) {
11339                 sta = 1;
11340                 AscWriteLramWord(iop_base, q_addr, saved_word);
11341         }
11342         return (sta);
11343 }
11344
11345 static void __devinit AscWaitEEPWrite(void)
11346 {
11347         mdelay(20);
11348 }
11349
11350 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11351 {
11352         ushort read_back;
11353         int retry;
11354
11355         retry = 0;
11356         while (TRUE) {
11357                 AscSetChipEEPData(iop_base, data_reg);
11358                 mdelay(1);
11359                 read_back = AscGetChipEEPData(iop_base);
11360                 if (read_back == data_reg) {
11361                         return (1);
11362                 }
11363                 if (retry++ > ASC_EEP_MAX_RETRY) {
11364                         return (0);
11365                 }
11366         }
11367 }
11368
11369 static ushort __devinit
11370 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11371 {
11372         ushort read_wval;
11373
11374         read_wval = AscReadEEPWord(iop_base, addr);
11375         if (read_wval != word_val) {
11376                 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11377                 AscWaitEEPRead();
11378                 AscWriteEEPDataReg(iop_base, word_val);
11379                 AscWaitEEPRead();
11380                 AscWriteEEPCmdReg(iop_base,
11381                                   (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11382                 AscWaitEEPWrite();
11383                 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11384                 AscWaitEEPRead();
11385                 return (AscReadEEPWord(iop_base, addr));
11386         }
11387         return (read_wval);
11388 }
11389
11390 static int __devinit
11391 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11392 {
11393         int n_error;
11394         ushort *wbuf;
11395         ushort word;
11396         ushort sum;
11397         int s_addr;
11398         int cfg_beg;
11399         int cfg_end;
11400         int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11401
11402         wbuf = (ushort *)cfg_buf;
11403         n_error = 0;
11404         sum = 0;
11405         /* Write two config words; AscWriteEEPWord() will swap bytes. */
11406         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11407                 sum += *wbuf;
11408                 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11409                         n_error++;
11410                 }
11411         }
11412         if (bus_type & ASC_IS_VL) {
11413                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11414                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11415         } else {
11416                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11417                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11418         }
11419         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11420                 if (s_addr <= uchar_end_in_config) {
11421                         /*
11422                          * This is a char field. Swap char fields before they are
11423                          * swapped again by AscWriteEEPWord().
11424                          */
11425                         word = cpu_to_le16(*wbuf);
11426                         if (word !=
11427                             AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11428                                 n_error++;
11429                         }
11430                 } else {
11431                         /* Don't swap word field at the end - cntl field. */
11432                         if (*wbuf !=
11433                             AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11434                                 n_error++;
11435                         }
11436                 }
11437                 sum += *wbuf;   /* Checksum calculated from word values. */
11438         }
11439         /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11440         *wbuf = sum;
11441         if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11442                 n_error++;
11443         }
11444
11445         /* Read EEPROM back again. */
11446         wbuf = (ushort *)cfg_buf;
11447         /*
11448          * Read two config words; Byte-swapping done by AscReadEEPWord().
11449          */
11450         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11451                 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11452                         n_error++;
11453                 }
11454         }
11455         if (bus_type & ASC_IS_VL) {
11456                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11457                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11458         } else {
11459                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11460                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11461         }
11462         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11463                 if (s_addr <= uchar_end_in_config) {
11464                         /*
11465                          * Swap all char fields. Must unswap bytes already swapped
11466                          * by AscReadEEPWord().
11467                          */
11468                         word =
11469                             le16_to_cpu(AscReadEEPWord
11470                                         (iop_base, (uchar)s_addr));
11471                 } else {
11472                         /* Don't swap word field at the end - cntl field. */
11473                         word = AscReadEEPWord(iop_base, (uchar)s_addr);
11474                 }
11475                 if (*wbuf != word) {
11476                         n_error++;
11477                 }
11478         }
11479         /* Read checksum; Byte swapping not needed. */
11480         if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
11481                 n_error++;
11482         }
11483         return n_error;
11484 }
11485
11486 static int __devinit
11487 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11488 {
11489         int retry;
11490         int n_error;
11491
11492         retry = 0;
11493         while (TRUE) {
11494                 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
11495                                                    bus_type)) == 0) {
11496                         break;
11497                 }
11498                 if (++retry > ASC_EEP_MAX_RETRY) {
11499                         break;
11500                 }
11501         }
11502         return n_error;
11503 }
11504
11505 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11506 {
11507         ASCEEP_CONFIG eep_config_buf;
11508         ASCEEP_CONFIG *eep_config;
11509         PortAddr iop_base;
11510         ushort chksum;
11511         ushort warn_code;
11512         ushort cfg_msw, cfg_lsw;
11513         int i;
11514         int write_eep = 0;
11515
11516         iop_base = asc_dvc->iop_base;
11517         warn_code = 0;
11518         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
11519         AscStopQueueExe(iop_base);
11520         if ((AscStopChip(iop_base) == FALSE) ||
11521             (AscGetChipScsiCtrl(iop_base) != 0)) {
11522                 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
11523                 AscResetChipAndScsiBus(asc_dvc);
11524                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
11525         }
11526         if (AscIsChipHalted(iop_base) == FALSE) {
11527                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
11528                 return (warn_code);
11529         }
11530         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
11531         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
11532                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
11533                 return (warn_code);
11534         }
11535         eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
11536         cfg_msw = AscGetChipCfgMsw(iop_base);
11537         cfg_lsw = AscGetChipCfgLsw(iop_base);
11538         if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11539                 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11540                 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11541                 AscSetChipCfgMsw(iop_base, cfg_msw);
11542         }
11543         chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
11544         ASC_DBG(1, "chksum 0x%x\n", chksum);
11545         if (chksum == 0) {
11546                 chksum = 0xaa55;
11547         }
11548         if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11549                 warn_code |= ASC_WARN_AUTO_CONFIG;
11550                 if (asc_dvc->cfg->chip_version == 3) {
11551                         if (eep_config->cfg_lsw != cfg_lsw) {
11552                                 warn_code |= ASC_WARN_EEPROM_RECOVER;
11553                                 eep_config->cfg_lsw =
11554                                     AscGetChipCfgLsw(iop_base);
11555                         }
11556                         if (eep_config->cfg_msw != cfg_msw) {
11557                                 warn_code |= ASC_WARN_EEPROM_RECOVER;
11558                                 eep_config->cfg_msw =
11559                                     AscGetChipCfgMsw(iop_base);
11560                         }
11561                 }
11562         }
11563         eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11564         eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
11565         ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
11566         if (chksum != eep_config->chksum) {
11567                 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
11568                     ASC_CHIP_VER_PCI_ULTRA_3050) {
11569                         ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
11570                         eep_config->init_sdtr = 0xFF;
11571                         eep_config->disc_enable = 0xFF;
11572                         eep_config->start_motor = 0xFF;
11573                         eep_config->use_cmd_qng = 0;
11574                         eep_config->max_total_qng = 0xF0;
11575                         eep_config->max_tag_qng = 0x20;
11576                         eep_config->cntl = 0xBFFF;
11577                         ASC_EEP_SET_CHIP_ID(eep_config, 7);
11578                         eep_config->no_scam = 0;
11579                         eep_config->adapter_info[0] = 0;
11580                         eep_config->adapter_info[1] = 0;
11581                         eep_config->adapter_info[2] = 0;
11582                         eep_config->adapter_info[3] = 0;
11583                         eep_config->adapter_info[4] = 0;
11584                         /* Indicate EEPROM-less board. */
11585                         eep_config->adapter_info[5] = 0xBB;
11586                 } else {
11587                         ASC_PRINT
11588                             ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11589                         write_eep = 1;
11590                         warn_code |= ASC_WARN_EEPROM_CHKSUM;
11591                 }
11592         }
11593         asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
11594         asc_dvc->cfg->disc_enable = eep_config->disc_enable;
11595         asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
11596         asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
11597         asc_dvc->start_motor = eep_config->start_motor;
11598         asc_dvc->dvc_cntl = eep_config->cntl;
11599         asc_dvc->no_scam = eep_config->no_scam;
11600         asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
11601         asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
11602         asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
11603         asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
11604         asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
11605         asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
11606         if (!AscTestExternalLram(asc_dvc)) {
11607                 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
11608                      ASC_IS_PCI_ULTRA)) {
11609                         eep_config->max_total_qng =
11610                             ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
11611                         eep_config->max_tag_qng =
11612                             ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
11613                 } else {
11614                         eep_config->cfg_msw |= 0x0800;
11615                         cfg_msw |= 0x0800;
11616                         AscSetChipCfgMsw(iop_base, cfg_msw);
11617                         eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
11618                         eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
11619                 }
11620         } else {
11621         }
11622         if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
11623                 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
11624         }
11625         if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
11626                 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
11627         }
11628         if (eep_config->max_tag_qng > eep_config->max_total_qng) {
11629                 eep_config->max_tag_qng = eep_config->max_total_qng;
11630         }
11631         if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
11632                 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
11633         }
11634         asc_dvc->max_total_qng = eep_config->max_total_qng;
11635         if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
11636             eep_config->use_cmd_qng) {
11637                 eep_config->disc_enable = eep_config->use_cmd_qng;
11638                 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11639         }
11640         ASC_EEP_SET_CHIP_ID(eep_config,
11641                             ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
11642         asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
11643         if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
11644             !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
11645                 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
11646         }
11647
11648         for (i = 0; i <= ASC_MAX_TID; i++) {
11649                 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
11650                 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
11651                 asc_dvc->cfg->sdtr_period_offset[i] =
11652                     (uchar)(ASC_DEF_SDTR_OFFSET |
11653                             (asc_dvc->min_sdtr_index << 4));
11654         }
11655         eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
11656         if (write_eep) {
11657                 if ((i = AscSetEEPConfig(iop_base, eep_config,
11658                                      asc_dvc->bus_type)) != 0) {
11659                         ASC_PRINT1
11660                             ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
11661                              i);
11662                 } else {
11663                         ASC_PRINT
11664                             ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
11665                 }
11666         }
11667         return (warn_code);
11668 }
11669
11670 static int __devinit AscInitGetConfig(struct Scsi_Host *shost)
11671 {
11672         struct asc_board *board = shost_priv(shost);
11673         ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11674         unsigned short warn_code = 0;
11675
11676         asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11677         if (asc_dvc->err_code != 0)
11678                 return asc_dvc->err_code;
11679
11680         if (AscFindSignature(asc_dvc->iop_base)) {
11681                 warn_code |= AscInitAscDvcVar(asc_dvc);
11682                 warn_code |= AscInitFromEEP(asc_dvc);
11683                 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11684                 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
11685                         asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11686         } else {
11687                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11688         }
11689
11690         switch (warn_code) {
11691         case 0: /* No error */
11692                 break;
11693         case ASC_WARN_IO_PORT_ROTATE:
11694                 shost_printk(KERN_WARNING, shost, "I/O port address "
11695                                 "modified\n");
11696                 break;
11697         case ASC_WARN_AUTO_CONFIG:
11698                 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11699                                 "enabled\n");
11700                 break;
11701         case ASC_WARN_EEPROM_CHKSUM:
11702                 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
11703                 break;
11704         case ASC_WARN_IRQ_MODIFIED:
11705                 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
11706                 break;
11707         case ASC_WARN_CMD_QNG_CONFLICT:
11708                 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
11709                                 "disconnects\n");
11710                 break;
11711         default:
11712                 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
11713                                 warn_code);
11714                 break;
11715         }
11716
11717         if (asc_dvc->err_code != 0)
11718                 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
11719                         "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
11720
11721         return asc_dvc->err_code;
11722 }
11723
11724 static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11725 {
11726         struct asc_board *board = shost_priv(shost);
11727         ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11728         PortAddr iop_base = asc_dvc->iop_base;
11729         unsigned short cfg_msw;
11730         unsigned short warn_code = 0;
11731
11732         asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11733         if (asc_dvc->err_code != 0)
11734                 return asc_dvc->err_code;
11735         if (!AscFindSignature(asc_dvc->iop_base)) {
11736                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11737                 return asc_dvc->err_code;
11738         }
11739
11740         cfg_msw = AscGetChipCfgMsw(iop_base);
11741         if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11742                 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11743                 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11744                 AscSetChipCfgMsw(iop_base, cfg_msw);
11745         }
11746         if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
11747             asc_dvc->cfg->cmd_qng_enabled) {
11748                 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
11749                 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11750         }
11751         if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11752                 warn_code |= ASC_WARN_AUTO_CONFIG;
11753         }
11754 #ifdef CONFIG_PCI
11755         if (asc_dvc->bus_type & ASC_IS_PCI) {
11756                 cfg_msw &= 0xFFC0;
11757                 AscSetChipCfgMsw(iop_base, cfg_msw);
11758                 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
11759                 } else {
11760                         if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11761                             (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11762                                 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
11763                                 asc_dvc->bug_fix_cntl |=
11764                                     ASC_BUG_FIX_ASYN_USE_SYN;
11765                         }
11766                 }
11767         } else
11768 #endif /* CONFIG_PCI */
11769         if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
11770                 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
11771                     == ASC_CHIP_VER_ASYN_BUG) {
11772                         asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
11773                 }
11774         }
11775         if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
11776             asc_dvc->cfg->chip_scsi_id) {
11777                 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
11778         }
11779 #ifdef CONFIG_ISA
11780         if (asc_dvc->bus_type & ASC_IS_ISA) {
11781                 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
11782                 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
11783         }
11784 #endif /* CONFIG_ISA */
11785
11786         asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
11787
11788         switch (warn_code) {
11789         case 0: /* No error. */
11790                 break;
11791         case ASC_WARN_IO_PORT_ROTATE:
11792                 shost_printk(KERN_WARNING, shost, "I/O port address "
11793                                 "modified\n");
11794                 break;
11795         case ASC_WARN_AUTO_CONFIG:
11796                 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11797                                 "enabled\n");
11798                 break;
11799         case ASC_WARN_EEPROM_CHKSUM:
11800                 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
11801                 break;
11802         case ASC_WARN_IRQ_MODIFIED:
11803                 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
11804                 break;
11805         case ASC_WARN_CMD_QNG_CONFLICT:
11806                 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
11807                                 "disconnects\n");
11808                 break;
11809         default:
11810                 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
11811                                 warn_code);
11812                 break;
11813         }
11814
11815         if (asc_dvc->err_code != 0)
11816                 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
11817                         "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
11818
11819         return asc_dvc->err_code;
11820 }
11821
11822 /*
11823  * EEPROM Configuration.
11824  *
11825  * All drivers should use this structure to set the default EEPROM
11826  * configuration. The BIOS now uses this structure when it is built.
11827  * Additional structure information can be found in a_condor.h where
11828  * the structure is defined.
11829  *
11830  * The *_Field_IsChar structs are needed to correct for endianness.
11831  * These values are read from the board 16 bits at a time directly
11832  * into the structs. Because some fields are char, the values will be
11833  * in the wrong order. The *_Field_IsChar tells when to flip the
11834  * bytes. Data read and written to PCI memory is automatically swapped
11835  * on big-endian platforms so char fields read as words are actually being
11836  * unswapped on big-endian platforms.
11837  */
11838 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
11839         ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
11840         0x0000,                 /* cfg_msw */
11841         0xFFFF,                 /* disc_enable */
11842         0xFFFF,                 /* wdtr_able */
11843         0xFFFF,                 /* sdtr_able */
11844         0xFFFF,                 /* start_motor */
11845         0xFFFF,                 /* tagqng_able */
11846         0xFFFF,                 /* bios_scan */
11847         0,                      /* scam_tolerant */
11848         7,                      /* adapter_scsi_id */
11849         0,                      /* bios_boot_delay */
11850         3,                      /* scsi_reset_delay */
11851         0,                      /* bios_id_lun */
11852         0,                      /* termination */
11853         0,                      /* reserved1 */
11854         0xFFE7,                 /* bios_ctrl */
11855         0xFFFF,                 /* ultra_able */
11856         0,                      /* reserved2 */
11857         ASC_DEF_MAX_HOST_QNG,   /* max_host_qng */
11858         ASC_DEF_MAX_DVC_QNG,    /* max_dvc_qng */
11859         0,                      /* dvc_cntl */
11860         0,                      /* bug_fix */
11861         0,                      /* serial_number_word1 */
11862         0,                      /* serial_number_word2 */
11863         0,                      /* serial_number_word3 */
11864         0,                      /* check_sum */
11865         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11866         ,                       /* oem_name[16] */
11867         0,                      /* dvc_err_code */
11868         0,                      /* adv_err_code */
11869         0,                      /* adv_err_addr */
11870         0,                      /* saved_dvc_err_code */
11871         0,                      /* saved_adv_err_code */
11872         0,                      /* saved_adv_err_addr */
11873         0                       /* num_of_err */
11874 };
11875
11876 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
11877         0,                      /* cfg_lsw */
11878         0,                      /* cfg_msw */
11879         0,                      /* -disc_enable */
11880         0,                      /* wdtr_able */
11881         0,                      /* sdtr_able */
11882         0,                      /* start_motor */
11883         0,                      /* tagqng_able */
11884         0,                      /* bios_scan */
11885         0,                      /* scam_tolerant */
11886         1,                      /* adapter_scsi_id */
11887         1,                      /* bios_boot_delay */
11888         1,                      /* scsi_reset_delay */
11889         1,                      /* bios_id_lun */
11890         1,                      /* termination */
11891         1,                      /* reserved1 */
11892         0,                      /* bios_ctrl */
11893         0,                      /* ultra_able */
11894         0,                      /* reserved2 */
11895         1,                      /* max_host_qng */
11896         1,                      /* max_dvc_qng */
11897         0,                      /* dvc_cntl */
11898         0,                      /* bug_fix */
11899         0,                      /* serial_number_word1 */
11900         0,                      /* serial_number_word2 */
11901         0,                      /* serial_number_word3 */
11902         0,                      /* check_sum */
11903         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
11904         ,                       /* oem_name[16] */
11905         0,                      /* dvc_err_code */
11906         0,                      /* adv_err_code */
11907         0,                      /* adv_err_addr */
11908         0,                      /* saved_dvc_err_code */
11909         0,                      /* saved_adv_err_code */
11910         0,                      /* saved_adv_err_addr */
11911         0                       /* num_of_err */
11912 };
11913
11914 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
11915         ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
11916         0x0000,                 /* 01 cfg_msw */
11917         0xFFFF,                 /* 02 disc_enable */
11918         0xFFFF,                 /* 03 wdtr_able */
11919         0x4444,                 /* 04 sdtr_speed1 */
11920         0xFFFF,                 /* 05 start_motor */
11921         0xFFFF,                 /* 06 tagqng_able */
11922         0xFFFF,                 /* 07 bios_scan */
11923         0,                      /* 08 scam_tolerant */
11924         7,                      /* 09 adapter_scsi_id */
11925         0,                      /*    bios_boot_delay */
11926         3,                      /* 10 scsi_reset_delay */
11927         0,                      /*    bios_id_lun */
11928         0,                      /* 11 termination_se */
11929         0,                      /*    termination_lvd */
11930         0xFFE7,                 /* 12 bios_ctrl */
11931         0x4444,                 /* 13 sdtr_speed2 */
11932         0x4444,                 /* 14 sdtr_speed3 */
11933         ASC_DEF_MAX_HOST_QNG,   /* 15 max_host_qng */
11934         ASC_DEF_MAX_DVC_QNG,    /*    max_dvc_qng */
11935         0,                      /* 16 dvc_cntl */
11936         0x4444,                 /* 17 sdtr_speed4 */
11937         0,                      /* 18 serial_number_word1 */
11938         0,                      /* 19 serial_number_word2 */
11939         0,                      /* 20 serial_number_word3 */
11940         0,                      /* 21 check_sum */
11941         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11942         ,                       /* 22-29 oem_name[16] */
11943         0,                      /* 30 dvc_err_code */
11944         0,                      /* 31 adv_err_code */
11945         0,                      /* 32 adv_err_addr */
11946         0,                      /* 33 saved_dvc_err_code */
11947         0,                      /* 34 saved_adv_err_code */
11948         0,                      /* 35 saved_adv_err_addr */
11949         0,                      /* 36 reserved */
11950         0,                      /* 37 reserved */
11951         0,                      /* 38 reserved */
11952         0,                      /* 39 reserved */
11953         0,                      /* 40 reserved */
11954         0,                      /* 41 reserved */
11955         0,                      /* 42 reserved */
11956         0,                      /* 43 reserved */
11957         0,                      /* 44 reserved */
11958         0,                      /* 45 reserved */
11959         0,                      /* 46 reserved */
11960         0,                      /* 47 reserved */
11961         0,                      /* 48 reserved */
11962         0,                      /* 49 reserved */
11963         0,                      /* 50 reserved */
11964         0,                      /* 51 reserved */
11965         0,                      /* 52 reserved */
11966         0,                      /* 53 reserved */
11967         0,                      /* 54 reserved */
11968         0,                      /* 55 reserved */
11969         0,                      /* 56 cisptr_lsw */
11970         0,                      /* 57 cisprt_msw */
11971         PCI_VENDOR_ID_ASP,      /* 58 subsysvid */
11972         PCI_DEVICE_ID_38C0800_REV1,     /* 59 subsysid */
11973         0,                      /* 60 reserved */
11974         0,                      /* 61 reserved */
11975         0,                      /* 62 reserved */
11976         0                       /* 63 reserved */
11977 };
11978
11979 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
11980         0,                      /* 00 cfg_lsw */
11981         0,                      /* 01 cfg_msw */
11982         0,                      /* 02 disc_enable */
11983         0,                      /* 03 wdtr_able */
11984         0,                      /* 04 sdtr_speed1 */
11985         0,                      /* 05 start_motor */
11986         0,                      /* 06 tagqng_able */
11987         0,                      /* 07 bios_scan */
11988         0,                      /* 08 scam_tolerant */
11989         1,                      /* 09 adapter_scsi_id */
11990         1,                      /*    bios_boot_delay */
11991         1,                      /* 10 scsi_reset_delay */
11992         1,                      /*    bios_id_lun */
11993         1,                      /* 11 termination_se */
11994         1,                      /*    termination_lvd */
11995         0,                      /* 12 bios_ctrl */
11996         0,                      /* 13 sdtr_speed2 */
11997         0,                      /* 14 sdtr_speed3 */
11998         1,                      /* 15 max_host_qng */
11999         1,                      /*    max_dvc_qng */
12000         0,                      /* 16 dvc_cntl */
12001         0,                      /* 17 sdtr_speed4 */
12002         0,                      /* 18 serial_number_word1 */
12003         0,                      /* 19 serial_number_word2 */
12004         0,                      /* 20 serial_number_word3 */
12005         0,                      /* 21 check_sum */
12006         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12007         ,                       /* 22-29 oem_name[16] */
12008         0,                      /* 30 dvc_err_code */
12009         0,                      /* 31 adv_err_code */
12010         0,                      /* 32 adv_err_addr */
12011         0,                      /* 33 saved_dvc_err_code */
12012         0,                      /* 34 saved_adv_err_code */
12013         0,                      /* 35 saved_adv_err_addr */
12014         0,                      /* 36 reserved */
12015         0,                      /* 37 reserved */
12016         0,                      /* 38 reserved */
12017         0,                      /* 39 reserved */
12018         0,                      /* 40 reserved */
12019         0,                      /* 41 reserved */
12020         0,                      /* 42 reserved */
12021         0,                      /* 43 reserved */
12022         0,                      /* 44 reserved */
12023         0,                      /* 45 reserved */
12024         0,                      /* 46 reserved */
12025         0,                      /* 47 reserved */
12026         0,                      /* 48 reserved */
12027         0,                      /* 49 reserved */
12028         0,                      /* 50 reserved */
12029         0,                      /* 51 reserved */
12030         0,                      /* 52 reserved */
12031         0,                      /* 53 reserved */
12032         0,                      /* 54 reserved */
12033         0,                      /* 55 reserved */
12034         0,                      /* 56 cisptr_lsw */
12035         0,                      /* 57 cisprt_msw */
12036         0,                      /* 58 subsysvid */
12037         0,                      /* 59 subsysid */
12038         0,                      /* 60 reserved */
12039         0,                      /* 61 reserved */
12040         0,                      /* 62 reserved */
12041         0                       /* 63 reserved */
12042 };
12043
12044 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12045         ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12046         0x0000,                 /* 01 cfg_msw */
12047         0xFFFF,                 /* 02 disc_enable */
12048         0xFFFF,                 /* 03 wdtr_able */
12049         0x5555,                 /* 04 sdtr_speed1 */
12050         0xFFFF,                 /* 05 start_motor */
12051         0xFFFF,                 /* 06 tagqng_able */
12052         0xFFFF,                 /* 07 bios_scan */
12053         0,                      /* 08 scam_tolerant */
12054         7,                      /* 09 adapter_scsi_id */
12055         0,                      /*    bios_boot_delay */
12056         3,                      /* 10 scsi_reset_delay */
12057         0,                      /*    bios_id_lun */
12058         0,                      /* 11 termination_se */
12059         0,                      /*    termination_lvd */
12060         0xFFE7,                 /* 12 bios_ctrl */
12061         0x5555,                 /* 13 sdtr_speed2 */
12062         0x5555,                 /* 14 sdtr_speed3 */
12063         ASC_DEF_MAX_HOST_QNG,   /* 15 max_host_qng */
12064         ASC_DEF_MAX_DVC_QNG,    /*    max_dvc_qng */
12065         0,                      /* 16 dvc_cntl */
12066         0x5555,                 /* 17 sdtr_speed4 */
12067         0,                      /* 18 serial_number_word1 */
12068         0,                      /* 19 serial_number_word2 */
12069         0,                      /* 20 serial_number_word3 */
12070         0,                      /* 21 check_sum */
12071         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12072         ,                       /* 22-29 oem_name[16] */
12073         0,                      /* 30 dvc_err_code */
12074         0,                      /* 31 adv_err_code */
12075         0,                      /* 32 adv_err_addr */
12076         0,                      /* 33 saved_dvc_err_code */
12077         0,                      /* 34 saved_adv_err_code */
12078         0,                      /* 35 saved_adv_err_addr */
12079         0,                      /* 36 reserved */
12080         0,                      /* 37 reserved */
12081         0,                      /* 38 reserved */
12082         0,                      /* 39 reserved */
12083         0,                      /* 40 reserved */
12084         0,                      /* 41 reserved */
12085         0,                      /* 42 reserved */
12086         0,                      /* 43 reserved */
12087         0,                      /* 44 reserved */
12088         0,                      /* 45 reserved */
12089         0,                      /* 46 reserved */
12090         0,                      /* 47 reserved */
12091         0,                      /* 48 reserved */
12092         0,                      /* 49 reserved */
12093         0,                      /* 50 reserved */
12094         0,                      /* 51 reserved */
12095         0,                      /* 52 reserved */
12096         0,                      /* 53 reserved */
12097         0,                      /* 54 reserved */
12098         0,                      /* 55 reserved */
12099         0,                      /* 56 cisptr_lsw */
12100         0,                      /* 57 cisprt_msw */
12101         PCI_VENDOR_ID_ASP,      /* 58 subsysvid */
12102         PCI_DEVICE_ID_38C1600_REV1,     /* 59 subsysid */
12103         0,                      /* 60 reserved */
12104         0,                      /* 61 reserved */
12105         0,                      /* 62 reserved */
12106         0                       /* 63 reserved */
12107 };
12108
12109 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12110         0,                      /* 00 cfg_lsw */
12111         0,                      /* 01 cfg_msw */
12112         0,                      /* 02 disc_enable */
12113         0,                      /* 03 wdtr_able */
12114         0,                      /* 04 sdtr_speed1 */
12115         0,                      /* 05 start_motor */
12116         0,                      /* 06 tagqng_able */
12117         0,                      /* 07 bios_scan */
12118         0,                      /* 08 scam_tolerant */
12119         1,                      /* 09 adapter_scsi_id */
12120         1,                      /*    bios_boot_delay */
12121         1,                      /* 10 scsi_reset_delay */
12122         1,                      /*    bios_id_lun */
12123         1,                      /* 11 termination_se */
12124         1,                      /*    termination_lvd */
12125         0,                      /* 12 bios_ctrl */
12126         0,                      /* 13 sdtr_speed2 */
12127         0,                      /* 14 sdtr_speed3 */
12128         1,                      /* 15 max_host_qng */
12129         1,                      /*    max_dvc_qng */
12130         0,                      /* 16 dvc_cntl */
12131         0,                      /* 17 sdtr_speed4 */
12132         0,                      /* 18 serial_number_word1 */
12133         0,                      /* 19 serial_number_word2 */
12134         0,                      /* 20 serial_number_word3 */
12135         0,                      /* 21 check_sum */
12136         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12137         ,                       /* 22-29 oem_name[16] */
12138         0,                      /* 30 dvc_err_code */
12139         0,                      /* 31 adv_err_code */
12140         0,                      /* 32 adv_err_addr */
12141         0,                      /* 33 saved_dvc_err_code */
12142         0,                      /* 34 saved_adv_err_code */
12143         0,                      /* 35 saved_adv_err_addr */
12144         0,                      /* 36 reserved */
12145         0,                      /* 37 reserved */
12146         0,                      /* 38 reserved */
12147         0,                      /* 39 reserved */
12148         0,                      /* 40 reserved */
12149         0,                      /* 41 reserved */
12150         0,                      /* 42 reserved */
12151         0,                      /* 43 reserved */
12152         0,                      /* 44 reserved */
12153         0,                      /* 45 reserved */
12154         0,                      /* 46 reserved */
12155         0,                      /* 47 reserved */
12156         0,                      /* 48 reserved */
12157         0,                      /* 49 reserved */
12158         0,                      /* 50 reserved */
12159         0,                      /* 51 reserved */
12160         0,                      /* 52 reserved */
12161         0,                      /* 53 reserved */
12162         0,                      /* 54 reserved */
12163         0,                      /* 55 reserved */
12164         0,                      /* 56 cisptr_lsw */
12165         0,                      /* 57 cisprt_msw */
12166         0,                      /* 58 subsysvid */
12167         0,                      /* 59 subsysid */
12168         0,                      /* 60 reserved */
12169         0,                      /* 61 reserved */
12170         0,                      /* 62 reserved */
12171         0                       /* 63 reserved */
12172 };
12173
12174 #ifdef CONFIG_PCI
12175 /*
12176  * Wait for EEPROM command to complete
12177  */
12178 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12179 {
12180         int eep_delay_ms;
12181
12182         for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12183                 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12184                     ASC_EEP_CMD_DONE) {
12185                         break;
12186                 }
12187                 mdelay(1);
12188         }
12189         if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12190             0)
12191                 BUG();
12192 }
12193
12194 /*
12195  * Read the EEPROM from specified location
12196  */
12197 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12198 {
12199         AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12200                              ASC_EEP_CMD_READ | eep_word_addr);
12201         AdvWaitEEPCmd(iop_base);
12202         return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12203 }
12204
12205 /*
12206  * Write the EEPROM from 'cfg_buf'.
12207  */
12208 void __devinit
12209 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12210 {
12211         ushort *wbuf;
12212         ushort addr, chksum;
12213         ushort *charfields;
12214
12215         wbuf = (ushort *)cfg_buf;
12216         charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12217         chksum = 0;
12218
12219         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12220         AdvWaitEEPCmd(iop_base);
12221
12222         /*
12223          * Write EEPROM from word 0 to word 20.
12224          */
12225         for (addr = ADV_EEP_DVC_CFG_BEGIN;
12226              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12227                 ushort word;
12228
12229                 if (*charfields++) {
12230                         word = cpu_to_le16(*wbuf);
12231                 } else {
12232                         word = *wbuf;
12233                 }
12234                 chksum += *wbuf;        /* Checksum is calculated from word values. */
12235                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12236                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12237                                      ASC_EEP_CMD_WRITE | addr);
12238                 AdvWaitEEPCmd(iop_base);
12239                 mdelay(ADV_EEP_DELAY_MS);
12240         }
12241
12242         /*
12243          * Write EEPROM checksum at word 21.
12244          */
12245         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12246         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12247         AdvWaitEEPCmd(iop_base);
12248         wbuf++;
12249         charfields++;
12250
12251         /*
12252          * Write EEPROM OEM name at words 22 to 29.
12253          */
12254         for (addr = ADV_EEP_DVC_CTL_BEGIN;
12255              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12256                 ushort word;
12257
12258                 if (*charfields++) {
12259                         word = cpu_to_le16(*wbuf);
12260                 } else {
12261                         word = *wbuf;
12262                 }
12263                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12264                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12265                                      ASC_EEP_CMD_WRITE | addr);
12266                 AdvWaitEEPCmd(iop_base);
12267         }
12268         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12269         AdvWaitEEPCmd(iop_base);
12270 }
12271
12272 /*
12273  * Write the EEPROM from 'cfg_buf'.
12274  */
12275 void __devinit
12276 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12277 {
12278         ushort *wbuf;
12279         ushort *charfields;
12280         ushort addr, chksum;
12281
12282         wbuf = (ushort *)cfg_buf;
12283         charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12284         chksum = 0;
12285
12286         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12287         AdvWaitEEPCmd(iop_base);
12288
12289         /*
12290          * Write EEPROM from word 0 to word 20.
12291          */
12292         for (addr = ADV_EEP_DVC_CFG_BEGIN;
12293              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12294                 ushort word;
12295
12296                 if (*charfields++) {
12297                         word = cpu_to_le16(*wbuf);
12298                 } else {
12299                         word = *wbuf;
12300                 }
12301                 chksum += *wbuf;        /* Checksum is calculated from word values. */
12302                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12303                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12304                                      ASC_EEP_CMD_WRITE | addr);
12305                 AdvWaitEEPCmd(iop_base);
12306                 mdelay(ADV_EEP_DELAY_MS);
12307         }
12308
12309         /*
12310          * Write EEPROM checksum at word 21.
12311          */
12312         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12313         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12314         AdvWaitEEPCmd(iop_base);
12315         wbuf++;
12316         charfields++;
12317
12318         /*
12319          * Write EEPROM OEM name at words 22 to 29.
12320          */
12321         for (addr = ADV_EEP_DVC_CTL_BEGIN;
12322              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12323                 ushort word;
12324
12325                 if (*charfields++) {
12326                         word = cpu_to_le16(*wbuf);
12327                 } else {
12328                         word = *wbuf;
12329                 }
12330                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12331                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12332                                      ASC_EEP_CMD_WRITE | addr);
12333                 AdvWaitEEPCmd(iop_base);
12334         }
12335         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12336         AdvWaitEEPCmd(iop_base);
12337 }
12338
12339 /*
12340  * Write the EEPROM from 'cfg_buf'.
12341  */
12342 void __devinit
12343 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12344 {
12345         ushort *wbuf;
12346         ushort *charfields;
12347         ushort addr, chksum;
12348
12349         wbuf = (ushort *)cfg_buf;
12350         charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12351         chksum = 0;
12352
12353         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12354         AdvWaitEEPCmd(iop_base);
12355
12356         /*
12357          * Write EEPROM from word 0 to word 20.
12358          */
12359         for (addr = ADV_EEP_DVC_CFG_BEGIN;
12360              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12361                 ushort word;
12362
12363                 if (*charfields++) {
12364                         word = cpu_to_le16(*wbuf);
12365                 } else {
12366                         word = *wbuf;
12367                 }
12368                 chksum += *wbuf;        /* Checksum is calculated from word values. */
12369                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12370                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12371                                      ASC_EEP_CMD_WRITE | addr);
12372                 AdvWaitEEPCmd(iop_base);
12373                 mdelay(ADV_EEP_DELAY_MS);
12374         }
12375
12376         /*
12377          * Write EEPROM checksum at word 21.
12378          */
12379         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12380         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12381         AdvWaitEEPCmd(iop_base);
12382         wbuf++;
12383         charfields++;
12384
12385         /*
12386          * Write EEPROM OEM name at words 22 to 29.
12387          */
12388         for (addr = ADV_EEP_DVC_CTL_BEGIN;
12389              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12390                 ushort word;
12391
12392                 if (*charfields++) {
12393                         word = cpu_to_le16(*wbuf);
12394                 } else {
12395                         word = *wbuf;
12396                 }
12397                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12398                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12399                                      ASC_EEP_CMD_WRITE | addr);
12400                 AdvWaitEEPCmd(iop_base);
12401         }
12402         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12403         AdvWaitEEPCmd(iop_base);
12404 }
12405
12406 /*
12407  * Read EEPROM configuration into the specified buffer.
12408  *
12409  * Return a checksum based on the EEPROM configuration read.
12410  */
12411 static ushort __devinit
12412 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12413 {
12414         ushort wval, chksum;
12415         ushort *wbuf;
12416         int eep_addr;
12417         ushort *charfields;
12418
12419         charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12420         wbuf = (ushort *)cfg_buf;
12421         chksum = 0;
12422
12423         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12424              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12425                 wval = AdvReadEEPWord(iop_base, eep_addr);
12426                 chksum += wval; /* Checksum is calculated from word values. */
12427                 if (*charfields++) {
12428                         *wbuf = le16_to_cpu(wval);
12429                 } else {
12430                         *wbuf = wval;
12431                 }
12432         }
12433         /* Read checksum word. */
12434         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12435         wbuf++;
12436         charfields++;
12437
12438         /* Read rest of EEPROM not covered by the checksum. */
12439         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12440              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12441                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12442                 if (*charfields++) {
12443                         *wbuf = le16_to_cpu(*wbuf);
12444                 }
12445         }
12446         return chksum;
12447 }
12448
12449 /*
12450  * Read EEPROM configuration into the specified buffer.
12451  *
12452  * Return a checksum based on the EEPROM configuration read.
12453  */
12454 static ushort __devinit
12455 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12456 {
12457         ushort wval, chksum;
12458         ushort *wbuf;
12459         int eep_addr;
12460         ushort *charfields;
12461
12462         charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12463         wbuf = (ushort *)cfg_buf;
12464         chksum = 0;
12465
12466         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12467              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12468                 wval = AdvReadEEPWord(iop_base, eep_addr);
12469                 chksum += wval; /* Checksum is calculated from word values. */
12470                 if (*charfields++) {
12471                         *wbuf = le16_to_cpu(wval);
12472                 } else {
12473                         *wbuf = wval;
12474                 }
12475         }
12476         /* Read checksum word. */
12477         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12478         wbuf++;
12479         charfields++;
12480
12481         /* Read rest of EEPROM not covered by the checksum. */
12482         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12483              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12484                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12485                 if (*charfields++) {
12486                         *wbuf = le16_to_cpu(*wbuf);
12487                 }
12488         }
12489         return chksum;
12490 }
12491
12492 /*
12493  * Read EEPROM configuration into the specified buffer.
12494  *
12495  * Return a checksum based on the EEPROM configuration read.
12496  */
12497 static ushort __devinit
12498 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12499 {
12500         ushort wval, chksum;
12501         ushort *wbuf;
12502         int eep_addr;
12503         ushort *charfields;
12504
12505         charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12506         wbuf = (ushort *)cfg_buf;
12507         chksum = 0;
12508
12509         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12510              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12511                 wval = AdvReadEEPWord(iop_base, eep_addr);
12512                 chksum += wval; /* Checksum is calculated from word values. */
12513                 if (*charfields++) {
12514                         *wbuf = le16_to_cpu(wval);
12515                 } else {
12516                         *wbuf = wval;
12517                 }
12518         }
12519         /* Read checksum word. */
12520         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12521         wbuf++;
12522         charfields++;
12523
12524         /* Read rest of EEPROM not covered by the checksum. */
12525         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12526              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12527                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12528                 if (*charfields++) {
12529                         *wbuf = le16_to_cpu(*wbuf);
12530                 }
12531         }
12532         return chksum;
12533 }
12534
12535 /*
12536  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12537  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12538  * all of this is done.
12539  *
12540  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12541  *
12542  * For a non-fatal error return a warning code. If there are no warnings
12543  * then 0 is returned.
12544  *
12545  * Note: Chip is stopped on entry.
12546  */
12547 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
12548 {
12549         AdvPortAddr iop_base;
12550         ushort warn_code;
12551         ADVEEP_3550_CONFIG eep_config;
12552
12553         iop_base = asc_dvc->iop_base;
12554
12555         warn_code = 0;
12556
12557         /*
12558          * Read the board's EEPROM configuration.
12559          *
12560          * Set default values if a bad checksum is found.
12561          */
12562         if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
12563                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12564
12565                 /*
12566                  * Set EEPROM default values.
12567                  */
12568                 memcpy(&eep_config, &Default_3550_EEPROM_Config,
12569                         sizeof(ADVEEP_3550_CONFIG));
12570
12571                 /*
12572                  * Assume the 6 byte board serial number that was read from
12573                  * EEPROM is correct even if the EEPROM checksum failed.
12574                  */
12575                 eep_config.serial_number_word3 =
12576                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12577
12578                 eep_config.serial_number_word2 =
12579                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12580
12581                 eep_config.serial_number_word1 =
12582                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12583
12584                 AdvSet3550EEPConfig(iop_base, &eep_config);
12585         }
12586         /*
12587          * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12588          * EEPROM configuration that was read.
12589          *
12590          * This is the mapping of EEPROM fields to Adv Library fields.
12591          */
12592         asc_dvc->wdtr_able = eep_config.wdtr_able;
12593         asc_dvc->sdtr_able = eep_config.sdtr_able;
12594         asc_dvc->ultra_able = eep_config.ultra_able;
12595         asc_dvc->tagqng_able = eep_config.tagqng_able;
12596         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12597         asc_dvc->max_host_qng = eep_config.max_host_qng;
12598         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12599         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12600         asc_dvc->start_motor = eep_config.start_motor;
12601         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12602         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12603         asc_dvc->no_scam = eep_config.scam_tolerant;
12604         asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12605         asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12606         asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12607
12608         /*
12609          * Set the host maximum queuing (max. 253, min. 16) and the per device
12610          * maximum queuing (max. 63, min. 4).
12611          */
12612         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12613                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12614         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12615                 /* If the value is zero, assume it is uninitialized. */
12616                 if (eep_config.max_host_qng == 0) {
12617                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12618                 } else {
12619                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12620                 }
12621         }
12622
12623         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12624                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12625         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12626                 /* If the value is zero, assume it is uninitialized. */
12627                 if (eep_config.max_dvc_qng == 0) {
12628                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12629                 } else {
12630                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12631                 }
12632         }
12633
12634         /*
12635          * If 'max_dvc_qng' is greater than 'max_host_qng', then
12636          * set 'max_dvc_qng' to 'max_host_qng'.
12637          */
12638         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12639                 eep_config.max_dvc_qng = eep_config.max_host_qng;
12640         }
12641
12642         /*
12643          * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12644          * values based on possibly adjusted EEPROM values.
12645          */
12646         asc_dvc->max_host_qng = eep_config.max_host_qng;
12647         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12648
12649         /*
12650          * If the EEPROM 'termination' field is set to automatic (0), then set
12651          * the ADV_DVC_CFG 'termination' field to automatic also.
12652          *
12653          * If the termination is specified with a non-zero 'termination'
12654          * value check that a legal value is set and set the ADV_DVC_CFG
12655          * 'termination' field appropriately.
12656          */
12657         if (eep_config.termination == 0) {
12658                 asc_dvc->cfg->termination = 0;  /* auto termination */
12659         } else {
12660                 /* Enable manual control with low off / high off. */
12661                 if (eep_config.termination == 1) {
12662                         asc_dvc->cfg->termination = TERM_CTL_SEL;
12663
12664                         /* Enable manual control with low off / high on. */
12665                 } else if (eep_config.termination == 2) {
12666                         asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
12667
12668                         /* Enable manual control with low on / high on. */
12669                 } else if (eep_config.termination == 3) {
12670                         asc_dvc->cfg->termination =
12671                             TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
12672                 } else {
12673                         /*
12674                          * The EEPROM 'termination' field contains a bad value. Use
12675                          * automatic termination instead.
12676                          */
12677                         asc_dvc->cfg->termination = 0;
12678                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
12679                 }
12680         }
12681
12682         return warn_code;
12683 }
12684
12685 /*
12686  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12687  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12688  * all of this is done.
12689  *
12690  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12691  *
12692  * For a non-fatal error return a warning code. If there are no warnings
12693  * then 0 is returned.
12694  *
12695  * Note: Chip is stopped on entry.
12696  */
12697 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
12698 {
12699         AdvPortAddr iop_base;
12700         ushort warn_code;
12701         ADVEEP_38C0800_CONFIG eep_config;
12702         uchar tid, termination;
12703         ushort sdtr_speed = 0;
12704
12705         iop_base = asc_dvc->iop_base;
12706
12707         warn_code = 0;
12708
12709         /*
12710          * Read the board's EEPROM configuration.
12711          *
12712          * Set default values if a bad checksum is found.
12713          */
12714         if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
12715             eep_config.check_sum) {
12716                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12717
12718                 /*
12719                  * Set EEPROM default values.
12720                  */
12721                 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
12722                         sizeof(ADVEEP_38C0800_CONFIG));
12723
12724                 /*
12725                  * Assume the 6 byte board serial number that was read from
12726                  * EEPROM is correct even if the EEPROM checksum failed.
12727                  */
12728                 eep_config.serial_number_word3 =
12729                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12730
12731                 eep_config.serial_number_word2 =
12732                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12733
12734                 eep_config.serial_number_word1 =
12735                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12736
12737                 AdvSet38C0800EEPConfig(iop_base, &eep_config);
12738         }
12739         /*
12740          * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
12741          * EEPROM configuration that was read.
12742          *
12743          * This is the mapping of EEPROM fields to Adv Library fields.
12744          */
12745         asc_dvc->wdtr_able = eep_config.wdtr_able;
12746         asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
12747         asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
12748         asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
12749         asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
12750         asc_dvc->tagqng_able = eep_config.tagqng_able;
12751         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12752         asc_dvc->max_host_qng = eep_config.max_host_qng;
12753         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12754         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12755         asc_dvc->start_motor = eep_config.start_motor;
12756         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12757         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12758         asc_dvc->no_scam = eep_config.scam_tolerant;
12759         asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12760         asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12761         asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12762
12763         /*
12764          * For every Target ID if any of its 'sdtr_speed[1234]' bits
12765          * are set, then set an 'sdtr_able' bit for it.
12766          */
12767         asc_dvc->sdtr_able = 0;
12768         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
12769                 if (tid == 0) {
12770                         sdtr_speed = asc_dvc->sdtr_speed1;
12771                 } else if (tid == 4) {
12772                         sdtr_speed = asc_dvc->sdtr_speed2;
12773                 } else if (tid == 8) {
12774                         sdtr_speed = asc_dvc->sdtr_speed3;
12775                 } else if (tid == 12) {
12776                         sdtr_speed = asc_dvc->sdtr_speed4;
12777                 }
12778                 if (sdtr_speed & ADV_MAX_TID) {
12779                         asc_dvc->sdtr_able |= (1 << tid);
12780                 }
12781                 sdtr_speed >>= 4;
12782         }
12783
12784         /*
12785          * Set the host maximum queuing (max. 253, min. 16) and the per device
12786          * maximum queuing (max. 63, min. 4).
12787          */
12788         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12789                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12790         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12791                 /* If the value is zero, assume it is uninitialized. */
12792                 if (eep_config.max_host_qng == 0) {
12793                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12794                 } else {
12795                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12796                 }
12797         }
12798
12799         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12800                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12801         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12802                 /* If the value is zero, assume it is uninitialized. */
12803                 if (eep_config.max_dvc_qng == 0) {
12804                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12805                 } else {
12806                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12807                 }
12808         }
12809
12810         /*
12811          * If 'max_dvc_qng' is greater than 'max_host_qng', then
12812          * set 'max_dvc_qng' to 'max_host_qng'.
12813          */
12814         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12815                 eep_config.max_dvc_qng = eep_config.max_host_qng;
12816         }
12817
12818         /*
12819          * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12820          * values based on possibly adjusted EEPROM values.
12821          */
12822         asc_dvc->max_host_qng = eep_config.max_host_qng;
12823         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12824
12825         /*
12826          * If the EEPROM 'termination' field is set to automatic (0), then set
12827          * the ADV_DVC_CFG 'termination' field to automatic also.
12828          *
12829          * If the termination is specified with a non-zero 'termination'
12830          * value check that a legal value is set and set the ADV_DVC_CFG
12831          * 'termination' field appropriately.
12832          */
12833         if (eep_config.termination_se == 0) {
12834                 termination = 0;        /* auto termination for SE */
12835         } else {
12836                 /* Enable manual control with low off / high off. */
12837                 if (eep_config.termination_se == 1) {
12838                         termination = 0;
12839
12840                         /* Enable manual control with low off / high on. */
12841                 } else if (eep_config.termination_se == 2) {
12842                         termination = TERM_SE_HI;
12843
12844                         /* Enable manual control with low on / high on. */
12845                 } else if (eep_config.termination_se == 3) {
12846                         termination = TERM_SE;
12847                 } else {
12848                         /*
12849                          * The EEPROM 'termination_se' field contains a bad value.
12850                          * Use automatic termination instead.
12851                          */
12852                         termination = 0;
12853                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
12854                 }
12855         }
12856
12857         if (eep_config.termination_lvd == 0) {
12858                 asc_dvc->cfg->termination = termination;        /* auto termination for LVD */
12859         } else {
12860                 /* Enable manual control with low off / high off. */
12861                 if (eep_config.termination_lvd == 1) {
12862                         asc_dvc->cfg->termination = termination;
12863
12864                         /* Enable manual control with low off / high on. */
12865                 } else if (eep_config.termination_lvd == 2) {
12866                         asc_dvc->cfg->termination = termination | TERM_LVD_HI;
12867
12868                         /* Enable manual control with low on / high on. */
12869                 } else if (eep_config.termination_lvd == 3) {
12870                         asc_dvc->cfg->termination = termination | TERM_LVD;
12871                 } else {
12872                         /*
12873                          * The EEPROM 'termination_lvd' field contains a bad value.
12874                          * Use automatic termination instead.
12875                          */
12876                         asc_dvc->cfg->termination = termination;
12877                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
12878                 }
12879         }
12880
12881         return warn_code;
12882 }
12883
12884 /*
12885  * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
12886  * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
12887  * all of this is done.
12888  *
12889  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
12890  *
12891  * For a non-fatal error return a warning code. If there are no warnings
12892  * then 0 is returned.
12893  *
12894  * Note: Chip is stopped on entry.
12895  */
12896 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
12897 {
12898         AdvPortAddr iop_base;
12899         ushort warn_code;
12900         ADVEEP_38C1600_CONFIG eep_config;
12901         uchar tid, termination;
12902         ushort sdtr_speed = 0;
12903
12904         iop_base = asc_dvc->iop_base;
12905
12906         warn_code = 0;
12907
12908         /*
12909          * Read the board's EEPROM configuration.
12910          *
12911          * Set default values if a bad checksum is found.
12912          */
12913         if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
12914             eep_config.check_sum) {
12915                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
12916                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12917
12918                 /*
12919                  * Set EEPROM default values.
12920                  */
12921                 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
12922                         sizeof(ADVEEP_38C1600_CONFIG));
12923
12924                 if (PCI_FUNC(pdev->devfn) != 0) {
12925                         u8 ints;
12926                         /*
12927                          * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
12928                          * and old Mac system booting problem. The Expansion
12929                          * ROM must be disabled in Function 1 for these systems
12930                          */
12931                         eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
12932                         /*
12933                          * Clear the INTAB (bit 11) if the GPIO 0 input
12934                          * indicates the Function 1 interrupt line is wired
12935                          * to INTB.
12936                          *
12937                          * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
12938                          *   1 - Function 1 interrupt line wired to INT A.
12939                          *   0 - Function 1 interrupt line wired to INT B.
12940                          *
12941                          * Note: Function 0 is always wired to INTA.
12942                          * Put all 5 GPIO bits in input mode and then read
12943                          * their input values.
12944                          */
12945                         AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
12946                         ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
12947                         if ((ints & 0x01) == 0)
12948                                 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
12949                 }
12950
12951                 /*
12952                  * Assume the 6 byte board serial number that was read from
12953                  * EEPROM is correct even if the EEPROM checksum failed.
12954                  */
12955                 eep_config.serial_number_word3 =
12956                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12957                 eep_config.serial_number_word2 =
12958                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12959                 eep_config.serial_number_word1 =
12960                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12961
12962                 AdvSet38C1600EEPConfig(iop_base, &eep_config);
12963         }
12964
12965         /*
12966          * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12967          * EEPROM configuration that was read.
12968          *
12969          * This is the mapping of EEPROM fields to Adv Library fields.
12970          */
12971         asc_dvc->wdtr_able = eep_config.wdtr_able;
12972         asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
12973         asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
12974         asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
12975         asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
12976         asc_dvc->ppr_able = 0;
12977         asc_dvc->tagqng_able = eep_config.tagqng_able;
12978         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12979         asc_dvc->max_host_qng = eep_config.max_host_qng;
12980         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12981         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
12982         asc_dvc->start_motor = eep_config.start_motor;
12983         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12984         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12985         asc_dvc->no_scam = eep_config.scam_tolerant;
12986
12987         /*
12988          * For every Target ID if any of its 'sdtr_speed[1234]' bits
12989          * are set, then set an 'sdtr_able' bit for it.
12990          */
12991         asc_dvc->sdtr_able = 0;
12992         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
12993                 if (tid == 0) {
12994                         sdtr_speed = asc_dvc->sdtr_speed1;
12995                 } else if (tid == 4) {
12996                         sdtr_speed = asc_dvc->sdtr_speed2;
12997                 } else if (tid == 8) {
12998                         sdtr_speed = asc_dvc->sdtr_speed3;
12999                 } else if (tid == 12) {
13000                         sdtr_speed = asc_dvc->sdtr_speed4;
13001                 }
13002                 if (sdtr_speed & ASC_MAX_TID) {
13003                         asc_dvc->sdtr_able |= (1 << tid);
13004                 }
13005                 sdtr_speed >>= 4;
13006         }
13007
13008         /*
13009          * Set the host maximum queuing (max. 253, min. 16) and the per device
13010          * maximum queuing (max. 63, min. 4).
13011          */
13012         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13013                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13014         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13015                 /* If the value is zero, assume it is uninitialized. */
13016                 if (eep_config.max_host_qng == 0) {
13017                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13018                 } else {
13019                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13020                 }
13021         }
13022
13023         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13024                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13025         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13026                 /* If the value is zero, assume it is uninitialized. */
13027                 if (eep_config.max_dvc_qng == 0) {
13028                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13029                 } else {
13030                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13031                 }
13032         }
13033
13034         /*
13035          * If 'max_dvc_qng' is greater than 'max_host_qng', then
13036          * set 'max_dvc_qng' to 'max_host_qng'.
13037          */
13038         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13039                 eep_config.max_dvc_qng = eep_config.max_host_qng;
13040         }
13041
13042         /*
13043          * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13044          * values based on possibly adjusted EEPROM values.
13045          */
13046         asc_dvc->max_host_qng = eep_config.max_host_qng;
13047         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13048
13049         /*
13050          * If the EEPROM 'termination' field is set to automatic (0), then set
13051          * the ASC_DVC_CFG 'termination' field to automatic also.
13052          *
13053          * If the termination is specified with a non-zero 'termination'
13054          * value check that a legal value is set and set the ASC_DVC_CFG
13055          * 'termination' field appropriately.
13056          */
13057         if (eep_config.termination_se == 0) {
13058                 termination = 0;        /* auto termination for SE */
13059         } else {
13060                 /* Enable manual control with low off / high off. */
13061                 if (eep_config.termination_se == 1) {
13062                         termination = 0;
13063
13064                         /* Enable manual control with low off / high on. */
13065                 } else if (eep_config.termination_se == 2) {
13066                         termination = TERM_SE_HI;
13067
13068                         /* Enable manual control with low on / high on. */
13069                 } else if (eep_config.termination_se == 3) {
13070                         termination = TERM_SE;
13071                 } else {
13072                         /*
13073                          * The EEPROM 'termination_se' field contains a bad value.
13074                          * Use automatic termination instead.
13075                          */
13076                         termination = 0;
13077                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
13078                 }
13079         }
13080
13081         if (eep_config.termination_lvd == 0) {
13082                 asc_dvc->cfg->termination = termination;        /* auto termination for LVD */
13083         } else {
13084                 /* Enable manual control with low off / high off. */
13085                 if (eep_config.termination_lvd == 1) {
13086                         asc_dvc->cfg->termination = termination;
13087
13088                         /* Enable manual control with low off / high on. */
13089                 } else if (eep_config.termination_lvd == 2) {
13090                         asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13091
13092                         /* Enable manual control with low on / high on. */
13093                 } else if (eep_config.termination_lvd == 3) {
13094                         asc_dvc->cfg->termination = termination | TERM_LVD;
13095                 } else {
13096                         /*
13097                          * The EEPROM 'termination_lvd' field contains a bad value.
13098                          * Use automatic termination instead.
13099                          */
13100                         asc_dvc->cfg->termination = termination;
13101                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
13102                 }
13103         }
13104
13105         return warn_code;
13106 }
13107
13108 /*
13109  * Initialize the ADV_DVC_VAR structure.
13110  *
13111  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13112  *
13113  * For a non-fatal error return a warning code. If there are no warnings
13114  * then 0 is returned.
13115  */
13116 static int __devinit
13117 AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
13118 {
13119         struct asc_board *board = shost_priv(shost);
13120         ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
13121         unsigned short warn_code = 0;
13122         AdvPortAddr iop_base = asc_dvc->iop_base;
13123         u16 cmd;
13124         int status;
13125
13126         asc_dvc->err_code = 0;
13127
13128         /*
13129          * Save the state of the PCI Configuration Command Register
13130          * "Parity Error Response Control" Bit. If the bit is clear (0),
13131          * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13132          * DMA parity errors.
13133          */
13134         asc_dvc->cfg->control_flag = 0;
13135         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13136         if ((cmd & PCI_COMMAND_PARITY) == 0)
13137                 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13138
13139         asc_dvc->cfg->chip_version =
13140             AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13141
13142         ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
13143                  (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13144                  (ushort)ADV_CHIP_ID_BYTE);
13145
13146         ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
13147                  (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13148                  (ushort)ADV_CHIP_ID_WORD);
13149
13150         /*
13151          * Reset the chip to start and allow register writes.
13152          */
13153         if (AdvFindSignature(iop_base) == 0) {
13154                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13155                 return ADV_ERROR;
13156         } else {
13157                 /*
13158                  * The caller must set 'chip_type' to a valid setting.
13159                  */
13160                 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13161                     asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13162                     asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13163                         asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13164                         return ADV_ERROR;
13165                 }
13166
13167                 /*
13168                  * Reset Chip.
13169                  */
13170                 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13171                                      ADV_CTRL_REG_CMD_RESET);
13172                 mdelay(100);
13173                 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13174                                      ADV_CTRL_REG_CMD_WR_IO_REG);
13175
13176                 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13177                         status = AdvInitFrom38C1600EEP(asc_dvc);
13178                 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13179                         status = AdvInitFrom38C0800EEP(asc_dvc);
13180                 } else {
13181                         status = AdvInitFrom3550EEP(asc_dvc);
13182                 }
13183                 warn_code |= status;
13184         }
13185
13186         if (warn_code != 0)
13187                 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
13188
13189         if (asc_dvc->err_code)
13190                 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
13191                                 asc_dvc->err_code);
13192
13193         return asc_dvc->err_code;
13194 }
13195 #endif
13196
13197 static struct scsi_host_template advansys_template = {
13198         .proc_name = DRV_NAME,
13199 #ifdef CONFIG_PROC_FS
13200         .proc_info = advansys_proc_info,
13201 #endif
13202         .name = DRV_NAME,
13203         .info = advansys_info,
13204         .queuecommand = advansys_queuecommand,
13205         .eh_bus_reset_handler = advansys_reset,
13206         .bios_param = advansys_biosparam,
13207         .slave_configure = advansys_slave_configure,
13208         /*
13209          * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13210          * must be set. The flag will be cleared in advansys_board_found
13211          * for non-ISA adapters.
13212          */
13213         .unchecked_isa_dma = 1,
13214         /*
13215          * All adapters controlled by this driver are capable of large
13216          * scatter-gather lists. According to the mid-level SCSI documentation
13217          * this obviates any performance gain provided by setting
13218          * 'use_clustering'. But empirically while CPU utilization is increased
13219          * by enabling clustering, I/O throughput increases as well.
13220          */
13221         .use_clustering = ENABLE_CLUSTERING,
13222 };
13223
13224 static int __devinit advansys_wide_init_chip(struct Scsi_Host *shost)
13225 {
13226         struct asc_board *board = shost_priv(shost);
13227         struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13228         int req_cnt = 0;
13229         adv_req_t *reqp = NULL;
13230         int sg_cnt = 0;
13231         adv_sgblk_t *sgp;
13232         int warn_code, err_code;
13233
13234         /*
13235          * Allocate buffer carrier structures. The total size
13236          * is about 4 KB, so allocate all at once.
13237          */
13238         adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13239         ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
13240
13241         if (!adv_dvc->carrier_buf)
13242                 goto kmalloc_failed;
13243
13244         /*
13245          * Allocate up to 'max_host_qng' request structures for the Wide
13246          * board. The total size is about 16 KB, so allocate all at once.
13247          * If the allocation fails decrement and try again.
13248          */
13249         for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
13250                 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13251
13252                 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
13253                          (ulong)sizeof(adv_req_t) * req_cnt);
13254
13255                 if (reqp)
13256                         break;
13257         }
13258
13259         if (!reqp)
13260                 goto kmalloc_failed;
13261
13262         adv_dvc->orig_reqp = reqp;
13263
13264         /*
13265          * Allocate up to ADV_TOT_SG_BLOCK request structures for
13266          * the Wide board. Each structure is about 136 bytes.
13267          */
13268         board->adv_sgblkp = NULL;
13269         for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13270                 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13271
13272                 if (!sgp)
13273                         break;
13274
13275                 sgp->next_sgblkp = board->adv_sgblkp;
13276                 board->adv_sgblkp = sgp;
13277
13278         }
13279
13280         ASC_DBG(1, "sg_cnt %d * %u = %u bytes\n", sg_cnt, sizeof(adv_sgblk_t),
13281                  (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13282
13283         if (!board->adv_sgblkp)
13284                 goto kmalloc_failed;
13285
13286         /*
13287          * Point 'adv_reqp' to the request structures and
13288          * link them together.
13289          */
13290         req_cnt--;
13291         reqp[req_cnt].next_reqp = NULL;
13292         for (; req_cnt > 0; req_cnt--) {
13293                 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13294         }
13295         board->adv_reqp = &reqp[0];
13296
13297         if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
13298                 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
13299                 warn_code = AdvInitAsc3550Driver(adv_dvc);
13300         } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13301                 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
13302                 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
13303         } else {
13304                 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
13305                 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
13306         }
13307         err_code = adv_dvc->err_code;
13308
13309         if (warn_code || err_code) {
13310                 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
13311                         "0x%x\n", warn_code, err_code);
13312         }
13313
13314         goto exit;
13315
13316  kmalloc_failed:
13317         shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
13318         err_code = ADV_ERROR;
13319  exit:
13320         return err_code;
13321 }
13322
13323 static void advansys_wide_free_mem(struct asc_board *board)
13324 {
13325         struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13326         kfree(adv_dvc->carrier_buf);
13327         adv_dvc->carrier_buf = NULL;
13328         kfree(adv_dvc->orig_reqp);
13329         adv_dvc->orig_reqp = board->adv_reqp = NULL;
13330         while (board->adv_sgblkp) {
13331                 adv_sgblk_t *sgp = board->adv_sgblkp;
13332                 board->adv_sgblkp = sgp->next_sgblkp;
13333                 kfree(sgp);
13334         }
13335 }
13336
13337 static int __devinit advansys_board_found(struct Scsi_Host *shost,
13338                                           unsigned int iop, int bus_type)
13339 {
13340         struct pci_dev *pdev;
13341         struct asc_board *boardp = shost_priv(shost);
13342         ASC_DVC_VAR *asc_dvc_varp = NULL;
13343         ADV_DVC_VAR *adv_dvc_varp = NULL;
13344         int share_irq, warn_code, ret;
13345
13346         pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
13347
13348         if (ASC_NARROW_BOARD(boardp)) {
13349                 ASC_DBG(1, "narrow board\n");
13350                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13351                 asc_dvc_varp->bus_type = bus_type;
13352                 asc_dvc_varp->drv_ptr = boardp;
13353                 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13354                 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13355                 asc_dvc_varp->iop_base = iop;
13356         } else {
13357 #ifdef CONFIG_PCI
13358                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13359                 adv_dvc_varp->drv_ptr = boardp;
13360                 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13361                 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13362                         ASC_DBG(1, "wide board ASC-3550\n");
13363                         adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13364                 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13365                         ASC_DBG(1, "wide board ASC-38C0800\n");
13366                         adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13367                 } else {
13368                         ASC_DBG(1, "wide board ASC-38C1600\n");
13369                         adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13370                 }
13371
13372                 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13373                 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13374                                                boardp->asc_n_io_port);
13375                 if (!boardp->ioremap_addr) {
13376                         shost_printk(KERN_ERR, shost, "ioremap(%x, %d) "
13377                                         "returned NULL\n",
13378                                         pci_resource_start(pdev, 1),
13379                                         boardp->asc_n_io_port);
13380                         ret = -ENODEV;
13381                         goto err_shost;
13382                 }
13383                 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
13384                 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
13385
13386                 /*
13387                  * Even though it isn't used to access wide boards, other
13388                  * than for the debug line below, save I/O Port address so
13389                  * that it can be reported.
13390                  */
13391                 boardp->ioport = iop;
13392
13393                 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
13394                                 (ushort)inp(iop + 1), (ushort)inpw(iop));
13395 #endif /* CONFIG_PCI */
13396         }
13397
13398 #ifdef CONFIG_PROC_FS
13399         /*
13400          * Allocate buffer for printing information from
13401          * /proc/scsi/advansys/[0...].
13402          */
13403         boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13404         if (!boardp->prtbuf) {
13405                 shost_printk(KERN_ERR, shost, "kmalloc(%d) returned NULL\n",
13406                                 ASC_PRTBUF_SIZE);
13407                 ret = -ENOMEM;
13408                 goto err_unmap;
13409         }
13410 #endif /* CONFIG_PROC_FS */
13411
13412         if (ASC_NARROW_BOARD(boardp)) {
13413                 /*
13414                  * Set the board bus type and PCI IRQ before
13415                  * calling AscInitGetConfig().
13416                  */
13417                 switch (asc_dvc_varp->bus_type) {
13418 #ifdef CONFIG_ISA
13419                 case ASC_IS_ISA:
13420                         shost->unchecked_isa_dma = TRUE;
13421                         share_irq = 0;
13422                         break;
13423                 case ASC_IS_VL:
13424                         shost->unchecked_isa_dma = FALSE;
13425                         share_irq = 0;
13426                         break;
13427                 case ASC_IS_EISA:
13428                         shost->unchecked_isa_dma = FALSE;
13429                         share_irq = IRQF_SHARED;
13430                         break;
13431 #endif /* CONFIG_ISA */
13432 #ifdef CONFIG_PCI
13433                 case ASC_IS_PCI:
13434                         shost->unchecked_isa_dma = FALSE;
13435                         share_irq = IRQF_SHARED;
13436                         break;
13437 #endif /* CONFIG_PCI */
13438                 default:
13439                         shost_printk(KERN_ERR, shost, "unknown adapter type: "
13440                                         "%d\n", asc_dvc_varp->bus_type);
13441                         shost->unchecked_isa_dma = TRUE;
13442                         share_irq = 0;
13443                         break;
13444                 }
13445
13446                 /*
13447                  * NOTE: AscInitGetConfig() may change the board's
13448                  * bus_type value. The bus_type value should no
13449                  * longer be used. If the bus_type field must be
13450                  * referenced only use the bit-wise AND operator "&".
13451                  */
13452                 ASC_DBG(2, "AscInitGetConfig()\n");
13453                 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
13454         } else {
13455 #ifdef CONFIG_PCI
13456                 /*
13457                  * For Wide boards set PCI information before calling
13458                  * AdvInitGetConfig().
13459                  */
13460                 shost->unchecked_isa_dma = FALSE;
13461                 share_irq = IRQF_SHARED;
13462                 ASC_DBG(2, "AdvInitGetConfig()\n");
13463
13464                 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
13465 #endif /* CONFIG_PCI */
13466         }
13467
13468         if (ret)
13469                 goto err_free_proc;
13470
13471         /*
13472          * Save the EEPROM configuration so that it can be displayed
13473          * from /proc/scsi/advansys/[0...].
13474          */
13475         if (ASC_NARROW_BOARD(boardp)) {
13476
13477                 ASCEEP_CONFIG *ep;
13478
13479                 /*
13480                  * Set the adapter's target id bit in the 'init_tidmask' field.
13481                  */
13482                 boardp->init_tidmask |=
13483                     ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
13484
13485                 /*
13486                  * Save EEPROM settings for the board.
13487                  */
13488                 ep = &boardp->eep_config.asc_eep;
13489
13490                 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
13491                 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
13492                 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
13493                 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
13494                 ep->start_motor = asc_dvc_varp->start_motor;
13495                 ep->cntl = asc_dvc_varp->dvc_cntl;
13496                 ep->no_scam = asc_dvc_varp->no_scam;
13497                 ep->max_total_qng = asc_dvc_varp->max_total_qng;
13498                 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
13499                 /* 'max_tag_qng' is set to the same value for every device. */
13500                 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
13501                 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
13502                 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
13503                 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
13504                 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
13505                 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
13506                 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
13507
13508                 /*
13509                  * Modify board configuration.
13510                  */
13511                 ASC_DBG(2, "AscInitSetConfig()\n");
13512                 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
13513                 if (ret)
13514                         goto err_free_proc;
13515         } else {
13516                 ADVEEP_3550_CONFIG *ep_3550;
13517                 ADVEEP_38C0800_CONFIG *ep_38C0800;
13518                 ADVEEP_38C1600_CONFIG *ep_38C1600;
13519
13520                 /*
13521                  * Save Wide EEP Configuration Information.
13522                  */
13523                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13524                         ep_3550 = &boardp->eep_config.adv_3550_eep;
13525
13526                         ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
13527                         ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
13528                         ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13529                         ep_3550->termination = adv_dvc_varp->cfg->termination;
13530                         ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
13531                         ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
13532                         ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
13533                         ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
13534                         ep_3550->ultra_able = adv_dvc_varp->ultra_able;
13535                         ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
13536                         ep_3550->start_motor = adv_dvc_varp->start_motor;
13537                         ep_3550->scsi_reset_delay =
13538                             adv_dvc_varp->scsi_reset_wait;
13539                         ep_3550->serial_number_word1 =
13540                             adv_dvc_varp->cfg->serial1;
13541                         ep_3550->serial_number_word2 =
13542                             adv_dvc_varp->cfg->serial2;
13543                         ep_3550->serial_number_word3 =
13544                             adv_dvc_varp->cfg->serial3;
13545                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13546                         ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
13547
13548                         ep_38C0800->adapter_scsi_id =
13549                             adv_dvc_varp->chip_scsi_id;
13550                         ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
13551                         ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13552                         ep_38C0800->termination_lvd =
13553                             adv_dvc_varp->cfg->termination;
13554                         ep_38C0800->disc_enable =
13555                             adv_dvc_varp->cfg->disc_enable;
13556                         ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
13557                         ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
13558                         ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13559                         ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13560                         ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13561                         ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13562                         ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13563                         ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13564                         ep_38C0800->start_motor = adv_dvc_varp->start_motor;
13565                         ep_38C0800->scsi_reset_delay =
13566                             adv_dvc_varp->scsi_reset_wait;
13567                         ep_38C0800->serial_number_word1 =
13568                             adv_dvc_varp->cfg->serial1;
13569                         ep_38C0800->serial_number_word2 =
13570                             adv_dvc_varp->cfg->serial2;
13571                         ep_38C0800->serial_number_word3 =
13572                             adv_dvc_varp->cfg->serial3;
13573                 } else {
13574                         ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
13575
13576                         ep_38C1600->adapter_scsi_id =
13577                             adv_dvc_varp->chip_scsi_id;
13578                         ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
13579                         ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13580                         ep_38C1600->termination_lvd =
13581                             adv_dvc_varp->cfg->termination;
13582                         ep_38C1600->disc_enable =
13583                             adv_dvc_varp->cfg->disc_enable;
13584                         ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
13585                         ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
13586                         ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13587                         ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13588                         ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13589                         ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13590                         ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13591                         ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13592                         ep_38C1600->start_motor = adv_dvc_varp->start_motor;
13593                         ep_38C1600->scsi_reset_delay =
13594                             adv_dvc_varp->scsi_reset_wait;
13595                         ep_38C1600->serial_number_word1 =
13596                             adv_dvc_varp->cfg->serial1;
13597                         ep_38C1600->serial_number_word2 =
13598                             adv_dvc_varp->cfg->serial2;
13599                         ep_38C1600->serial_number_word3 =
13600                             adv_dvc_varp->cfg->serial3;
13601                 }
13602
13603                 /*
13604                  * Set the adapter's target id bit in the 'init_tidmask' field.
13605                  */
13606                 boardp->init_tidmask |=
13607                     ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
13608         }
13609
13610         /*
13611          * Channels are numbered beginning with 0. For AdvanSys one host
13612          * structure supports one channel. Multi-channel boards have a
13613          * separate host structure for each channel.
13614          */
13615         shost->max_channel = 0;
13616         if (ASC_NARROW_BOARD(boardp)) {
13617                 shost->max_id = ASC_MAX_TID + 1;
13618                 shost->max_lun = ASC_MAX_LUN + 1;
13619                 shost->max_cmd_len = ASC_MAX_CDB_LEN;
13620
13621                 shost->io_port = asc_dvc_varp->iop_base;
13622                 boardp->asc_n_io_port = ASC_IOADR_GAP;
13623                 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
13624
13625                 /* Set maximum number of queues the adapter can handle. */
13626                 shost->can_queue = asc_dvc_varp->max_total_qng;
13627         } else {
13628                 shost->max_id = ADV_MAX_TID + 1;
13629                 shost->max_lun = ADV_MAX_LUN + 1;
13630                 shost->max_cmd_len = ADV_MAX_CDB_LEN;
13631
13632                 /*
13633                  * Save the I/O Port address and length even though
13634                  * I/O ports are not used to access Wide boards.
13635                  * Instead the Wide boards are accessed with
13636                  * PCI Memory Mapped I/O.
13637                  */
13638                 shost->io_port = iop;
13639
13640                 shost->this_id = adv_dvc_varp->chip_scsi_id;
13641
13642                 /* Set maximum number of queues the adapter can handle. */
13643                 shost->can_queue = adv_dvc_varp->max_host_qng;
13644         }
13645
13646         /*
13647          * Following v1.3.89, 'cmd_per_lun' is no longer needed
13648          * and should be set to zero.
13649          *
13650          * But because of a bug introduced in v1.3.89 if the driver is
13651          * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
13652          * SCSI function 'allocate_device' will panic. To allow the driver
13653          * to work as a module in these kernels set 'cmd_per_lun' to 1.
13654          *
13655          * Note: This is wrong.  cmd_per_lun should be set to the depth
13656          * you want on untagged devices always.
13657          #ifdef MODULE
13658          */
13659         shost->cmd_per_lun = 1;
13660 /* #else
13661             shost->cmd_per_lun = 0;
13662 #endif */
13663
13664         /*
13665          * Set the maximum number of scatter-gather elements the
13666          * adapter can handle.
13667          */
13668         if (ASC_NARROW_BOARD(boardp)) {
13669                 /*
13670                  * Allow two commands with 'sg_tablesize' scatter-gather
13671                  * elements to be executed simultaneously. This value is
13672                  * the theoretical hardware limit. It may be decreased
13673                  * below.
13674                  */
13675                 shost->sg_tablesize =
13676                     (((asc_dvc_varp->max_total_qng - 2) / 2) *
13677                      ASC_SG_LIST_PER_Q) + 1;
13678         } else {
13679                 shost->sg_tablesize = ADV_MAX_SG_LIST;
13680         }
13681
13682         /*
13683          * The value of 'sg_tablesize' can not exceed the SCSI
13684          * mid-level driver definition of SG_ALL. SG_ALL also
13685          * must not be exceeded, because it is used to define the
13686          * size of the scatter-gather table in 'struct asc_sg_head'.
13687          */
13688         if (shost->sg_tablesize > SG_ALL) {
13689                 shost->sg_tablesize = SG_ALL;
13690         }
13691
13692         ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
13693
13694         /* BIOS start address. */
13695         if (ASC_NARROW_BOARD(boardp)) {
13696                 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
13697                                                     asc_dvc_varp->bus_type);
13698         } else {
13699                 /*
13700                  * Fill-in BIOS board variables. The Wide BIOS saves
13701                  * information in LRAM that is used by the driver.
13702                  */
13703                 AdvReadWordLram(adv_dvc_varp->iop_base,
13704                                 BIOS_SIGNATURE, boardp->bios_signature);
13705                 AdvReadWordLram(adv_dvc_varp->iop_base,
13706                                 BIOS_VERSION, boardp->bios_version);
13707                 AdvReadWordLram(adv_dvc_varp->iop_base,
13708                                 BIOS_CODESEG, boardp->bios_codeseg);
13709                 AdvReadWordLram(adv_dvc_varp->iop_base,
13710                                 BIOS_CODELEN, boardp->bios_codelen);
13711
13712                 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
13713                          boardp->bios_signature, boardp->bios_version);
13714
13715                 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
13716                          boardp->bios_codeseg, boardp->bios_codelen);
13717
13718                 /*
13719                  * If the BIOS saved a valid signature, then fill in
13720                  * the BIOS code segment base address.
13721                  */
13722                 if (boardp->bios_signature == 0x55AA) {
13723                         /*
13724                          * Convert x86 realmode code segment to a linear
13725                          * address by shifting left 4.
13726                          */
13727                         shost->base = ((ulong)boardp->bios_codeseg << 4);
13728                 } else {
13729                         shost->base = 0;
13730                 }
13731         }
13732
13733         /*
13734          * Register Board Resources - I/O Port, DMA, IRQ
13735          */
13736
13737         /* Register DMA Channel for Narrow boards. */
13738         shost->dma_channel = NO_ISA_DMA;        /* Default to no ISA DMA. */
13739 #ifdef CONFIG_ISA
13740         if (ASC_NARROW_BOARD(boardp)) {
13741                 /* Register DMA channel for ISA bus. */
13742                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
13743                         shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
13744                         ret = request_dma(shost->dma_channel, DRV_NAME);
13745                         if (ret) {
13746                                 shost_printk(KERN_ERR, shost, "request_dma() "
13747                                                 "%d failed %d\n",
13748                                                 shost->dma_channel, ret);
13749                                 goto err_free_proc;
13750                         }
13751                         AscEnableIsaDma(shost->dma_channel);
13752                 }
13753         }
13754 #endif /* CONFIG_ISA */
13755
13756         /* Register IRQ Number. */
13757         ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
13758
13759         ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
13760                           DRV_NAME, shost);
13761
13762         if (ret) {
13763                 if (ret == -EBUSY) {
13764                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13765                                         "already in use\n", boardp->irq);
13766                 } else if (ret == -EINVAL) {
13767                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13768                                         "not valid\n", boardp->irq);
13769                 } else {
13770                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13771                                         "failed with %d\n", boardp->irq, ret);
13772                 }
13773                 goto err_free_dma;
13774         }
13775
13776         /*
13777          * Initialize board RISC chip and enable interrupts.
13778          */
13779         if (ASC_NARROW_BOARD(boardp)) {
13780                 ASC_DBG(2, "AscInitAsc1000Driver()\n");
13781                 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
13782
13783                 if (warn_code || asc_dvc_varp->err_code) {
13784                         shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
13785                                         "warn 0x%x, error 0x%x\n",
13786                                         asc_dvc_varp->init_state, warn_code,
13787                                         asc_dvc_varp->err_code);
13788                         if (asc_dvc_varp->err_code)
13789                                 ret = -ENODEV;
13790                 }
13791         } else {
13792                 if (advansys_wide_init_chip(shost))
13793                         ret = -ENODEV;
13794         }
13795
13796         if (ret)
13797                 goto err_free_wide_mem;
13798
13799         ASC_DBG_PRT_SCSI_HOST(2, shost);
13800
13801         ret = scsi_add_host(shost, boardp->dev);
13802         if (ret)
13803                 goto err_free_wide_mem;
13804
13805         scsi_scan_host(shost);
13806         return 0;
13807
13808  err_free_wide_mem:
13809         advansys_wide_free_mem(boardp);
13810         free_irq(boardp->irq, shost);
13811  err_free_dma:
13812         if (shost->dma_channel != NO_ISA_DMA)
13813                 free_dma(shost->dma_channel);
13814  err_free_proc:
13815         kfree(boardp->prtbuf);
13816  err_unmap:
13817         if (boardp->ioremap_addr)
13818                 iounmap(boardp->ioremap_addr);
13819  err_shost:
13820         return ret;
13821 }
13822
13823 /*
13824  * advansys_release()
13825  *
13826  * Release resources allocated for a single AdvanSys adapter.
13827  */
13828 static int advansys_release(struct Scsi_Host *shost)
13829 {
13830         struct asc_board *boardp = shost_priv(shost);
13831         ASC_DBG(1, "begin\n");
13832         scsi_remove_host(shost);
13833         free_irq(boardp->irq, shost);
13834         if (shost->dma_channel != NO_ISA_DMA) {
13835                 ASC_DBG(1, "free_dma()\n");
13836                 free_dma(shost->dma_channel);
13837         }
13838         if (!ASC_NARROW_BOARD(boardp)) {
13839                 iounmap(boardp->ioremap_addr);
13840                 advansys_wide_free_mem(boardp);
13841         }
13842         kfree(boardp->prtbuf);
13843         scsi_host_put(shost);
13844         ASC_DBG(1, "end\n");
13845         return 0;
13846 }
13847
13848 #define ASC_IOADR_TABLE_MAX_IX  11
13849
13850 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
13851         0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
13852         0x0210, 0x0230, 0x0250, 0x0330
13853 };
13854
13855 /*
13856  * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw.  It decodes as:
13857  * 00: 10
13858  * 01: 11
13859  * 10: 12
13860  * 11: 15
13861  */
13862 static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
13863 {
13864         unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
13865         unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
13866         if (chip_irq == 13)
13867                 chip_irq = 15;
13868         return chip_irq;
13869 }
13870
13871 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
13872 {
13873         int err = -ENODEV;
13874         PortAddr iop_base = _asc_def_iop_base[id];
13875         struct Scsi_Host *shost;
13876         struct asc_board *board;
13877
13878         if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
13879                 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
13880                 return -ENODEV;
13881         }
13882         ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
13883         if (!AscFindSignature(iop_base))
13884                 goto release_region;
13885         if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
13886                 goto release_region;
13887
13888         err = -ENOMEM;
13889         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
13890         if (!shost)
13891                 goto release_region;
13892
13893         board = shost_priv(shost);
13894         board->irq = advansys_isa_irq_no(iop_base);
13895         board->dev = dev;
13896
13897         err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
13898         if (err)
13899                 goto free_host;
13900
13901         dev_set_drvdata(dev, shost);
13902         return 0;
13903
13904  free_host:
13905         scsi_host_put(shost);
13906  release_region:
13907         release_region(iop_base, ASC_IOADR_GAP);
13908         return err;
13909 }
13910
13911 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
13912 {
13913         int ioport = _asc_def_iop_base[id];
13914         advansys_release(dev_get_drvdata(dev));
13915         release_region(ioport, ASC_IOADR_GAP);
13916         return 0;
13917 }
13918
13919 static struct isa_driver advansys_isa_driver = {
13920         .probe          = advansys_isa_probe,
13921         .remove         = __devexit_p(advansys_isa_remove),
13922         .driver = {
13923                 .owner  = THIS_MODULE,
13924                 .name   = DRV_NAME,
13925         },
13926 };
13927
13928 /*
13929  * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw.  It decodes as:
13930  * 000: invalid
13931  * 001: 10
13932  * 010: 11
13933  * 011: 12
13934  * 100: invalid
13935  * 101: 14
13936  * 110: 15
13937  * 111: invalid
13938  */
13939 static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
13940 {
13941         unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
13942         unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
13943         if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
13944                 return 0;
13945         return chip_irq;
13946 }
13947
13948 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
13949 {
13950         int err = -ENODEV;
13951         PortAddr iop_base = _asc_def_iop_base[id];
13952         struct Scsi_Host *shost;
13953         struct asc_board *board;
13954
13955         if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
13956                 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
13957                 return -ENODEV;
13958         }
13959         ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
13960         if (!AscFindSignature(iop_base))
13961                 goto release_region;
13962         /*
13963          * I don't think this condition can actually happen, but the old
13964          * driver did it, and the chances of finding a VLB setup in 2007
13965          * to do testing with is slight to none.
13966          */
13967         if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
13968                 goto release_region;
13969
13970         err = -ENOMEM;
13971         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
13972         if (!shost)
13973                 goto release_region;
13974
13975         board = shost_priv(shost);
13976         board->irq = advansys_vlb_irq_no(iop_base);
13977         board->dev = dev;
13978
13979         err = advansys_board_found(shost, iop_base, ASC_IS_VL);
13980         if (err)
13981                 goto free_host;
13982
13983         dev_set_drvdata(dev, shost);
13984         return 0;
13985
13986  free_host:
13987         scsi_host_put(shost);
13988  release_region:
13989         release_region(iop_base, ASC_IOADR_GAP);
13990         return -ENODEV;
13991 }
13992
13993 static struct isa_driver advansys_vlb_driver = {
13994         .probe          = advansys_vlb_probe,
13995         .remove         = __devexit_p(advansys_isa_remove),
13996         .driver = {
13997                 .owner  = THIS_MODULE,
13998                 .name   = "advansys_vlb",
13999         },
14000 };
14001
14002 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14003         { "ABP7401" },
14004         { "ABP7501" },
14005         { "" }
14006 };
14007
14008 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14009
14010 /*
14011  * EISA is a little more tricky than PCI; each EISA device may have two
14012  * channels, and this driver is written to make each channel its own Scsi_Host
14013  */
14014 struct eisa_scsi_data {
14015         struct Scsi_Host *host[2];
14016 };
14017
14018 /*
14019  * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw.  It decodes as:
14020  * 000: 10
14021  * 001: 11
14022  * 010: 12
14023  * 011: invalid
14024  * 100: 14
14025  * 101: 15
14026  * 110: invalid
14027  * 111: invalid
14028  */
14029 static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
14030 {
14031         unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
14032         unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
14033         if ((chip_irq == 13) || (chip_irq > 15))
14034                 return 0;
14035         return chip_irq;
14036 }
14037
14038 static int __devinit advansys_eisa_probe(struct device *dev)
14039 {
14040         int i, ioport, irq = 0;
14041         int err;
14042         struct eisa_device *edev = to_eisa_device(dev);
14043         struct eisa_scsi_data *data;
14044
14045         err = -ENOMEM;
14046         data = kzalloc(sizeof(*data), GFP_KERNEL);
14047         if (!data)
14048                 goto fail;
14049         ioport = edev->base_addr + 0xc30;
14050
14051         err = -ENODEV;
14052         for (i = 0; i < 2; i++, ioport += 0x20) {
14053                 struct asc_board *board;
14054                 struct Scsi_Host *shost;
14055                 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14056                         printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14057                                ioport + ASC_IOADR_GAP - 1);
14058                         continue;
14059                 }
14060                 if (!AscFindSignature(ioport)) {
14061                         release_region(ioport, ASC_IOADR_GAP);
14062                         continue;
14063                 }
14064
14065                 /*
14066                  * I don't know why we need to do this for EISA chips, but
14067                  * not for any others.  It looks to be equivalent to
14068                  * AscGetChipCfgMsw, but I may have overlooked something,
14069                  * so I'm not converting it until I get an EISA board to
14070                  * test with.
14071                  */
14072                 inw(ioport + 4);
14073
14074                 if (!irq)
14075                         irq = advansys_eisa_irq_no(edev);
14076
14077                 err = -ENOMEM;
14078                 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14079                 if (!shost)
14080                         goto release_region;
14081
14082                 board = shost_priv(shost);
14083                 board->irq = irq;
14084                 board->dev = dev;
14085
14086                 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
14087                 if (!err) {
14088                         data->host[i] = shost;
14089                         continue;
14090                 }
14091
14092                 scsi_host_put(shost);
14093  release_region:
14094                 release_region(ioport, ASC_IOADR_GAP);
14095                 break;
14096         }
14097
14098         if (err)
14099                 goto free_data;
14100         dev_set_drvdata(dev, data);
14101         return 0;
14102
14103  free_data:
14104         kfree(data->host[0]);
14105         kfree(data->host[1]);
14106         kfree(data);
14107  fail:
14108         return err;
14109 }
14110
14111 static __devexit int advansys_eisa_remove(struct device *dev)
14112 {
14113         int i;
14114         struct eisa_scsi_data *data = dev_get_drvdata(dev);
14115
14116         for (i = 0; i < 2; i++) {
14117                 int ioport;
14118                 struct Scsi_Host *shost = data->host[i];
14119                 if (!shost)
14120                         continue;
14121                 ioport = shost->io_port;
14122                 advansys_release(shost);
14123                 release_region(ioport, ASC_IOADR_GAP);
14124         }
14125
14126         kfree(data);
14127         return 0;
14128 }
14129
14130 static struct eisa_driver advansys_eisa_driver = {
14131         .id_table =             advansys_eisa_table,
14132         .driver = {
14133                 .name =         DRV_NAME,
14134                 .probe =        advansys_eisa_probe,
14135                 .remove =       __devexit_p(advansys_eisa_remove),
14136         }
14137 };
14138
14139 /* PCI Devices supported by this driver */
14140 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14141         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14142          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14143         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14144          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14145         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14146          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14147         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14148          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14149         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14150          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14151         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14152          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14153         {}
14154 };
14155
14156 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14157
14158 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14159 {
14160         if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14161             (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14162                 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14163         } else {
14164                 u8 latency;
14165                 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14166                 if (latency < 0x20)
14167                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14168         }
14169 }
14170
14171 static int __devinit
14172 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14173 {
14174         int err, ioport;
14175         struct Scsi_Host *shost;
14176         struct asc_board *board;
14177
14178         err = pci_enable_device(pdev);
14179         if (err)
14180                 goto fail;
14181         err = pci_request_regions(pdev, DRV_NAME);
14182         if (err)
14183                 goto disable_device;
14184         pci_set_master(pdev);
14185         advansys_set_latency(pdev);
14186
14187         err = -ENODEV;
14188         if (pci_resource_len(pdev, 0) == 0)
14189                 goto release_region;
14190
14191         ioport = pci_resource_start(pdev, 0);
14192
14193         err = -ENOMEM;
14194         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14195         if (!shost)
14196                 goto release_region;
14197
14198         board = shost_priv(shost);
14199         board->irq = pdev->irq;
14200         board->dev = &pdev->dev;
14201
14202         if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14203             pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14204             pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
14205                 board->flags |= ASC_IS_WIDE_BOARD;
14206         }
14207
14208         err = advansys_board_found(shost, ioport, ASC_IS_PCI);
14209         if (err)
14210                 goto free_host;
14211
14212         pci_set_drvdata(pdev, shost);
14213         return 0;
14214
14215  free_host:
14216         scsi_host_put(shost);
14217  release_region:
14218         pci_release_regions(pdev);
14219  disable_device:
14220         pci_disable_device(pdev);
14221  fail:
14222         return err;
14223 }
14224
14225 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14226 {
14227         advansys_release(pci_get_drvdata(pdev));
14228         pci_release_regions(pdev);
14229         pci_disable_device(pdev);
14230 }
14231
14232 static struct pci_driver advansys_pci_driver = {
14233         .name =         DRV_NAME,
14234         .id_table =     advansys_pci_tbl,
14235         .probe =        advansys_pci_probe,
14236         .remove =       __devexit_p(advansys_pci_remove),
14237 };
14238
14239 static int __init advansys_init(void)
14240 {
14241         int error;
14242
14243         error = isa_register_driver(&advansys_isa_driver,
14244                                     ASC_IOADR_TABLE_MAX_IX);
14245         if (error)
14246                 goto fail;
14247
14248         error = isa_register_driver(&advansys_vlb_driver,
14249                                     ASC_IOADR_TABLE_MAX_IX);
14250         if (error)
14251                 goto unregister_isa;
14252
14253         error = eisa_driver_register(&advansys_eisa_driver);
14254         if (error)
14255                 goto unregister_vlb;
14256
14257         error = pci_register_driver(&advansys_pci_driver);
14258         if (error)
14259                 goto unregister_eisa;
14260
14261         return 0;
14262
14263  unregister_eisa:
14264         eisa_driver_unregister(&advansys_eisa_driver);
14265  unregister_vlb:
14266         isa_unregister_driver(&advansys_vlb_driver);
14267  unregister_isa:
14268         isa_unregister_driver(&advansys_isa_driver);
14269  fail:
14270         return error;
14271 }
14272
14273 static void __exit advansys_exit(void)
14274 {
14275         pci_unregister_driver(&advansys_pci_driver);
14276         eisa_driver_unregister(&advansys_eisa_driver);
14277         isa_unregister_driver(&advansys_vlb_driver);
14278         isa_unregister_driver(&advansys_isa_driver);
14279 }
14280
14281 module_init(advansys_init);
14282 module_exit(advansys_exit);
14283
14284 MODULE_LICENSE("GPL");