Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6] / drivers / net / sunbmac.c
1 /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
2  * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
3  *
4  * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
5  */
6
7 #include <linux/module.h>
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/fcntl.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14 #include <linux/in.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/crc32.h>
20 #include <linux/errno.h>
21 #include <linux/ethtool.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/bitops.h>
26
27 #include <asm/auxio.h>
28 #include <asm/byteorder.h>
29 #include <asm/dma.h>
30 #include <asm/idprom.h>
31 #include <asm/io.h>
32 #include <asm/openprom.h>
33 #include <asm/oplib.h>
34 #include <asm/pgtable.h>
35 #include <asm/sbus.h>
36 #include <asm/system.h>
37
38 #include "sunbmac.h"
39
40 #define DRV_NAME        "sunbmac"
41 #define DRV_VERSION     "2.0"
42 #define DRV_RELDATE     "11/24/03"
43 #define DRV_AUTHOR      "David S. Miller (davem@redhat.com)"
44
45 static char version[] __initdata =
46         DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
47
48 MODULE_VERSION(DRV_VERSION);
49 MODULE_AUTHOR(DRV_AUTHOR);
50 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
51 MODULE_LICENSE("GPL");
52
53 #undef DEBUG_PROBE
54 #undef DEBUG_TX
55 #undef DEBUG_IRQ
56
57 #ifdef DEBUG_PROBE
58 #define DP(x)  printk x
59 #else
60 #define DP(x)
61 #endif
62
63 #ifdef DEBUG_TX
64 #define DTX(x)  printk x
65 #else
66 #define DTX(x)
67 #endif
68
69 #ifdef DEBUG_IRQ
70 #define DIRQ(x)  printk x
71 #else
72 #define DIRQ(x)
73 #endif
74
75 static struct bigmac *root_bigmac_dev;
76
77 #define DEFAULT_JAMSIZE    4 /* Toe jam */
78
79 #define QEC_RESET_TRIES 200
80
81 static int qec_global_reset(void __iomem *gregs)
82 {
83         int tries = QEC_RESET_TRIES;
84
85         sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
86         while (--tries) {
87                 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
88                         udelay(20);
89                         continue;
90                 }
91                 break;
92         }
93         if (tries)
94                 return 0;
95         printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
96         return -1;
97 }
98
99 static void qec_init(struct bigmac *bp)
100 {
101         void __iomem *gregs = bp->gregs;
102         struct sbus_dev *qec_sdev = bp->qec_sdev;
103         u8 bsizes = bp->bigmac_bursts;
104         u32 regval;
105
106         /* 64byte bursts do not work at the moment, do
107          * not even try to enable them.  -DaveM
108          */
109         if (bsizes & DMA_BURST32)
110                 regval = GLOB_CTRL_B32;
111         else
112                 regval = GLOB_CTRL_B16;
113         sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
114         sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
115
116         /* All of memsize is given to bigmac. */
117         sbus_writel(qec_sdev->reg_addrs[1].reg_size,
118                     gregs + GLOB_MSIZE);
119
120         /* Half to the transmitter, half to the receiver. */
121         sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
122                     gregs + GLOB_TSIZE);
123         sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
124                     gregs + GLOB_RSIZE);
125 }
126
127 #define TX_RESET_TRIES     32
128 #define RX_RESET_TRIES     32
129
130 static void bigmac_tx_reset(void __iomem *bregs)
131 {
132         int tries = TX_RESET_TRIES;
133
134         sbus_writel(0, bregs + BMAC_TXCFG);
135
136         /* The fifo threshold bit is read-only and does
137          * not clear.  -DaveM
138          */
139         while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
140                --tries != 0)
141                 udelay(20);
142
143         if (!tries) {
144                 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
145                 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
146                        sbus_readl(bregs + BMAC_TXCFG));
147         }
148 }
149
150 static void bigmac_rx_reset(void __iomem *bregs)
151 {
152         int tries = RX_RESET_TRIES;
153
154         sbus_writel(0, bregs + BMAC_RXCFG);
155         while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
156                 udelay(20);
157
158         if (!tries) {
159                 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
160                 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
161                        sbus_readl(bregs + BMAC_RXCFG));
162         }
163 }
164
165 /* Reset the transmitter and receiver. */
166 static void bigmac_stop(struct bigmac *bp)
167 {
168         bigmac_tx_reset(bp->bregs);
169         bigmac_rx_reset(bp->bregs);
170 }
171
172 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
173 {
174         struct net_device_stats *stats = &bp->enet_stats;
175
176         stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
177         sbus_writel(0, bregs + BMAC_RCRCECTR);
178
179         stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
180         sbus_writel(0, bregs + BMAC_UNALECTR);
181
182         stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
183         sbus_writel(0, bregs + BMAC_GLECTR);
184
185         stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
186
187         stats->collisions +=
188                 (sbus_readl(bregs + BMAC_EXCTR) +
189                  sbus_readl(bregs + BMAC_LTCTR));
190         sbus_writel(0, bregs + BMAC_EXCTR);
191         sbus_writel(0, bregs + BMAC_LTCTR);
192 }
193
194 static void bigmac_clean_rings(struct bigmac *bp)
195 {
196         int i;
197
198         for (i = 0; i < RX_RING_SIZE; i++) {
199                 if (bp->rx_skbs[i] != NULL) {
200                         dev_kfree_skb_any(bp->rx_skbs[i]);
201                         bp->rx_skbs[i] = NULL;
202                 }
203         }
204
205         for (i = 0; i < TX_RING_SIZE; i++) {
206                 if (bp->tx_skbs[i] != NULL) {
207                         dev_kfree_skb_any(bp->tx_skbs[i]);
208                         bp->tx_skbs[i] = NULL;
209                 }
210         }
211 }
212
213 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
214 {
215         struct bmac_init_block *bb = bp->bmac_block;
216         struct net_device *dev = bp->dev;
217         int i;
218         gfp_t gfp_flags = GFP_KERNEL;
219
220         if (from_irq || in_interrupt())
221                 gfp_flags = GFP_ATOMIC;
222
223         bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
224
225         /* Free any skippy bufs left around in the rings. */
226         bigmac_clean_rings(bp);
227
228         /* Now get new skbufs for the receive ring. */
229         for (i = 0; i < RX_RING_SIZE; i++) {
230                 struct sk_buff *skb;
231
232                 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
233                 if (!skb)
234                         continue;
235
236                 bp->rx_skbs[i] = skb;
237                 skb->dev = dev;
238
239                 /* Because we reserve afterwards. */
240                 skb_put(skb, ETH_FRAME_LEN);
241                 skb_reserve(skb, 34);
242
243                 bb->be_rxd[i].rx_addr =
244                         sbus_map_single(bp->bigmac_sdev, skb->data,
245                                         RX_BUF_ALLOC_SIZE - 34,
246                                         SBUS_DMA_FROMDEVICE);
247                 bb->be_rxd[i].rx_flags =
248                         (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
249         }
250
251         for (i = 0; i < TX_RING_SIZE; i++)
252                 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
253 }
254
255 #define MGMT_CLKON  (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
256 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
257
258 static void idle_transceiver(void __iomem *tregs)
259 {
260         int i = 20;
261
262         while (i--) {
263                 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
264                 sbus_readl(tregs + TCVR_MPAL);
265                 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
266                 sbus_readl(tregs + TCVR_MPAL);
267         }
268 }
269
270 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
271 {
272         if (bp->tcvr_type == internal) {
273                 bit = (bit & 1) << 3;
274                 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
275                             tregs + TCVR_MPAL);
276                 sbus_readl(tregs + TCVR_MPAL);
277                 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
278                             tregs + TCVR_MPAL);
279                 sbus_readl(tregs + TCVR_MPAL);
280         } else if (bp->tcvr_type == external) {
281                 bit = (bit & 1) << 2;
282                 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
283                             tregs + TCVR_MPAL);
284                 sbus_readl(tregs + TCVR_MPAL);
285                 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
286                             tregs + TCVR_MPAL);
287                 sbus_readl(tregs + TCVR_MPAL);
288         } else {
289                 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
290         }
291 }
292
293 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
294 {
295         int retval = 0;
296
297         if (bp->tcvr_type == internal) {
298                 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
299                 sbus_readl(tregs + TCVR_MPAL);
300                 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
301                             tregs + TCVR_MPAL);
302                 sbus_readl(tregs + TCVR_MPAL);
303                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
304         } else if (bp->tcvr_type == external) {
305                 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
306                 sbus_readl(tregs + TCVR_MPAL);
307                 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
308                 sbus_readl(tregs + TCVR_MPAL);
309                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
310         } else {
311                 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
312         }
313         return retval;
314 }
315
316 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
317 {
318         int retval = 0;
319
320         if (bp->tcvr_type == internal) {
321                 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
322                 sbus_readl(tregs + TCVR_MPAL);
323                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
324                 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
325                 sbus_readl(tregs + TCVR_MPAL);
326         } else if (bp->tcvr_type == external) {
327                 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
328                 sbus_readl(tregs + TCVR_MPAL);
329                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
330                 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
331                 sbus_readl(tregs + TCVR_MPAL);
332         } else {
333                 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
334         }
335         return retval;
336 }
337
338 static void put_tcvr_byte(struct bigmac *bp,
339                           void __iomem *tregs,
340                           unsigned int byte)
341 {
342         int shift = 4;
343
344         do {
345                 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
346                 shift -= 1;
347         } while (shift >= 0);
348 }
349
350 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
351                               int reg, unsigned short val)
352 {
353         int shift;
354
355         reg &= 0xff;
356         val &= 0xffff;
357         switch(bp->tcvr_type) {
358         case internal:
359         case external:
360                 break;
361
362         default:
363                 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
364                 return;
365         };
366
367         idle_transceiver(tregs);
368         write_tcvr_bit(bp, tregs, 0);
369         write_tcvr_bit(bp, tregs, 1);
370         write_tcvr_bit(bp, tregs, 0);
371         write_tcvr_bit(bp, tregs, 1);
372
373         put_tcvr_byte(bp, tregs,
374                       ((bp->tcvr_type == internal) ?
375                        BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
376
377         put_tcvr_byte(bp, tregs, reg);
378
379         write_tcvr_bit(bp, tregs, 1);
380         write_tcvr_bit(bp, tregs, 0);
381
382         shift = 15;
383         do {
384                 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
385                 shift -= 1;
386         } while (shift >= 0);
387 }
388
389 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
390                                        void __iomem *tregs,
391                                        int reg)
392 {
393         unsigned short retval = 0;
394
395         reg &= 0xff;
396         switch(bp->tcvr_type) {
397         case internal:
398         case external:
399                 break;
400
401         default:
402                 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
403                 return 0xffff;
404         };
405
406         idle_transceiver(tregs);
407         write_tcvr_bit(bp, tregs, 0);
408         write_tcvr_bit(bp, tregs, 1);
409         write_tcvr_bit(bp, tregs, 1);
410         write_tcvr_bit(bp, tregs, 0);
411
412         put_tcvr_byte(bp, tregs,
413                       ((bp->tcvr_type == internal) ?
414                        BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
415
416         put_tcvr_byte(bp, tregs, reg);
417
418         if (bp->tcvr_type == external) {
419                 int shift = 15;
420
421                 (void) read_tcvr_bit2(bp, tregs);
422                 (void) read_tcvr_bit2(bp, tregs);
423
424                 do {
425                         int tmp;
426
427                         tmp = read_tcvr_bit2(bp, tregs);
428                         retval |= ((tmp & 1) << shift);
429                         shift -= 1;
430                 } while (shift >= 0);
431
432                 (void) read_tcvr_bit2(bp, tregs);
433                 (void) read_tcvr_bit2(bp, tregs);
434                 (void) read_tcvr_bit2(bp, tregs);
435         } else {
436                 int shift = 15;
437
438                 (void) read_tcvr_bit(bp, tregs);
439                 (void) read_tcvr_bit(bp, tregs);
440
441                 do {
442                         int tmp;
443
444                         tmp = read_tcvr_bit(bp, tregs);
445                         retval |= ((tmp & 1) << shift);
446                         shift -= 1;
447                 } while (shift >= 0);
448
449                 (void) read_tcvr_bit(bp, tregs);
450                 (void) read_tcvr_bit(bp, tregs);
451                 (void) read_tcvr_bit(bp, tregs);
452         }
453         return retval;
454 }
455
456 static void bigmac_tcvr_init(struct bigmac *bp)
457 {
458         void __iomem *tregs = bp->tregs;
459         u32 mpal;
460
461         idle_transceiver(tregs);
462         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
463                     tregs + TCVR_MPAL);
464         sbus_readl(tregs + TCVR_MPAL);
465
466         /* Only the bit for the present transceiver (internal or
467          * external) will stick, set them both and see what stays.
468          */
469         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
470         sbus_readl(tregs + TCVR_MPAL);
471         udelay(20);
472
473         mpal = sbus_readl(tregs + TCVR_MPAL);
474         if (mpal & MGMT_PAL_EXT_MDIO) {
475                 bp->tcvr_type = external;
476                 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
477                             tregs + TCVR_TPAL);
478                 sbus_readl(tregs + TCVR_TPAL);
479         } else if (mpal & MGMT_PAL_INT_MDIO) {
480                 bp->tcvr_type = internal;
481                 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
482                               TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
483                             tregs + TCVR_TPAL);
484                 sbus_readl(tregs + TCVR_TPAL);
485         } else {
486                 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
487                        "external MDIO available!\n");
488                 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
489                        sbus_readl(tregs + TCVR_MPAL),
490                        sbus_readl(tregs + TCVR_TPAL));
491         }
492 }
493
494 static int bigmac_init(struct bigmac *, int);
495
496 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
497 {
498         if (bp->sw_bmcr & BMCR_SPEED100) {
499                 int timeout;
500
501                 /* Reset the PHY. */
502                 bp->sw_bmcr     = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
503                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
504                 bp->sw_bmcr     = (BMCR_RESET);
505                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
506
507                 timeout = 64;
508                 while (--timeout) {
509                         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
510                         if ((bp->sw_bmcr & BMCR_RESET) == 0)
511                                 break;
512                         udelay(20);
513                 }
514                 if (timeout == 0)
515                         printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
516
517                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
518
519                 /* Now we try 10baseT. */
520                 bp->sw_bmcr &= ~(BMCR_SPEED100);
521                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
522                 return 0;
523         }
524
525         /* We've tried them all. */
526         return -1;
527 }
528
529 static void bigmac_timer(unsigned long data)
530 {
531         struct bigmac *bp = (struct bigmac *) data;
532         void __iomem *tregs = bp->tregs;
533         int restart_timer = 0;
534
535         bp->timer_ticks++;
536         if (bp->timer_state == ltrywait) {
537                 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
538                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
539                 if (bp->sw_bmsr & BMSR_LSTATUS) {
540                         printk(KERN_INFO "%s: Link is now up at %s.\n",
541                                bp->dev->name,
542                                (bp->sw_bmcr & BMCR_SPEED100) ?
543                                "100baseT" : "10baseT");
544                         bp->timer_state = asleep;
545                         restart_timer = 0;
546                 } else {
547                         if (bp->timer_ticks >= 4) {
548                                 int ret;
549
550                                 ret = try_next_permutation(bp, tregs);
551                                 if (ret == -1) {
552                                         printk(KERN_ERR "%s: Link down, cable problem?\n",
553                                                bp->dev->name);
554                                         ret = bigmac_init(bp, 0);
555                                         if (ret) {
556                                                 printk(KERN_ERR "%s: Error, cannot re-init the "
557                                                        "BigMAC.\n", bp->dev->name);
558                                         }
559                                         return;
560                                 }
561                                 bp->timer_ticks = 0;
562                                 restart_timer = 1;
563                         } else {
564                                 restart_timer = 1;
565                         }
566                 }
567         } else {
568                 /* Can't happens.... */
569                 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
570                        bp->dev->name);
571                 restart_timer = 0;
572                 bp->timer_ticks = 0;
573                 bp->timer_state = asleep; /* foo on you */
574         }
575
576         if (restart_timer != 0) {
577                 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
578                 add_timer(&bp->bigmac_timer);
579         }
580 }
581
582 /* Well, really we just force the chip into 100baseT then
583  * 10baseT, each time checking for a link status.
584  */
585 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
586 {
587         void __iomem *tregs = bp->tregs;
588         int timeout;
589
590         /* Grab new software copies of PHY registers. */
591         bp->sw_bmsr     = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
592         bp->sw_bmcr     = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
593
594         /* Reset the PHY. */
595         bp->sw_bmcr     = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
596         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
597         bp->sw_bmcr     = (BMCR_RESET);
598         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
599
600         timeout = 64;
601         while (--timeout) {
602                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
603                 if ((bp->sw_bmcr & BMCR_RESET) == 0)
604                         break;
605                 udelay(20);
606         }
607         if (timeout == 0)
608                 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
609
610         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
611
612         /* First we try 100baseT. */
613         bp->sw_bmcr |= BMCR_SPEED100;
614         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
615
616         bp->timer_state = ltrywait;
617         bp->timer_ticks = 0;
618         bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
619         bp->bigmac_timer.data = (unsigned long) bp;
620         bp->bigmac_timer.function = &bigmac_timer;
621         add_timer(&bp->bigmac_timer);
622 }
623
624 static int bigmac_init(struct bigmac *bp, int from_irq)
625 {
626         void __iomem *gregs        = bp->gregs;
627         void __iomem *cregs        = bp->creg;
628         void __iomem *bregs        = bp->bregs;
629         unsigned char *e = &bp->dev->dev_addr[0];
630
631         /* Latch current counters into statistics. */
632         bigmac_get_counters(bp, bregs);
633
634         /* Reset QEC. */
635         qec_global_reset(gregs);
636
637         /* Init QEC. */
638         qec_init(bp);
639
640         /* Alloc and reset the tx/rx descriptor chains. */
641         bigmac_init_rings(bp, from_irq);
642
643         /* Initialize the PHY. */
644         bigmac_tcvr_init(bp);
645
646         /* Stop transmitter and receiver. */
647         bigmac_stop(bp);
648
649         /* Set hardware ethernet address. */
650         sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
651         sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
652         sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
653
654         /* Clear the hash table until mc upload occurs. */
655         sbus_writel(0, bregs + BMAC_HTABLE3);
656         sbus_writel(0, bregs + BMAC_HTABLE2);
657         sbus_writel(0, bregs + BMAC_HTABLE1);
658         sbus_writel(0, bregs + BMAC_HTABLE0);
659
660         /* Enable Big Mac hash table filter. */
661         sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
662                     bregs + BMAC_RXCFG);
663         udelay(20);
664
665         /* Ok, configure the Big Mac transmitter. */
666         sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
667
668         /* The HME docs recommend to use the 10LSB of our MAC here. */
669         sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
670                     bregs + BMAC_RSEED);
671
672         /* Enable the output drivers no matter what. */
673         sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
674                     bregs + BMAC_XIFCFG);
675
676         /* Tell the QEC where the ring descriptors are. */
677         sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
678                     cregs + CREG_RXDS);
679         sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
680                     cregs + CREG_TXDS);
681
682         /* Setup the FIFO pointers into QEC local memory. */
683         sbus_writel(0, cregs + CREG_RXRBUFPTR);
684         sbus_writel(0, cregs + CREG_RXWBUFPTR);
685         sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
686                     cregs + CREG_TXRBUFPTR);
687         sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
688                     cregs + CREG_TXWBUFPTR);
689
690         /* Tell bigmac what interrupts we don't want to hear about. */
691         sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
692                     bregs + BMAC_IMASK);
693
694         /* Enable the various other irq's. */
695         sbus_writel(0, cregs + CREG_RIMASK);
696         sbus_writel(0, cregs + CREG_TIMASK);
697         sbus_writel(0, cregs + CREG_QMASK);
698         sbus_writel(0, cregs + CREG_BMASK);
699
700         /* Set jam size to a reasonable default. */
701         sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
702
703         /* Clear collision counter. */
704         sbus_writel(0, cregs + CREG_CCNT);
705
706         /* Enable transmitter and receiver. */
707         sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
708                     bregs + BMAC_TXCFG);
709         sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
710                     bregs + BMAC_RXCFG);
711
712         /* Ok, start detecting link speed/duplex. */
713         bigmac_begin_auto_negotiation(bp);
714
715         /* Success. */
716         return 0;
717 }
718
719 /* Error interrupts get sent here. */
720 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
721 {
722         printk(KERN_ERR "bigmac_is_medium_rare: ");
723         if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
724                 if (qec_status & GLOB_STAT_ER)
725                         printk("QEC_ERROR, ");
726                 if (qec_status & GLOB_STAT_BM)
727                         printk("QEC_BMAC_ERROR, ");
728         }
729         if (bmac_status & CREG_STAT_ERRORS) {
730                 if (bmac_status & CREG_STAT_BERROR)
731                         printk("BMAC_ERROR, ");
732                 if (bmac_status & CREG_STAT_TXDERROR)
733                         printk("TXD_ERROR, ");
734                 if (bmac_status & CREG_STAT_TXLERR)
735                         printk("TX_LATE_ERROR, ");
736                 if (bmac_status & CREG_STAT_TXPERR)
737                         printk("TX_PARITY_ERROR, ");
738                 if (bmac_status & CREG_STAT_TXSERR)
739                         printk("TX_SBUS_ERROR, ");
740
741                 if (bmac_status & CREG_STAT_RXDROP)
742                         printk("RX_DROP_ERROR, ");
743
744                 if (bmac_status & CREG_STAT_RXSMALL)
745                         printk("RX_SMALL_ERROR, ");
746                 if (bmac_status & CREG_STAT_RXLERR)
747                         printk("RX_LATE_ERROR, ");
748                 if (bmac_status & CREG_STAT_RXPERR)
749                         printk("RX_PARITY_ERROR, ");
750                 if (bmac_status & CREG_STAT_RXSERR)
751                         printk("RX_SBUS_ERROR, ");
752         }
753
754         printk(" RESET\n");
755         bigmac_init(bp, 1);
756 }
757
758 /* BigMAC transmit complete service routines. */
759 static void bigmac_tx(struct bigmac *bp)
760 {
761         struct be_txd *txbase = &bp->bmac_block->be_txd[0];
762         struct net_device *dev = bp->dev;
763         int elem;
764
765         spin_lock(&bp->lock);
766
767         elem = bp->tx_old;
768         DTX(("bigmac_tx: tx_old[%d] ", elem));
769         while (elem != bp->tx_new) {
770                 struct sk_buff *skb;
771                 struct be_txd *this = &txbase[elem];
772
773                 DTX(("this(%p) [flags(%08x)addr(%08x)]",
774                      this, this->tx_flags, this->tx_addr));
775
776                 if (this->tx_flags & TXD_OWN)
777                         break;
778                 skb = bp->tx_skbs[elem];
779                 bp->enet_stats.tx_packets++;
780                 bp->enet_stats.tx_bytes += skb->len;
781                 sbus_unmap_single(bp->bigmac_sdev,
782                                   this->tx_addr, skb->len,
783                                   SBUS_DMA_TODEVICE);
784
785                 DTX(("skb(%p) ", skb));
786                 bp->tx_skbs[elem] = NULL;
787                 dev_kfree_skb_irq(skb);
788
789                 elem = NEXT_TX(elem);
790         }
791         DTX((" DONE, tx_old=%d\n", elem));
792         bp->tx_old = elem;
793
794         if (netif_queue_stopped(dev) &&
795             TX_BUFFS_AVAIL(bp) > 0)
796                 netif_wake_queue(bp->dev);
797
798         spin_unlock(&bp->lock);
799 }
800
801 /* BigMAC receive complete service routines. */
802 static void bigmac_rx(struct bigmac *bp)
803 {
804         struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
805         struct be_rxd *this;
806         int elem = bp->rx_new, drops = 0;
807         u32 flags;
808
809         this = &rxbase[elem];
810         while (!((flags = this->rx_flags) & RXD_OWN)) {
811                 struct sk_buff *skb;
812                 int len = (flags & RXD_LENGTH); /* FCS not included */
813
814                 /* Check for errors. */
815                 if (len < ETH_ZLEN) {
816                         bp->enet_stats.rx_errors++;
817                         bp->enet_stats.rx_length_errors++;
818
819         drop_it:
820                         /* Return it to the BigMAC. */
821                         bp->enet_stats.rx_dropped++;
822                         this->rx_flags =
823                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
824                         goto next;
825                 }
826                 skb = bp->rx_skbs[elem];
827                 if (len > RX_COPY_THRESHOLD) {
828                         struct sk_buff *new_skb;
829
830                         /* Now refill the entry, if we can. */
831                         new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
832                         if (new_skb == NULL) {
833                                 drops++;
834                                 goto drop_it;
835                         }
836                         sbus_unmap_single(bp->bigmac_sdev,
837                                           this->rx_addr,
838                                           RX_BUF_ALLOC_SIZE - 34,
839                                           SBUS_DMA_FROMDEVICE);
840                         bp->rx_skbs[elem] = new_skb;
841                         new_skb->dev = bp->dev;
842                         skb_put(new_skb, ETH_FRAME_LEN);
843                         skb_reserve(new_skb, 34);
844                         this->rx_addr = sbus_map_single(bp->bigmac_sdev,
845                                                         new_skb->data,
846                                                         RX_BUF_ALLOC_SIZE - 34,
847                                                         SBUS_DMA_FROMDEVICE);
848                         this->rx_flags =
849                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
850
851                         /* Trim the original skb for the netif. */
852                         skb_trim(skb, len);
853                 } else {
854                         struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
855
856                         if (copy_skb == NULL) {
857                                 drops++;
858                                 goto drop_it;
859                         }
860                         copy_skb->dev = bp->dev;
861                         skb_reserve(copy_skb, 2);
862                         skb_put(copy_skb, len);
863                         sbus_dma_sync_single_for_cpu(bp->bigmac_sdev,
864                                                      this->rx_addr, len,
865                                                      SBUS_DMA_FROMDEVICE);
866                         eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
867                         sbus_dma_sync_single_for_device(bp->bigmac_sdev,
868                                                         this->rx_addr, len,
869                                                         SBUS_DMA_FROMDEVICE);
870
871                         /* Reuse original ring buffer. */
872                         this->rx_flags =
873                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
874
875                         skb = copy_skb;
876                 }
877
878                 /* No checksums done by the BigMAC ;-( */
879                 skb->protocol = eth_type_trans(skb, bp->dev);
880                 netif_rx(skb);
881                 bp->dev->last_rx = jiffies;
882                 bp->enet_stats.rx_packets++;
883                 bp->enet_stats.rx_bytes += len;
884         next:
885                 elem = NEXT_RX(elem);
886                 this = &rxbase[elem];
887         }
888         bp->rx_new = elem;
889         if (drops)
890                 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
891 }
892
893 static irqreturn_t bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
894 {
895         struct bigmac *bp = (struct bigmac *) dev_id;
896         u32 qec_status, bmac_status;
897
898         DIRQ(("bigmac_interrupt: "));
899
900         /* Latch status registers now. */
901         bmac_status = sbus_readl(bp->creg + CREG_STAT);
902         qec_status = sbus_readl(bp->gregs + GLOB_STAT);
903
904         DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
905         if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
906            (bmac_status & CREG_STAT_ERRORS))
907                 bigmac_is_medium_rare(bp, qec_status, bmac_status);
908
909         if (bmac_status & CREG_STAT_TXIRQ)
910                 bigmac_tx(bp);
911
912         if (bmac_status & CREG_STAT_RXIRQ)
913                 bigmac_rx(bp);
914
915         return IRQ_HANDLED;
916 }
917
918 static int bigmac_open(struct net_device *dev)
919 {
920         struct bigmac *bp = (struct bigmac *) dev->priv;
921         int ret;
922
923         ret = request_irq(dev->irq, &bigmac_interrupt, SA_SHIRQ, dev->name, bp);
924         if (ret) {
925                 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
926                 return ret;
927         }
928         init_timer(&bp->bigmac_timer);
929         ret = bigmac_init(bp, 0);
930         if (ret)
931                 free_irq(dev->irq, bp);
932         return ret;
933 }
934
935 static int bigmac_close(struct net_device *dev)
936 {
937         struct bigmac *bp = (struct bigmac *) dev->priv;
938
939         del_timer(&bp->bigmac_timer);
940         bp->timer_state = asleep;
941         bp->timer_ticks = 0;
942
943         bigmac_stop(bp);
944         bigmac_clean_rings(bp);
945         free_irq(dev->irq, bp);
946         return 0;
947 }
948
949 static void bigmac_tx_timeout(struct net_device *dev)
950 {
951         struct bigmac *bp = (struct bigmac *) dev->priv;
952
953         bigmac_init(bp, 0);
954         netif_wake_queue(dev);
955 }
956
957 /* Put a packet on the wire. */
958 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
959 {
960         struct bigmac *bp = (struct bigmac *) dev->priv;
961         int len, entry;
962         u32 mapping;
963
964         len = skb->len;
965         mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
966
967         /* Avoid a race... */
968         spin_lock_irq(&bp->lock);
969         entry = bp->tx_new;
970         DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
971         bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
972         bp->tx_skbs[entry] = skb;
973         bp->bmac_block->be_txd[entry].tx_addr = mapping;
974         bp->bmac_block->be_txd[entry].tx_flags =
975                 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
976         bp->tx_new = NEXT_TX(entry);
977         if (TX_BUFFS_AVAIL(bp) <= 0)
978                 netif_stop_queue(dev);
979         spin_unlock_irq(&bp->lock);
980
981         /* Get it going. */
982         sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
983
984
985         dev->trans_start = jiffies;
986
987         return 0;
988 }
989
990 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
991 {
992         struct bigmac *bp = (struct bigmac *) dev->priv;
993
994         bigmac_get_counters(bp, bp->bregs);
995         return &bp->enet_stats;
996 }
997
998 static void bigmac_set_multicast(struct net_device *dev)
999 {
1000         struct bigmac *bp = (struct bigmac *) dev->priv;
1001         void __iomem *bregs = bp->bregs;
1002         struct dev_mc_list *dmi = dev->mc_list;
1003         char *addrs;
1004         int i;
1005         u32 tmp, crc;
1006
1007         /* Disable the receiver.  The bit self-clears when
1008          * the operation is complete.
1009          */
1010         tmp = sbus_readl(bregs + BMAC_RXCFG);
1011         tmp &= ~(BIGMAC_RXCFG_ENABLE);
1012         sbus_writel(tmp, bregs + BMAC_RXCFG);
1013         while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
1014                 udelay(20);
1015
1016         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1017                 sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1018                 sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1019                 sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1020                 sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1021         } else if (dev->flags & IFF_PROMISC) {
1022                 tmp = sbus_readl(bregs + BMAC_RXCFG);
1023                 tmp |= BIGMAC_RXCFG_PMISC;
1024                 sbus_writel(tmp, bregs + BMAC_RXCFG);
1025         } else {
1026                 u16 hash_table[4];
1027
1028                 for (i = 0; i < 4; i++)
1029                         hash_table[i] = 0;
1030
1031                 for (i = 0; i < dev->mc_count; i++) {
1032                         addrs = dmi->dmi_addr;
1033                         dmi = dmi->next;
1034
1035                         if (!(*addrs & 1))
1036                                 continue;
1037
1038                         crc = ether_crc_le(6, addrs);
1039                         crc >>= 26;
1040                         hash_table[crc >> 4] |= 1 << (crc & 0xf);
1041                 }
1042                 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1043                 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1044                 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1045                 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1046         }
1047
1048         /* Re-enable the receiver. */
1049         tmp = sbus_readl(bregs + BMAC_RXCFG);
1050         tmp |= BIGMAC_RXCFG_ENABLE;
1051         sbus_writel(tmp, bregs + BMAC_RXCFG);
1052 }
1053
1054 /* Ethtool support... */
1055 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1056 {
1057         struct bigmac *bp = dev->priv;
1058
1059         strcpy(info->driver, "sunbmac");
1060         strcpy(info->version, "2.0");
1061         sprintf(info->bus_info, "SBUS:%d",
1062                 bp->qec_sdev->slot);
1063 }
1064
1065 static u32 bigmac_get_link(struct net_device *dev)
1066 {
1067         struct bigmac *bp = dev->priv;
1068
1069         spin_lock_irq(&bp->lock);
1070         bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
1071         spin_unlock_irq(&bp->lock);
1072
1073         return (bp->sw_bmsr & BMSR_LSTATUS);
1074 }
1075
1076 static struct ethtool_ops bigmac_ethtool_ops = {
1077         .get_drvinfo            = bigmac_get_drvinfo,
1078         .get_link               = bigmac_get_link,
1079 };
1080
1081 static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
1082 {
1083         struct net_device *dev;
1084         static int version_printed;
1085         struct bigmac *bp;
1086         u8 bsizes, bsizes_more;
1087         int i;
1088
1089         /* Get a new device struct for this interface. */
1090         dev = alloc_etherdev(sizeof(struct bigmac));
1091         if (!dev)
1092                 return -ENOMEM;
1093         SET_MODULE_OWNER(dev);
1094
1095         if (version_printed++ == 0)
1096                 printk(KERN_INFO "%s", version);
1097
1098         dev->base_addr = (long) qec_sdev;
1099         for (i = 0; i < 6; i++)
1100                 dev->dev_addr[i] = idprom->id_ethaddr[i];
1101
1102         /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1103         bp = dev->priv;
1104         bp->qec_sdev = qec_sdev;
1105         bp->bigmac_sdev = qec_sdev->child;
1106
1107         spin_lock_init(&bp->lock);
1108
1109         /* Verify the registers we expect, are actually there. */
1110         if ((bp->bigmac_sdev->num_registers != 3) ||
1111            (bp->qec_sdev->num_registers != 2)) {
1112                 printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1113                        bp->qec_sdev->num_registers,
1114                        bp->bigmac_sdev->num_registers);
1115                 printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
1116                 goto fail_and_cleanup;
1117         }
1118
1119         /* Map in QEC global control registers. */
1120         bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
1121                                  GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1122         if (!bp->gregs) {
1123                 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1124                 goto fail_and_cleanup;
1125         }
1126
1127         /* Make sure QEC is in BigMAC mode. */
1128         if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1129                 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1130                 goto fail_and_cleanup;
1131         }
1132
1133         /* Reset the QEC. */
1134         if (qec_global_reset(bp->gregs))
1135                 goto fail_and_cleanup;
1136
1137         /* Get supported SBUS burst sizes. */
1138         bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
1139                                     "burst-sizes",
1140                                     0xff);
1141
1142         bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
1143                                          "burst-sizes",
1144                                          0xff);
1145
1146         bsizes &= 0xff;
1147         if (bsizes_more != 0xff)
1148                 bsizes &= bsizes_more;
1149         if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1150             (bsizes & DMA_BURST32) == 0)
1151                 bsizes = (DMA_BURST32 - 1);
1152         bp->bigmac_bursts = bsizes;
1153
1154         /* Perform QEC initialization. */
1155         qec_init(bp);
1156
1157         /* Map in the BigMAC channel registers. */
1158         bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
1159                                 CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1160         if (!bp->creg) {
1161                 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1162                 goto fail_and_cleanup;
1163         }
1164
1165         /* Map in the BigMAC control registers. */
1166         bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
1167                                  BMAC_REG_SIZE, "BigMAC Primary Regs");
1168         if (!bp->bregs) {
1169                 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1170                 goto fail_and_cleanup;
1171         }
1172
1173         /* Map in the BigMAC transceiver registers, this is how you poke at
1174          * the BigMAC's PHY.
1175          */
1176         bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
1177                                  TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1178         if (!bp->tregs) {
1179                 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1180                 goto fail_and_cleanup;
1181         }
1182
1183         /* Stop the BigMAC. */
1184         bigmac_stop(bp);
1185
1186         /* Allocate transmit/receive descriptor DVMA block. */
1187         bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
1188                                                PAGE_SIZE,
1189                                                &bp->bblock_dvma);
1190         if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
1191                 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
1192                 goto fail_and_cleanup;
1193         }
1194
1195         /* Get the board revision of this BigMAC. */
1196         bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
1197                                            "board-version", 1);
1198
1199         /* Init auto-negotiation timer state. */
1200         init_timer(&bp->bigmac_timer);
1201         bp->timer_state = asleep;
1202         bp->timer_ticks = 0;
1203
1204         /* Backlink to generic net device struct. */
1205         bp->dev = dev;
1206
1207         /* Set links to our BigMAC open and close routines. */
1208         dev->open = &bigmac_open;
1209         dev->stop = &bigmac_close;
1210         dev->hard_start_xmit = &bigmac_start_xmit;
1211         dev->ethtool_ops = &bigmac_ethtool_ops;
1212
1213         /* Set links to BigMAC statistic and multi-cast loading code. */
1214         dev->get_stats = &bigmac_get_stats;
1215         dev->set_multicast_list = &bigmac_set_multicast;
1216
1217         dev->tx_timeout = &bigmac_tx_timeout;
1218         dev->watchdog_timeo = 5*HZ;
1219
1220         /* Finish net device registration. */
1221         dev->irq = bp->bigmac_sdev->irqs[0];
1222         dev->dma = 0;
1223
1224         if (register_netdev(dev)) {
1225                 printk(KERN_ERR "BIGMAC: Cannot register device.\n");
1226                 goto fail_and_cleanup;
1227         }
1228
1229         /* Put us into the list of instances attached for later driver
1230          * exit.
1231          */
1232         bp->next_module = root_bigmac_dev;
1233         root_bigmac_dev = bp;
1234
1235         printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
1236         for (i = 0; i < 6; i++)
1237                 printk("%2.2x%c", dev->dev_addr[i],
1238                        i == 5 ? ' ' : ':');
1239         printk("\n");
1240
1241         return 0;
1242
1243 fail_and_cleanup:
1244         /* Something went wrong, undo whatever we did so far. */
1245         /* Free register mappings if any. */
1246         if (bp->gregs)
1247                 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1248         if (bp->creg)
1249                 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1250         if (bp->bregs)
1251                 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1252         if (bp->tregs)
1253                 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1254
1255         if (bp->bmac_block)
1256                 sbus_free_consistent(bp->bigmac_sdev,
1257                                      PAGE_SIZE,
1258                                      bp->bmac_block,
1259                                      bp->bblock_dvma);
1260
1261         /* This also frees the co-located 'dev->priv' */
1262         free_netdev(dev);
1263         return -ENODEV;
1264 }
1265
1266 /* QEC can be the parent of either QuadEthernet or
1267  * a BigMAC.  We want the latter.
1268  */
1269 static int __init bigmac_match(struct sbus_dev *sdev)
1270 {
1271         struct sbus_dev *child = sdev->child;
1272
1273         if (strcmp(sdev->prom_name, "qec") != 0)
1274                 return 0;
1275
1276         if (child == NULL)
1277                 return 0;
1278
1279         if (strcmp(child->prom_name, "be") != 0)
1280                 return 0;
1281
1282         return 1;
1283 }
1284
1285 static int __init bigmac_probe(void)
1286 {
1287         struct sbus_bus *sbus;
1288         struct sbus_dev *sdev = NULL;
1289         static int called;
1290         int cards = 0, v;
1291
1292         root_bigmac_dev = NULL;
1293
1294         if (called)
1295                 return -ENODEV;
1296         called++;
1297
1298         for_each_sbus(sbus) {
1299                 for_each_sbusdev(sdev, sbus) {
1300                         if (bigmac_match(sdev)) {
1301                                 cards++;
1302                                 if ((v = bigmac_ether_init(sdev)))
1303                                         return v;
1304                         }
1305                 }
1306         }
1307         if (!cards)
1308                 return -ENODEV;
1309         return 0;
1310 }
1311
1312 static void __exit bigmac_cleanup(void)
1313 {
1314         while (root_bigmac_dev) {
1315                 struct bigmac *bp = root_bigmac_dev;
1316                 struct bigmac *bp_nxt = root_bigmac_dev->next_module;
1317
1318                 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1319                 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1320                 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1321                 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1322                 sbus_free_consistent(bp->bigmac_sdev,
1323                                      PAGE_SIZE,
1324                                      bp->bmac_block,
1325                                      bp->bblock_dvma);
1326
1327                 unregister_netdev(bp->dev);
1328                 free_netdev(bp->dev);
1329                 root_bigmac_dev = bp_nxt;
1330         }
1331 }
1332
1333 module_init(bigmac_probe);
1334 module_exit(bigmac_cleanup);