3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/init.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/sched.h>
39 #include <linux/spinlock.h>
40 #include <linux/hardirq.h>
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
45 #include <asm/div64.h>
46 #include <asm/mach-au1x00/au1000.h>
48 #include <linux/mc146818rtc.h>
49 #include <linux/timex.h>
51 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
52 static unsigned long r4k_cur; /* What counter should be at next timer irq */
54 extern int allow_au1k_wait; /* default off for CP0 Counter */
56 /* Cycle counter value at the previous timer interrupt.. */
57 static unsigned int timerhi = 0, timerlo = 0;
60 #if HZ < 100 || HZ > 1000
61 #error "unsupported HZ value! Must be in [100,1000]"
63 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
64 extern void startup_match20_interrupt(irq_handler_t handler);
65 static unsigned long last_pc0, last_match20;
68 static DEFINE_SPINLOCK(time_lock);
70 static inline void ack_r4ktimer(unsigned long newval)
72 write_c0_compare(newval);
76 * There are a lot of conceptually broken versions of the MIPS timer interrupt
77 * handler floating around. This one is rather different, but the algorithm
78 * is provably more robust.
82 void mips_timer_interrupt(void)
88 kstat_this_cpu.irqs[irq]++;
94 count = read_c0_count();
95 timerhi += (count < timerlo); /* Wrap around */
98 kstat_this_cpu.irqs[irq]++;
101 update_process_times(user_mode(get_irq_regs()));
103 r4k_cur += r4k_offset;
104 ack_r4ktimer(r4k_cur);
106 } while (((unsigned long)read_c0_count()
107 - r4k_cur) < 0x7fffffff);
118 irqreturn_t counter0_irq(int irq, void *dev_id)
122 static int jiffie_drift = 0;
124 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
125 /* should never happen! */
126 printk(KERN_WARNING "counter 0 w status error\n");
130 pc0 = au_readl(SYS_TOYREAD);
131 if (pc0 < last_match20) {
132 /* counter overflowed */
133 time_elapsed = (0xffffffff - last_match20) + pc0;
136 time_elapsed = pc0 - last_match20;
139 while (time_elapsed > 0) {
142 update_process_times(user_mode(get_irq_regs()));
144 time_elapsed -= MATCH20_INC;
145 last_match20 += MATCH20_INC;
150 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
153 /* our counter ticks at 10.009765625 ms/tick, we we're running
154 * almost 10uS too slow per tick.
157 if (jiffie_drift >= 999) {
159 do_timer(1); /* increment jiffies by one */
161 update_process_times(user_mode(get_irq_regs()));
168 /* When we wakeup from sleep, we have to "catch up" on all of the
169 * timer ticks we have missed.
172 wakeup_counter0_adjust(void)
177 pc0 = au_readl(SYS_TOYREAD);
178 if (pc0 < last_match20) {
179 /* counter overflowed */
180 time_elapsed = (0xffffffff - last_match20) + pc0;
183 time_elapsed = pc0 - last_match20;
186 while (time_elapsed > 0) {
187 time_elapsed -= MATCH20_INC;
188 last_match20 += MATCH20_INC;
192 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
197 /* This is just for debugging to set the timer for a sleep delay.
200 wakeup_counter0_set(int ticks)
204 pc0 = au_readl(SYS_TOYREAD);
206 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
211 /* I haven't found anyone that doesn't use a 12 MHz source clock,
212 * but just in case.....
214 #ifdef CONFIG_AU1000_SRC_CLK
215 #define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
217 #define AU1000_SRC_CLK 12000000
221 * We read the real processor speed from the PLL. This is important
222 * because it is more accurate than computing it from the 32KHz
223 * counter, if it exists. If we don't have an accurate processor
224 * speed, all of the peripherals that derive their clocks based on
225 * this advertised speed will introduce error and sometimes not work
226 * properly. This function is futher convoluted to still allow configurations
227 * to do that in case they have really, really old silicon with a
228 * write-only PLL register, that we need the 32KHz when power management
229 * "wait" is enabled, and we need to detect if the 32KHz isn't present
230 * but requested......got it? :-) -- Dan
232 unsigned long cal_r4koff(void)
234 unsigned long cpu_speed;
236 unsigned long counter;
238 spin_lock_irqsave(&time_lock, flags);
240 /* Power management cares if we don't have a 32KHz counter.
243 counter = au_readl(SYS_COUNTER_CNTRL);
244 if (counter & SYS_CNTRL_E0) {
245 int trim_divide = 16;
247 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
249 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
250 /* RTC now ticks at 32.768/16 kHz */
251 au_writel(trim_divide-1, SYS_RTCTRIM);
252 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
254 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
255 au_writel (0, SYS_TOYWRITE);
256 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
258 #if defined(CONFIG_AU1000_USE32K)
260 unsigned long start, end, count;
262 start = au_readl(SYS_RTCREAD);
264 /* wait for the beginning of a new tick
266 while (au_readl(SYS_RTCREAD) < start);
268 /* Start r4k counter.
274 end = start + (32768 / trim_divide)/2;
276 while (end > au_readl(SYS_RTCREAD));
278 count = read_c0_count();
279 cpu_speed = count * 2;
282 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
287 /* The 32KHz oscillator isn't running, so assume there
288 * isn't one and grab the processor speed from the PLL.
289 * NOTE: some old silicon doesn't allow reading the PLL.
291 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
294 mips_hpt_frequency = cpu_speed;
295 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
296 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
297 spin_unlock_irqrestore(&time_lock, flags);
298 return (cpu_speed / HZ);
301 /* This is for machines which generate the exact clock. */
302 #define USECS_PER_JIFFY (1000000/HZ)
303 #define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
306 div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
309 do_div64_32(r0, v1, v2, v3);
313 static unsigned long do_fast_cp0_gettimeoffset(void)
316 unsigned long res, tmp;
319 /* Last jiffy when do_fast_gettimeoffset() was called. */
320 static unsigned long last_jiffies=0;
321 unsigned long quotient;
324 * Cached "1/(clocks per usec)*2^32" value.
325 * It has to be recalculated once each jiffy.
327 static unsigned long cached_quotient=0;
331 quotient = cached_quotient;
333 if (tmp && last_jiffies != tmp) {
335 if (last_jiffies != 0) {
336 r0 = div64_32(timerhi, timerlo, tmp);
337 quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
338 cached_quotient = quotient;
342 /* Get last timer tick in absolute kernel time */
343 count = read_c0_count();
345 /* .. relative to previous jiffy (32 bits is enough) */
348 __asm__("multu\t%1,%2\n\t"
351 : "r" (count), "r" (quotient)
352 : "hi", "lo", GCC_REG_ACCUM);
355 * Due to possible jiffies inconsistencies, we need to check
356 * the result so that we'll get a timer that is monotonic.
358 if (res >= USECS_PER_JIFFY)
359 res = USECS_PER_JIFFY-1;
365 static unsigned long do_fast_pm_gettimeoffset(void)
368 unsigned long offset;
370 pc0 = au_readl(SYS_TOYREAD);
372 offset = pc0 - last_pc0;
373 if (offset > 2*MATCH20_INC) {
374 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
375 (unsigned)offset, (unsigned)last_pc0,
376 (unsigned)last_match20, (unsigned)pc0);
378 offset = (unsigned long)((offset * 305) / 10);
383 void __init plat_timer_setup(struct irqaction *irq)
385 unsigned int est_freq;
387 printk("calculating r4koff... ");
388 r4k_offset = cal_r4koff();
389 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
391 //est_freq = 2*r4k_offset*HZ;
392 est_freq = r4k_offset*HZ;
393 est_freq += 5000; /* round */
394 est_freq -= est_freq%10000;
395 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
396 (est_freq%1000000)*100/1000000);
397 set_au1x00_speed(est_freq);
398 set_au1x00_lcd_clock(); // program the LCD clock
400 r4k_cur = (read_c0_count() + r4k_offset);
401 write_c0_compare(r4k_cur);
405 * setup counter 0, since it keeps ticking after a
406 * 'wait' instruction has been executed. The CP0 timer and
407 * counter 1 do NOT continue running after 'wait'
409 * It's too early to call request_irq() here, so we handle
410 * counter 0 interrupt as a special irq and it doesn't show
411 * up under /proc/interrupts.
413 * Check to ensure we really have a 32KHz oscillator before
416 if (no_au1xxx_32khz) {
417 unsigned int c0_status;
419 printk("WARNING: no 32KHz clock found.\n");
420 do_gettimeoffset = do_fast_cp0_gettimeoffset;
422 /* Ensure we get CPO_COUNTER interrupts.
424 c0_status = read_c0_status();
425 c0_status |= IE_IRQ5;
426 write_c0_status(c0_status);
429 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
430 au_writel(0, SYS_TOYWRITE);
431 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
433 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
434 au_writel(~0, SYS_WAKESRC);
436 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
438 /* setup match20 to interrupt once every HZ */
439 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
440 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
442 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
443 startup_match20_interrupt(counter0_irq);
445 do_gettimeoffset = do_fast_pm_gettimeoffset;
447 /* We can use the real 'wait' instruction.
453 /* We have to do this here instead of in timer_init because
454 * the generic code in arch/mips/kernel/time.c will write
455 * over our function pointer.
457 do_gettimeoffset = do_fast_cp0_gettimeoffset;
461 void __init au1xxx_time_init(void)