git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/platforms/ps3/spu.c

   1 /*
   2  *  PS3 Platform spu routines.
   3  *
   4  *  Copyright (C) 2006 Sony Computer Entertainment Inc.
   5  *  Copyright 2006 Sony Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; version 2 of the License.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/mmzone.h>
  24 #include <linux/io.h>
  25 #include <linux/mm.h>
  26
  27 #include <asm/spu.h>
  28 #include <asm/spu_priv1.h>
  29 #include <asm/lv1call.h>
  30
  31 #include "platform.h"
  32
  33 /* spu_management_ops */
  34
  35 /**
  36  * enum spe_type - Type of spe to create.
  37  * @spe_type_logical: Standard logical spe.
  38  *
  39  * For use with lv1_construct_logical_spe().  The current HV does not support
  40  * any types other than those listed.
  41  */
  42
  43 enum spe_type {
  44         SPE_TYPE_LOGICAL = 0,
  45 };
  46
  47 /**
  48  * struct spe_shadow - logical spe shadow register area.
  49  *
  50  * Read-only shadow of spe registers.
  51  */
  52
  53 struct spe_shadow {
  54         u8 padding_0140[0x0140];
  55         u64 int_status_class0_RW;       /* 0x0140 */
  56         u64 int_status_class1_RW;       /* 0x0148 */
  57         u64 int_status_class2_RW;       /* 0x0150 */
  58         u8 padding_0158[0x0610-0x0158];
  59         u64 mfc_dsisr_RW;               /* 0x0610 */
  60         u8 padding_0618[0x0620-0x0618];
  61         u64 mfc_dar_RW;                 /* 0x0620 */
  62         u8 padding_0628[0x0800-0x0628];
  63         u64 mfc_dsipr_R;                /* 0x0800 */
  64         u8 padding_0808[0x0810-0x0808];
  65         u64 mfc_lscrr_R;                /* 0x0810 */
  66         u8 padding_0818[0x0c00-0x0818];
  67         u64 mfc_cer_R;                  /* 0x0c00 */
  68         u8 padding_0c08[0x0f00-0x0c08];
  69         u64 spe_execution_status;       /* 0x0f00 */
  70         u8 padding_0f08[0x1000-0x0f08];
  71 };
  72
  73 /**
  74  * enum spe_ex_state - Logical spe execution state.
  75  * @spe_ex_state_unexecutable: Uninitialized.
  76  * @spe_ex_state_executable: Enabled, not ready.
  77  * @spe_ex_state_executed: Ready for use.
  78  *
  79  * The execution state (status) of the logical spe as reported in
  80  * struct spe_shadow:spe_execution_status.
  81  */
  82
  83 enum spe_ex_state {
  84         SPE_EX_STATE_UNEXECUTABLE = 0,
  85         SPE_EX_STATE_EXECUTABLE = 2,
  86         SPE_EX_STATE_EXECUTED = 3,
  87 };
  88
  89 /**
  90  * struct priv1_cache - Cached values of priv1 registers.
  91  * @masks[]: Array of cached spe interrupt masks, indexed by class.
  92  * @sr1: Cached mfc_sr1 register.
  93  * @tclass_id: Cached mfc_tclass_id register.
  94  */
  95
  96 struct priv1_cache {
  97         u64 masks[3];
  98         u64 sr1;
  99         u64 tclass_id;
 100 };
 101
 102 /**
 103  * struct spu_pdata - Platform state variables.
 104  * @spe_id: HV spe id returned by lv1_construct_logical_spe().
 105  * @resource_id: HV spe resource id returned by
 106  *      ps3_repository_read_spe_resource_id().
 107  * @priv2_addr: lpar address of spe priv2 area returned by
 108  *      lv1_construct_logical_spe().
 109  * @shadow_addr: lpar address of spe register shadow area returned by
 110  *      lv1_construct_logical_spe().
 111  * @shadow: Virtual (ioremap) address of spe register shadow area.
 112  * @cache: Cached values of priv1 registers.
 113  */
 114
 115 struct spu_pdata {
 116         u64 spe_id;
 117         u64 resource_id;
 118         u64 priv2_addr;
 119         u64 shadow_addr;
 120         struct spe_shadow __iomem *shadow;
 121         struct priv1_cache cache;
 122 };
 123
 124 static struct spu_pdata *spu_pdata(struct spu *spu)
 125 {
 126         return spu->pdata;
 127 }
 128
 129 #define dump_areas(_a, _b, _c, _d, _e) \
 130         _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
 131 static void _dump_areas(unsigned int spe_id, unsigned long priv2,
 132         unsigned long problem, unsigned long ls, unsigned long shadow,
 133         const char* func, int line)
 134 {
 135         pr_debug("%s:%d: spe_id:  %xh (%u)\n", func, line, spe_id, spe_id);
 136         pr_debug("%s:%d: priv2:   %lxh\n", func, line, priv2);
 137         pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
 138         pr_debug("%s:%d: ls:      %lxh\n", func, line, ls);
 139         pr_debug("%s:%d: shadow:  %lxh\n", func, line, shadow);
 140 }
 141
 142 static unsigned long get_vas_id(void)
 143 {
 144         unsigned long id;
 145
 146         lv1_get_logical_ppe_id(&id);
 147         lv1_get_virtual_address_space_id_of_ppe(id, &id);
 148
 149         return id;
 150 }
 151
 152 static int __init construct_spu(struct spu *spu)
 153 {
 154         int result;
 155         unsigned long unused;
 156
 157         result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
 158                 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
 159                 &spu_pdata(spu)->priv2_addr, &spu->problem_phys,
 160                 &spu->local_store_phys, &unused,
 161                 &spu_pdata(spu)->shadow_addr,
 162                 &spu_pdata(spu)->spe_id);
 163
 164         if (result) {
 165                 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
 166                         __func__, __LINE__, ps3_result(result));
 167                 return result;
 168         }
 169
 170         return result;
 171 }
 172
 173 static void spu_unmap(struct spu *spu)
 174 {
 175         iounmap(spu->priv2);
 176         iounmap(spu->problem);
 177         iounmap((__force u8 __iomem *)spu->local_store);
 178         iounmap(spu_pdata(spu)->shadow);
 179 }
 180
 181 static int __init setup_areas(struct spu *spu)
 182 {
 183         struct table {char* name; unsigned long addr; unsigned long size;};
 184
 185         spu_pdata(spu)->shadow = ioremap_flags(spu_pdata(spu)->shadow_addr,
 186                                                sizeof(struct spe_shadow),
 187                                                pgprot_val(PAGE_READONLY) |
 188                                                _PAGE_NO_CACHE);
 189         if (!spu_pdata(spu)->shadow) {
 190                 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
 191                 goto fail_ioremap;
 192         }
 193
 194         spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys,
 195                 LS_SIZE, _PAGE_NO_CACHE);
 196
 197         if (!spu->local_store) {
 198                 pr_debug("%s:%d: ioremap local_store failed\n",
 199                         __func__, __LINE__);
 200                 goto fail_ioremap;
 201         }
 202
 203         spu->problem = ioremap(spu->problem_phys,
 204                 sizeof(struct spu_problem));
 205
 206         if (!spu->problem) {
 207                 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
 208                 goto fail_ioremap;
 209         }
 210
 211         spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
 212                 sizeof(struct spu_priv2));
 213
 214         if (!spu->priv2) {
 215                 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
 216                 goto fail_ioremap;
 217         }
 218
 219         dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
 220                 spu->problem_phys, spu->local_store_phys,
 221                 spu_pdata(spu)->shadow_addr);
 222         dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
 223                 (unsigned long)spu->problem, (unsigned long)spu->local_store,
 224                 (unsigned long)spu_pdata(spu)->shadow);
 225
 226         return 0;
 227
 228 fail_ioremap:
 229         spu_unmap(spu);
 230
 231         return -ENOMEM;
 232 }
 233
 234 static int __init setup_interrupts(struct spu *spu)
 235 {
 236         int result;
 237
 238         result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
 239                 0, &spu->irqs[0]);
 240
 241         if (result)
 242                 goto fail_alloc_0;
 243
 244         result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
 245                 1, &spu->irqs[1]);
 246
 247         if (result)
 248                 goto fail_alloc_1;
 249
 250         result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
 251                 2, &spu->irqs[2]);
 252
 253         if (result)
 254                 goto fail_alloc_2;
 255
 256         return result;
 257
 258 fail_alloc_2:
 259         ps3_spe_irq_destroy(spu->irqs[1]);
 260 fail_alloc_1:
 261         ps3_spe_irq_destroy(spu->irqs[0]);
 262 fail_alloc_0:
 263         spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
 264         return result;
 265 }
 266
 267 static int __init enable_spu(struct spu *spu)
 268 {
 269         int result;
 270
 271         result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
 272                 spu_pdata(spu)->resource_id);
 273
 274         if (result) {
 275                 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
 276                         __func__, __LINE__, ps3_result(result));
 277                 goto fail_enable;
 278         }
 279
 280         result = setup_areas(spu);
 281
 282         if (result)
 283                 goto fail_areas;
 284
 285         result = setup_interrupts(spu);
 286
 287         if (result)
 288                 goto fail_interrupts;
 289
 290         return 0;
 291
 292 fail_interrupts:
 293         spu_unmap(spu);
 294 fail_areas:
 295         lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
 296 fail_enable:
 297         return result;
 298 }
 299
 300 static int ps3_destroy_spu(struct spu *spu)
 301 {
 302         int result;
 303
 304         pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
 305
 306         result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
 307         BUG_ON(result);
 308
 309         ps3_spe_irq_destroy(spu->irqs[2]);
 310         ps3_spe_irq_destroy(spu->irqs[1]);
 311         ps3_spe_irq_destroy(spu->irqs[0]);
 312
 313         spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
 314
 315         spu_unmap(spu);
 316
 317         result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
 318         BUG_ON(result);
 319
 320         kfree(spu->pdata);
 321         spu->pdata = NULL;
 322
 323         return 0;
 324 }
 325
 326 static int __init ps3_create_spu(struct spu *spu, void *data)
 327 {
 328         int result;
 329
 330         pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
 331
 332         spu->pdata = kzalloc(sizeof(struct spu_pdata),
 333                 GFP_KERNEL);
 334
 335         if (!spu->pdata) {
 336                 result = -ENOMEM;
 337                 goto fail_malloc;
 338         }
 339
 340         spu_pdata(spu)->resource_id = (unsigned long)data;
 341
 342         /* Init cached reg values to HV defaults. */
 343
 344         spu_pdata(spu)->cache.sr1 = 0x33;
 345
 346         result = construct_spu(spu);
 347
 348         if (result)
 349                 goto fail_construct;
 350
 351         /* For now, just go ahead and enable it. */
 352
 353         result = enable_spu(spu);
 354
 355         if (result)
 356                 goto fail_enable;
 357
 358         /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
 359
 360         /* need something better here!!! */
 361         while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
 362                 != SPE_EX_STATE_EXECUTED)
 363                 (void)0;
 364
 365         return result;
 366
 367 fail_enable:
 368 fail_construct:
 369         ps3_destroy_spu(spu);
 370 fail_malloc:
 371         return result;
 372 }
 373
 374 static int __init ps3_enumerate_spus(int (*fn)(void *data))
 375 {
 376         int result;
 377         unsigned int num_resource_id;
 378         unsigned int i;
 379
 380         result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
 381
 382         pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
 383                 num_resource_id);
 384
 385         /*
 386          * For now, just create logical spus equal to the number
 387          * of physical spus reserved for the partition.
 388          */
 389
 390         for (i = 0; i < num_resource_id; i++) {
 391                 enum ps3_spu_resource_type resource_type;
 392                 unsigned int resource_id;
 393
 394                 result = ps3_repository_read_spu_resource_id(i,
 395                         &resource_type, &resource_id);
 396
 397                 if (result)
 398                         break;
 399
 400                 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
 401                         result = fn((void*)(unsigned long)resource_id);
 402
 403                         if (result)
 404                                 break;
 405                 }
 406         }
 407
 408         if (result)
 409                 printk(KERN_WARNING "%s:%d: Error initializing spus\n",
 410                         __func__, __LINE__);
 411
 412         return result;
 413 }
 414
 415 const struct spu_management_ops spu_management_ps3_ops = {
 416         .enumerate_spus = ps3_enumerate_spus,
 417         .create_spu = ps3_create_spu,
 418         .destroy_spu = ps3_destroy_spu,
 419 };
 420
 421 /* spu_priv1_ops */
 422
 423 static void int_mask_and(struct spu *spu, int class, u64 mask)
 424 {
 425         u64 old_mask;
 426
 427         /* are these serialized by caller??? */
 428         old_mask = spu_int_mask_get(spu, class);
 429         spu_int_mask_set(spu, class, old_mask & mask);
 430 }
 431
 432 static void int_mask_or(struct spu *spu, int class, u64 mask)
 433 {
 434         u64 old_mask;
 435
 436         old_mask = spu_int_mask_get(spu, class);
 437         spu_int_mask_set(spu, class, old_mask | mask);
 438 }
 439
 440 static void int_mask_set(struct spu *spu, int class, u64 mask)
 441 {
 442         spu_pdata(spu)->cache.masks[class] = mask;
 443         lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
 444                 spu_pdata(spu)->cache.masks[class]);
 445 }
 446
 447 static u64 int_mask_get(struct spu *spu, int class)
 448 {
 449         return spu_pdata(spu)->cache.masks[class];
 450 }
 451
 452 static void int_stat_clear(struct spu *spu, int class, u64 stat)
 453 {
 454         /* Note that MFC_DSISR will be cleared when class1[MF] is set. */
 455
 456         lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
 457                 stat, 0);
 458 }
 459
 460 static u64 int_stat_get(struct spu *spu, int class)
 461 {
 462         u64 stat;
 463
 464         lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
 465         return stat;
 466 }
 467
 468 static void cpu_affinity_set(struct spu *spu, int cpu)
 469 {
 470         /* No support. */
 471 }
 472
 473 static u64 mfc_dar_get(struct spu *spu)
 474 {
 475         return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
 476 }
 477
 478 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
 479 {
 480         /* Nothing to do, cleared in int_stat_clear(). */
 481 }
 482
 483 static u64 mfc_dsisr_get(struct spu *spu)
 484 {
 485         return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
 486 }
 487
 488 static void mfc_sdr_setup(struct spu *spu)
 489 {
 490         /* Nothing to do. */
 491 }
 492
 493 static void mfc_sr1_set(struct spu *spu, u64 sr1)
 494 {
 495         /* Check bits allowed by HV. */
 496
 497         static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
 498                 | MFC_STATE1_PROBLEM_STATE_MASK);
 499
 500         BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
 501
 502         spu_pdata(spu)->cache.sr1 = sr1;
 503         lv1_set_spe_privilege_state_area_1_register(
 504                 spu_pdata(spu)->spe_id,
 505                 offsetof(struct spu_priv1, mfc_sr1_RW),
 506                 spu_pdata(spu)->cache.sr1);
 507 }
 508
 509 static u64 mfc_sr1_get(struct spu *spu)
 510 {
 511         return spu_pdata(spu)->cache.sr1;
 512 }
 513
 514 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
 515 {
 516         spu_pdata(spu)->cache.tclass_id = tclass_id;
 517         lv1_set_spe_privilege_state_area_1_register(
 518                 spu_pdata(spu)->spe_id,
 519                 offsetof(struct spu_priv1, mfc_tclass_id_RW),
 520                 spu_pdata(spu)->cache.tclass_id);
 521 }
 522
 523 static u64 mfc_tclass_id_get(struct spu *spu)
 524 {
 525         return spu_pdata(spu)->cache.tclass_id;
 526 }
 527
 528 static void tlb_invalidate(struct spu *spu)
 529 {
 530         /* Nothing to do. */
 531 }
 532
 533 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
 534 {
 535         /* No support. */
 536 }
 537
 538 static u64 resource_allocation_groupID_get(struct spu *spu)
 539 {
 540         return 0; /* No support. */
 541 }
 542
 543 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
 544 {
 545         /* No support. */
 546 }
 547
 548 static u64 resource_allocation_enable_get(struct spu *spu)
 549 {
 550         return 0; /* No support. */
 551 }
 552
 553 const struct spu_priv1_ops spu_priv1_ps3_ops = {
 554         .int_mask_and = int_mask_and,
 555         .int_mask_or = int_mask_or,
 556         .int_mask_set = int_mask_set,
 557         .int_mask_get = int_mask_get,
 558         .int_stat_clear = int_stat_clear,
 559         .int_stat_get = int_stat_get,
 560         .cpu_affinity_set = cpu_affinity_set,
 561         .mfc_dar_get = mfc_dar_get,
 562         .mfc_dsisr_set = mfc_dsisr_set,
 563         .mfc_dsisr_get = mfc_dsisr_get,
 564         .mfc_sdr_setup = mfc_sdr_setup,
 565         .mfc_sr1_set = mfc_sr1_set,
 566         .mfc_sr1_get = mfc_sr1_get,
 567         .mfc_tclass_id_set = mfc_tclass_id_set,
 568         .mfc_tclass_id_get = mfc_tclass_id_get,
 569         .tlb_invalidate = tlb_invalidate,
 570         .resource_allocation_groupID_set = resource_allocation_groupID_set,
 571         .resource_allocation_groupID_get = resource_allocation_groupID_get,
 572         .resource_allocation_enable_set = resource_allocation_enable_set,
 573         .resource_allocation_enable_get = resource_allocation_enable_get,
 574 };
 575
 576 void ps3_spu_set_platform(void)
 577 {
 578         spu_priv1_ops = &spu_priv1_ps3_ops;
 579         spu_management_ops = &spu_management_ps3_ops;
 580 }