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   1 #ifndef VMX_H
   2 #define VMX_H
   3
   4 /*
   5  * vmx.h: VMX Architecture related definitions
   6  * Copyright (c) 2004, Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  19  * Place - Suite 330, Boston, MA 02111-1307 USA.
  20  *
  21  * A few random additions are:
  22  * Copyright (C) 2006 Qumranet
  23  *    Avi Kivity <avi@qumranet.com>
  24  *    Yaniv Kamay <yaniv@qumranet.com>
  25  *
  26  */
  27
  28 /*
  29  * Definitions of Primary Processor-Based VM-Execution Controls.
  30  */
  31 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
  32 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
  33 #define CPU_BASED_HLT_EXITING                   0x00000080
  34 #define CPU_BASED_INVLPG_EXITING                0x00000200
  35 #define CPU_BASED_MWAIT_EXITING                 0x00000400
  36 #define CPU_BASED_RDPMC_EXITING                 0x00000800
  37 #define CPU_BASED_RDTSC_EXITING                 0x00001000
  38 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
  39 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
  40 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
  41 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
  42 #define CPU_BASED_TPR_SHADOW                    0x00200000
  43 #define CPU_BASED_MOV_DR_EXITING                0x00800000
  44 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
  45 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
  46 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
  47 #define CPU_BASED_MONITOR_EXITING               0x20000000
  48 #define CPU_BASED_PAUSE_EXITING                 0x40000000
  49 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
  50 /*
  51  * Definitions of Secondary Processor-Based VM-Execution Controls.
  52  */
  53 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
  54 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
  55 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
  56 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
  57
  58
  59 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
  60 #define PIN_BASED_NMI_EXITING                   0x00000008
  61 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
  62
  63 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
  64 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
  65
  66 #define VM_ENTRY_IA32E_MODE                     0x00000200
  67 #define VM_ENTRY_SMM                            0x00000400
  68 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
  69
  70 /* VMCS Encodings */
  71 enum vmcs_field {
  72         VIRTUAL_PROCESSOR_ID            = 0x00000000,
  73         GUEST_ES_SELECTOR               = 0x00000800,
  74         GUEST_CS_SELECTOR               = 0x00000802,
  75         GUEST_SS_SELECTOR               = 0x00000804,
  76         GUEST_DS_SELECTOR               = 0x00000806,
  77         GUEST_FS_SELECTOR               = 0x00000808,
  78         GUEST_GS_SELECTOR               = 0x0000080a,
  79         GUEST_LDTR_SELECTOR             = 0x0000080c,
  80         GUEST_TR_SELECTOR               = 0x0000080e,
  81         HOST_ES_SELECTOR                = 0x00000c00,
  82         HOST_CS_SELECTOR                = 0x00000c02,
  83         HOST_SS_SELECTOR                = 0x00000c04,
  84         HOST_DS_SELECTOR                = 0x00000c06,
  85         HOST_FS_SELECTOR                = 0x00000c08,
  86         HOST_GS_SELECTOR                = 0x00000c0a,
  87         HOST_TR_SELECTOR                = 0x00000c0c,
  88         IO_BITMAP_A                     = 0x00002000,
  89         IO_BITMAP_A_HIGH                = 0x00002001,
  90         IO_BITMAP_B                     = 0x00002002,
  91         IO_BITMAP_B_HIGH                = 0x00002003,
  92         MSR_BITMAP                      = 0x00002004,
  93         MSR_BITMAP_HIGH                 = 0x00002005,
  94         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
  95         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
  96         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
  97         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
  98         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
  99         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
 100         TSC_OFFSET                      = 0x00002010,
 101         TSC_OFFSET_HIGH                 = 0x00002011,
 102         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 103         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
 104         APIC_ACCESS_ADDR                = 0x00002014,
 105         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
 106         EPT_POINTER                     = 0x0000201a,
 107         EPT_POINTER_HIGH                = 0x0000201b,
 108         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 109         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 110         VMCS_LINK_POINTER               = 0x00002800,
 111         VMCS_LINK_POINTER_HIGH          = 0x00002801,
 112         GUEST_IA32_DEBUGCTL             = 0x00002802,
 113         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
 114         GUEST_PDPTR0                    = 0x0000280a,
 115         GUEST_PDPTR0_HIGH               = 0x0000280b,
 116         GUEST_PDPTR1                    = 0x0000280c,
 117         GUEST_PDPTR1_HIGH               = 0x0000280d,
 118         GUEST_PDPTR2                    = 0x0000280e,
 119         GUEST_PDPTR2_HIGH               = 0x0000280f,
 120         GUEST_PDPTR3                    = 0x00002810,
 121         GUEST_PDPTR3_HIGH               = 0x00002811,
 122         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
 123         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
 124         EXCEPTION_BITMAP                = 0x00004004,
 125         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
 126         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
 127         CR3_TARGET_COUNT                = 0x0000400a,
 128         VM_EXIT_CONTROLS                = 0x0000400c,
 129         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
 130         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
 131         VM_ENTRY_CONTROLS               = 0x00004012,
 132         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
 133         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
 134         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
 135         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
 136         TPR_THRESHOLD                   = 0x0000401c,
 137         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 138         VM_INSTRUCTION_ERROR            = 0x00004400,
 139         VM_EXIT_REASON                  = 0x00004402,
 140         VM_EXIT_INTR_INFO               = 0x00004404,
 141         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
 142         IDT_VECTORING_INFO_FIELD        = 0x00004408,
 143         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
 144         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
 145         VMX_INSTRUCTION_INFO            = 0x0000440e,
 146         GUEST_ES_LIMIT                  = 0x00004800,
 147         GUEST_CS_LIMIT                  = 0x00004802,
 148         GUEST_SS_LIMIT                  = 0x00004804,
 149         GUEST_DS_LIMIT                  = 0x00004806,
 150         GUEST_FS_LIMIT                  = 0x00004808,
 151         GUEST_GS_LIMIT                  = 0x0000480a,
 152         GUEST_LDTR_LIMIT                = 0x0000480c,
 153         GUEST_TR_LIMIT                  = 0x0000480e,
 154         GUEST_GDTR_LIMIT                = 0x00004810,
 155         GUEST_IDTR_LIMIT                = 0x00004812,
 156         GUEST_ES_AR_BYTES               = 0x00004814,
 157         GUEST_CS_AR_BYTES               = 0x00004816,
 158         GUEST_SS_AR_BYTES               = 0x00004818,
 159         GUEST_DS_AR_BYTES               = 0x0000481a,
 160         GUEST_FS_AR_BYTES               = 0x0000481c,
 161         GUEST_GS_AR_BYTES               = 0x0000481e,
 162         GUEST_LDTR_AR_BYTES             = 0x00004820,
 163         GUEST_TR_AR_BYTES               = 0x00004822,
 164         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
 165         GUEST_ACTIVITY_STATE            = 0X00004826,
 166         GUEST_SYSENTER_CS               = 0x0000482A,
 167         HOST_IA32_SYSENTER_CS           = 0x00004c00,
 168         CR0_GUEST_HOST_MASK             = 0x00006000,
 169         CR4_GUEST_HOST_MASK             = 0x00006002,
 170         CR0_READ_SHADOW                 = 0x00006004,
 171         CR4_READ_SHADOW                 = 0x00006006,
 172         CR3_TARGET_VALUE0               = 0x00006008,
 173         CR3_TARGET_VALUE1               = 0x0000600a,
 174         CR3_TARGET_VALUE2               = 0x0000600c,
 175         CR3_TARGET_VALUE3               = 0x0000600e,
 176         EXIT_QUALIFICATION              = 0x00006400,
 177         GUEST_LINEAR_ADDRESS            = 0x0000640a,
 178         GUEST_CR0                       = 0x00006800,
 179         GUEST_CR3                       = 0x00006802,
 180         GUEST_CR4                       = 0x00006804,
 181         GUEST_ES_BASE                   = 0x00006806,
 182         GUEST_CS_BASE                   = 0x00006808,
 183         GUEST_SS_BASE                   = 0x0000680a,
 184         GUEST_DS_BASE                   = 0x0000680c,
 185         GUEST_FS_BASE                   = 0x0000680e,
 186         GUEST_GS_BASE                   = 0x00006810,
 187         GUEST_LDTR_BASE                 = 0x00006812,
 188         GUEST_TR_BASE                   = 0x00006814,
 189         GUEST_GDTR_BASE                 = 0x00006816,
 190         GUEST_IDTR_BASE                 = 0x00006818,
 191         GUEST_DR7                       = 0x0000681a,
 192         GUEST_RSP                       = 0x0000681c,
 193         GUEST_RIP                       = 0x0000681e,
 194         GUEST_RFLAGS                    = 0x00006820,
 195         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
 196         GUEST_SYSENTER_ESP              = 0x00006824,
 197         GUEST_SYSENTER_EIP              = 0x00006826,
 198         HOST_CR0                        = 0x00006c00,
 199         HOST_CR3                        = 0x00006c02,
 200         HOST_CR4                        = 0x00006c04,
 201         HOST_FS_BASE                    = 0x00006c06,
 202         HOST_GS_BASE                    = 0x00006c08,
 203         HOST_TR_BASE                    = 0x00006c0a,
 204         HOST_GDTR_BASE                  = 0x00006c0c,
 205         HOST_IDTR_BASE                  = 0x00006c0e,
 206         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
 207         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
 208         HOST_RSP                        = 0x00006c14,
 209         HOST_RIP                        = 0x00006c16,
 210 };
 211
 212 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
 213
 214 #define EXIT_REASON_EXCEPTION_NMI       0
 215 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
 216 #define EXIT_REASON_TRIPLE_FAULT        2
 217
 218 #define EXIT_REASON_PENDING_INTERRUPT   7
 219
 220 #define EXIT_REASON_TASK_SWITCH         9
 221 #define EXIT_REASON_CPUID               10
 222 #define EXIT_REASON_HLT                 12
 223 #define EXIT_REASON_INVLPG              14
 224 #define EXIT_REASON_RDPMC               15
 225 #define EXIT_REASON_RDTSC               16
 226 #define EXIT_REASON_VMCALL              18
 227 #define EXIT_REASON_VMCLEAR             19
 228 #define EXIT_REASON_VMLAUNCH            20
 229 #define EXIT_REASON_VMPTRLD             21
 230 #define EXIT_REASON_VMPTRST             22
 231 #define EXIT_REASON_VMREAD              23
 232 #define EXIT_REASON_VMRESUME            24
 233 #define EXIT_REASON_VMWRITE             25
 234 #define EXIT_REASON_VMOFF               26
 235 #define EXIT_REASON_VMON                27
 236 #define EXIT_REASON_CR_ACCESS           28
 237 #define EXIT_REASON_DR_ACCESS           29
 238 #define EXIT_REASON_IO_INSTRUCTION      30
 239 #define EXIT_REASON_MSR_READ            31
 240 #define EXIT_REASON_MSR_WRITE           32
 241 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 242 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
 243 #define EXIT_REASON_APIC_ACCESS         44
 244 #define EXIT_REASON_EPT_VIOLATION       48
 245 #define EXIT_REASON_EPT_MISCONFIG       49
 246 #define EXIT_REASON_WBINVD              54
 247
 248 /*
 249  * Interruption-information format
 250  */
 251 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
 252 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
 253 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
 254 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
 255
 256 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
 257 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
 258 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
 259 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
 260
 261 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
 262 #define INTR_TYPE_EXCEPTION             (3 << 8) /* processor exception */
 263 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
 264
 265 /*
 266  * Exit Qualifications for MOV for Control Register Access
 267  */
 268 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
 269 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
 270 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
 271 #define LMSW_SOURCE_DATA_SHIFT 16
 272 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
 273 #define REG_EAX                         (0 << 8)
 274 #define REG_ECX                         (1 << 8)
 275 #define REG_EDX                         (2 << 8)
 276 #define REG_EBX                         (3 << 8)
 277 #define REG_ESP                         (4 << 8)
 278 #define REG_EBP                         (5 << 8)
 279 #define REG_ESI                         (6 << 8)
 280 #define REG_EDI                         (7 << 8)
 281 #define REG_R8                         (8 << 8)
 282 #define REG_R9                         (9 << 8)
 283 #define REG_R10                        (10 << 8)
 284 #define REG_R11                        (11 << 8)
 285 #define REG_R12                        (12 << 8)
 286 #define REG_R13                        (13 << 8)
 287 #define REG_R14                        (14 << 8)
 288 #define REG_R15                        (15 << 8)
 289
 290 /*
 291  * Exit Qualifications for MOV for Debug Register Access
 292  */
 293 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
 294 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
 295 #define TYPE_MOV_TO_DR                  (0 << 4)
 296 #define TYPE_MOV_FROM_DR                (1 << 4)
 297 #define DEBUG_REG_ACCESS_REG            0xf00   /* 11:8, general purpose reg. */
 298
 299
 300 /* segment AR */
 301 #define SEGMENT_AR_L_MASK (1 << 13)
 302
 303 #define AR_TYPE_ACCESSES_MASK 1
 304 #define AR_TYPE_READABLE_MASK (1 << 1)
 305 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
 306 #define AR_TYPE_CODE_MASK (1 << 3)
 307 #define AR_TYPE_MASK 0x0f
 308 #define AR_TYPE_BUSY_64_TSS 11
 309 #define AR_TYPE_BUSY_32_TSS 11
 310 #define AR_TYPE_BUSY_16_TSS 3
 311 #define AR_TYPE_LDT 2
 312
 313 #define AR_UNUSABLE_MASK (1 << 16)
 314 #define AR_S_MASK (1 << 4)
 315 #define AR_P_MASK (1 << 7)
 316 #define AR_L_MASK (1 << 13)
 317 #define AR_DB_MASK (1 << 14)
 318 #define AR_G_MASK (1 << 15)
 319 #define AR_DPL_SHIFT 5
 320 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
 321
 322 #define AR_RESERVD_MASK 0xfffe0f00
 323
 324 #define MSR_IA32_VMX_BASIC                      0x480
 325 #define MSR_IA32_VMX_PINBASED_CTLS              0x481
 326 #define MSR_IA32_VMX_PROCBASED_CTLS             0x482
 327 #define MSR_IA32_VMX_EXIT_CTLS                  0x483
 328 #define MSR_IA32_VMX_ENTRY_CTLS                 0x484
 329 #define MSR_IA32_VMX_MISC                       0x485
 330 #define MSR_IA32_VMX_CR0_FIXED0                 0x486
 331 #define MSR_IA32_VMX_CR0_FIXED1                 0x487
 332 #define MSR_IA32_VMX_CR4_FIXED0                 0x488
 333 #define MSR_IA32_VMX_CR4_FIXED1                 0x489
 334 #define MSR_IA32_VMX_VMCS_ENUM                  0x48a
 335 #define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
 336 #define MSR_IA32_VMX_EPT_VPID_CAP               0x48c
 337
 338 #define MSR_IA32_FEATURE_CONTROL                0x3a
 339 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
 340 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
 341
 342 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        9
 343 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      10
 344
 345 #define VMX_NR_VPIDS                            (1 << 16)
 346 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
 347 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
 348
 349 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
 350 #define VMX_EPT_EXTENT_CONTEXT                  1
 351 #define VMX_EPT_EXTENT_GLOBAL                   2
 352 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 353 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 354 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 355 #define VMX_EPT_DEFAULT_GAW                     3
 356 #define VMX_EPT_MAX_GAW                         0x4
 357 #define VMX_EPT_MT_EPTE_SHIFT                   3
 358 #define VMX_EPT_GAW_EPTP_SHIFT                  3
 359 #define VMX_EPT_DEFAULT_MT                      0x6ull
 360 #define VMX_EPT_READABLE_MASK                   0x1ull
 361 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 362 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 363 #define VMX_EPT_FAKE_ACCESSED_MASK              (1ull << 62)
 364 #define VMX_EPT_FAKE_DIRTY_MASK                 (1ull << 63)
 365
 366 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 367
 368 #endif