2 * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
4 * Copyright (C) 1997 Geert Uytterhoeven
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
10 * This is a duplicate of open_pic.c that deals with U3s MPIC on
11 * G5 PowerMacs. It's the same file except it's using big endian
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/sysdev.h>
23 #include <linux/errno.h>
24 #include <asm/ptrace.h>
25 #include <asm/signal.h>
28 #include <asm/sections.h>
29 #include <asm/open_pic.h>
30 #include <asm/i8259.h>
32 #include "open_pic_defs.h"
35 static volatile struct OpenPIC *OpenPIC2 = NULL;
37 * We define OpenPIC_InitSenses table thusly:
38 * bit 0x1: sense, 0 for edge and 1 for level.
39 * bit 0x2: polarity, 0 for negative, 1 for positive.
41 extern u_int OpenPIC_NumInitSenses;
42 extern u_char *OpenPIC_InitSenses;
43 extern int use_of_interrupt_tree;
45 static u_int NumProcessors;
46 static u_int NumSources;
47 static int open_pic2_irq_offset;
48 static volatile OpenPIC_Source *ISR[NR_IRQS];
50 /* Global Operations */
51 static void openpic2_disable_8259_pass_through(void);
52 static void openpic2_set_priority(u_int pri);
53 static void openpic2_set_spurious(u_int vector);
55 /* Timer Interrupts */
56 static void openpic2_inittimer(u_int timer, u_int pri, u_int vector);
57 static void openpic2_maptimer(u_int timer, u_int cpumask);
59 /* Interrupt Sources */
60 static void openpic2_enable_irq(u_int irq);
61 static void openpic2_disable_irq(u_int irq);
62 static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity,
64 static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask);
67 * These functions are not used but the code is kept here
68 * for completeness and future reference.
70 static void openpic2_reset(void);
72 static void openpic2_enable_8259_pass_through(void);
73 static u_int openpic2_get_priority(void);
74 static u_int openpic2_get_spurious(void);
75 static void openpic2_set_sense(u_int irq, int sense);
79 * Description of the openpic for the higher-level irq code
81 static void openpic2_end_irq(unsigned int irq_nr);
82 static void openpic2_ack_irq(unsigned int irq_nr);
84 struct hw_interrupt_type open_pic2 = {
95 * Accesses to the current processor's openpic registers
96 * On cascaded controller, this is only CPU 0
98 #define THIS_CPU Processor[0]
100 #define CHECK_THIS_CPU
103 #define check_arg_ipi(ipi) \
104 if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
105 printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi);
106 #define check_arg_timer(timer) \
107 if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
108 printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer);
109 #define check_arg_vec(vec) \
110 if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
111 printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec);
112 #define check_arg_pri(pri) \
113 if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
114 printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri);
116 * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
117 * data has probably been corrupted and we're going to panic or deadlock later
120 extern unsigned long* _get_SP(void);
121 #define check_arg_irq(irq) \
122 if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \
123 || ISR[irq - open_pic2_irq_offset] == 0) { \
124 printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \
125 /*print_backtrace(_get_SP());*/ }
126 #define check_arg_cpu(cpu) \
127 if (cpu < 0 || cpu >= NumProcessors){ \
128 printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \
129 /*print_backtrace(_get_SP());*/ }
131 #define check_arg_ipi(ipi) do {} while (0)
132 #define check_arg_timer(timer) do {} while (0)
133 #define check_arg_vec(vec) do {} while (0)
134 #define check_arg_pri(pri) do {} while (0)
135 #define check_arg_irq(irq) do {} while (0)
136 #define check_arg_cpu(cpu) do {} while (0)
139 static u_int openpic2_read(volatile u_int *addr)
147 static inline void openpic2_write(volatile u_int *addr, u_int val)
152 static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask)
154 u_int val = openpic2_read(addr);
158 inline void openpic2_writefield(volatile u_int *addr, u_int mask,
161 u_int val = openpic2_read(addr);
162 openpic2_write(addr, (val & ~mask) | (field & mask));
165 static inline void openpic2_clearfield(volatile u_int *addr, u_int mask)
167 openpic2_writefield(addr, mask, 0);
170 static inline void openpic2_setfield(volatile u_int *addr, u_int mask)
172 openpic2_writefield(addr, mask, mask);
175 static void openpic2_safe_writefield(volatile u_int *addr, u_int mask,
178 openpic2_setfield(addr, OPENPIC_MASK);
179 while (openpic2_read(addr) & OPENPIC_ACTIVITY);
180 openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
183 static void openpic2_reset(void)
185 openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
186 OPENPIC_CONFIG_RESET);
187 while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0,
188 OPENPIC_CONFIG_RESET))
192 void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR)
194 volatile OpenPIC_Source *src = first_ISR;
197 last_irq = first_irq + num_irqs;
198 if (last_irq > NumSources)
199 NumSources = last_irq;
201 src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq];
202 for (i = first_irq; i < last_irq; ++i, ++src)
207 * The `offset' parameter defines where the interrupts handled by the
208 * OpenPIC start in the space of interrupt numbers that the kernel knows
209 * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the
210 * kernel's interrupt numbering scheme.
211 * We assume there is only one OpenPIC.
213 void __init openpic2_init(int offset)
219 if (!OpenPIC2_Addr) {
220 printk("No OpenPIC2 found !\n");
223 OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr;
225 if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
227 t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0);
228 switch (t & OPENPIC_FEATURE_VERSION_MASK) {
242 NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
243 OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
245 openpic2_set_sources(0,
246 ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
247 OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
249 printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n",
250 version, NumProcessors, NumSources, OpenPIC2);
251 timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency);
253 printk("OpenPIC timer frequency is %d.%06d MHz\n",
254 timerfreq / 1000000, timerfreq % 1000000);
256 open_pic2_irq_offset = offset;
258 /* Initialize timer interrupts */
259 if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba);
260 for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
261 /* Disabled, Priority 0 */
262 openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset);
264 openpic2_maptimer(i, 0);
267 /* Initialize external interrupts */
268 if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc);
270 openpic2_set_priority(0xf);
272 /* Init all external sources, including possibly the cascade. */
273 for (i = 0; i < NumSources; i++) {
279 /* the bootloader may have left it enabled (bad !) */
280 openpic2_disable_irq(i+offset);
282 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
283 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
285 if (sense & IRQ_SENSE_MASK)
286 irq_desc[i+offset].status = IRQ_LEVEL;
288 /* Enabled, Priority 8 */
289 openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
290 (sense & IRQ_SENSE_MASK));
292 openpic2_mapirq(i, 1<<0, 0);
295 /* Init descriptors */
296 for (i = offset; i < NumSources + offset; i++)
297 irq_desc[i].handler = &open_pic2;
299 /* Initialize the spurious interrupt */
300 if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd);
301 openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset);
303 openpic2_disable_8259_pass_through();
304 openpic2_set_priority(0);
306 if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222);
310 static void openpic2_enable_8259_pass_through(void)
312 openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0,
313 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
317 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
318 static void openpic2_disable_8259_pass_through(void)
320 openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
321 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
325 * Find out the current interrupt
327 u_int openpic2_irq(void)
333 vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge,
334 OPENPIC_VECTOR_MASK);
338 void openpic2_eoi(void)
343 openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0);
344 /* Handle PCI write posting */
345 (void)openpic2_read(&OpenPIC2->THIS_CPU.EOI);
349 static u_int openpic2_get_priority(void)
354 return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
355 OPENPIC_CURRENT_TASK_PRIORITY_MASK);
359 static void __init openpic2_set_priority(u_int pri)
365 openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
366 OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
370 * Get/set the spurious vector
373 static u_int openpic2_get_spurious(void)
375 return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector,
376 OPENPIC_VECTOR_MASK);
380 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
381 static void openpic2_set_spurious(u_int vec)
384 openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
388 static DEFINE_SPINLOCK(openpic2_setup_lock);
391 * Initialize a timer interrupt (and disable it)
393 * timer: OpenPIC timer number
394 * pri: interrupt source priority
395 * vec: the vector it will produce
397 static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec)
399 check_arg_timer(timer);
402 openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority,
403 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
404 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
408 * Map a timer interrupt to one or more CPUs
410 static void __init openpic2_maptimer(u_int timer, u_int cpumask)
412 check_arg_timer(timer);
413 openpic2_write(&OpenPIC2->Global.Timer[timer].Destination,
418 * Initalize the interrupt source which will generate an NMI.
419 * This raises the interrupt's priority from 8 to 9.
421 * irq: The logical IRQ which generates an NMI.
424 openpic2_init_nmi_irq(u_int irq)
427 openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority,
428 OPENPIC_PRIORITY_MASK,
429 9 << OPENPIC_PRIORITY_SHIFT);
434 * All functions below take an offset'ed irq argument
440 * Enable/disable an external interrupt source
442 * Externally called, irq is an offseted system-wide interrupt number
444 static void openpic2_enable_irq(u_int irq)
449 vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
450 openpic2_clearfield(vpp, OPENPIC_MASK);
451 /* make sure mask gets to controller before we return to user */
453 mb(); /* sync is probably useless here */
454 } while (openpic2_readfield(vpp, OPENPIC_MASK));
457 static void openpic2_disable_irq(u_int irq)
463 vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
464 openpic2_setfield(vpp, OPENPIC_MASK);
465 /* make sure mask gets to controller before we return to user */
467 mb(); /* sync is probably useless here */
468 vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
469 } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
474 * Initialize an interrupt source (and disable it!)
476 * irq: OpenPIC interrupt number
477 * pri: interrupt source priority
478 * vec: the vector it will produce
479 * pol: polarity (1 for positive, 0 for negative)
480 * sense: 1 for level, 0 for edge
483 openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
485 openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
486 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
487 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
488 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
489 (pol ? OPENPIC_POLARITY_POSITIVE :
490 OPENPIC_POLARITY_NEGATIVE) |
491 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
495 * Map an interrupt source to one or more CPUs
497 static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask)
502 physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask;
503 openpic2_write(&ISR[irq]->Destination, physmask);
508 * Set the sense for an interrupt source (and disable it!)
510 * sense: 1 for level, 0 for edge
512 static void openpic2_set_sense(u_int irq, int sense)
515 openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
517 (sense ? OPENPIC_SENSE_LEVEL : 0));
521 /* No spinlocks, should not be necessary with the OpenPIC
522 * (1 register = 1 interrupt and we have the desc lock).
524 static void openpic2_ack_irq(unsigned int irq_nr)
526 openpic2_disable_irq(irq_nr);
530 static void openpic2_end_irq(unsigned int irq_nr)
532 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
533 openpic2_enable_irq(irq_nr);
537 openpic2_get_irq(struct pt_regs *regs)
539 int irq = openpic2_irq();
541 if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset))
549 * We implement the IRQ controller as a sysdev and put it
550 * to sleep at powerdown stage (the callback is named suspend,
551 * but it's old semantics, for the Device Model, it's really
552 * powerdown). The possible problem is that another sysdev that
553 * happens to be suspend after this one will have interrupts off,
554 * that may be an issue... For now, this isn't an issue on pmac
558 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
559 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
560 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
561 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
562 static int openpic_suspend_count;
564 static void openpic2_cached_enable_irq(u_int irq)
567 save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK;
570 static void openpic2_cached_disable_irq(u_int irq)
573 save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK;
576 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
577 * we need something better to deal with that... Maybe switch to S1 for
580 int openpic2_suspend(struct sys_device *sysdev, u32 state)
585 spin_lock_irqsave(&openpic2_setup_lock, flags);
587 if (openpic_suspend_count++ > 0) {
588 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
592 open_pic2.enable = openpic2_cached_enable_irq;
593 open_pic2.disable = openpic2_cached_disable_irq;
595 for (i=0; i<NumProcessors; i++) {
596 save_cpu_task_pri[i] = openpic2_read(&OpenPIC2->Processor[i].Current_Task_Priority);
597 openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority,
598 OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
601 for (i=0; i<OPENPIC_NUM_IPI; i++)
602 save_ipi_vp[i] = openpic2_read(&OpenPIC2->Global.IPI_Vector_Priority(i));
603 for (i=0; i<NumSources; i++) {
606 save_irq_src_vp[i] = openpic2_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
607 save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination);
610 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
615 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
616 * we need something better to deal with that... Maybe switch to S1 for
619 int openpic2_resume(struct sys_device *sysdev)
623 u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
624 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
627 spin_lock_irqsave(&openpic2_setup_lock, flags);
629 if ((--openpic_suspend_count) > 0) {
630 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
636 /* OpenPIC sometimes seem to need some time to be fully back up... */
638 openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset);
639 } while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
640 != (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset));
642 openpic2_disable_8259_pass_through();
644 for (i=0; i<OPENPIC_NUM_IPI; i++)
645 openpic2_write(&OpenPIC2->Global.IPI_Vector_Priority(i),
647 for (i=0; i<NumSources; i++) {
650 openpic2_write(&ISR[i]->Destination, save_irq_src_dest[i]);
651 openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
652 /* make sure mask gets to controller before we return to user */
654 openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
655 } while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask)
656 != (save_irq_src_vp[i] & vppmask));
658 for (i=0; i<NumProcessors; i++)
659 openpic2_write(&OpenPIC2->Processor[i].Current_Task_Priority,
660 save_cpu_task_pri[i]);
662 open_pic2.enable = openpic2_enable_irq;
663 open_pic2.disable = openpic2_disable_irq;
665 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
670 #endif /* CONFIG_PM */
673 static struct sysdev_class openpic2_sysclass = {
674 set_kset_name("openpic2"),
677 static struct sys_device device_openpic2 = {
679 .cls = &openpic2_sysclass,
682 static struct sysdev_driver driver_openpic2 = {
684 .suspend = &openpic2_suspend,
685 .resume = &openpic2_resume,
686 #endif /* CONFIG_PM */
689 static int __init init_openpic2_sysfs(void)
695 printk(KERN_DEBUG "Registering openpic2 with sysfs...\n");
696 rc = sysdev_class_register(&openpic2_sysclass);
698 printk(KERN_ERR "Failed registering openpic sys class\n");
701 rc = sysdev_register(&device_openpic2);
703 printk(KERN_ERR "Failed registering openpic sys device\n");
706 rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2);
708 printk(KERN_ERR "Failed registering openpic sys driver\n");
714 subsys_initcall(init_openpic2_sysfs);