git.oblomov.eu Git - linux-2.6/blob - drivers/mtd/nand/cafe_nand.c

   1 /*
   2  * cafe_nand.c
   3  *
   4  * Copyright © 2006 Red Hat, Inc.
   5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 //#define DEBUG
   9
  10 #include <linux/device.h>
  11 #undef DEBUG
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/nand.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <asm/io.h>
  18
  19 #define CAFE_NAND_CTRL1         0x00
  20 #define CAFE_NAND_CTRL2         0x04
  21 #define CAFE_NAND_CTRL3         0x08
  22 #define CAFE_NAND_STATUS        0x0c
  23 #define CAFE_NAND_IRQ           0x10
  24 #define CAFE_NAND_IRQ_MASK      0x14
  25 #define CAFE_NAND_DATA_LEN      0x18
  26 #define CAFE_NAND_ADDR1         0x1c
  27 #define CAFE_NAND_ADDR2         0x20
  28 #define CAFE_NAND_TIMING1       0x24
  29 #define CAFE_NAND_TIMING2       0x28
  30 #define CAFE_NAND_TIMING3       0x2c
  31 #define CAFE_NAND_NONMEM        0x30
  32 #define CAFE_NAND_DMA_CTRL      0x40
  33 #define CAFE_NAND_DMA_ADDR0     0x44
  34 #define CAFE_NAND_DMA_ADDR1     0x48
  35 #define CAFE_NAND_READ_DATA     0x1000
  36 #define CAFE_NAND_WRITE_DATA    0x2000
  37
  38 struct cafe_priv {
  39         struct nand_chip nand;
  40         struct pci_dev *pdev;
  41         void __iomem *mmio;
  42         uint32_t ctl1;
  43         uint32_t ctl2;
  44         int datalen;
  45         int nr_data;
  46         int data_pos;
  47         int page_addr;
  48         dma_addr_t dmaaddr;
  49         unsigned char *dmabuf;
  50
  51 };
  52
  53 static int usedma = 1;
  54 module_param(usedma, int, 0644);
  55
  56 static int cafe_device_ready(struct mtd_info *mtd)
  57 {
  58         struct cafe_priv *cafe = mtd->priv;
  59         int result = !!(readl(cafe->mmio + CAFE_NAND_STATUS) | 0x40000000);
  60
  61         uint32_t irqs = readl(cafe->mmio + 0x10);
  62         writel(irqs, cafe->mmio+0x10);
  63         dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
  64                 result?"":" not", irqs, readl(cafe->mmio + 0x10),
  65                 readl(cafe->mmio + 0x3008), readl(cafe->mmio + 0x300c));
  66         return result;
  67 }
  68
  69
  70 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  71 {
  72         struct cafe_priv *cafe = mtd->priv;
  73
  74         if (usedma)
  75                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
  76         else
  77                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
  78         cafe->datalen += len;
  79
  80         dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
  81                 len, cafe->datalen);
  82 }
  83
  84 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  85 {
  86         struct cafe_priv *cafe = mtd->priv;
  87
  88         if (usedma)
  89                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
  90         else
  91                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
  92
  93         dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
  94                   len, cafe->datalen);
  95         cafe->datalen += len;
  96 }
  97
  98 static uint8_t cafe_read_byte(struct mtd_info *mtd)
  99 {
 100         struct cafe_priv *cafe = mtd->priv;
 101         uint8_t d;
 102
 103         cafe_read_buf(mtd, &d, 1);
 104         dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 105
 106         return d;
 107 }
 108
 109 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 110                               int column, int page_addr)
 111 {
 112         struct cafe_priv *cafe = mtd->priv;
 113         int adrbytes = 0;
 114         uint32_t ctl1;
 115         uint32_t doneint = 0x80000000;
 116         int i;
 117
 118         dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 119                 command, column, page_addr);
 120
 121         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 122                 /* Second half of a command we already calculated */
 123                 writel(cafe->ctl2 | 0x100 | command, cafe->mmio + 0x04);
 124                 ctl1 = cafe->ctl1;
 125                 dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 126                           cafe->ctl1, cafe->nr_data);
 127                 goto do_command;
 128         }
 129         /* Reset ECC engine */
 130         writel(0, cafe->mmio + CAFE_NAND_CTRL2);
 131
 132         /* Emulate NAND_CMD_READOOB on large-page chips */
 133         if (mtd->writesize > 512 &&
 134             command == NAND_CMD_READOOB) {
 135                 column += mtd->writesize;
 136                 command = NAND_CMD_READ0;
 137         }
 138
 139         /* FIXME: Do we need to send read command before sending data
 140            for small-page chips, to position the buffer correctly? */
 141
 142         if (column != -1) {
 143                 writel(column, cafe->mmio + 0x1c);
 144                 adrbytes = 2;
 145                 if (page_addr != -1)
 146                         goto write_adr2;
 147         } else if (page_addr != -1) {
 148                 writel(page_addr & 0xffff, cafe->mmio + 0x1c);
 149                 page_addr >>= 16;
 150         write_adr2:
 151                 writel(page_addr, cafe->mmio+0x20);
 152                 adrbytes += 2;
 153                 if (mtd->size > mtd->writesize << 16)
 154                         adrbytes++;
 155         }
 156
 157         cafe->data_pos = cafe->datalen = 0;
 158
 159         /* Set command valid bit */
 160         ctl1 = 0x80000000 | command;
 161
 162         /* Set RD or WR bits as appropriate */
 163         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 164                 ctl1 |= (1<<26); /* rd */
 165                 /* Always 5 bytes, for now */
 166                 cafe->datalen = 5;
 167                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 168                 adrbytes = 1;
 169         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 170                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 171                 ctl1 |= 1<<26; /* rd */
 172                 /* For now, assume just read to end of page */
 173                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 174         } else if (command == NAND_CMD_SEQIN)
 175                 ctl1 |= 1<<25; /* wr */
 176
 177         /* Set number of address bytes */
 178         if (adrbytes)
 179                 ctl1 |= ((adrbytes-1)|8) << 27;
 180
 181         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 182                 /* Ignore the first command of a pair; the hardware
 183                    deals with them both at once, later */
 184                 cafe->ctl1 = ctl1;
 185                 cafe->ctl2 = 0;
 186                 dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 187                           cafe->ctl1, cafe->datalen);
 188                 return;
 189         }
 190         /* RNDOUT and READ0 commands need a following byte */
 191         if (command == NAND_CMD_RNDOUT)
 192                 writel(cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, cafe->mmio + CAFE_NAND_CTRL2);
 193         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 194                 writel(cafe->ctl2 | 0x100 | NAND_CMD_READSTART, cafe->mmio + CAFE_NAND_CTRL2);
 195
 196  do_command:
 197         if (cafe->datalen == 2112)
 198                 cafe->datalen = 2062;
 199         dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 200                 cafe->datalen, ctl1, readl(cafe->mmio+CAFE_NAND_CTRL2));
 201         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 202         writel(cafe->datalen, cafe->mmio + CAFE_NAND_DATA_LEN);
 203         writel(0x90000000, cafe->mmio + 0x10);
 204         if (usedma && (ctl1 & (3<<25))) {
 205                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 206                 /* If WR or RD bits set, set up DMA */
 207                 if (ctl1 & (1<<26)) {
 208                         /* It's a read */
 209                         dmactl |= (1<<29);
 210                         /* ... so it's done when the DMA is done, not just
 211                            the command. */
 212                         doneint = 0x10000000;
 213                 }
 214                 writel(dmactl, cafe->mmio + 0x40);
 215         }
 216 #if 0
 217         printk("DMA setup is %x, status %x, ctl1 %x\n", readl(cafe->mmio + 0x40), readl(cafe->mmio + 0x0c), readl(cafe->mmio));
 218         printk("DMA setup is %x, status %x, ctl1 %x\n", readl(cafe->mmio + 0x40), readl(cafe->mmio + 0x0c), readl(cafe->mmio));
 219 #endif
 220         cafe->datalen = 0;
 221
 222 #if 0
 223         printk("About to write command %08x\n", ctl1);
 224         for (i=0; i< 0x5c; i+=4)
 225                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 226 #endif
 227         writel(ctl1, cafe->mmio + CAFE_NAND_CTRL1);
 228         /* Apply this short delay always to ensure that we do wait tWB in
 229          * any case on any machine. */
 230         ndelay(100);
 231
 232         if (1) {
 233                 int c = 50000;
 234                 uint32_t irqs;
 235
 236                 while (c--) {
 237                         irqs = readl(cafe->mmio + 0x10);
 238                         if (irqs & doneint)
 239                                 break;
 240                         udelay(1);
 241                         if (!(c & 1000))
 242                         dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 243                         cpu_relax();
 244                 }
 245                 writel(doneint, cafe->mmio + 0x10);
 246                 dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", command, 50000-c, irqs, readl(cafe->mmio + 0x10));
 247         }
 248
 249
 250         cafe->ctl2 &= ~(1<<8);
 251         cafe->ctl2 &= ~(1<<30);
 252
 253         switch (command) {
 254
 255         case NAND_CMD_CACHEDPROG:
 256         case NAND_CMD_PAGEPROG:
 257         case NAND_CMD_ERASE1:
 258         case NAND_CMD_ERASE2:
 259         case NAND_CMD_SEQIN:
 260         case NAND_CMD_RNDIN:
 261         case NAND_CMD_STATUS:
 262         case NAND_CMD_DEPLETE1:
 263         case NAND_CMD_RNDOUT:
 264         case NAND_CMD_STATUS_ERROR:
 265         case NAND_CMD_STATUS_ERROR0:
 266         case NAND_CMD_STATUS_ERROR1:
 267         case NAND_CMD_STATUS_ERROR2:
 268         case NAND_CMD_STATUS_ERROR3:
 269                 writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 270                 return;
 271         }
 272         nand_wait_ready(mtd);
 273         writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 274 }
 275
 276 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 277 {
 278         //struct cafe_priv *cafe = mtd->priv;
 279         //      dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 280 }
 281 static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs)
 282 {
 283         struct mtd_info *mtd = id;
 284         struct cafe_priv *cafe = mtd->priv;
 285         uint32_t irqs = readl(cafe->mmio + 0x10);
 286         writel(irqs & ~0x90000000, cafe->mmio + 0x10);
 287         if (!irqs)
 288                 return IRQ_NONE;
 289
 290         dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, readl(cafe->mmio + 0x10));
 291         return IRQ_HANDLED;
 292 }
 293
 294 static void cafe_nand_bug(struct mtd_info *mtd)
 295 {
 296         BUG();
 297 }
 298
 299 static int cafe_nand_write_oob(struct mtd_info *mtd,
 300                                struct nand_chip *chip, int page)
 301 {
 302         int status = 0;
 303
 304         WARN_ON(chip->oob_poi != chip->buffers->oobwbuf);
 305
 306         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 307         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 308         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 309         status = chip->waitfunc(mtd, chip);
 310
 311         return status & NAND_STATUS_FAIL ? -EIO : 0;
 312 }
 313
 314 /* Don't use -- use nand_read_oob_std for now */
 315 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 316                               int page, int sndcmd)
 317 {
 318         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 319         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 320         return 1;
 321 }
 322 /**
 323  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 324  * @mtd:        mtd info structure
 325  * @chip:       nand chip info structure
 326  * @buf:        buffer to store read data
 327  *
 328  * The hw generator calculates the error syndrome automatically. Therefor
 329  * we need a special oob layout and handling.
 330  */
 331 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 332                                uint8_t *buf)
 333 {
 334         struct cafe_priv *cafe = mtd->priv;
 335
 336         WARN_ON(chip->oob_poi != chip->buffers->oobrbuf);
 337
 338         dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", readl(cafe->mmio + 0x3c), readl(cafe->mmio + 0x50));
 339
 340         chip->read_buf(mtd, buf, mtd->writesize);
 341         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 342
 343         return 0;
 344 }
 345
 346 static char foo[14];
 347 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 348                                           struct nand_chip *chip, const uint8_t *buf)
 349 {
 350         struct cafe_priv *cafe = mtd->priv;
 351
 352         WARN_ON(chip->oob_poi != chip->buffers->oobwbuf);
 353
 354         chip->write_buf(mtd, buf, mtd->writesize);
 355         chip->write_buf(mtd, foo, 14);
 356         //      chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 357
 358         /* Set up ECC autogeneration */
 359         cafe->ctl2 |= (1<<27) | (1<<30);
 360         if (mtd->writesize == 2048)
 361                 cafe->ctl2 |= (1<<29);
 362 }
 363
 364 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 365                                 const uint8_t *buf, int page, int cached, int raw)
 366 {
 367         int status;
 368
 369         WARN_ON(chip->oob_poi != chip->buffers->oobwbuf);
 370
 371         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 372
 373         if (unlikely(raw))
 374                 chip->ecc.write_page_raw(mtd, chip, buf);
 375         else
 376                 chip->ecc.write_page(mtd, chip, buf);
 377
 378         /*
 379          * Cached progamming disabled for now, Not sure if its worth the
 380          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 381          */
 382         cached = 0;
 383
 384         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 385
 386                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 387                 status = chip->waitfunc(mtd, chip);
 388                 /*
 389                  * See if operation failed and additional status checks are
 390                  * available
 391                  */
 392                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 393                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 394                                                page);
 395
 396                 if (status & NAND_STATUS_FAIL)
 397                         return -EIO;
 398         } else {
 399                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 400                 status = chip->waitfunc(mtd, chip);
 401         }
 402
 403 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 404         /* Send command to read back the data */
 405         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 406
 407         if (chip->verify_buf(mtd, buf, mtd->writesize))
 408                 return -EIO;
 409 #endif
 410         return 0;
 411 }
 412
 413
 414 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 415                                      const struct pci_device_id *ent)
 416 {
 417         struct mtd_info *mtd;
 418         struct cafe_priv *cafe;
 419         uint32_t ctrl;
 420         int err = 0;
 421
 422         err = pci_enable_device(pdev);
 423         if (err)
 424                 return err;
 425
 426         pci_set_master(pdev);
 427
 428         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 429         if (!mtd) {
 430                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 431                 return  -ENOMEM;
 432         }
 433         cafe = (void *)(&mtd[1]);
 434
 435         mtd->priv = cafe;
 436         mtd->owner = THIS_MODULE;
 437
 438         cafe->pdev = pdev;
 439         cafe->mmio = pci_iomap(pdev, 0, 0);
 440         if (!cafe->mmio) {
 441                 dev_warn(&pdev->dev, "failed to iomap\n");
 442                 err = -ENOMEM;
 443                 goto out_free_mtd;
 444         }
 445         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 446                                           &cafe->dmaaddr, GFP_KERNEL);
 447         if (!cafe->dmabuf) {
 448                 err = -ENOMEM;
 449                 goto out_ior;
 450         }
 451         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 452
 453         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 454         cafe->nand.dev_ready = cafe_device_ready;
 455         cafe->nand.read_byte = cafe_read_byte;
 456         cafe->nand.read_buf = cafe_read_buf;
 457         cafe->nand.write_buf = cafe_write_buf;
 458         cafe->nand.select_chip = cafe_select_chip;
 459
 460         cafe->nand.chip_delay = 0;
 461
 462         /* Enable the following for a flash based bad block table */
 463         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 464
 465         /* Timings from Marvell's test code (not verified or calculated by us) */
 466         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 467 #if 1
 468         writel(0x01010a0a, cafe->mmio + CAFE_NAND_TIMING1);
 469         writel(0x24121212, cafe->mmio + CAFE_NAND_TIMING2);
 470         writel(0x11000000, cafe->mmio + CAFE_NAND_TIMING3);
 471 #else
 472         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING1);
 473         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING2);
 474         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING3);
 475 #endif
 476         writel(0xdfffffff, cafe->mmio + 0x14);
 477         err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
 478         if (err) {
 479                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 480
 481                 goto out_free_dma;
 482         }
 483 #if 1
 484         /* Disable master reset, enable NAND clock */
 485         ctrl = readl(cafe->mmio + 0x3004);
 486         ctrl &= 0xffffeff0;
 487         ctrl |= 0x00007000;
 488         writel(ctrl | 0x05, cafe->mmio + 0x3004);
 489         writel(ctrl | 0x0a, cafe->mmio + 0x3004);
 490         writel(0, cafe->mmio + 0x40);
 491
 492         writel(0x7006, cafe->mmio + 0x3004);
 493         writel(0x700a, cafe->mmio + 0x3004);
 494
 495         /* Set up DMA address */
 496         writel(cafe->dmaaddr & 0xffffffff, cafe->mmio + 0x44);
 497         if (sizeof(cafe->dmaaddr) > 4)
 498                 writel((cafe->dmaaddr >> 16) >> 16, cafe->mmio + 0x48);
 499         else
 500                 writel(0, cafe->mmio + 0x48);
 501         dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 502                 readl(cafe->mmio+0x44), cafe->dmabuf);
 503
 504         /* Enable NAND IRQ in global IRQ mask register */
 505         writel(0x80000007, cafe->mmio + 0x300c);
 506         dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 507                 readl(cafe->mmio + 0x3004), readl(cafe->mmio + 0x300c));
 508 #endif
 509 #if 1
 510         mtd->writesize=2048;
 511         mtd->oobsize = 0x40;
 512         memset(cafe->dmabuf, 0xa5, 2112);
 513         cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
 514         cafe->nand.read_byte(mtd);
 515         cafe->nand.read_byte(mtd);
 516         cafe->nand.read_byte(mtd);
 517         cafe->nand.read_byte(mtd);
 518         cafe->nand.read_byte(mtd);
 519 #endif
 520 #if 0
 521         cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
 522         //      nand_wait_ready(mtd);
 523         cafe->nand.read_byte(mtd);
 524         cafe->nand.read_byte(mtd);
 525         cafe->nand.read_byte(mtd);
 526         cafe->nand.read_byte(mtd);
 527 #endif
 528 #if 0
 529         writel(0x84600070, cafe->mmio);
 530         udelay(10);
 531         dev_dbg(&cafe->pdev->dev, "Status %x\n", readl(cafe->mmio + 0x30));
 532 #endif
 533         /* Scan to find existance of the device */
 534         if (nand_scan_ident(mtd, 1)) {
 535                 err = -ENXIO;
 536                 goto out_irq;
 537         }
 538
 539         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 540         if (mtd->writesize == 2048)
 541                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 542
 543         /* Set up ECC according to the type of chip we found */
 544         if (mtd->writesize == 512 || mtd->writesize == 2048) {
 545                 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 546                 cafe->nand.ecc.size = mtd->writesize;
 547                 cafe->nand.ecc.bytes = 14;
 548                 cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 549                 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 550                 cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 551                 cafe->nand.write_page = cafe_nand_write_page;
 552                 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 553                 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 554                 cafe->nand.ecc.read_page = cafe_nand_read_page;
 555                 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 556
 557         } else {
 558                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Using software ECC\n",
 559                        mtd->writesize);
 560                 cafe->nand.ecc.mode = NAND_ECC_NONE;
 561         }
 562
 563         err = nand_scan_tail(mtd);
 564         if (err)
 565                 goto out_irq;
 566
 567
 568         pci_set_drvdata(pdev, mtd);
 569         add_mtd_device(mtd);
 570         goto out;
 571
 572  out_irq:
 573         /* Disable NAND IRQ in global IRQ mask register */
 574         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 575         free_irq(pdev->irq, mtd);
 576  out_free_dma:
 577         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 578  out_ior:
 579         pci_iounmap(pdev, cafe->mmio);
 580  out_free_mtd:
 581         kfree(mtd);
 582  out:
 583         return err;
 584 }
 585
 586 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 587 {
 588         struct mtd_info *mtd = pci_get_drvdata(pdev);
 589         struct cafe_priv *cafe = mtd->priv;
 590
 591         del_mtd_device(mtd);
 592         /* Disable NAND IRQ in global IRQ mask register */
 593         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 594         free_irq(pdev->irq, mtd);
 595         nand_release(mtd);
 596         pci_iounmap(pdev, cafe->mmio);
 597         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 598         kfree(mtd);
 599 }
 600
 601 static struct pci_device_id cafe_nand_tbl[] = {
 602         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
 603 };
 604
 605 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 606
 607 static struct pci_driver cafe_nand_pci_driver = {
 608         .name = "CAFÉ NAND",
 609         .id_table = cafe_nand_tbl,
 610         .probe = cafe_nand_probe,
 611         .remove = __devexit_p(cafe_nand_remove),
 612 #ifdef CONFIG_PMx
 613         .suspend = cafe_nand_suspend,
 614         .resume = cafe_nand_resume,
 615 #endif
 616 };
 617
 618 static int cafe_nand_init(void)
 619 {
 620         return pci_register_driver(&cafe_nand_pci_driver);
 621 }
 622
 623 static void cafe_nand_exit(void)
 624 {
 625         pci_unregister_driver(&cafe_nand_pci_driver);
 626 }
 627 module_init(cafe_nand_init);
 628 module_exit(cafe_nand_exit);
 629
 630 MODULE_LICENSE("GPL");
 631 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 632 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
 633
 634 /* Correct ECC for 2048 bytes of 0xff:
 635    41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */