2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/console.h>
25 #include <linux/backlight.h>
31 #include <asm/pci-bridge.h>
39 #ifndef CONFIG_PCI /* sanity check */
40 #error This driver requires PCI support.
43 #undef CONFIG_FB_NVIDIA_DEBUG
44 #ifdef CONFIG_FB_NVIDIA_DEBUG
45 #define NVTRACE printk
47 #define NVTRACE if (0) printk
50 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
51 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
53 #ifdef CONFIG_FB_NVIDIA_DEBUG
54 #define assert(expr) \
56 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
57 #expr,__FILE__,__FUNCTION__,__LINE__); \
64 #define PFX "nvidiafb: "
66 /* HW cursor parameters */
69 static struct pci_device_id nvidiafb_pci_tbl[] = {
70 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
71 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
74 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
76 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
77 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
78 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
79 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
80 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
81 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
82 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
83 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
84 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
85 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
86 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
87 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
88 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
90 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
92 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
94 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
96 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
97 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
98 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
100 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
102 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
104 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
106 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
108 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
110 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
112 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
114 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
116 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
118 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
120 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
122 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
124 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
126 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
128 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
130 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
132 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
134 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
136 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
138 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
140 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
142 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
144 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
148 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
150 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
152 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
154 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
156 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
158 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
160 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
164 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
166 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
168 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
170 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
172 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
174 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
176 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
180 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
182 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
184 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
186 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
188 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
190 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
192 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
194 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
196 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
198 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
200 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
202 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
204 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
206 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
208 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
210 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
212 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
214 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
216 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
218 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
220 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
222 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
224 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
226 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
228 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
230 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
232 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
234 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
236 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
238 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
240 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
242 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
244 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
246 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
248 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
250 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
252 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
254 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
256 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
258 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
260 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
262 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
264 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
266 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
268 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
270 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
272 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
274 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
276 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
278 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
280 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
282 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
284 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
286 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
288 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1,
289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
290 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1,
291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
292 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2,
293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
294 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1,
295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
296 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
298 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280,
299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
300 {PCI_VENDOR_ID_NVIDIA, 0x0252,
301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
302 {PCI_VENDOR_ID_NVIDIA, 0x0313,
303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
304 {PCI_VENDOR_ID_NVIDIA, 0x0316,
305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
306 {PCI_VENDOR_ID_NVIDIA, 0x0317,
307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
308 {PCI_VENDOR_ID_NVIDIA, 0x031D,
309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
310 {PCI_VENDOR_ID_NVIDIA, 0x031E,
311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
312 {PCI_VENDOR_ID_NVIDIA, 0x031F,
313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
314 {PCI_VENDOR_ID_NVIDIA, 0x0329,
315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
316 {PCI_VENDOR_ID_NVIDIA, 0x032F,
317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
318 {PCI_VENDOR_ID_NVIDIA, 0x0345,
319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
320 {PCI_VENDOR_ID_NVIDIA, 0x0349,
321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
322 {PCI_VENDOR_ID_NVIDIA, 0x034B,
323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
324 {PCI_VENDOR_ID_NVIDIA, 0x034F,
325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
326 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
328 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
330 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
332 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
334 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
336 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
338 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
340 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
342 {PCI_VENDOR_ID_NVIDIA, 0x0142,
343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
344 {PCI_VENDOR_ID_NVIDIA, 0x0143,
345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
346 {PCI_VENDOR_ID_NVIDIA, 0x0144,
347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
348 {PCI_VENDOR_ID_NVIDIA, 0x0145,
349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
350 {PCI_VENDOR_ID_NVIDIA, 0x0146,
351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
352 {PCI_VENDOR_ID_NVIDIA, 0x0147,
353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
354 {PCI_VENDOR_ID_NVIDIA, 0x0148,
355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
356 {PCI_VENDOR_ID_NVIDIA, 0x0149,
357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
358 {PCI_VENDOR_ID_NVIDIA, 0x014b,
359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
360 {PCI_VENDOR_ID_NVIDIA, 0x14c,
361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
362 {PCI_VENDOR_ID_NVIDIA, 0x014d,
363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
364 {PCI_VENDOR_ID_NVIDIA, 0x0160,
365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
366 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
367 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
368 {PCI_VENDOR_ID_NVIDIA, 0x0162,
369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
370 {PCI_VENDOR_ID_NVIDIA, 0x0163,
371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
372 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
374 {PCI_VENDOR_ID_NVIDIA, 0x0165,
375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
376 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
378 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
380 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
382 {PCI_VENDOR_ID_NVIDIA, 0x0169,
383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
384 {PCI_VENDOR_ID_NVIDIA, 0x016b,
385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
386 {PCI_VENDOR_ID_NVIDIA, 0x016c,
387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
388 {PCI_VENDOR_ID_NVIDIA, 0x016d,
389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
390 {PCI_VENDOR_ID_NVIDIA, 0x016e,
391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
392 {PCI_VENDOR_ID_NVIDIA, 0x0210,
393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
394 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
396 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
398 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
400 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
402 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
404 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
406 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
408 {PCI_VENDOR_ID_NVIDIA, 0x021d,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
410 {PCI_VENDOR_ID_NVIDIA, 0x021e,
411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
412 {PCI_VENDOR_ID_NVIDIA, 0x0220,
413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
414 {PCI_VENDOR_ID_NVIDIA, 0x0221,
415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
416 {PCI_VENDOR_ID_NVIDIA, 0x0222,
417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
418 {PCI_VENDOR_ID_NVIDIA, 0x0228,
419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
420 {0,} /* terminate list */
423 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
425 /* command line data, set in nvidiafb_setup() */
426 static int flatpanel __devinitdata = -1; /* Autodetect later */
427 static int fpdither __devinitdata = -1;
428 static int forceCRTC __devinitdata = -1;
429 static int hwcur __devinitdata = 0;
430 static int noaccel __devinitdata = 0;
431 static int noscale __devinitdata = 0;
432 static int paneltweak __devinitdata = 0;
433 static int vram __devinitdata = 0;
434 static int bpp __devinitdata = 8;
436 static int nomtrr __devinitdata = 0;
439 static char *mode_option __devinitdata = NULL;
441 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
442 .type = FB_TYPE_PACKED_PIXELS,
447 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
457 .activate = FB_ACTIVATE_NOW,
467 .vmode = FB_VMODE_NONINTERLACED
470 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
471 u16 bg, u16 fg, u32 w, u32 h)
473 u32 *data = (u32 *) data8;
479 for (i = 0; i < h; i++) {
483 for (j = 0; j < w / 2; j++) {
485 #if defined (__BIG_ENDIAN)
486 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
488 tmp |= (b & (1 << 31)) ? fg : bg;
491 tmp = (b & 1) ? fg : bg;
493 tmp |= (b & 1) ? fg << 16 : bg << 16;
496 NV_WR32(&par->CURSOR[k++], 0, tmp);
498 k += (MAX_CURS - w) / 2;
502 static void nvidia_write_clut(struct nvidia_par *par,
503 u8 regnum, u8 red, u8 green, u8 blue)
505 NVWriteDacMask(par, 0xff);
506 NVWriteDacWriteAddr(par, regnum);
507 NVWriteDacData(par, red);
508 NVWriteDacData(par, green);
509 NVWriteDacData(par, blue);
512 static void nvidia_read_clut(struct nvidia_par *par,
513 u8 regnum, u8 * red, u8 * green, u8 * blue)
515 NVWriteDacMask(par, 0xff);
516 NVWriteDacReadAddr(par, regnum);
517 *red = NVReadDacData(par);
518 *green = NVReadDacData(par);
519 *blue = NVReadDacData(par);
522 static int nvidia_panel_tweak(struct nvidia_par *par,
523 struct _riva_hw_state *state)
527 if (par->paneltweak) {
528 tweak = par->paneltweak;
530 /* begin flat panel hacks */
531 /* This is unfortunate, but some chips need this register
532 tweaked or else you get artifacts where adjacent pixels are
533 swapped. There are no hard rules for what to set here so all
534 we can do is experiment and apply hacks. */
536 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
537 /* At least one NV34 laptop needs this workaround. */
541 if((par->Chipset & 0xfff0) == 0x0310) {
544 /* end flat panel hacks */
550 static void nvidia_vga_protect(struct nvidia_par *par, int on)
556 * Turn off screen and disable sequencer.
558 tmp = NVReadSeq(par, 0x01);
560 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
561 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
564 * Reenable sequencer, then turn on screen.
567 tmp = NVReadSeq(par, 0x01);
569 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
570 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
574 static void nvidia_save_vga(struct nvidia_par *par,
575 struct _riva_hw_state *state)
580 NVLockUnlock(par, 0);
582 NVUnloadStateExt(par, state);
584 state->misc_output = NVReadMiscOut(par);
586 for (i = 0; i < NUM_CRT_REGS; i++)
587 state->crtc[i] = NVReadCrtc(par, i);
589 for (i = 0; i < NUM_ATC_REGS; i++)
590 state->attr[i] = NVReadAttr(par, i);
592 for (i = 0; i < NUM_GRC_REGS; i++)
593 state->gra[i] = NVReadGr(par, i);
595 for (i = 0; i < NUM_SEQ_REGS; i++)
596 state->seq[i] = NVReadSeq(par, i);
602 static void nvidia_write_regs(struct nvidia_par *par,
603 struct _riva_hw_state *state)
609 NVLoadStateExt(par, state);
611 NVWriteMiscOut(par, state->misc_output);
613 for (i = 1; i < NUM_SEQ_REGS; i++) {
615 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
617 NVWriteSeq(par, i, state->seq[i]);
620 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
621 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
623 for (i = 0; i < NUM_CRT_REGS; i++) {
630 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
632 NVWriteCrtc(par, i, state->crtc[i]);
636 for (i = 0; i < NUM_GRC_REGS; i++) {
638 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
640 NVWriteGr(par, i, state->gra[i]);
643 for (i = 0; i < NUM_ATC_REGS; i++) {
645 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
647 NVWriteAttr(par, i, state->attr[i]);
653 static int nvidia_calc_regs(struct fb_info *info)
655 struct nvidia_par *par = info->par;
656 struct _riva_hw_state *state = &par->ModeReg;
657 int i, depth = fb_get_color_depth(&info->var, &info->fix);
658 int h_display = info->var.xres / 8 - 1;
659 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
660 int h_end = (info->var.xres + info->var.right_margin +
661 info->var.hsync_len) / 8 - 1;
662 int h_total = (info->var.xres + info->var.right_margin +
663 info->var.hsync_len + info->var.left_margin) / 8 - 5;
664 int h_blank_s = h_display;
665 int h_blank_e = h_total + 4;
666 int v_display = info->var.yres - 1;
667 int v_start = info->var.yres + info->var.lower_margin - 1;
668 int v_end = (info->var.yres + info->var.lower_margin +
669 info->var.vsync_len) - 1;
670 int v_total = (info->var.yres + info->var.lower_margin +
671 info->var.vsync_len + info->var.upper_margin) - 2;
672 int v_blank_s = v_display;
673 int v_blank_e = v_total + 1;
676 * Set all CRTC values.
679 if (info->var.vmode & FB_VMODE_INTERLACED)
682 if (par->FlatPanel == 1) {
683 v_start = v_total - 3;
686 h_start = h_total - 5;
688 h_blank_e = h_total + 4;
691 state->crtc[0x0] = Set8Bits(h_total);
692 state->crtc[0x1] = Set8Bits(h_display);
693 state->crtc[0x2] = Set8Bits(h_blank_s);
694 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
696 state->crtc[0x4] = Set8Bits(h_start);
697 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
698 | SetBitField(h_end, 4: 0, 4:0);
699 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
700 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
701 | SetBitField(v_display, 8: 8, 1:1)
702 | SetBitField(v_start, 8: 8, 2:2)
703 | SetBitField(v_blank_s, 8: 8, 3:3)
705 | SetBitField(v_total, 9: 9, 5:5)
706 | SetBitField(v_display, 9: 9, 6:6)
707 | SetBitField(v_start, 9: 9, 7:7);
708 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
710 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
711 state->crtc[0x10] = Set8Bits(v_start);
712 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
713 state->crtc[0x12] = Set8Bits(v_display);
714 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
715 (info->var.bits_per_pixel / 8));
716 state->crtc[0x15] = Set8Bits(v_blank_s);
717 state->crtc[0x16] = Set8Bits(v_blank_e);
719 state->attr[0x10] = 0x01;
722 state->attr[0x11] = 0x00;
724 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
725 | SetBitField(v_blank_s, 10: 10, 3:3)
726 | SetBitField(v_start, 10: 10, 2:2)
727 | SetBitField(v_display, 10: 10, 1:1)
728 | SetBitField(v_total, 10: 10, 0:0);
730 state->horiz = SetBitField(h_total, 8: 8, 0:0)
731 | SetBitField(h_display, 8: 8, 1:1)
732 | SetBitField(h_blank_s, 8: 8, 2:2)
733 | SetBitField(h_start, 8: 8, 3:3);
735 state->extra = SetBitField(v_total, 11: 11, 0:0)
736 | SetBitField(v_display, 11: 11, 2:2)
737 | SetBitField(v_start, 11: 11, 4:4)
738 | SetBitField(v_blank_s, 11: 11, 6:6);
740 if (info->var.vmode & FB_VMODE_INTERLACED) {
741 h_total = (h_total >> 1) & ~1;
742 state->interlace = Set8Bits(h_total);
743 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
745 state->interlace = 0xff; /* interlace off */
749 * Calculate the extended registers.
757 if (par->Architecture >= NV_ARCH_10)
758 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
761 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
762 state->misc_output &= ~0x40;
764 state->misc_output |= 0x40;
765 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
766 state->misc_output &= ~0x80;
768 state->misc_output |= 0x80;
770 NVCalcStateExt(par, state, i, info->var.xres_virtual,
771 info->var.xres, info->var.yres_virtual,
772 1000000000 / info->var.pixclock, info->var.vmode);
774 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
775 if (par->FlatPanel == 1) {
776 state->pixel |= (1 << 7);
778 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
779 || (par->fpHeight <= info->var.yres)) {
780 state->scale |= (1 << 8);
783 if (!par->crtcSync_read) {
784 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
785 par->crtcSync_read = 1;
788 par->PanelTweak = nvidia_panel_tweak(par, state);
791 state->vpll = state->pll;
792 state->vpll2 = state->pll;
793 state->vpllB = state->pllB;
794 state->vpll2B = state->pllB;
796 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
797 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
799 if (par->CRTCnumber) {
800 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
801 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
802 state->crtcOwner = 3;
803 state->pllsel |= 0x20000800;
804 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
805 if (par->twoStagePLL)
806 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
807 } else if (par->twoHeads) {
808 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
809 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
810 state->crtcOwner = 0;
811 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
812 if (par->twoStagePLL)
813 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
816 state->cursorConfig = 0x00000100;
818 if (info->var.vmode & FB_VMODE_DOUBLE)
819 state->cursorConfig |= (1 << 4);
821 if (par->alphaCursor) {
822 if ((par->Chipset & 0x0ff0) != 0x0110)
823 state->cursorConfig |= 0x04011000;
825 state->cursorConfig |= 0x14011000;
826 state->general |= (1 << 29);
828 state->cursorConfig |= 0x02000000;
831 if ((par->Chipset & 0x0ff0) == 0x0110) {
832 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
835 state->dither |= 0x00010000;
837 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
845 state->displayV = info->var.xres;
850 static void nvidia_init_vga(struct fb_info *info)
852 struct nvidia_par *par = info->par;
853 struct _riva_hw_state *state = &par->ModeReg;
856 for (i = 0; i < 0x10; i++)
858 state->attr[0x10] = 0x41;
859 state->attr[0x11] = 0xff;
860 state->attr[0x12] = 0x0f;
861 state->attr[0x13] = 0x00;
862 state->attr[0x14] = 0x00;
864 memset(state->crtc, 0x00, NUM_CRT_REGS);
865 state->crtc[0x0a] = 0x20;
866 state->crtc[0x17] = 0xe3;
867 state->crtc[0x18] = 0xff;
868 state->crtc[0x28] = 0x40;
870 memset(state->gra, 0x00, NUM_GRC_REGS);
871 state->gra[0x05] = 0x40;
872 state->gra[0x06] = 0x05;
873 state->gra[0x07] = 0x0f;
874 state->gra[0x08] = 0xff;
876 state->seq[0x00] = 0x03;
877 state->seq[0x01] = 0x01;
878 state->seq[0x02] = 0x0f;
879 state->seq[0x03] = 0x00;
880 state->seq[0x04] = 0x0e;
882 state->misc_output = 0xeb;
885 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
887 struct nvidia_par *par = info->par;
888 u8 data[MAX_CURS * MAX_CURS / 8];
889 int i, set = cursor->set;
892 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
895 NVShowHideCursor(par, 0);
897 if (par->cursor_reset) {
899 par->cursor_reset = 0;
902 if (set & FB_CUR_SETSIZE)
903 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
905 if (set & FB_CUR_SETPOS) {
908 yy = cursor->image.dy - info->var.yoffset;
909 xx = cursor->image.dx - info->var.xoffset;
913 NV_WR32(par->PRAMDAC, 0x0000300, temp);
916 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
917 u32 bg_idx = cursor->image.bg_color;
918 u32 fg_idx = cursor->image.fg_color;
919 u32 s_pitch = (cursor->image.width + 7) >> 3;
920 u32 d_pitch = MAX_CURS / 8;
921 u8 *dat = (u8 *) cursor->image.data;
922 u8 *msk = (u8 *) cursor->mask;
925 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
928 switch (cursor->rop) {
930 for (i = 0; i < s_pitch * cursor->image.height; i++)
931 src[i] = dat[i] ^ msk[i];
935 for (i = 0; i < s_pitch * cursor->image.height; i++)
936 src[i] = dat[i] & msk[i];
940 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
941 cursor->image.height);
943 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
944 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
945 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
947 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
948 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
949 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
951 NVLockUnlock(par, 0);
953 nvidiafb_load_cursor_image(par, data, bg, fg,
955 cursor->image.height);
961 NVShowHideCursor(par, 1);
966 static int nvidiafb_set_par(struct fb_info *info)
968 struct nvidia_par *par = info->par;
972 NVLockUnlock(par, 1);
973 if (!par->FlatPanel || !par->twoHeads)
976 if (par->FPDither < 0) {
977 if ((par->Chipset & 0x0ff0) == 0x0110)
978 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
981 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
982 printk(KERN_INFO PFX "Flat panel dithering %s\n",
983 par->FPDither ? "enabled" : "disabled");
986 info->fix.visual = (info->var.bits_per_pixel == 8) ?
987 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
989 nvidia_init_vga(info);
990 nvidia_calc_regs(info);
992 NVLockUnlock(par, 0);
994 VGA_WR08(par->PCIO, 0x03D4, 0x44);
995 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
996 NVLockUnlock(par, 0);
999 nvidia_vga_protect(par, 1);
1001 nvidia_write_regs(par, &par->ModeReg);
1002 NVSetStartAddress(par, 0);
1004 #if defined (__BIG_ENDIAN)
1005 /* turn on LFB swapping */
1009 VGA_WR08(par->PCIO, 0x3d4, 0x46);
1010 tmp = VGA_RD08(par->PCIO, 0x3d5);
1012 VGA_WR08(par->PCIO, 0x3d5, tmp);
1016 info->fix.line_length = (info->var.xres_virtual *
1017 info->var.bits_per_pixel) >> 3;
1018 if (info->var.accel_flags) {
1019 info->fbops->fb_imageblit = nvidiafb_imageblit;
1020 info->fbops->fb_fillrect = nvidiafb_fillrect;
1021 info->fbops->fb_copyarea = nvidiafb_copyarea;
1022 info->fbops->fb_sync = nvidiafb_sync;
1023 info->pixmap.scan_align = 4;
1024 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1025 NVResetGraphics(info);
1027 info->fbops->fb_imageblit = cfb_imageblit;
1028 info->fbops->fb_fillrect = cfb_fillrect;
1029 info->fbops->fb_copyarea = cfb_copyarea;
1030 info->fbops->fb_sync = NULL;
1031 info->pixmap.scan_align = 1;
1032 info->flags |= FBINFO_HWACCEL_DISABLED;
1035 par->cursor_reset = 1;
1037 nvidia_vga_protect(par, 0);
1043 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1044 unsigned blue, unsigned transp,
1045 struct fb_info *info)
1047 struct nvidia_par *par = info->par;
1051 if (regno >= (1 << info->var.green.length))
1054 if (info->var.grayscale) {
1055 /* gray = 0.30*R + 0.59*G + 0.11*B */
1056 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1059 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1060 ((u32 *) info->pseudo_palette)[regno] =
1061 (regno << info->var.red.offset) |
1062 (regno << info->var.green.offset) |
1063 (regno << info->var.blue.offset);
1066 switch (info->var.bits_per_pixel) {
1068 /* "transparent" stuff is completely ignored. */
1069 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1072 if (info->var.green.length == 5) {
1073 for (i = 0; i < 8; i++) {
1074 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1075 green >> 8, blue >> 8);
1081 for (i = 0; i < 8; i++) {
1082 nvidia_write_clut(par, regno * 8 + i,
1083 red >> 8, green >> 8,
1088 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1090 for (i = 0; i < 4; i++)
1091 nvidia_write_clut(par, regno * 4 + i, r,
1096 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1107 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1108 struct fb_info *info)
1110 struct nvidia_par *par = info->par;
1111 int memlen, vramlen, mode_valid = 0;
1116 var->transp.offset = 0;
1117 var->transp.length = 0;
1121 if (var->bits_per_pixel <= 8)
1122 var->bits_per_pixel = 8;
1123 else if (var->bits_per_pixel <= 16)
1124 var->bits_per_pixel = 16;
1126 var->bits_per_pixel = 32;
1128 switch (var->bits_per_pixel) {
1130 var->red.offset = 0;
1131 var->red.length = 8;
1132 var->green.offset = 0;
1133 var->green.length = 8;
1134 var->blue.offset = 0;
1135 var->blue.length = 8;
1136 var->transp.offset = 0;
1137 var->transp.length = 0;
1140 var->green.length = (var->green.length < 6) ? 5 : 6;
1141 var->red.length = 5;
1142 var->blue.length = 5;
1143 var->transp.length = 6 - var->green.length;
1144 var->blue.offset = 0;
1145 var->green.offset = 5;
1146 var->red.offset = 5 + var->green.length;
1147 var->transp.offset = (5 + var->red.offset) & 15;
1149 case 32: /* RGBA 8888 */
1150 var->red.offset = 16;
1151 var->red.length = 8;
1152 var->green.offset = 8;
1153 var->green.length = 8;
1154 var->blue.offset = 0;
1155 var->blue.length = 8;
1156 var->transp.length = 8;
1157 var->transp.offset = 24;
1161 var->red.msb_right = 0;
1162 var->green.msb_right = 0;
1163 var->blue.msb_right = 0;
1164 var->transp.msb_right = 0;
1166 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1167 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1170 /* calculate modeline if supported by monitor */
1171 if (!mode_valid && info->monspecs.gtf) {
1172 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1177 struct fb_videomode *mode;
1179 mode = fb_find_best_mode(var, &info->modelist);
1181 fb_videomode_to_var(var, mode);
1186 if (!mode_valid && info->monspecs.modedb_len)
1189 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1190 par->fpHeight < var->yres))
1193 if (var->yres_virtual < var->yres)
1194 var->yres_virtual = var->yres;
1196 if (var->xres_virtual < var->xres)
1197 var->xres_virtual = var->xres;
1199 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1201 vramlen = info->screen_size;
1202 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1203 memlen = pitch * var->yres_virtual;
1205 if (memlen > vramlen) {
1206 var->yres_virtual = vramlen / pitch;
1208 if (var->yres_virtual < var->yres) {
1209 var->yres_virtual = var->yres;
1210 var->xres_virtual = vramlen / var->yres_virtual;
1211 var->xres_virtual /= var->bits_per_pixel / 8;
1212 var->xres_virtual &= ~63;
1213 pitch = (var->xres_virtual *
1214 var->bits_per_pixel + 7) / 8;
1215 memlen = pitch * var->yres;
1217 if (var->xres_virtual < var->xres) {
1218 printk("nvidiafb: required video memory, "
1219 "%d bytes, for %dx%d-%d (virtual) "
1220 "is out of range\n",
1221 memlen, var->xres_virtual,
1222 var->yres_virtual, var->bits_per_pixel);
1228 if (var->accel_flags) {
1229 if (var->yres_virtual > 0x7fff)
1230 var->yres_virtual = 0x7fff;
1231 if (var->xres_virtual > 0x7fff)
1232 var->xres_virtual = 0x7fff;
1235 var->xres_virtual &= ~63;
1242 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1243 struct fb_info *info)
1245 struct nvidia_par *par = info->par;
1248 total = var->yoffset * info->fix.line_length + var->xoffset;
1250 NVSetStartAddress(par, total);
1255 static int nvidiafb_blank(int blank, struct fb_info *info)
1257 struct nvidia_par *par = info->par;
1258 unsigned char tmp, vesa;
1260 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1261 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1269 case FB_BLANK_UNBLANK:
1270 case FB_BLANK_NORMAL:
1272 case FB_BLANK_VSYNC_SUSPEND:
1275 case FB_BLANK_HSYNC_SUSPEND:
1278 case FB_BLANK_POWERDOWN:
1283 NVWriteSeq(par, 0x01, tmp);
1284 NVWriteCrtc(par, 0x1a, vesa);
1286 #ifdef CONFIG_FB_NVIDIA_BACKLIGHT
1287 mutex_lock(&info->bl_mutex);
1289 down(&info->bl_dev->sem);
1290 info->bl_dev->props->power = blank;
1291 info->bl_dev->props->update_status(info->bl_dev);
1292 up(&info->bl_dev->sem);
1294 mutex_unlock(&info->bl_mutex);
1302 static struct fb_ops nvidia_fb_ops = {
1303 .owner = THIS_MODULE,
1304 .fb_check_var = nvidiafb_check_var,
1305 .fb_set_par = nvidiafb_set_par,
1306 .fb_setcolreg = nvidiafb_setcolreg,
1307 .fb_pan_display = nvidiafb_pan_display,
1308 .fb_blank = nvidiafb_blank,
1309 .fb_fillrect = nvidiafb_fillrect,
1310 .fb_copyarea = nvidiafb_copyarea,
1311 .fb_imageblit = nvidiafb_imageblit,
1312 .fb_cursor = nvidiafb_cursor,
1313 .fb_sync = nvidiafb_sync,
1317 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t state)
1319 struct fb_info *info = pci_get_drvdata(dev);
1320 struct nvidia_par *par = info->par;
1322 acquire_console_sem();
1323 par->pm_state = state.event;
1325 if (state.event == PM_EVENT_FREEZE) {
1326 dev->dev.power.power_state = state;
1328 fb_set_suspend(info, 1);
1329 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1330 nvidia_write_regs(par, &par->SavedReg);
1331 pci_save_state(dev);
1332 pci_disable_device(dev);
1333 pci_set_power_state(dev, pci_choose_state(dev, state));
1336 release_console_sem();
1340 static int nvidiafb_resume(struct pci_dev *dev)
1342 struct fb_info *info = pci_get_drvdata(dev);
1343 struct nvidia_par *par = info->par;
1345 acquire_console_sem();
1346 pci_set_power_state(dev, PCI_D0);
1348 if (par->pm_state != PM_EVENT_FREEZE) {
1349 pci_restore_state(dev);
1350 pci_enable_device(dev);
1351 pci_set_master(dev);
1354 par->pm_state = PM_EVENT_ON;
1355 nvidiafb_set_par(info);
1356 fb_set_suspend (info, 0);
1357 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1359 release_console_sem();
1363 #define nvidiafb_suspend NULL
1364 #define nvidiafb_resume NULL
1367 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1369 struct fb_monspecs *specs = &info->monspecs;
1370 struct fb_videomode modedb;
1371 struct nvidia_par *par = info->par;
1375 info->flags = FBINFO_DEFAULT
1376 | FBINFO_HWACCEL_IMAGEBLIT
1377 | FBINFO_HWACCEL_FILLRECT
1378 | FBINFO_HWACCEL_COPYAREA
1379 | FBINFO_HWACCEL_YPAN;
1381 fb_videomode_to_modelist(info->monspecs.modedb,
1382 info->monspecs.modedb_len, &info->modelist);
1383 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1397 if (specs->modedb != NULL) {
1398 struct fb_videomode *modedb;
1400 modedb = fb_find_best_display(specs, &info->modelist);
1401 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1402 nvidiafb_default_var.bits_per_pixel = bpp;
1403 } else if (par->fpWidth && par->fpHeight) {
1407 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1408 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1409 specs->modedb_len, &modedb, bpp);
1413 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1414 specs->modedb, specs->modedb_len, &modedb, bpp);
1416 info->var = nvidiafb_default_var;
1417 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1418 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1419 info->pseudo_palette = par->pseudo_palette;
1420 fb_alloc_cmap(&info->cmap, 256, 0);
1421 fb_destroy_modedb(info->monspecs.modedb);
1422 info->monspecs.modedb = NULL;
1424 /* maximize virtual vertical length */
1425 lpitch = info->var.xres_virtual *
1426 ((info->var.bits_per_pixel + 7) >> 3);
1427 info->var.yres_virtual = info->screen_size / lpitch;
1429 info->pixmap.scan_align = 4;
1430 info->pixmap.buf_align = 4;
1431 info->pixmap.access_align = 32;
1432 info->pixmap.size = 8 * 1024;
1433 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1436 info->fbops->fb_cursor = NULL;
1438 info->var.accel_flags = (!noaccel);
1440 switch (par->Architecture) {
1442 info->fix.accel = FB_ACCEL_NV4;
1445 info->fix.accel = FB_ACCEL_NV_10;
1448 info->fix.accel = FB_ACCEL_NV_20;
1451 info->fix.accel = FB_ACCEL_NV_30;
1454 info->fix.accel = FB_ACCEL_NV_40;
1460 return nvidiafb_check_var(&info->var, info);
1463 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1465 struct nvidia_par *par = info->par;
1466 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1468 printk("nvidiafb: PCI id - %x\n", id);
1469 if ((id & 0xfff0) == 0x00f0) {
1471 printk("nvidiafb: PCI-E card\n");
1472 id = NV_RD32(par->REGS, 0x1800);
1474 if ((id & 0x0000ffff) == 0x000010DE)
1475 id = 0x10DE0000 | (id >> 16);
1476 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1477 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1478 ((id >> 8) & 0x000000ff);
1481 printk("nvidiafb: Actual id - %x\n", id);
1485 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1487 struct nvidia_par *par = info->par;
1490 switch (par->Chipset & 0x0ff0) {
1491 case 0x0100: /* GeForce 256 */
1492 case 0x0110: /* GeForce2 MX */
1493 case 0x0150: /* GeForce2 */
1494 case 0x0170: /* GeForce4 MX */
1495 case 0x0180: /* GeForce4 MX (8x AGP) */
1496 case 0x01A0: /* nForce */
1497 case 0x01F0: /* nForce2 */
1500 case 0x0200: /* GeForce3 */
1501 case 0x0250: /* GeForce4 Ti */
1502 case 0x0280: /* GeForce4 Ti (8x AGP) */
1505 case 0x0300: /* GeForceFX 5800 */
1506 case 0x0310: /* GeForceFX 5600 */
1507 case 0x0320: /* GeForceFX 5200 */
1508 case 0x0330: /* GeForceFX 5900 */
1509 case 0x0340: /* GeForceFX 5700 */
1527 case 0x0020: /* TNT, TNT2 */
1530 default: /* unknown architecture */
1537 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1538 const struct pci_device_id *ent)
1540 struct nvidia_par *par;
1541 struct fb_info *info;
1548 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1556 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1558 if (info->pixmap.addr == NULL)
1561 memset(info->pixmap.addr, 0, 8 * 1024);
1563 if (pci_enable_device(pd)) {
1564 printk(KERN_ERR PFX "cannot enable PCI device\n");
1565 goto err_out_enable;
1568 if (pci_request_regions(pd, "nvidiafb")) {
1569 printk(KERN_ERR PFX "cannot request PCI regions\n");
1570 goto err_out_request;
1573 par->FlatPanel = flatpanel;
1575 printk(KERN_INFO PFX "flatpanel support enabled\n");
1576 par->FPDither = fpdither;
1578 par->CRTCnumber = forceCRTC;
1579 par->FpScale = (!noscale);
1580 par->paneltweak = paneltweak;
1582 /* enable IO and mem if not already done */
1583 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1584 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1585 pci_write_config_word(pd, PCI_COMMAND, cmd);
1587 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1588 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1589 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1591 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1594 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1595 goto err_out_free_base0;
1598 par->Chipset = nvidia_get_chipset(info);
1599 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1600 par->Architecture = nvidia_get_arch(info);
1602 if (par->Architecture == 0) {
1603 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1607 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1609 if (NVCommonSetup(info))
1612 par->FbAddress = nvidiafb_fix.smem_start;
1613 par->FbMapSize = par->RamAmountKBytes * 1024;
1614 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1615 par->FbMapSize = vram * 1024 * 1024;
1617 /* Limit amount of vram to 64 MB */
1618 if (par->FbMapSize > 64 * 1024 * 1024)
1619 par->FbMapSize = 64 * 1024 * 1024;
1621 if(par->Architecture >= NV_ARCH_40)
1622 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1624 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1625 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1627 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1628 par->CursorStart = par->FbUsableSize + (32 * 1024);
1630 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1631 info->screen_size = par->FbUsableSize;
1632 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1634 if (!info->screen_base) {
1635 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1636 goto err_out_free_base1;
1639 par->FbStart = info->screen_base;
1643 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1644 par->RamAmountKBytes * 1024,
1645 MTRR_TYPE_WRCOMB, 1);
1646 if (par->mtrr.vram < 0) {
1647 printk(KERN_ERR PFX "unable to setup MTRR\n");
1649 par->mtrr.vram_valid = 1;
1650 /* let there be speed */
1651 printk(KERN_INFO PFX "MTRR set to ON\n");
1654 #endif /* CONFIG_MTRR */
1656 info->fbops = &nvidia_fb_ops;
1657 info->fix = nvidiafb_fix;
1659 if (nvidia_set_fbinfo(info) < 0) {
1660 printk(KERN_ERR PFX "error setting initial video mode\n");
1661 goto err_out_iounmap_fb;
1664 nvidia_save_vga(par, &par->SavedReg);
1666 if (register_framebuffer(info) < 0) {
1667 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1668 goto err_out_iounmap_fb;
1671 pci_set_drvdata(pd, info);
1673 printk(KERN_INFO PFX
1674 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1676 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1678 nvidia_bl_init(par);
1684 iounmap(info->screen_base);
1686 fb_destroy_modedb(info->monspecs.modedb);
1687 nvidia_delete_i2c_busses(par);
1691 pci_release_regions(pd);
1693 pci_disable_device(pd);
1695 kfree(info->pixmap.addr);
1697 framebuffer_release(info);
1702 static void __exit nvidiafb_remove(struct pci_dev *pd)
1704 struct fb_info *info = pci_get_drvdata(pd);
1705 struct nvidia_par *par = info->par;
1709 nvidia_bl_exit(par);
1711 unregister_framebuffer(info);
1713 if (par->mtrr.vram_valid)
1714 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1715 info->fix.smem_len);
1716 #endif /* CONFIG_MTRR */
1718 iounmap(info->screen_base);
1719 fb_destroy_modedb(info->monspecs.modedb);
1720 nvidia_delete_i2c_busses(par);
1722 pci_release_regions(pd);
1723 pci_disable_device(pd);
1724 kfree(info->pixmap.addr);
1725 framebuffer_release(info);
1726 pci_set_drvdata(pd, NULL);
1730 /* ------------------------------------------------------------------------- *
1734 * ------------------------------------------------------------------------- */
1737 static int __devinit nvidiafb_setup(char *options)
1742 if (!options || !*options)
1745 while ((this_opt = strsep(&options, ",")) != NULL) {
1746 if (!strncmp(this_opt, "forceCRTC", 9)) {
1752 forceCRTC = *p - '0';
1753 if (forceCRTC < 0 || forceCRTC > 1)
1755 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1757 } else if (!strncmp(this_opt, "hwcur", 5)) {
1759 } else if (!strncmp(this_opt, "noaccel", 6)) {
1761 } else if (!strncmp(this_opt, "noscale", 7)) {
1763 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1764 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1765 } else if (!strncmp(this_opt, "vram:", 5)) {
1766 vram = simple_strtoul(this_opt+5, NULL, 0);
1768 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1771 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1772 fpdither = simple_strtol(this_opt+9, NULL, 0);
1773 } else if (!strncmp(this_opt, "bpp:", 4)) {
1774 bpp = simple_strtoul(this_opt+4, NULL, 0);
1776 mode_option = this_opt;
1781 #endif /* !MODULE */
1783 static struct pci_driver nvidiafb_driver = {
1785 .id_table = nvidiafb_pci_tbl,
1786 .probe = nvidiafb_probe,
1787 .suspend = nvidiafb_suspend,
1788 .resume = nvidiafb_resume,
1789 .remove = __exit_p(nvidiafb_remove),
1792 /* ------------------------------------------------------------------------- *
1796 * ------------------------------------------------------------------------- */
1798 static int __devinit nvidiafb_init(void)
1801 char *option = NULL;
1803 if (fb_get_options("nvidiafb", &option))
1805 nvidiafb_setup(option);
1807 return pci_register_driver(&nvidiafb_driver);
1810 module_init(nvidiafb_init);
1813 static void __exit nvidiafb_exit(void)
1815 pci_unregister_driver(&nvidiafb_driver);
1818 module_exit(nvidiafb_exit);
1820 module_param(flatpanel, int, 0);
1821 MODULE_PARM_DESC(flatpanel,
1822 "Enables experimental flat panel support for some chipsets. "
1823 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1824 module_param(fpdither, int, 0);
1825 MODULE_PARM_DESC(fpdither,
1826 "Enables dithering of flat panel for 6 bits panels. "
1827 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1828 module_param(hwcur, int, 0);
1829 MODULE_PARM_DESC(hwcur,
1830 "Enables hardware cursor implementation. (0 or 1=enabled) "
1832 module_param(noaccel, int, 0);
1833 MODULE_PARM_DESC(noaccel,
1834 "Disables hardware acceleration. (0 or 1=disable) "
1836 module_param(noscale, int, 0);
1837 MODULE_PARM_DESC(noscale,
1838 "Disables screen scaleing. (0 or 1=disable) "
1839 "(default=0, do scaling)");
1840 module_param(paneltweak, int, 0);
1841 MODULE_PARM_DESC(paneltweak,
1842 "Tweak display settings for flatpanels. "
1843 "(default=0, no tweaks)");
1844 module_param(forceCRTC, int, 0);
1845 MODULE_PARM_DESC(forceCRTC,
1846 "Forces usage of a particular CRTC in case autodetection "
1847 "fails. (0 or 1) (default=autodetect)");
1848 module_param(vram, int, 0);
1849 MODULE_PARM_DESC(vram,
1850 "amount of framebuffer memory to remap in MiB"
1851 "(default=0 - remap entire memory)");
1852 module_param(mode_option, charp, 0);
1853 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1854 module_param(bpp, int, 0);
1855 MODULE_PARM_DESC(bpp, "pixel width in bits"
1858 module_param(nomtrr, bool, 0);
1859 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1863 MODULE_AUTHOR("Antonino Daplas");
1864 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1865 MODULE_LICENSE("GPL");