git.oblomov.eu Git - linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "0.5"
  37 #define DRV_MODULE_RELDATE      "October 5, 2007"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return (((u64)readl(reg + 0x4UL) << 32) |
  55                 (u64)readl(reg));
  56 }
  57
  58 static void writeq(u64 val, void __iomem *reg)
  59 {
  60         writel(val & 0xffffffff, reg);
  61         writel(val >> 32, reg + 0x4UL);
  62 }
  63 #endif
  64
  65 static struct pci_device_id niu_pci_tbl[] = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  67         {}
  68 };
  69
  70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  71
  72 #define NIU_TX_TIMEOUT                  (5 * HZ)
  73
  74 #define nr64(reg)               readq(np->regs + (reg))
  75 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  76
  77 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  78 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  79
  80 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  81 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  82
  83 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  84 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  85
  86 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  87 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  88
  89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  90
  91 static int niu_debug;
  92 static int debug = -1;
  93 module_param(debug, int, 0);
  94 MODULE_PARM_DESC(debug, "NIU debug level");
  95
  96 #define niudbg(TYPE, f, a...) \
  97 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  98                 printk(KERN_DEBUG PFX f, ## a); \
  99 } while (0)
 100
 101 #define niuinfo(TYPE, f, a...) \
 102 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 103                 printk(KERN_INFO PFX f, ## a); \
 104 } while (0)
 105
 106 #define niuwarn(TYPE, f, a...) \
 107 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 108                 printk(KERN_WARNING PFX f, ## a); \
 109 } while (0)
 110
 111 #define niu_lock_parent(np, flags) \
 112         spin_lock_irqsave(&np->parent->lock, flags)
 113 #define niu_unlock_parent(np, flags) \
 114         spin_unlock_irqrestore(&np->parent->lock, flags)
 115
 116 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 117                                      u64 bits, int limit, int delay)
 118 {
 119         while (--limit >= 0) {
 120                 u64 val = nr64_mac(reg);
 121
 122                 if (!(val & bits))
 123                         break;
 124                 udelay(delay);
 125         }
 126         if (limit < 0)
 127                 return -ENODEV;
 128         return 0;
 129 }
 130
 131 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 132                                         u64 bits, int limit, int delay,
 133                                         const char *reg_name)
 134 {
 135         int err;
 136
 137         nw64_mac(reg, bits);
 138         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 139         if (err)
 140                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 141                         "would not clear, val[%llx]\n",
 142                         np->dev->name, (unsigned long long) bits, reg_name,
 143                         (unsigned long long) nr64_mac(reg));
 144         return err;
 145 }
 146
 147 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 148 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 149         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 150 })
 151
 152 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 153                                      u64 bits, int limit, int delay)
 154 {
 155         while (--limit >= 0) {
 156                 u64 val = nr64_ipp(reg);
 157
 158                 if (!(val & bits))
 159                         break;
 160                 udelay(delay);
 161         }
 162         if (limit < 0)
 163                 return -ENODEV;
 164         return 0;
 165 }
 166
 167 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 168                                         u64 bits, int limit, int delay,
 169                                         const char *reg_name)
 170 {
 171         int err;
 172         u64 val;
 173
 174         val = nr64_ipp(reg);
 175         val |= bits;
 176         nw64_ipp(reg, val);
 177
 178         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 179         if (err)
 180                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 181                         "would not clear, val[%llx]\n",
 182                         np->dev->name, (unsigned long long) bits, reg_name,
 183                         (unsigned long long) nr64_ipp(reg));
 184         return err;
 185 }
 186
 187 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 188 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 189         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 190 })
 191
 192 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 193                                  u64 bits, int limit, int delay)
 194 {
 195         while (--limit >= 0) {
 196                 u64 val = nr64(reg);
 197
 198                 if (!(val & bits))
 199                         break;
 200                 udelay(delay);
 201         }
 202         if (limit < 0)
 203                 return -ENODEV;
 204         return 0;
 205 }
 206
 207 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 208 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 209         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 210 })
 211
 212 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 213                                     u64 bits, int limit, int delay,
 214                                     const char *reg_name)
 215 {
 216         int err;
 217
 218         nw64(reg, bits);
 219         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 220         if (err)
 221                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 222                         "would not clear, val[%llx]\n",
 223                         np->dev->name, (unsigned long long) bits, reg_name,
 224                         (unsigned long long) nr64(reg));
 225         return err;
 226 }
 227
 228 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 229 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 230         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 231 })
 232
 233 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 234 {
 235         u64 val = (u64) lp->timer;
 236
 237         if (on)
 238                 val |= LDG_IMGMT_ARM;
 239
 240         nw64(LDG_IMGMT(lp->ldg_num), val);
 241 }
 242
 243 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 244 {
 245         unsigned long mask_reg, bits;
 246         u64 val;
 247
 248         if (ldn < 0 || ldn > LDN_MAX)
 249                 return -EINVAL;
 250
 251         if (ldn < 64) {
 252                 mask_reg = LD_IM0(ldn);
 253                 bits = LD_IM0_MASK;
 254         } else {
 255                 mask_reg = LD_IM1(ldn - 64);
 256                 bits = LD_IM1_MASK;
 257         }
 258
 259         val = nr64(mask_reg);
 260         if (on)
 261                 val &= ~bits;
 262         else
 263                 val |= bits;
 264         nw64(mask_reg, val);
 265
 266         return 0;
 267 }
 268
 269 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 270 {
 271         struct niu_parent *parent = np->parent;
 272         int i;
 273
 274         for (i = 0; i <= LDN_MAX; i++) {
 275                 int err;
 276
 277                 if (parent->ldg_map[i] != lp->ldg_num)
 278                         continue;
 279
 280                 err = niu_ldn_irq_enable(np, i, on);
 281                 if (err)
 282                         return err;
 283         }
 284         return 0;
 285 }
 286
 287 static int niu_enable_interrupts(struct niu *np, int on)
 288 {
 289         int i;
 290
 291         for (i = 0; i < np->num_ldg; i++) {
 292                 struct niu_ldg *lp = &np->ldg[i];
 293                 int err;
 294
 295                 err = niu_enable_ldn_in_ldg(np, lp, on);
 296                 if (err)
 297                         return err;
 298         }
 299         for (i = 0; i < np->num_ldg; i++)
 300                 niu_ldg_rearm(np, &np->ldg[i], on);
 301
 302         return 0;
 303 }
 304
 305 static u32 phy_encode(u32 type, int port)
 306 {
 307         return (type << (port * 2));
 308 }
 309
 310 static u32 phy_decode(u32 val, int port)
 311 {
 312         return (val >> (port * 2)) & PORT_TYPE_MASK;
 313 }
 314
 315 static int mdio_wait(struct niu *np)
 316 {
 317         int limit = 1000;
 318         u64 val;
 319
 320         while (--limit > 0) {
 321                 val = nr64(MIF_FRAME_OUTPUT);
 322                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 323                         return val & MIF_FRAME_OUTPUT_DATA;
 324
 325                 udelay(10);
 326         }
 327
 328         return -ENODEV;
 329 }
 330
 331 static int mdio_read(struct niu *np, int port, int dev, int reg)
 332 {
 333         int err;
 334
 335         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 336         err = mdio_wait(np);
 337         if (err < 0)
 338                 return err;
 339
 340         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 341         return mdio_wait(np);
 342 }
 343
 344 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 345 {
 346         int err;
 347
 348         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 349         err = mdio_wait(np);
 350         if (err < 0)
 351                 return err;
 352
 353         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 354         err = mdio_wait(np);
 355         if (err < 0)
 356                 return err;
 357
 358         return 0;
 359 }
 360
 361 static int mii_read(struct niu *np, int port, int reg)
 362 {
 363         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 364         return mdio_wait(np);
 365 }
 366
 367 static int mii_write(struct niu *np, int port, int reg, int data)
 368 {
 369         int err;
 370
 371         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 372         err = mdio_wait(np);
 373         if (err < 0)
 374                 return err;
 375
 376         return 0;
 377 }
 378
 379 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 380 {
 381         int err;
 382
 383         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 384                          ESR2_TI_PLL_TX_CFG_L(channel),
 385                          val & 0xffff);
 386         if (!err)
 387                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 388                                  ESR2_TI_PLL_TX_CFG_H(channel),
 389                                  val >> 16);
 390         return err;
 391 }
 392
 393 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 394 {
 395         int err;
 396
 397         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 398                          ESR2_TI_PLL_RX_CFG_L(channel),
 399                          val & 0xffff);
 400         if (!err)
 401                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 402                                  ESR2_TI_PLL_RX_CFG_H(channel),
 403                                  val >> 16);
 404         return err;
 405 }
 406
 407 /* Mode is always 10G fiber.  */
 408 static int serdes_init_niu(struct niu *np)
 409 {
 410         struct niu_link_config *lp = &np->link_config;
 411         u32 tx_cfg, rx_cfg;
 412         unsigned long i;
 413
 414         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 415         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 416                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 417                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 418
 419         if (lp->loopback_mode == LOOPBACK_PHY) {
 420                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 421
 422                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 423                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 424
 425                 tx_cfg |= PLL_TX_CFG_ENTEST;
 426                 rx_cfg |= PLL_RX_CFG_ENTEST;
 427         }
 428
 429         /* Initialize all 4 lanes of the SERDES.  */
 430         for (i = 0; i < 4; i++) {
 431                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 432                 if (err)
 433                         return err;
 434         }
 435
 436         for (i = 0; i < 4; i++) {
 437                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 438                 if (err)
 439                         return err;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 446 {
 447         int err;
 448
 449         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 450         if (err >= 0) {
 451                 *val = (err & 0xffff);
 452                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 453                                 ESR_RXTX_CTRL_H(chan));
 454                 if (err >= 0)
 455                         *val |= ((err & 0xffff) << 16);
 456                 err = 0;
 457         }
 458         return err;
 459 }
 460
 461 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 462 {
 463         int err;
 464
 465         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 466                         ESR_GLUE_CTRL0_L(chan));
 467         if (err >= 0) {
 468                 *val = (err & 0xffff);
 469                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 470                                 ESR_GLUE_CTRL0_H(chan));
 471                 if (err >= 0) {
 472                         *val |= ((err & 0xffff) << 16);
 473                         err = 0;
 474                 }
 475         }
 476         return err;
 477 }
 478
 479 static int esr_read_reset(struct niu *np, u32 *val)
 480 {
 481         int err;
 482
 483         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 484                         ESR_RXTX_RESET_CTRL_L);
 485         if (err >= 0) {
 486                 *val = (err & 0xffff);
 487                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 488                                 ESR_RXTX_RESET_CTRL_H);
 489                 if (err >= 0) {
 490                         *val |= ((err & 0xffff) << 16);
 491                         err = 0;
 492                 }
 493         }
 494         return err;
 495 }
 496
 497 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 498 {
 499         int err;
 500
 501         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 502                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 503         if (!err)
 504                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 505                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 506         return err;
 507 }
 508
 509 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 510 {
 511         int err;
 512
 513         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 514                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 515         if (!err)
 516                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 517                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 518         return err;
 519 }
 520
 521 static int esr_reset(struct niu *np)
 522 {
 523         u32 reset;
 524         int err;
 525
 526         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 527                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 528         if (err)
 529                 return err;
 530         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 531                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 532         if (err)
 533                 return err;
 534         udelay(200);
 535
 536         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 537                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 538         if (err)
 539                 return err;
 540         udelay(200);
 541
 542         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 543                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 544         if (err)
 545                 return err;
 546         udelay(200);
 547
 548         err = esr_read_reset(np, &reset);
 549         if (err)
 550                 return err;
 551         if (reset != 0) {
 552                 dev_err(np->device, PFX "Port %u ESR_RESET "
 553                         "did not clear [%08x]\n",
 554                         np->port, reset);
 555                 return -ENODEV;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int serdes_init_10g(struct niu *np)
 562 {
 563         struct niu_link_config *lp = &np->link_config;
 564         unsigned long ctrl_reg, test_cfg_reg, i;
 565         u64 ctrl_val, test_cfg_val, sig, mask, val;
 566         int err;
 567
 568         switch (np->port) {
 569         case 0:
 570                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 571                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 572                 break;
 573         case 1:
 574                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 575                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 576                 break;
 577
 578         default:
 579                 return -EINVAL;
 580         }
 581         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 582                     ENET_SERDES_CTRL_SDET_1 |
 583                     ENET_SERDES_CTRL_SDET_2 |
 584                     ENET_SERDES_CTRL_SDET_3 |
 585                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 586                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 587                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 588                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 589                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 590                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 591                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 592                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 593         test_cfg_val = 0;
 594
 595         if (lp->loopback_mode == LOOPBACK_PHY) {
 596                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 597                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 598                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 599                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 600                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 601                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 602                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 603                                   ENET_SERDES_TEST_MD_3_SHIFT));
 604         }
 605
 606         nw64(ctrl_reg, ctrl_val);
 607         nw64(test_cfg_reg, test_cfg_val);
 608
 609         /* Initialize all 4 lanes of the SERDES.  */
 610         for (i = 0; i < 4; i++) {
 611                 u32 rxtx_ctrl, glue0;
 612
 613                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 614                 if (err)
 615                         return err;
 616                 err = esr_read_glue0(np, i, &glue0);
 617                 if (err)
 618                         return err;
 619
 620                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 621                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 622                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 623
 624                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 625                            ESR_GLUE_CTRL0_THCNT |
 626                            ESR_GLUE_CTRL0_BLTIME);
 627                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 628                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 629                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 630                           (BLTIME_300_CYCLES <<
 631                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 632
 633                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 634                 if (err)
 635                         return err;
 636                 err = esr_write_glue0(np, i, glue0);
 637                 if (err)
 638                         return err;
 639         }
 640
 641         err = esr_reset(np);
 642         if (err)
 643                 return err;
 644
 645         sig = nr64(ESR_INT_SIGNALS);
 646         switch (np->port) {
 647         case 0:
 648                 mask = ESR_INT_SIGNALS_P0_BITS;
 649                 val = (ESR_INT_SRDY0_P0 |
 650                        ESR_INT_DET0_P0 |
 651                        ESR_INT_XSRDY_P0 |
 652                        ESR_INT_XDP_P0_CH3 |
 653                        ESR_INT_XDP_P0_CH2 |
 654                        ESR_INT_XDP_P0_CH1 |
 655                        ESR_INT_XDP_P0_CH0);
 656                 break;
 657
 658         case 1:
 659                 mask = ESR_INT_SIGNALS_P1_BITS;
 660                 val = (ESR_INT_SRDY0_P1 |
 661                        ESR_INT_DET0_P1 |
 662                        ESR_INT_XSRDY_P1 |
 663                        ESR_INT_XDP_P1_CH3 |
 664                        ESR_INT_XDP_P1_CH2 |
 665                        ESR_INT_XDP_P1_CH1 |
 666                        ESR_INT_XDP_P1_CH0);
 667                 break;
 668
 669         default:
 670                 return -EINVAL;
 671         }
 672
 673         if ((sig & mask) != val) {
 674                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 675                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 676                 return -ENODEV;
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int serdes_init_1g(struct niu *np)
 683 {
 684         u64 val;
 685
 686         val = nr64(ENET_SERDES_1_PLL_CFG);
 687         val &= ~ENET_SERDES_PLL_FBDIV2;
 688         switch (np->port) {
 689         case 0:
 690                 val |= ENET_SERDES_PLL_HRATE0;
 691                 break;
 692         case 1:
 693                 val |= ENET_SERDES_PLL_HRATE1;
 694                 break;
 695         case 2:
 696                 val |= ENET_SERDES_PLL_HRATE2;
 697                 break;
 698         case 3:
 699                 val |= ENET_SERDES_PLL_HRATE3;
 700                 break;
 701         default:
 702                 return -EINVAL;
 703         }
 704         nw64(ENET_SERDES_1_PLL_CFG, val);
 705
 706         return 0;
 707 }
 708
 709 static int bcm8704_reset(struct niu *np)
 710 {
 711         int err, limit;
 712
 713         err = mdio_read(np, np->phy_addr,
 714                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 715         if (err < 0)
 716                 return err;
 717         err |= BMCR_RESET;
 718         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
 719                          MII_BMCR, err);
 720         if (err)
 721                 return err;
 722
 723         limit = 1000;
 724         while (--limit >= 0) {
 725                 err = mdio_read(np, np->phy_addr,
 726                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 727                 if (err < 0)
 728                         return err;
 729                 if (!(err & BMCR_RESET))
 730                         break;
 731         }
 732         if (limit < 0) {
 733                 dev_err(np->device, PFX "Port %u PHY will not reset "
 734                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
 735                 return -ENODEV;
 736         }
 737         return 0;
 738 }
 739
 740 /* When written, certain PHY registers need to be read back twice
 741  * in order for the bits to settle properly.
 742  */
 743 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
 744 {
 745         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 746         if (err < 0)
 747                 return err;
 748         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 749         if (err < 0)
 750                 return err;
 751         return 0;
 752 }
 753
 754 static int bcm8704_init_user_dev3(struct niu *np)
 755 {
 756         int err;
 757
 758         err = mdio_write(np, np->phy_addr,
 759                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
 760                          (USER_CONTROL_OPTXRST_LVL |
 761                           USER_CONTROL_OPBIASFLT_LVL |
 762                           USER_CONTROL_OBTMPFLT_LVL |
 763                           USER_CONTROL_OPPRFLT_LVL |
 764                           USER_CONTROL_OPTXFLT_LVL |
 765                           USER_CONTROL_OPRXLOS_LVL |
 766                           USER_CONTROL_OPRXFLT_LVL |
 767                           USER_CONTROL_OPTXON_LVL |
 768                           (0x3f << USER_CONTROL_RES1_SHIFT)));
 769         if (err)
 770                 return err;
 771
 772         err = mdio_write(np, np->phy_addr,
 773                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
 774                          (USER_PMD_TX_CTL_XFP_CLKEN |
 775                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
 776                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
 777                           USER_PMD_TX_CTL_TSCK_LPWREN));
 778         if (err)
 779                 return err;
 780
 781         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
 782         if (err)
 783                 return err;
 784         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
 785         if (err)
 786                 return err;
 787
 788         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 789                         BCM8704_USER_OPT_DIGITAL_CTRL);
 790         if (err < 0)
 791                 return err;
 792         err &= ~USER_ODIG_CTRL_GPIOS;
 793         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
 794         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 795                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
 796         if (err)
 797                 return err;
 798
 799         mdelay(1000);
 800
 801         return 0;
 802 }
 803
 804 static int xcvr_init_10g(struct niu *np)
 805 {
 806         struct niu_link_config *lp = &np->link_config;
 807         u16 analog_stat0, tx_alarm_status;
 808         int err;
 809         u64 val;
 810
 811         val = nr64_mac(XMAC_CONFIG);
 812         val &= ~XMAC_CONFIG_LED_POLARITY;
 813         val |= XMAC_CONFIG_FORCE_LED_ON;
 814         nw64_mac(XMAC_CONFIG, val);
 815
 816         /* XXX shared resource, lock parent XXX */
 817         val = nr64(MIF_CONFIG);
 818         val |= MIF_CONFIG_INDIRECT_MODE;
 819         nw64(MIF_CONFIG, val);
 820
 821         err = bcm8704_reset(np);
 822         if (err)
 823                 return err;
 824
 825         err = bcm8704_init_user_dev3(np);
 826         if (err)
 827                 return err;
 828
 829         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
 830                         MII_BMCR);
 831         if (err < 0)
 832                 return err;
 833         err &= ~BMCR_LOOPBACK;
 834
 835         if (lp->loopback_mode == LOOPBACK_MAC)
 836                 err |= BMCR_LOOPBACK;
 837
 838         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
 839                          MII_BMCR, err);
 840         if (err)
 841                 return err;
 842
 843 #if 1
 844         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
 845                         MII_STAT1000);
 846         if (err < 0)
 847                 return err;
 848         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
 849                 np->port, err);
 850
 851         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
 852         if (err < 0)
 853                 return err;
 854         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
 855                 np->port, err);
 856
 857         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
 858                         MII_NWAYTEST);
 859         if (err < 0)
 860                 return err;
 861         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
 862                 np->port, err);
 863 #endif
 864
 865         /* XXX dig this out it might not be so useful XXX */
 866         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 867                         BCM8704_USER_ANALOG_STATUS0);
 868         if (err < 0)
 869                 return err;
 870         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 871                         BCM8704_USER_ANALOG_STATUS0);
 872         if (err < 0)
 873                 return err;
 874         analog_stat0 = err;
 875
 876         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 877                         BCM8704_USER_TX_ALARM_STATUS);
 878         if (err < 0)
 879                 return err;
 880         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 881                         BCM8704_USER_TX_ALARM_STATUS);
 882         if (err < 0)
 883                 return err;
 884         tx_alarm_status = err;
 885
 886         if (analog_stat0 != 0x03fc) {
 887                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
 888                         pr_info(PFX "Port %u cable not connected "
 889                                 "or bad cable.\n", np->port);
 890                 } else if (analog_stat0 == 0x639c) {
 891                         pr_info(PFX "Port %u optical module is bad "
 892                                 "or missing.\n", np->port);
 893                 }
 894         }
 895
 896         return 0;
 897 }
 898
 899 static int mii_reset(struct niu *np)
 900 {
 901         int limit, err;
 902
 903         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
 904         if (err)
 905                 return err;
 906
 907         limit = 1000;
 908         while (--limit >= 0) {
 909                 udelay(500);
 910                 err = mii_read(np, np->phy_addr, MII_BMCR);
 911                 if (err < 0)
 912                         return err;
 913                 if (!(err & BMCR_RESET))
 914                         break;
 915         }
 916         if (limit < 0) {
 917                 dev_err(np->device, PFX "Port %u MII would not reset, "
 918                         "bmcr[%04x]\n", np->port, err);
 919                 return -ENODEV;
 920         }
 921
 922         return 0;
 923 }
 924
 925 static int mii_init_common(struct niu *np)
 926 {
 927         struct niu_link_config *lp = &np->link_config;
 928         u16 bmcr, bmsr, adv, estat;
 929         int err;
 930
 931         err = mii_reset(np);
 932         if (err)
 933                 return err;
 934
 935         err = mii_read(np, np->phy_addr, MII_BMSR);
 936         if (err < 0)
 937                 return err;
 938         bmsr = err;
 939
 940         estat = 0;
 941         if (bmsr & BMSR_ESTATEN) {
 942                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
 943                 if (err < 0)
 944                         return err;
 945                 estat = err;
 946         }
 947
 948         bmcr = 0;
 949         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
 950         if (err)
 951                 return err;
 952
 953         if (lp->loopback_mode == LOOPBACK_MAC) {
 954                 bmcr |= BMCR_LOOPBACK;
 955                 if (lp->active_speed == SPEED_1000)
 956                         bmcr |= BMCR_SPEED1000;
 957                 if (lp->active_duplex == DUPLEX_FULL)
 958                         bmcr |= BMCR_FULLDPLX;
 959         }
 960
 961         if (lp->loopback_mode == LOOPBACK_PHY) {
 962                 u16 aux;
 963
 964                 aux = (BCM5464R_AUX_CTL_EXT_LB |
 965                        BCM5464R_AUX_CTL_WRITE_1);
 966                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
 967                 if (err)
 968                         return err;
 969         }
 970
 971         /* XXX configurable XXX */
 972         /* XXX for now don't advertise half-duplex or asym pause... XXX */
 973         adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
 974         if (bmsr & BMSR_10FULL)
 975                 adv |= ADVERTISE_10FULL;
 976         if (bmsr & BMSR_100FULL)
 977                 adv |= ADVERTISE_100FULL;
 978         err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
 979         if (err)
 980                 return err;
 981
 982         if (bmsr & BMSR_ESTATEN) {
 983                 u16 ctrl1000 = 0;
 984
 985                 if (estat & ESTATUS_1000_TFULL)
 986                         ctrl1000 |= ADVERTISE_1000FULL;
 987                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
 988                 if (err)
 989                         return err;
 990         }
 991         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
 992
 993         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
 994         if (err)
 995                 return err;
 996
 997         err = mii_read(np, np->phy_addr, MII_BMCR);
 998         if (err < 0)
 999                 return err;
1000         err = mii_read(np, np->phy_addr, MII_BMSR);
1001         if (err < 0)
1002                 return err;
1003 #if 0
1004         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1005                 np->port, bmcr, bmsr);
1006 #endif
1007
1008         return 0;
1009 }
1010
1011 static int xcvr_init_1g(struct niu *np)
1012 {
1013         u64 val;
1014
1015         /* XXX shared resource, lock parent XXX */
1016         val = nr64(MIF_CONFIG);
1017         val &= ~MIF_CONFIG_INDIRECT_MODE;
1018         nw64(MIF_CONFIG, val);
1019
1020         return mii_init_common(np);
1021 }
1022
1023 static int niu_xcvr_init(struct niu *np)
1024 {
1025         const struct niu_phy_ops *ops = np->phy_ops;
1026         int err;
1027
1028         err = 0;
1029         if (ops->xcvr_init)
1030                 err = ops->xcvr_init(np);
1031
1032         return err;
1033 }
1034
1035 static int niu_serdes_init(struct niu *np)
1036 {
1037         const struct niu_phy_ops *ops = np->phy_ops;
1038         int err;
1039
1040         err = 0;
1041         if (ops->serdes_init)
1042                 err = ops->serdes_init(np);
1043
1044         return err;
1045 }
1046
1047 static void niu_init_xif(struct niu *);
1048
1049 static int niu_link_status_common(struct niu *np, int link_up)
1050 {
1051         struct niu_link_config *lp = &np->link_config;
1052         struct net_device *dev = np->dev;
1053         unsigned long flags;
1054
1055         if (!netif_carrier_ok(dev) && link_up) {
1056                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1057                        dev->name,
1058                        (lp->active_speed == SPEED_10000 ?
1059                         "10Gb/sec" :
1060                         (lp->active_speed == SPEED_1000 ?
1061                          "1Gb/sec" :
1062                          (lp->active_speed == SPEED_100 ?
1063                           "100Mbit/sec" : "10Mbit/sec"))),
1064                        (lp->active_duplex == DUPLEX_FULL ?
1065                         "full" : "half"));
1066
1067                 spin_lock_irqsave(&np->lock, flags);
1068                 niu_init_xif(np);
1069                 spin_unlock_irqrestore(&np->lock, flags);
1070
1071                 netif_carrier_on(dev);
1072         } else if (netif_carrier_ok(dev) && !link_up) {
1073                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1074                 netif_carrier_off(dev);
1075         }
1076
1077         return 0;
1078 }
1079
1080 static int link_status_10g(struct niu *np, int *link_up_p)
1081 {
1082         unsigned long flags;
1083         int err, link_up;
1084
1085         link_up = 0;
1086
1087         spin_lock_irqsave(&np->lock, flags);
1088
1089         err = -EINVAL;
1090         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1091                 goto out;
1092
1093         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1094                         BCM8704_PMD_RCV_SIGDET);
1095         if (err < 0)
1096                 goto out;
1097         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1098                 err = 0;
1099                 goto out;
1100         }
1101
1102         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1103                         BCM8704_PCS_10G_R_STATUS);
1104         if (err < 0)
1105                 goto out;
1106         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1107                 err = 0;
1108                 goto out;
1109         }
1110
1111         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1112                         BCM8704_PHYXS_XGXS_LANE_STAT);
1113         if (err < 0)
1114                 goto out;
1115
1116         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1117                     PHYXS_XGXS_LANE_STAT_MAGIC |
1118                     PHYXS_XGXS_LANE_STAT_LANE3 |
1119                     PHYXS_XGXS_LANE_STAT_LANE2 |
1120                     PHYXS_XGXS_LANE_STAT_LANE1 |
1121                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1122                 err = 0;
1123                 goto out;
1124         }
1125
1126         link_up = 1;
1127         np->link_config.active_speed = SPEED_10000;
1128         np->link_config.active_duplex = DUPLEX_FULL;
1129         err = 0;
1130
1131 out:
1132         spin_unlock_irqrestore(&np->lock, flags);
1133
1134         *link_up_p = link_up;
1135         return err;
1136 }
1137
1138 static int link_status_1g(struct niu *np, int *link_up_p)
1139 {
1140         u16 current_speed, bmsr;
1141         unsigned long flags;
1142         u8 current_duplex;
1143         int err, link_up;
1144
1145         link_up = 0;
1146         current_speed = SPEED_INVALID;
1147         current_duplex = DUPLEX_INVALID;
1148
1149         spin_lock_irqsave(&np->lock, flags);
1150
1151         err = -EINVAL;
1152         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1153                 goto out;
1154
1155         err = mii_read(np, np->phy_addr, MII_BMSR);
1156         if (err < 0)
1157                 goto out;
1158
1159         bmsr = err;
1160         if (bmsr & BMSR_LSTATUS) {
1161                 u16 adv, lpa, common, estat;
1162
1163                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1164                 if (err < 0)
1165                         goto out;
1166                 adv = err;
1167
1168                 err = mii_read(np, np->phy_addr, MII_LPA);
1169                 if (err < 0)
1170                         goto out;
1171                 lpa = err;
1172
1173                 common = adv & lpa;
1174
1175                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1176                 if (err < 0)
1177                         goto out;
1178                 estat = err;
1179
1180                 link_up = 1;
1181                 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1182                         current_speed = SPEED_1000;
1183                         if (estat & ESTATUS_1000_TFULL)
1184                                 current_duplex = DUPLEX_FULL;
1185                         else
1186                                 current_duplex = DUPLEX_HALF;
1187                 } else {
1188                         if (common & ADVERTISE_100BASE4) {
1189                                 current_speed = SPEED_100;
1190                                 current_duplex = DUPLEX_HALF;
1191                         } else if (common & ADVERTISE_100FULL) {
1192                                 current_speed = SPEED_100;
1193                                 current_duplex = DUPLEX_FULL;
1194                         } else if (common & ADVERTISE_100HALF) {
1195                                 current_speed = SPEED_100;
1196                                 current_duplex = DUPLEX_HALF;
1197                         } else if (common & ADVERTISE_10FULL) {
1198                                 current_speed = SPEED_10;
1199                                 current_duplex = DUPLEX_FULL;
1200                         } else if (common & ADVERTISE_10HALF) {
1201                                 current_speed = SPEED_10;
1202                                 current_duplex = DUPLEX_HALF;
1203                         } else
1204                                 link_up = 0;
1205                 }
1206         }
1207         err = 0;
1208
1209 out:
1210         spin_unlock_irqrestore(&np->lock, flags);
1211
1212         *link_up_p = link_up;
1213         return err;
1214 }
1215
1216 static int niu_link_status(struct niu *np, int *link_up_p)
1217 {
1218         const struct niu_phy_ops *ops = np->phy_ops;
1219         int err;
1220
1221         err = 0;
1222         if (ops->link_status)
1223                 err = ops->link_status(np, link_up_p);
1224
1225         return err;
1226 }
1227
1228 static void niu_timer(unsigned long __opaque)
1229 {
1230         struct niu *np = (struct niu *) __opaque;
1231         unsigned long off;
1232         int err, link_up;
1233
1234         err = niu_link_status(np, &link_up);
1235         if (!err)
1236                 niu_link_status_common(np, link_up);
1237
1238         if (netif_carrier_ok(np->dev))
1239                 off = 5 * HZ;
1240         else
1241                 off = 1 * HZ;
1242         np->timer.expires = jiffies + off;
1243
1244         add_timer(&np->timer);
1245 }
1246
1247 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1248         .serdes_init            = serdes_init_niu,
1249         .xcvr_init              = xcvr_init_10g,
1250         .link_status            = link_status_10g,
1251 };
1252
1253 static const struct niu_phy_ops phy_ops_10g_fiber = {
1254         .serdes_init            = serdes_init_10g,
1255         .xcvr_init              = xcvr_init_10g,
1256         .link_status            = link_status_10g,
1257 };
1258
1259 static const struct niu_phy_ops phy_ops_10g_copper = {
1260         .serdes_init            = serdes_init_10g,
1261         .link_status            = link_status_10g, /* XXX */
1262 };
1263
1264 static const struct niu_phy_ops phy_ops_1g_fiber = {
1265         .serdes_init            = serdes_init_1g,
1266         .xcvr_init              = xcvr_init_1g,
1267         .link_status            = link_status_1g,
1268 };
1269
1270 static const struct niu_phy_ops phy_ops_1g_copper = {
1271         .xcvr_init              = xcvr_init_1g,
1272         .link_status            = link_status_1g,
1273 };
1274
1275 struct niu_phy_template {
1276         const struct niu_phy_ops        *ops;
1277         u32                             phy_addr_base;
1278 };
1279
1280 static const struct niu_phy_template phy_template_niu = {
1281         .ops            = &phy_ops_10g_fiber_niu,
1282         .phy_addr_base  = 16,
1283 };
1284
1285 static const struct niu_phy_template phy_template_10g_fiber = {
1286         .ops            = &phy_ops_10g_fiber,
1287         .phy_addr_base  = 8,
1288 };
1289
1290 static const struct niu_phy_template phy_template_10g_copper = {
1291         .ops            = &phy_ops_10g_copper,
1292         .phy_addr_base  = 10,
1293 };
1294
1295 static const struct niu_phy_template phy_template_1g_fiber = {
1296         .ops            = &phy_ops_1g_fiber,
1297         .phy_addr_base  = 0,
1298 };
1299
1300 static const struct niu_phy_template phy_template_1g_copper = {
1301         .ops            = &phy_ops_1g_copper,
1302         .phy_addr_base  = 0,
1303 };
1304
1305 static int niu_determine_phy_disposition(struct niu *np)
1306 {
1307         struct niu_parent *parent = np->parent;
1308         u8 plat_type = parent->plat_type;
1309         const struct niu_phy_template *tp;
1310         u32 phy_addr_off = 0;
1311
1312         if (plat_type == PLAT_TYPE_NIU) {
1313                 tp = &phy_template_niu;
1314                 phy_addr_off += np->port;
1315         } else {
1316                 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
1317                 case 0:
1318                         /* 1G copper */
1319                         tp = &phy_template_1g_copper;
1320                         if (plat_type == PLAT_TYPE_VF_P0)
1321                                 phy_addr_off = 10;
1322                         else if (plat_type == PLAT_TYPE_VF_P1)
1323                                 phy_addr_off = 26;
1324
1325                         phy_addr_off += (np->port ^ 0x3);
1326                         break;
1327
1328                 case NIU_FLAGS_10G:
1329                         /* 10G copper */
1330                         tp = &phy_template_1g_copper;
1331                         break;
1332
1333                 case NIU_FLAGS_FIBER:
1334                         /* 1G fiber */
1335                         tp = &phy_template_1g_fiber;
1336                         break;
1337
1338                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1339                         /* 10G fiber */
1340                         tp = &phy_template_10g_fiber;
1341                         if (plat_type == PLAT_TYPE_VF_P0 ||
1342                             plat_type == PLAT_TYPE_VF_P1)
1343                                 phy_addr_off = 8;
1344                         phy_addr_off += np->port;
1345                         break;
1346
1347                 default:
1348                         return -EINVAL;
1349                 }
1350         }
1351
1352         np->phy_ops = tp->ops;
1353         np->phy_addr = tp->phy_addr_base + phy_addr_off;
1354
1355         return 0;
1356 }
1357
1358 static int niu_init_link(struct niu *np)
1359 {
1360         struct niu_parent *parent = np->parent;
1361         int err, ignore;
1362
1363         if (parent->plat_type == PLAT_TYPE_NIU) {
1364                 err = niu_xcvr_init(np);
1365                 if (err)
1366                         return err;
1367                 msleep(200);
1368         }
1369         err = niu_serdes_init(np);
1370         if (err)
1371                 return err;
1372         msleep(200);
1373         err = niu_xcvr_init(np);
1374         if (!err)
1375                 niu_link_status(np, &ignore);
1376         return 0;
1377 }
1378
1379 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
1380 {
1381         u16 reg0 = addr[4] << 8 | addr[5];
1382         u16 reg1 = addr[2] << 8 | addr[3];
1383         u16 reg2 = addr[0] << 8 | addr[1];
1384
1385         if (np->flags & NIU_FLAGS_XMAC) {
1386                 nw64_mac(XMAC_ADDR0, reg0);
1387                 nw64_mac(XMAC_ADDR1, reg1);
1388                 nw64_mac(XMAC_ADDR2, reg2);
1389         } else {
1390                 nw64_mac(BMAC_ADDR0, reg0);
1391                 nw64_mac(BMAC_ADDR1, reg1);
1392                 nw64_mac(BMAC_ADDR2, reg2);
1393         }
1394 }
1395
1396 static int niu_num_alt_addr(struct niu *np)
1397 {
1398         if (np->flags & NIU_FLAGS_XMAC)
1399                 return XMAC_NUM_ALT_ADDR;
1400         else
1401                 return BMAC_NUM_ALT_ADDR;
1402 }
1403
1404 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
1405 {
1406         u16 reg0 = addr[4] << 8 | addr[5];
1407         u16 reg1 = addr[2] << 8 | addr[3];
1408         u16 reg2 = addr[0] << 8 | addr[1];
1409
1410         if (index >= niu_num_alt_addr(np))
1411                 return -EINVAL;
1412
1413         if (np->flags & NIU_FLAGS_XMAC) {
1414                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
1415                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
1416                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
1417         } else {
1418                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
1419                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
1420                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
1421         }
1422
1423         return 0;
1424 }
1425
1426 static int niu_enable_alt_mac(struct niu *np, int index, int on)
1427 {
1428         unsigned long reg;
1429         u64 val, mask;
1430
1431         if (index >= niu_num_alt_addr(np))
1432                 return -EINVAL;
1433
1434         if (np->flags & NIU_FLAGS_XMAC)
1435                 reg = XMAC_ADDR_CMPEN;
1436         else
1437                 reg = BMAC_ADDR_CMPEN;
1438
1439         mask = 1 << index;
1440
1441         val = nr64_mac(reg);
1442         if (on)
1443                 val |= mask;
1444         else
1445                 val &= ~mask;
1446         nw64_mac(reg, val);
1447
1448         return 0;
1449 }
1450
1451 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
1452                                    int num, int mac_pref)
1453 {
1454         u64 val = nr64_mac(reg);
1455         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
1456         val |= num;
1457         if (mac_pref)
1458                 val |= HOST_INFO_MPR;
1459         nw64_mac(reg, val);
1460 }
1461
1462 static int __set_rdc_table_num(struct niu *np,
1463                                int xmac_index, int bmac_index,
1464                                int rdc_table_num, int mac_pref)
1465 {
1466         unsigned long reg;
1467
1468         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
1469                 return -EINVAL;
1470         if (np->flags & NIU_FLAGS_XMAC)
1471                 reg = XMAC_HOST_INFO(xmac_index);
1472         else
1473                 reg = BMAC_HOST_INFO(bmac_index);
1474         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
1475         return 0;
1476 }
1477
1478 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
1479                                          int mac_pref)
1480 {
1481         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
1482 }
1483
1484 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
1485                                            int mac_pref)
1486 {
1487         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
1488 }
1489
1490 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
1491                                      int table_num, int mac_pref)
1492 {
1493         if (idx >= niu_num_alt_addr(np))
1494                 return -EINVAL;
1495         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
1496 }
1497
1498 static u64 vlan_entry_set_parity(u64 reg_val)
1499 {
1500         u64 port01_mask;
1501         u64 port23_mask;
1502
1503         port01_mask = 0x00ff;
1504         port23_mask = 0xff00;
1505
1506         if (hweight64(reg_val & port01_mask) & 1)
1507                 reg_val |= ENET_VLAN_TBL_PARITY0;
1508         else
1509                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
1510
1511         if (hweight64(reg_val & port23_mask) & 1)
1512                 reg_val |= ENET_VLAN_TBL_PARITY1;
1513         else
1514                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
1515
1516         return reg_val;
1517 }
1518
1519 static void vlan_tbl_write(struct niu *np, unsigned long index,
1520                            int port, int vpr, int rdc_table)
1521 {
1522         u64 reg_val = nr64(ENET_VLAN_TBL(index));
1523
1524         reg_val &= ~((ENET_VLAN_TBL_VPR |
1525                       ENET_VLAN_TBL_VLANRDCTBLN) <<
1526                      ENET_VLAN_TBL_SHIFT(port));
1527         if (vpr)
1528                 reg_val |= (ENET_VLAN_TBL_VPR <<
1529                             ENET_VLAN_TBL_SHIFT(port));
1530         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
1531
1532         reg_val = vlan_entry_set_parity(reg_val);
1533
1534         nw64(ENET_VLAN_TBL(index), reg_val);
1535 }
1536
1537 static void vlan_tbl_clear(struct niu *np)
1538 {
1539         int i;
1540
1541         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
1542                 nw64(ENET_VLAN_TBL(i), 0);
1543 }
1544
1545 static int tcam_wait_bit(struct niu *np, u64 bit)
1546 {
1547         int limit = 1000;
1548
1549         while (--limit > 0) {
1550                 if (nr64(TCAM_CTL) & bit)
1551                         break;
1552                 udelay(1);
1553         }
1554         if (limit < 0)
1555                 return -ENODEV;
1556
1557         return 0;
1558 }
1559
1560 static int tcam_flush(struct niu *np, int index)
1561 {
1562         nw64(TCAM_KEY_0, 0x00);
1563         nw64(TCAM_KEY_MASK_0, 0xff);
1564         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1565
1566         return tcam_wait_bit(np, TCAM_CTL_STAT);
1567 }
1568
1569 #if 0
1570 static int tcam_read(struct niu *np, int index,
1571                      u64 *key, u64 *mask)
1572 {
1573         int err;
1574
1575         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
1576         err = tcam_wait_bit(np, TCAM_CTL_STAT);
1577         if (!err) {
1578                 key[0] = nr64(TCAM_KEY_0);
1579                 key[1] = nr64(TCAM_KEY_1);
1580                 key[2] = nr64(TCAM_KEY_2);
1581                 key[3] = nr64(TCAM_KEY_3);
1582                 mask[0] = nr64(TCAM_KEY_MASK_0);
1583                 mask[1] = nr64(TCAM_KEY_MASK_1);
1584                 mask[2] = nr64(TCAM_KEY_MASK_2);
1585                 mask[3] = nr64(TCAM_KEY_MASK_3);
1586         }
1587         return err;
1588 }
1589 #endif
1590
1591 static int tcam_write(struct niu *np, int index,
1592                       u64 *key, u64 *mask)
1593 {
1594         nw64(TCAM_KEY_0, key[0]);
1595         nw64(TCAM_KEY_1, key[1]);
1596         nw64(TCAM_KEY_2, key[2]);
1597         nw64(TCAM_KEY_3, key[3]);
1598         nw64(TCAM_KEY_MASK_0, mask[0]);
1599         nw64(TCAM_KEY_MASK_1, mask[1]);
1600         nw64(TCAM_KEY_MASK_2, mask[2]);
1601         nw64(TCAM_KEY_MASK_3, mask[3]);
1602         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1603
1604         return tcam_wait_bit(np, TCAM_CTL_STAT);
1605 }
1606
1607 #if 0
1608 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
1609 {
1610         int err;
1611
1612         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
1613         err = tcam_wait_bit(np, TCAM_CTL_STAT);
1614         if (!err)
1615                 *data = nr64(TCAM_KEY_1);
1616
1617         return err;
1618 }
1619 #endif
1620
1621 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
1622 {
1623         nw64(TCAM_KEY_1, assoc_data);
1624         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
1625
1626         return tcam_wait_bit(np, TCAM_CTL_STAT);
1627 }
1628
1629 static void tcam_enable(struct niu *np, int on)
1630 {
1631         u64 val = nr64(FFLP_CFG_1);
1632
1633         if (on)
1634                 val &= ~FFLP_CFG_1_TCAM_DIS;
1635         else
1636                 val |= FFLP_CFG_1_TCAM_DIS;
1637         nw64(FFLP_CFG_1, val);
1638 }
1639
1640 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
1641 {
1642         u64 val = nr64(FFLP_CFG_1);
1643
1644         val &= ~(FFLP_CFG_1_FFLPINITDONE |
1645                  FFLP_CFG_1_CAMLAT |
1646                  FFLP_CFG_1_CAMRATIO);
1647         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
1648         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
1649         nw64(FFLP_CFG_1, val);
1650
1651         val = nr64(FFLP_CFG_1);
1652         val |= FFLP_CFG_1_FFLPINITDONE;
1653         nw64(FFLP_CFG_1, val);
1654 }
1655
1656 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
1657                                       int on)
1658 {
1659         unsigned long reg;
1660         u64 val;
1661
1662         if (class < CLASS_CODE_ETHERTYPE1 ||
1663             class > CLASS_CODE_ETHERTYPE2)
1664                 return -EINVAL;
1665
1666         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1667         val = nr64(reg);
1668         if (on)
1669                 val |= L2_CLS_VLD;
1670         else
1671                 val &= ~L2_CLS_VLD;
1672         nw64(reg, val);
1673
1674         return 0;
1675 }
1676
1677 #if 0
1678 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
1679                                    u64 ether_type)
1680 {
1681         unsigned long reg;
1682         u64 val;
1683
1684         if (class < CLASS_CODE_ETHERTYPE1 ||
1685             class > CLASS_CODE_ETHERTYPE2 ||
1686             (ether_type & ~(u64)0xffff) != 0)
1687                 return -EINVAL;
1688
1689         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1690         val = nr64(reg);
1691         val &= ~L2_CLS_ETYPE;
1692         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
1693         nw64(reg, val);
1694
1695         return 0;
1696 }
1697 #endif
1698
1699 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
1700                                      int on)
1701 {
1702         unsigned long reg;
1703         u64 val;
1704
1705         if (class < CLASS_CODE_USER_PROG1 ||
1706             class > CLASS_CODE_USER_PROG4)
1707                 return -EINVAL;
1708
1709         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1710         val = nr64(reg);
1711         if (on)
1712                 val |= L3_CLS_VALID;
1713         else
1714                 val &= ~L3_CLS_VALID;
1715         nw64(reg, val);
1716
1717         return 0;
1718 }
1719
1720 #if 0
1721 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
1722                                   int ipv6, u64 protocol_id,
1723                                   u64 tos_mask, u64 tos_val)
1724 {
1725         unsigned long reg;
1726         u64 val;
1727
1728         if (class < CLASS_CODE_USER_PROG1 ||
1729             class > CLASS_CODE_USER_PROG4 ||
1730             (protocol_id & ~(u64)0xff) != 0 ||
1731             (tos_mask & ~(u64)0xff) != 0 ||
1732             (tos_val & ~(u64)0xff) != 0)
1733                 return -EINVAL;
1734
1735         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1736         val = nr64(reg);
1737         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
1738                  L3_CLS_TOSMASK | L3_CLS_TOS);
1739         if (ipv6)
1740                 val |= L3_CLS_IPVER;
1741         val |= (protocol_id << L3_CLS_PID_SHIFT);
1742         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
1743         val |= (tos_val << L3_CLS_TOS_SHIFT);
1744         nw64(reg, val);
1745
1746         return 0;
1747 }
1748 #endif
1749
1750 static int tcam_early_init(struct niu *np)
1751 {
1752         unsigned long i;
1753         int err;
1754
1755         tcam_enable(np, 0);
1756         tcam_set_lat_and_ratio(np,
1757                                DEFAULT_TCAM_LATENCY,
1758                                DEFAULT_TCAM_ACCESS_RATIO);
1759         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
1760                 err = tcam_user_eth_class_enable(np, i, 0);
1761                 if (err)
1762                         return err;
1763         }
1764         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
1765                 err = tcam_user_ip_class_enable(np, i, 0);
1766                 if (err)
1767                         return err;
1768         }
1769
1770         return 0;
1771 }
1772
1773 static int tcam_flush_all(struct niu *np)
1774 {
1775         unsigned long i;
1776
1777         for (i = 0; i < np->parent->tcam_num_entries; i++) {
1778                 int err = tcam_flush(np, i);
1779                 if (err)
1780                         return err;
1781         }
1782         return 0;
1783 }
1784
1785 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
1786 {
1787         return ((u64)index | (num_entries == 1 ?
1788                               HASH_TBL_ADDR_AUTOINC : 0));
1789 }
1790
1791 #if 0
1792 static int hash_read(struct niu *np, unsigned long partition,
1793                      unsigned long index, unsigned long num_entries,
1794                      u64 *data)
1795 {
1796         u64 val = hash_addr_regval(index, num_entries);
1797         unsigned long i;
1798
1799         if (partition >= FCRAM_NUM_PARTITIONS ||
1800             index + num_entries > FCRAM_SIZE)
1801                 return -EINVAL;
1802
1803         nw64(HASH_TBL_ADDR(partition), val);
1804         for (i = 0; i < num_entries; i++)
1805                 data[i] = nr64(HASH_TBL_DATA(partition));
1806
1807         return 0;
1808 }
1809 #endif
1810
1811 static int hash_write(struct niu *np, unsigned long partition,
1812                       unsigned long index, unsigned long num_entries,
1813                       u64 *data)
1814 {
1815         u64 val = hash_addr_regval(index, num_entries);
1816         unsigned long i;
1817
1818         if (partition >= FCRAM_NUM_PARTITIONS ||
1819             index + (num_entries * 8) > FCRAM_SIZE)
1820                 return -EINVAL;
1821
1822         nw64(HASH_TBL_ADDR(partition), val);
1823         for (i = 0; i < num_entries; i++)
1824                 nw64(HASH_TBL_DATA(partition), data[i]);
1825
1826         return 0;
1827 }
1828
1829 static void fflp_reset(struct niu *np)
1830 {
1831         u64 val;
1832
1833         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
1834         udelay(10);
1835         nw64(FFLP_CFG_1, 0);
1836
1837         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
1838         nw64(FFLP_CFG_1, val);
1839 }
1840
1841 static void fflp_set_timings(struct niu *np)
1842 {
1843         u64 val = nr64(FFLP_CFG_1);
1844
1845         val &= ~FFLP_CFG_1_FFLPINITDONE;
1846         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
1847         nw64(FFLP_CFG_1, val);
1848
1849         val = nr64(FFLP_CFG_1);
1850         val |= FFLP_CFG_1_FFLPINITDONE;
1851         nw64(FFLP_CFG_1, val);
1852
1853         val = nr64(FCRAM_REF_TMR);
1854         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
1855         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
1856         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
1857         nw64(FCRAM_REF_TMR, val);
1858 }
1859
1860 static int fflp_set_partition(struct niu *np, u64 partition,
1861                               u64 mask, u64 base, int enable)
1862 {
1863         unsigned long reg;
1864         u64 val;
1865
1866         if (partition >= FCRAM_NUM_PARTITIONS ||
1867             (mask & ~(u64)0x1f) != 0 ||
1868             (base & ~(u64)0x1f) != 0)
1869                 return -EINVAL;
1870
1871         reg = FLW_PRT_SEL(partition);
1872
1873         val = nr64(reg);
1874         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
1875         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
1876         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
1877         if (enable)
1878                 val |= FLW_PRT_SEL_EXT;
1879         nw64(reg, val);
1880
1881         return 0;
1882 }
1883
1884 static int fflp_disable_all_partitions(struct niu *np)
1885 {
1886         unsigned long i;
1887
1888         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
1889                 int err = fflp_set_partition(np, 0, 0, 0, 0);
1890                 if (err)
1891                         return err;
1892         }
1893         return 0;
1894 }
1895
1896 static void fflp_llcsnap_enable(struct niu *np, int on)
1897 {
1898         u64 val = nr64(FFLP_CFG_1);
1899
1900         if (on)
1901                 val |= FFLP_CFG_1_LLCSNAP;
1902         else
1903                 val &= ~FFLP_CFG_1_LLCSNAP;
1904         nw64(FFLP_CFG_1, val);
1905 }
1906
1907 static void fflp_errors_enable(struct niu *np, int on)
1908 {
1909         u64 val = nr64(FFLP_CFG_1);
1910
1911         if (on)
1912                 val &= ~FFLP_CFG_1_ERRORDIS;
1913         else
1914                 val |= FFLP_CFG_1_ERRORDIS;
1915         nw64(FFLP_CFG_1, val);
1916 }
1917
1918 static int fflp_hash_clear(struct niu *np)
1919 {
1920         struct fcram_hash_ipv4 ent;
1921         unsigned long i;
1922
1923         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
1924         memset(&ent, 0, sizeof(ent));
1925         ent.header = HASH_HEADER_EXT;
1926
1927         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
1928                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
1929                 if (err)
1930                         return err;
1931         }
1932         return 0;
1933 }
1934
1935 static int fflp_early_init(struct niu *np)
1936 {
1937         struct niu_parent *parent;
1938         unsigned long flags;
1939         int err;
1940
1941         niu_lock_parent(np, flags);
1942
1943         parent = np->parent;
1944         err = 0;
1945         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
1946                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
1947                        np->port);
1948                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1949                         fflp_reset(np);
1950                         fflp_set_timings(np);
1951                         err = fflp_disable_all_partitions(np);
1952                         if (err) {
1953                                 niudbg(PROBE, "fflp_disable_all_partitions "
1954                                        "failed, err=%d\n", err);
1955                                 goto out;
1956                         }
1957                 }
1958
1959                 err = tcam_early_init(np);
1960                 if (err) {
1961                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
1962                                err);
1963                         goto out;
1964                 }
1965                 fflp_llcsnap_enable(np, 1);
1966                 fflp_errors_enable(np, 0);
1967                 nw64(H1POLY, 0);
1968                 nw64(H2POLY, 0);
1969
1970                 err = tcam_flush_all(np);
1971                 if (err) {
1972                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
1973                                err);
1974                         goto out;
1975                 }
1976                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1977                         err = fflp_hash_clear(np);
1978                         if (err) {
1979                                 niudbg(PROBE, "fflp_hash_clear failed, "
1980                                        "err=%d\n", err);
1981                                 goto out;
1982                         }
1983                 }
1984
1985                 vlan_tbl_clear(np);
1986
1987                 niudbg(PROBE, "fflp_early_init: Success\n");
1988                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
1989         }
1990 out:
1991         niu_unlock_parent(np, flags);
1992         return err;
1993 }
1994
1995 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
1996 {
1997         if (class_code < CLASS_CODE_USER_PROG1 ||
1998             class_code > CLASS_CODE_SCTP_IPV6)
1999                 return -EINVAL;
2000
2001         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2002         return 0;
2003 }
2004
2005 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2006 {
2007         if (class_code < CLASS_CODE_USER_PROG1 ||
2008             class_code > CLASS_CODE_SCTP_IPV6)
2009                 return -EINVAL;
2010
2011         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2012         return 0;
2013 }
2014
2015 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2016                               u32 offset, u32 size)
2017 {
2018         int i = skb_shinfo(skb)->nr_frags;
2019         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2020
2021         frag->page = page;
2022         frag->page_offset = offset;
2023         frag->size = size;
2024
2025         skb->len += size;
2026         skb->data_len += size;
2027         skb->truesize += size;
2028
2029         skb_shinfo(skb)->nr_frags = i + 1;
2030 }
2031
2032 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2033 {
2034         a >>= PAGE_SHIFT;
2035         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2036
2037         return (a & (MAX_RBR_RING_SIZE - 1));
2038 }
2039
2040 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2041                                     struct page ***link)
2042 {
2043         unsigned int h = niu_hash_rxaddr(rp, addr);
2044         struct page *p, **pp;
2045
2046         addr &= PAGE_MASK;
2047         pp = &rp->rxhash[h];
2048         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2049                 if (p->index == addr) {
2050                         *link = pp;
2051                         break;
2052                 }
2053         }
2054
2055         return p;
2056 }
2057
2058 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2059 {
2060         unsigned int h = niu_hash_rxaddr(rp, base);
2061
2062         page->index = base;
2063         page->mapping = (struct address_space *) rp->rxhash[h];
2064         rp->rxhash[h] = page;
2065 }
2066
2067 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2068                             gfp_t mask, int start_index)
2069 {
2070         struct page *page;
2071         u64 addr;
2072         int i;
2073
2074         page = alloc_page(mask);
2075         if (!page)
2076                 return -ENOMEM;
2077
2078         addr = np->ops->map_page(np->device, page, 0,
2079                                  PAGE_SIZE, DMA_FROM_DEVICE);
2080
2081         niu_hash_page(rp, page, addr);
2082         if (rp->rbr_blocks_per_page > 1)
2083                 atomic_add(rp->rbr_blocks_per_page - 1,
2084                            &compound_head(page)->_count);
2085
2086         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2087                 __le32 *rbr = &rp->rbr[start_index + i];
2088
2089                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2090                 addr += rp->rbr_block_size;
2091         }
2092
2093         return 0;
2094 }
2095
2096 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2097 {
2098         int index = rp->rbr_index;
2099
2100         rp->rbr_pending++;
2101         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2102                 int err = niu_rbr_add_page(np, rp, mask, index);
2103
2104                 if (unlikely(err)) {
2105                         rp->rbr_pending--;
2106                         return;
2107                 }
2108
2109                 rp->rbr_index += rp->rbr_blocks_per_page;
2110                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2111                 if (rp->rbr_index == rp->rbr_table_size)
2112                         rp->rbr_index = 0;
2113
2114                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2115                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2116                         rp->rbr_pending = 0;
2117                 }
2118         }
2119 }
2120
2121 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2122 {
2123         unsigned int index = rp->rcr_index;
2124         int num_rcr = 0;
2125
2126         rp->rx_dropped++;
2127         while (1) {
2128                 struct page *page, **link;
2129                 u64 addr, val;
2130                 u32 rcr_size;
2131
2132                 num_rcr++;
2133
2134                 val = le64_to_cpup(&rp->rcr[index]);
2135                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2136                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2137                 page = niu_find_rxpage(rp, addr, &link);
2138
2139                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2140                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
2141                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2142                         *link = (struct page *) page->mapping;
2143                         np->ops->unmap_page(np->device, page->index,
2144                                             PAGE_SIZE, DMA_FROM_DEVICE);
2145                         page->index = 0;
2146                         page->mapping = NULL;
2147                         __free_page(page);
2148                         rp->rbr_refill_pending++;
2149                 }
2150
2151                 index = NEXT_RCR(rp, index);
2152                 if (!(val & RCR_ENTRY_MULTI))
2153                         break;
2154
2155         }
2156         rp->rcr_index = index;
2157
2158         return num_rcr;
2159 }
2160
2161 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2162 {
2163         unsigned int index = rp->rcr_index;
2164         struct sk_buff *skb;
2165         int len, num_rcr;
2166
2167         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2168         if (unlikely(!skb))
2169                 return niu_rx_pkt_ignore(np, rp);
2170
2171         num_rcr = 0;
2172         while (1) {
2173                 struct page *page, **link;
2174                 u32 rcr_size, append_size;
2175                 u64 addr, val, off;
2176
2177                 num_rcr++;
2178
2179                 val = le64_to_cpup(&rp->rcr[index]);
2180
2181                 len = (val & RCR_ENTRY_L2_LEN) >>
2182                         RCR_ENTRY_L2_LEN_SHIFT;
2183                 len -= ETH_FCS_LEN;
2184
2185                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2186                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2187                 page = niu_find_rxpage(rp, addr, &link);
2188
2189                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2190                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
2191
2192                 off = addr & ~PAGE_MASK;
2193                 append_size = rcr_size;
2194                 if (num_rcr == 1) {
2195                         int ptype;
2196
2197                         off += 2;
2198                         append_size -= 2;
2199
2200                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2201                         if ((ptype == RCR_PKT_TYPE_TCP ||
2202                              ptype == RCR_PKT_TYPE_UDP) &&
2203                             !(val & (RCR_ENTRY_NOPORT |
2204                                      RCR_ENTRY_ERROR)))
2205                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2206                         else
2207                                 skb->ip_summed = CHECKSUM_NONE;
2208                 }
2209                 if (!(val & RCR_ENTRY_MULTI))
2210                         append_size = len - skb->len;
2211
2212                 niu_rx_skb_append(skb, page, off, append_size);
2213                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2214                         *link = (struct page *) page->mapping;
2215                         np->ops->unmap_page(np->device, page->index,
2216                                             PAGE_SIZE, DMA_FROM_DEVICE);
2217                         page->index = 0;
2218                         page->mapping = NULL;
2219                         rp->rbr_refill_pending++;
2220                 } else
2221                         get_page(page);
2222
2223                 index = NEXT_RCR(rp, index);
2224                 if (!(val & RCR_ENTRY_MULTI))
2225                         break;
2226
2227         }
2228         rp->rcr_index = index;
2229
2230         skb_reserve(skb, NET_IP_ALIGN);
2231         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2232
2233         rp->rx_packets++;
2234         rp->rx_bytes += skb->len;
2235
2236         skb->protocol = eth_type_trans(skb, np->dev);
2237         netif_receive_skb(skb);
2238
2239         return num_rcr;
2240 }
2241
2242 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2243 {
2244         int blocks_per_page = rp->rbr_blocks_per_page;
2245         int err, index = rp->rbr_index;
2246
2247         err = 0;
2248         while (index < (rp->rbr_table_size - blocks_per_page)) {
2249                 err = niu_rbr_add_page(np, rp, mask, index);
2250                 if (err)
2251                         break;
2252
2253                 index += blocks_per_page;
2254         }
2255
2256         rp->rbr_index = index;
2257         return err;
2258 }
2259
2260 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2261 {
2262         int i;
2263
2264         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2265                 struct page *page;
2266
2267                 page = rp->rxhash[i];
2268                 while (page) {
2269                         struct page *next = (struct page *) page->mapping;
2270                         u64 base = page->index;
2271
2272                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
2273                                             DMA_FROM_DEVICE);
2274                         page->index = 0;
2275                         page->mapping = NULL;
2276
2277                         __free_page(page);
2278
2279                         page = next;
2280                 }
2281         }
2282
2283         for (i = 0; i < rp->rbr_table_size; i++)
2284                 rp->rbr[i] = cpu_to_le32(0);
2285         rp->rbr_index = 0;
2286 }
2287
2288 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2289 {
2290         struct tx_buff_info *tb = &rp->tx_buffs[idx];
2291         struct sk_buff *skb = tb->skb;
2292         struct tx_pkt_hdr *tp;
2293         u64 tx_flags;
2294         int i, len;
2295
2296         tp = (struct tx_pkt_hdr *) skb->data;
2297         tx_flags = le64_to_cpup(&tp->flags);
2298
2299         rp->tx_packets++;
2300         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2301                          ((tx_flags & TXHDR_PAD) / 2));
2302
2303         len = skb_headlen(skb);
2304         np->ops->unmap_single(np->device, tb->mapping,
2305                               len, DMA_TO_DEVICE);
2306
2307         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2308                 rp->mark_pending--;
2309
2310         tb->skb = NULL;
2311         do {
2312                 idx = NEXT_TX(rp, idx);
2313                 len -= MAX_TX_DESC_LEN;
2314         } while (len > 0);
2315
2316         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2317                 tb = &rp->tx_buffs[idx];
2318                 BUG_ON(tb->skb != NULL);
2319                 np->ops->unmap_page(np->device, tb->mapping,
2320                                     skb_shinfo(skb)->frags[i].size,
2321                                     DMA_TO_DEVICE);
2322                 idx = NEXT_TX(rp, idx);
2323         }
2324
2325         dev_kfree_skb(skb);
2326
2327         return idx;
2328 }
2329
2330 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
2331
2332 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
2333 {
2334         u16 pkt_cnt, tmp;
2335         int cons;
2336         u64 cs;
2337
2338         cs = rp->tx_cs;
2339         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
2340                 goto out;
2341
2342         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
2343         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
2344                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
2345
2346         rp->last_pkt_cnt = tmp;
2347
2348         cons = rp->cons;
2349
2350         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
2351                np->dev->name, pkt_cnt, cons);
2352
2353         while (pkt_cnt--)
2354                 cons = release_tx_packet(np, rp, cons);
2355
2356         rp->cons = cons;
2357         smp_mb();
2358
2359 out:
2360         if (unlikely(netif_queue_stopped(np->dev) &&
2361                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
2362                 netif_tx_lock(np->dev);
2363                 if (netif_queue_stopped(np->dev) &&
2364                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
2365                         netif_wake_queue(np->dev);
2366                 netif_tx_unlock(np->dev);
2367         }
2368 }
2369
2370 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
2371 {
2372         int qlen, rcr_done = 0, work_done = 0;
2373         struct rxdma_mailbox *mbox = rp->mbox;
2374         u64 stat;
2375
2376 #if 1
2377         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2378         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
2379 #else
2380         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2381         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
2382 #endif
2383         mbox->rx_dma_ctl_stat = 0;
2384         mbox->rcrstat_a = 0;
2385
2386         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
2387                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
2388
2389         rcr_done = work_done = 0;
2390         qlen = min(qlen, budget);
2391         while (work_done < qlen) {
2392                 rcr_done += niu_process_rx_pkt(np, rp);
2393                 work_done++;
2394         }
2395
2396         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
2397                 unsigned int i;
2398
2399                 for (i = 0; i < rp->rbr_refill_pending; i++)
2400                         niu_rbr_refill(np, rp, GFP_ATOMIC);
2401                 rp->rbr_refill_pending = 0;
2402         }
2403
2404         stat = (RX_DMA_CTL_STAT_MEX |
2405                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
2406                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
2407
2408         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
2409
2410         return work_done;
2411 }
2412
2413 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
2414 {
2415         u64 v0 = lp->v0;
2416         u32 tx_vec = (v0 >> 32);
2417         u32 rx_vec = (v0 & 0xffffffff);
2418         int i, work_done = 0;
2419
2420         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
2421                np->dev->name, (unsigned long long) v0);
2422
2423         for (i = 0; i < np->num_tx_rings; i++) {
2424                 struct tx_ring_info *rp = &np->tx_rings[i];
2425                 if (tx_vec & (1 << rp->tx_channel))
2426                         niu_tx_work(np, rp);
2427                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
2428         }
2429
2430         for (i = 0; i < np->num_rx_rings; i++) {
2431                 struct rx_ring_info *rp = &np->rx_rings[i];
2432
2433                 if (rx_vec & (1 << rp->rx_channel)) {
2434                         int this_work_done;
2435
2436                         this_work_done = niu_rx_work(np, rp,
2437                                                      budget);
2438
2439                         budget -= this_work_done;
2440                         work_done += this_work_done;
2441                 }
2442                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
2443         }
2444
2445         return work_done;
2446 }
2447
2448 static int niu_poll(struct napi_struct *napi, int budget)
2449 {
2450         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
2451         struct niu *np = lp->np;
2452         int work_done;
2453
2454         work_done = niu_poll_core(np, lp, budget);
2455
2456         if (work_done < budget) {
2457                 netif_rx_complete(np->dev, napi);
2458                 niu_ldg_rearm(np, lp, 1);
2459         }
2460         return work_done;
2461 }
2462
2463 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
2464                                   u64 stat)
2465 {
2466         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
2467                 np->dev->name, rp->rx_channel);
2468
2469         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
2470                 printk("RBR_TMOUT ");
2471         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
2472                 printk("RSP_CNT ");
2473         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
2474                 printk("BYTE_EN_BUS ");
2475         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
2476                 printk("RSP_DAT ");
2477         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
2478                 printk("RCR_ACK ");
2479         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
2480                 printk("RCR_SHA_PAR ");
2481         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
2482                 printk("RBR_PRE_PAR ");
2483         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
2484                 printk("CONFIG ");
2485         if (stat & RX_DMA_CTL_STAT_RCRINCON)
2486                 printk("RCRINCON ");
2487         if (stat & RX_DMA_CTL_STAT_RCRFULL)
2488                 printk("RCRFULL ");
2489         if (stat & RX_DMA_CTL_STAT_RBRFULL)
2490                 printk("RBRFULL ");
2491         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
2492                 printk("RBRLOGPAGE ");
2493         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
2494                 printk("CFIGLOGPAGE ");
2495         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
2496                 printk("DC_FIDO ");
2497
2498         printk(")\n");
2499 }
2500
2501 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
2502 {
2503         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2504         int err = 0;
2505
2506         dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
2507                 np->dev->name, rp->rx_channel, (unsigned long long) stat);
2508
2509         niu_log_rxchan_errors(np, rp, stat);
2510
2511         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
2512                     RX_DMA_CTL_STAT_PORT_FATAL))
2513                 err = -EINVAL;
2514
2515         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2516              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
2517
2518         return err;
2519 }
2520
2521 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
2522                                   u64 cs)
2523 {
2524         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
2525                 np->dev->name, rp->tx_channel);
2526
2527         if (cs & TX_CS_MBOX_ERR)
2528                 printk("MBOX ");
2529         if (cs & TX_CS_PKT_SIZE_ERR)
2530                 printk("PKT_SIZE ");
2531         if (cs & TX_CS_TX_RING_OFLOW)
2532                 printk("TX_RING_OFLOW ");
2533         if (cs & TX_CS_PREF_BUF_PAR_ERR)
2534                 printk("PREF_BUF_PAR ");
2535         if (cs & TX_CS_NACK_PREF)
2536                 printk("NACK_PREF ");
2537         if (cs & TX_CS_NACK_PKT_RD)
2538                 printk("NACK_PKT_RD ");
2539         if (cs & TX_CS_CONF_PART_ERR)
2540                 printk("CONF_PART ");
2541         if (cs & TX_CS_PKT_PRT_ERR)
2542                 printk("PKT_PTR ");
2543
2544         printk(")\n");
2545 }
2546
2547 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
2548 {
2549         u64 cs, logh, logl;
2550
2551         cs = nr64(TX_CS(rp->tx_channel));
2552         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
2553         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
2554
2555         dev_err(np->device, PFX "%s: TX channel %u error, "
2556                 "cs[%llx] logh[%llx] logl[%llx]\n",
2557                 np->dev->name, rp->tx_channel,
2558                 (unsigned long long) cs,
2559                 (unsigned long long) logh,
2560                 (unsigned long long) logl);
2561
2562         niu_log_txchan_errors(np, rp, cs);
2563
2564         return -ENODEV;
2565 }
2566
2567 static int niu_mif_interrupt(struct niu *np)
2568 {
2569         u64 mif_status = nr64(MIF_STATUS);
2570         int phy_mdint = 0;
2571
2572         if (np->flags & NIU_FLAGS_XMAC) {
2573                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
2574
2575                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
2576                         phy_mdint = 1;
2577         }
2578
2579         dev_err(np->device, PFX "%s: MIF interrupt, "
2580                 "stat[%llx] phy_mdint(%d)\n",
2581                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
2582
2583         return -ENODEV;
2584 }
2585
2586 static void niu_xmac_interrupt(struct niu *np)
2587 {
2588         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
2589         u64 val;
2590
2591         val = nr64_mac(XTXMAC_STATUS);
2592         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
2593                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
2594         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
2595                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
2596         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
2597                 mp->tx_fifo_errors++;
2598         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
2599                 mp->tx_overflow_errors++;
2600         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
2601                 mp->tx_max_pkt_size_errors++;
2602         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
2603                 mp->tx_underflow_errors++;
2604
2605         val = nr64_mac(XRXMAC_STATUS);
2606         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
2607                 mp->rx_local_faults++;
2608         if (val & XRXMAC_STATUS_RFLT_DET)
2609                 mp->rx_remote_faults++;
2610         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
2611                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
2612         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
2613                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
2614         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
2615                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
2616         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
2617                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
2618         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2619                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2620         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2621                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2622         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
2623                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
2624         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
2625                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
2626         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
2627                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
2628         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
2629                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
2630         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
2631                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
2632         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
2633                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
2634         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
2635                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
2636         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
2637                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
2638         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
2639                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
2640         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
2641                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
2642         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
2643                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
2644         if (val & XRXMAC_STATUS_RXUFLOW)
2645                 mp->rx_underflows++;
2646         if (val & XRXMAC_STATUS_RXOFLOW)
2647                 mp->rx_overflows++;
2648
2649         val = nr64_mac(XMAC_FC_STAT);
2650         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
2651                 mp->pause_off_state++;
2652         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
2653                 mp->pause_on_state++;
2654         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
2655                 mp->pause_received++;
2656 }
2657
2658 static void niu_bmac_interrupt(struct niu *np)
2659 {
2660         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
2661         u64 val;
2662
2663         val = nr64_mac(BTXMAC_STATUS);
2664         if (val & BTXMAC_STATUS_UNDERRUN)
2665                 mp->tx_underflow_errors++;
2666         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
2667                 mp->tx_max_pkt_size_errors++;
2668         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
2669                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
2670         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
2671                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
2672
2673         val = nr64_mac(BRXMAC_STATUS);
2674         if (val & BRXMAC_STATUS_OVERFLOW)
2675                 mp->rx_overflows++;
2676         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
2677                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
2678         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
2679                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2680         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
2681                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2682         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
2683                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
2684
2685         val = nr64_mac(BMAC_CTRL_STATUS);
2686         if (val & BMAC_CTRL_STATUS_NOPAUSE)
2687                 mp->pause_off_state++;
2688         if (val & BMAC_CTRL_STATUS_PAUSE)
2689                 mp->pause_on_state++;
2690         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
2691                 mp->pause_received++;
2692 }
2693
2694 static int niu_mac_interrupt(struct niu *np)
2695 {
2696         if (np->flags & NIU_FLAGS_XMAC)
2697                 niu_xmac_interrupt(np);
2698         else
2699                 niu_bmac_interrupt(np);
2700
2701         return 0;
2702 }
2703
2704 static void niu_log_device_error(struct niu *np, u64 stat)
2705 {
2706         dev_err(np->device, PFX "%s: Core device errors ( ",
2707                 np->dev->name);
2708
2709         if (stat & SYS_ERR_MASK_META2)
2710                 printk("META2 ");
2711         if (stat & SYS_ERR_MASK_META1)
2712                 printk("META1 ");
2713         if (stat & SYS_ERR_MASK_PEU)
2714                 printk("PEU ");
2715         if (stat & SYS_ERR_MASK_TXC)
2716                 printk("TXC ");
2717         if (stat & SYS_ERR_MASK_RDMC)
2718                 printk("RDMC ");
2719         if (stat & SYS_ERR_MASK_TDMC)
2720                 printk("TDMC ");
2721         if (stat & SYS_ERR_MASK_ZCP)
2722                 printk("ZCP ");
2723         if (stat & SYS_ERR_MASK_FFLP)
2724                 printk("FFLP ");
2725         if (stat & SYS_ERR_MASK_IPP)
2726                 printk("IPP ");
2727         if (stat & SYS_ERR_MASK_MAC)
2728                 printk("MAC ");
2729         if (stat & SYS_ERR_MASK_SMX)
2730                 printk("SMX ");
2731
2732         printk(")\n");
2733 }
2734
2735 static int niu_device_error(struct niu *np)
2736 {
2737         u64 stat = nr64(SYS_ERR_STAT);
2738
2739         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
2740                 np->dev->name, (unsigned long long) stat);
2741
2742         niu_log_device_error(np, stat);
2743
2744         return -ENODEV;
2745 }
2746
2747 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp)
2748 {
2749         u64 v0 = lp->v0;
2750         u64 v1 = lp->v1;
2751         u64 v2 = lp->v2;
2752         int i, err = 0;
2753
2754         if (v1 & 0x00000000ffffffffULL) {
2755                 u32 rx_vec = (v1 & 0xffffffff);
2756
2757                 for (i = 0; i < np->num_rx_rings; i++) {
2758                         struct rx_ring_info *rp = &np->rx_rings[i];
2759
2760                         if (rx_vec & (1 << rp->rx_channel)) {
2761                                 int r = niu_rx_error(np, rp);
2762                                 if (r)
2763                                         err = r;
2764                         }
2765                 }
2766         }
2767         if (v1 & 0x7fffffff00000000ULL) {
2768                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
2769
2770                 for (i = 0; i < np->num_tx_rings; i++) {
2771                         struct tx_ring_info *rp = &np->tx_rings[i];
2772
2773                         if (tx_vec & (1 << rp->tx_channel)) {
2774                                 int r = niu_tx_error(np, rp);
2775                                 if (r)
2776                                         err = r;
2777                         }
2778                 }
2779         }
2780         if ((v0 | v1) & 0x8000000000000000ULL) {
2781                 int r = niu_mif_interrupt(np);
2782                 if (r)
2783                         err = r;
2784         }
2785         if (v2) {
2786                 if (v2 & 0x01ef) {
2787                         int r = niu_mac_interrupt(np);
2788                         if (r)
2789                                 err = r;
2790                 }
2791                 if (v2 & 0x0210) {
2792                         int r = niu_device_error(np);
2793                         if (r)
2794                                 err = r;
2795                 }
2796         }
2797
2798         if (err)
2799                 niu_enable_interrupts(np, 0);
2800
2801         return -EINVAL;
2802 }
2803
2804 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
2805                             int ldn)
2806 {
2807         struct rxdma_mailbox *mbox = rp->mbox;
2808         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2809
2810         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
2811                       RX_DMA_CTL_STAT_RCRTO);
2812         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
2813
2814         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
2815                np->dev->name, (unsigned long long) stat);
2816 }
2817
2818 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
2819                             int ldn)
2820 {
2821         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
2822
2823         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
2824                np->dev->name, (unsigned long long) rp->tx_cs);
2825 }
2826
2827 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
2828 {
2829         struct niu_parent *parent = np->parent;
2830         u32 rx_vec, tx_vec;
2831         int i;
2832
2833         tx_vec = (v0 >> 32);
2834         rx_vec = (v0 & 0xffffffff);
2835
2836         for (i = 0; i < np->num_rx_rings; i++) {
2837                 struct rx_ring_info *rp = &np->rx_rings[i];
2838                 int ldn = LDN_RXDMA(rp->rx_channel);
2839
2840                 if (parent->ldg_map[ldn] != ldg)
2841                         continue;
2842
2843                 nw64(LD_IM0(ldn), LD_IM0_MASK);
2844                 if (rx_vec & (1 << rp->rx_channel))
2845                         niu_rxchan_intr(np, rp, ldn);
2846         }
2847
2848         for (i = 0; i < np->num_tx_rings; i++) {
2849                 struct tx_ring_info *rp = &np->tx_rings[i];
2850                 int ldn = LDN_TXDMA(rp->tx_channel);
2851
2852                 if (parent->ldg_map[ldn] != ldg)
2853                         continue;
2854
2855                 nw64(LD_IM0(ldn), LD_IM0_MASK);
2856                 if (tx_vec & (1 << rp->tx_channel))
2857                         niu_txchan_intr(np, rp, ldn);
2858         }
2859 }
2860
2861 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
2862                               u64 v0, u64 v1, u64 v2)
2863 {
2864         if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
2865                 lp->v0 = v0;
2866                 lp->v1 = v1;
2867                 lp->v2 = v2;
2868                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
2869                 __netif_rx_schedule(np->dev, &lp->napi);
2870         }
2871 }
2872
2873 static irqreturn_t niu_interrupt(int irq, void *dev_id)
2874 {
2875         struct niu_ldg *lp = dev_id;
2876         struct niu *np = lp->np;
2877         int ldg = lp->ldg_num;
2878         unsigned long flags;
2879         u64 v0, v1, v2;
2880
2881         if (netif_msg_intr(np))
2882                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
2883                        lp, ldg);
2884
2885         spin_lock_irqsave(&np->lock, flags);
2886
2887         v0 = nr64(LDSV0(ldg));
2888         v1 = nr64(LDSV1(ldg));
2889         v2 = nr64(LDSV2(ldg));
2890
2891         if (netif_msg_intr(np))
2892                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
2893                        (unsigned long long) v0,
2894                        (unsigned long long) v1,
2895                        (unsigned long long) v2);
2896
2897         if (unlikely(!v0 && !v1 && !v2)) {
2898                 spin_unlock_irqrestore(&np->lock, flags);
2899                 return IRQ_NONE;
2900         }
2901
2902         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
2903                 int err = niu_slowpath_interrupt(np, lp);
2904                 if (err)
2905                         goto out;
2906         }
2907         if (likely(v0 & ~((u64)1 << LDN_MIF)))
2908                 niu_schedule_napi(np, lp, v0, v1, v2);
2909         else
2910                 niu_ldg_rearm(np, lp, 1);
2911 out:
2912         spin_unlock_irqrestore(&np->lock, flags);
2913
2914         return IRQ_HANDLED;
2915 }
2916
2917 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
2918 {
2919         if (rp->mbox) {
2920                 np->ops->free_coherent(np->device,
2921                                        sizeof(struct rxdma_mailbox),
2922                                        rp->mbox, rp->mbox_dma);
2923                 rp->mbox = NULL;
2924         }
2925         if (rp->rcr) {
2926                 np->ops->free_coherent(np->device,
2927                                        MAX_RCR_RING_SIZE * sizeof(__le64),
2928                                        rp->rcr, rp->rcr_dma);
2929                 rp->rcr = NULL;
2930                 rp->rcr_table_size = 0;
2931                 rp->rcr_index = 0;
2932         }
2933         if (rp->rbr) {
2934                 niu_rbr_free(np, rp);
2935
2936                 np->ops->free_coherent(np->device,
2937                                        MAX_RBR_RING_SIZE * sizeof(__le32),
2938                                        rp->rbr, rp->rbr_dma);
2939                 rp->rbr = NULL;
2940                 rp->rbr_table_size = 0;
2941                 rp->rbr_index = 0;
2942         }
2943         kfree(rp->rxhash);
2944         rp->rxhash = NULL;
2945 }
2946
2947 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
2948 {
2949         if (rp->mbox) {
2950                 np->ops->free_coherent(np->device,
2951                                        sizeof(struct txdma_mailbox),
2952                                        rp->mbox, rp->mbox_dma);
2953                 rp->mbox = NULL;
2954         }
2955         if (rp->descr) {
2956                 int i;
2957
2958                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
2959                         if (rp->tx_buffs[i].skb)
2960                                 (void) release_tx_packet(np, rp, i);
2961                 }
2962
2963                 np->ops->free_coherent(np->device,
2964                                        MAX_TX_RING_SIZE * sizeof(__le64),
2965                                        rp->descr, rp->descr_dma);
2966                 rp->descr = NULL;
2967                 rp->pending = 0;
2968                 rp->prod = 0;
2969                 rp->cons = 0;
2970                 rp->wrap_bit = 0;
2971         }
2972 }
2973
2974 static void niu_free_channels(struct niu *np)
2975 {
2976         int i;
2977
2978         if (np->rx_rings) {
2979                 for (i = 0; i < np->num_rx_rings; i++) {
2980                         struct rx_ring_info *rp = &np->rx_rings[i];
2981
2982                         niu_free_rx_ring_info(np, rp);
2983                 }
2984                 kfree(np->rx_rings);
2985                 np->rx_rings = NULL;
2986                 np->num_rx_rings = 0;
2987         }
2988
2989         if (np->tx_rings) {
2990                 for (i = 0; i < np->num_tx_rings; i++) {
2991                         struct tx_ring_info *rp = &np->tx_rings[i];
2992
2993                         niu_free_tx_ring_info(np, rp);
2994                 }
2995                 kfree(np->tx_rings);
2996                 np->tx_rings = NULL;
2997                 np->num_tx_rings = 0;
2998         }
2999 }
3000
3001 static int niu_alloc_rx_ring_info(struct niu *np,
3002                                   struct rx_ring_info *rp)
3003 {
3004         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3005
3006         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3007                              GFP_KERNEL);
3008         if (!rp->rxhash)
3009                 return -ENOMEM;
3010
3011         rp->mbox = np->ops->alloc_coherent(np->device,
3012                                            sizeof(struct rxdma_mailbox),
3013                                            &rp->mbox_dma, GFP_KERNEL);
3014         if (!rp->mbox)
3015                 return -ENOMEM;
3016         if ((unsigned long)rp->mbox & (64UL - 1)) {
3017                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3018                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3019                 return -EINVAL;
3020         }
3021
3022         rp->rcr = np->ops->alloc_coherent(np->device,
3023                                           MAX_RCR_RING_SIZE * sizeof(__le64),
3024                                           &rp->rcr_dma, GFP_KERNEL);
3025         if (!rp->rcr)
3026                 return -ENOMEM;
3027         if ((unsigned long)rp->rcr & (64UL - 1)) {
3028                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3029                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3030                 return -EINVAL;
3031         }
3032         rp->rcr_table_size = MAX_RCR_RING_SIZE;
3033         rp->rcr_index = 0;
3034
3035         rp->rbr = np->ops->alloc_coherent(np->device,
3036                                           MAX_RBR_RING_SIZE * sizeof(__le32),
3037                                           &rp->rbr_dma, GFP_KERNEL);
3038         if (!rp->rbr)
3039                 return -ENOMEM;
3040         if ((unsigned long)rp->rbr & (64UL - 1)) {
3041                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3042                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3043                 return -EINVAL;
3044         }
3045         rp->rbr_table_size = MAX_RBR_RING_SIZE;
3046         rp->rbr_index = 0;
3047         rp->rbr_pending = 0;
3048
3049         return 0;
3050 }
3051
3052 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3053 {
3054         int mtu = np->dev->mtu;
3055
3056         /* These values are recommended by the HW designers for fair
3057          * utilization of DRR amongst the rings.
3058          */
3059         rp->max_burst = mtu + 32;
3060         if (rp->max_burst > 4096)
3061                 rp->max_burst = 4096;
3062 }
3063
3064 static int niu_alloc_tx_ring_info(struct niu *np,
3065                                   struct tx_ring_info *rp)
3066 {
3067         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3068
3069         rp->mbox = np->ops->alloc_coherent(np->device,
3070                                            sizeof(struct txdma_mailbox),
3071                                            &rp->mbox_dma, GFP_KERNEL);
3072         if (!rp->mbox)
3073                 return -ENOMEM;
3074         if ((unsigned long)rp->mbox & (64UL - 1)) {
3075                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3076                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3077                 return -EINVAL;
3078         }
3079
3080         rp->descr = np->ops->alloc_coherent(np->device,
3081                                             MAX_TX_RING_SIZE * sizeof(__le64),
3082                                             &rp->descr_dma, GFP_KERNEL);
3083         if (!rp->descr)
3084                 return -ENOMEM;
3085         if ((unsigned long)rp->descr & (64UL - 1)) {
3086                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3087                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
3088                 return -EINVAL;
3089         }
3090
3091         rp->pending = MAX_TX_RING_SIZE;
3092         rp->prod = 0;
3093         rp->cons = 0;
3094         rp->wrap_bit = 0;
3095
3096         /* XXX make these configurable... XXX */
3097         rp->mark_freq = rp->pending / 4;
3098
3099         niu_set_max_burst(np, rp);
3100
3101         return 0;
3102 }
3103
3104 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3105 {
3106         u16 bss;
3107
3108         bss = min(PAGE_SHIFT, 15);
3109
3110         rp->rbr_block_size = 1 << bss;
3111         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
3112
3113         rp->rbr_sizes[0] = 256;
3114         rp->rbr_sizes[1] = 1024;
3115         if (np->dev->mtu > ETH_DATA_LEN) {
3116                 switch (PAGE_SIZE) {
3117                 case 4 * 1024:
3118                         rp->rbr_sizes[2] = 4096;
3119                         break;
3120
3121                 default:
3122                         rp->rbr_sizes[2] = 8192;
3123                         break;
3124                 }
3125         } else {
3126                 rp->rbr_sizes[2] = 2048;
3127         }
3128         rp->rbr_sizes[3] = rp->rbr_block_size;
3129 }
3130
3131 static int niu_alloc_channels(struct niu *np)
3132 {
3133         struct niu_parent *parent = np->parent;
3134         int first_rx_channel, first_tx_channel;
3135         int i, port, err;
3136
3137         port = np->port;
3138         first_rx_channel = first_tx_channel = 0;
3139         for (i = 0; i < port; i++) {
3140                 first_rx_channel += parent->rxchan_per_port[i];
3141                 first_tx_channel += parent->txchan_per_port[i];
3142         }
3143
3144         np->num_rx_rings = parent->rxchan_per_port[port];
3145         np->num_tx_rings = parent->txchan_per_port[port];
3146
3147         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3148                                GFP_KERNEL);
3149         err = -ENOMEM;
3150         if (!np->rx_rings)
3151                 goto out_err;
3152
3153         for (i = 0; i < np->num_rx_rings; i++) {
3154                 struct rx_ring_info *rp = &np->rx_rings[i];
3155
3156                 rp->np = np;
3157                 rp->rx_channel = first_rx_channel + i;
3158
3159                 err = niu_alloc_rx_ring_info(np, rp);
3160                 if (err)
3161                         goto out_err;
3162
3163                 niu_size_rbr(np, rp);
3164
3165                 /* XXX better defaults, configurable, etc... XXX */
3166                 rp->nonsyn_window = 64;
3167                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3168                 rp->syn_window = 64;
3169                 rp->syn_threshold = rp->rcr_table_size - 64;
3170                 rp->rcr_pkt_threshold = 16;
3171                 rp->rcr_timeout = 8;
3172                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3173                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3174                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3175
3176                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3177                 if (err)
3178                         return err;
3179         }
3180
3181         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3182                                GFP_KERNEL);
3183         err = -ENOMEM;
3184         if (!np->tx_rings)
3185                 goto out_err;
3186
3187         for (i = 0; i < np->num_tx_rings; i++) {
3188                 struct tx_ring_info *rp = &np->tx_rings[i];
3189
3190                 rp->np = np;
3191                 rp->tx_channel = first_tx_channel + i;
3192
3193                 err = niu_alloc_tx_ring_info(np, rp);
3194                 if (err)
3195                         goto out_err;
3196         }
3197
3198         return 0;
3199
3200 out_err:
3201         niu_free_channels(np);
3202         return err;
3203 }
3204
3205 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3206 {
3207         int limit = 1000;
3208
3209         while (--limit > 0) {
3210                 u64 val = nr64(TX_CS(channel));
3211                 if (val & TX_CS_SNG_STATE)
3212                         return 0;
3213         }
3214         return -ENODEV;
3215 }
3216
3217 static int niu_tx_channel_stop(struct niu *np, int channel)
3218 {
3219         u64 val = nr64(TX_CS(channel));
3220
3221         val |= TX_CS_STOP_N_GO;
3222         nw64(TX_CS(channel), val);
3223
3224         return niu_tx_cs_sng_poll(np, channel);
3225 }
3226
3227 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3228 {
3229         int limit = 1000;
3230
3231         while (--limit > 0) {
3232                 u64 val = nr64(TX_CS(channel));
3233                 if (!(val & TX_CS_RST))
3234                         return 0;
3235         }
3236         return -ENODEV;
3237 }
3238
3239 static int niu_tx_channel_reset(struct niu *np, int channel)
3240 {
3241         u64 val = nr64(TX_CS(channel));
3242         int err;
3243
3244         val |= TX_CS_RST;
3245         nw64(TX_CS(channel), val);
3246
3247         err = niu_tx_cs_reset_poll(np, channel);
3248         if (!err)
3249                 nw64(TX_RING_KICK(channel), 0);
3250
3251         return err;
3252 }
3253
3254 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3255 {
3256         u64 val;
3257
3258         nw64(TX_LOG_MASK1(channel), 0);
3259         nw64(TX_LOG_VAL1(channel), 0);
3260         nw64(TX_LOG_MASK2(channel), 0);
3261         nw64(TX_LOG_VAL2(channel), 0);
3262         nw64(TX_LOG_PAGE_RELO1(channel), 0);
3263         nw64(TX_LOG_PAGE_RELO2(channel), 0);
3264         nw64(TX_LOG_PAGE_HDL(channel), 0);
3265
3266         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3267         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3268         nw64(TX_LOG_PAGE_VLD(channel), val);
3269
3270         /* XXX TXDMA 32bit mode? XXX */
3271
3272         return 0;
3273 }
3274
3275 static void niu_txc_enable_port(struct niu *np, int on)
3276 {
3277         unsigned long flags;
3278         u64 val, mask;
3279
3280         niu_lock_parent(np, flags);
3281         val = nr64(TXC_CONTROL);
3282         mask = (u64)1 << np->port;
3283         if (on) {
3284                 val |= TXC_CONTROL_ENABLE | mask;
3285         } else {
3286                 val &= ~mask;
3287                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3288                         val &= ~TXC_CONTROL_ENABLE;
3289         }
3290         nw64(TXC_CONTROL, val);
3291         niu_unlock_parent(np, flags);
3292 }
3293
3294 static void niu_txc_set_imask(struct niu *np, u64 imask)
3295 {
3296         unsigned long flags;
3297         u64 val;
3298
3299         niu_lock_parent(np, flags);
3300         val = nr64(TXC_INT_MASK);
3301         val &= ~TXC_INT_MASK_VAL(np->port);
3302         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3303         niu_unlock_parent(np, flags);
3304 }
3305
3306 static void niu_txc_port_dma_enable(struct niu *np, int on)
3307 {
3308         u64 val = 0;
3309
3310         if (on) {
3311                 int i;
3312
3313                 for (i = 0; i < np->num_tx_rings; i++)
3314                         val |= (1 << np->tx_rings[i].tx_channel);
3315         }
3316         nw64(TXC_PORT_DMA(np->port), val);
3317 }
3318
3319 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
3320 {
3321         int err, channel = rp->tx_channel;
3322         u64 val, ring_len;
3323
3324         err = niu_tx_channel_stop(np, channel);
3325         if (err)
3326                 return err;
3327
3328         err = niu_tx_channel_reset(np, channel);
3329         if (err)
3330                 return err;
3331
3332         err = niu_tx_channel_lpage_init(np, channel);
3333         if (err)
3334                 return err;
3335
3336         nw64(TXC_DMA_MAX(channel), rp->max_burst);
3337         nw64(TX_ENT_MSK(channel), 0);
3338
3339         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
3340                               TX_RNG_CFIG_STADDR)) {
3341                 dev_err(np->device, PFX "%s: TX ring channel %d "
3342                         "DMA addr (%llx) is not aligned.\n",
3343                         np->dev->name, channel,
3344                         (unsigned long long) rp->descr_dma);
3345                 return -EINVAL;
3346         }
3347
3348         /* The length field in TX_RNG_CFIG is measured in 64-byte
3349          * blocks.  rp->pending is the number of TX descriptors in
3350          * our ring, 8 bytes each, thus we divide by 8 bytes more
3351          * to get the proper value the chip wants.
3352          */
3353         ring_len = (rp->pending / 8);
3354
3355         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
3356                rp->descr_dma);
3357         nw64(TX_RNG_CFIG(channel), val);
3358
3359         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
3360             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
3361                 dev_err(np->device, PFX "%s: TX ring channel %d "
3362                         "MBOX addr (%llx) is has illegal bits.\n",
3363                         np->dev->name, channel,
3364                         (unsigned long long) rp->mbox_dma);
3365                 return -EINVAL;
3366         }
3367         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
3368         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
3369
3370         nw64(TX_CS(channel), 0);
3371
3372         rp->last_pkt_cnt = 0;
3373
3374         return 0;
3375 }
3376
3377 static void niu_init_rdc_groups(struct niu *np)
3378 {
3379         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
3380         int i, first_table_num = tp->first_table_num;
3381
3382         for (i = 0; i < tp->num_tables; i++) {
3383                 struct rdc_table *tbl = &tp->tables[i];
3384                 int this_table = first_table_num + i;
3385                 int slot;
3386
3387                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
3388                         nw64(RDC_TBL(this_table, slot),
3389                              tbl->rxdma_channel[slot]);
3390         }
3391
3392         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
3393 }
3394
3395 static void niu_init_drr_weight(struct niu *np)
3396 {
3397         int type = phy_decode(np->parent->port_phy, np->port);
3398         u64 val;
3399
3400         switch (type) {
3401         case PORT_TYPE_10G:
3402                 val = PT_DRR_WEIGHT_DEFAULT_10G;
3403                 break;
3404
3405         case PORT_TYPE_1G:
3406         default:
3407                 val = PT_DRR_WEIGHT_DEFAULT_1G;
3408                 break;
3409         }
3410         nw64(PT_DRR_WT(np->port), val);
3411 }
3412
3413 static int niu_init_hostinfo(struct niu *np)
3414 {
3415         struct niu_parent *parent = np->parent;
3416         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
3417         int i, err, num_alt = niu_num_alt_addr(np);
3418         int first_rdc_table = tp->first_table_num;
3419
3420         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
3421         if (err)
3422                 return err;
3423
3424         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
3425         if (err)
3426                 return err;
3427
3428         for (i = 0; i < num_alt; i++) {
3429                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
3430                 if (err)
3431                         return err;
3432         }
3433
3434         return 0;
3435 }
3436
3437 static int niu_rx_channel_reset(struct niu *np, int channel)
3438 {
3439         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
3440                                       RXDMA_CFIG1_RST, 1000, 10,
3441                                       "RXDMA_CFIG1");
3442 }
3443
3444 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
3445 {
3446         u64 val;
3447
3448         nw64(RX_LOG_MASK1(channel), 0);
3449         nw64(RX_LOG_VAL1(channel), 0);
3450         nw64(RX_LOG_MASK2(channel), 0);
3451         nw64(RX_LOG_VAL2(channel), 0);
3452         nw64(RX_LOG_PAGE_RELO1(channel), 0);
3453         nw64(RX_LOG_PAGE_RELO2(channel), 0);
3454         nw64(RX_LOG_PAGE_HDL(channel), 0);
3455
3456         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
3457         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
3458         nw64(RX_LOG_PAGE_VLD(channel), val);
3459
3460         return 0;
3461 }
3462
3463 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
3464 {
3465         u64 val;
3466
3467         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
3468                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
3469                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
3470                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
3471         nw64(RDC_RED_PARA(rp->rx_channel), val);
3472 }
3473
3474 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
3475 {
3476         u64 val = 0;
3477
3478         switch (rp->rbr_block_size) {
3479         case 4 * 1024:
3480                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
3481                 break;
3482         case 8 * 1024:
3483                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
3484                 break;
3485         case 16 * 1024:
3486                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
3487                 break;
3488         case 32 * 1024:
3489                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
3490                 break;
3491         default:
3492                 return -EINVAL;
3493         }
3494         val |= RBR_CFIG_B_VLD2;
3495         switch (rp->rbr_sizes[2]) {
3496         case 2 * 1024:
3497                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
3498                 break;
3499         case 4 * 1024:
3500                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
3501                 break;
3502         case 8 * 1024:
3503                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
3504                 break;
3505         case 16 * 1024:
3506                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
3507                 break;
3508
3509         default:
3510                 return -EINVAL;
3511         }
3512         val |= RBR_CFIG_B_VLD1;
3513         switch (rp->rbr_sizes[1]) {
3514         case 1 * 1024:
3515                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
3516                 break;
3517         case 2 * 1024:
3518                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
3519                 break;
3520         case 4 * 1024:
3521                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
3522                 break;
3523         case 8 * 1024:
3524                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
3525                 break;
3526
3527         default:
3528                 return -EINVAL;
3529         }
3530         val |= RBR_CFIG_B_VLD0;
3531         switch (rp->rbr_sizes[0]) {
3532         case 256:
3533                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
3534                 break;
3535         case 512:
3536                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
3537                 break;
3538         case 1 * 1024:
3539                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
3540                 break;
3541         case 2 * 1024:
3542                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
3543                 break;
3544
3545         default:
3546                 return -EINVAL;
3547         }
3548
3549         *ret = val;
3550         return 0;
3551 }
3552
3553 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
3554 {
3555         u64 val = nr64(RXDMA_CFIG1(channel));
3556         int limit;
3557
3558         if (on)
3559                 val |= RXDMA_CFIG1_EN;
3560         else
3561                 val &= ~RXDMA_CFIG1_EN;
3562         nw64(RXDMA_CFIG1(channel), val);
3563
3564         limit = 1000;
3565         while (--limit > 0) {
3566                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
3567                         break;
3568                 udelay(10);
3569         }
3570         if (limit <= 0)
3571                 return -ENODEV;
3572         return 0;
3573 }
3574
3575 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
3576 {
3577         int err, channel = rp->rx_channel;
3578         u64 val;
3579
3580         err = niu_rx_channel_reset(np, channel);
3581         if (err)
3582                 return err;
3583
3584         err = niu_rx_channel_lpage_init(np, channel);
3585         if (err)
3586                 return err;
3587
3588         niu_rx_channel_wred_init(np, rp);
3589
3590         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
3591         nw64(RX_DMA_CTL_STAT(channel),
3592              (RX_DMA_CTL_STAT_MEX |
3593               RX_DMA_CTL_STAT_RCRTHRES |
3594               RX_DMA_CTL_STAT_RCRTO |
3595               RX_DMA_CTL_STAT_RBR_EMPTY));
3596         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3597         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
3598         nw64(RBR_CFIG_A(channel),
3599              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
3600              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
3601         err = niu_compute_rbr_cfig_b(rp, &val);
3602         if (err)
3603                 return err;
3604         nw64(RBR_CFIG_B(channel), val);
3605         nw64(RCRCFIG_A(channel),
3606              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
3607              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
3608         nw64(RCRCFIG_B(channel),
3609              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
3610              RCRCFIG_B_ENTOUT |
3611              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
3612
3613         err = niu_enable_rx_channel(np, channel, 1);
3614         if (err)
3615                 return err;
3616
3617         nw64(RBR_KICK(channel), rp->rbr_index);
3618
3619         val = nr64(RX_DMA_CTL_STAT(channel));
3620         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
3621         nw64(RX_DMA_CTL_STAT(channel), val);
3622
3623         return 0;
3624 }
3625
3626 static int niu_init_rx_channels(struct niu *np)
3627 {
3628         unsigned long flags;
3629         u64 seed = jiffies_64;
3630         int err, i;
3631
3632         niu_lock_parent(np, flags);
3633         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
3634         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
3635         niu_unlock_parent(np, flags);
3636
3637         /* XXX RXDMA 32bit mode? XXX */
3638
3639         niu_init_rdc_groups(np);
3640         niu_init_drr_weight(np);
3641
3642         err = niu_init_hostinfo(np);
3643         if (err)
3644                 return err;
3645
3646         for (i = 0; i < np->num_rx_rings; i++) {
3647                 struct rx_ring_info *rp = &np->rx_rings[i];
3648
3649                 err = niu_init_one_rx_channel(np, rp);
3650                 if (err)
3651                         return err;
3652         }
3653
3654         return 0;
3655 }
3656
3657 static int niu_set_ip_frag_rule(struct niu *np)
3658 {
3659         struct niu_parent *parent = np->parent;
3660         struct niu_classifier *cp = &np->clas;
3661         struct niu_tcam_entry *tp;
3662         int index, err;
3663
3664         /* XXX fix this allocation scheme XXX */
3665         index = cp->tcam_index;
3666         tp = &parent->tcam[index];
3667
3668         /* Note that the noport bit is the same in both ipv4 and
3669          * ipv6 format TCAM entries.
3670          */
3671         memset(tp, 0, sizeof(*tp));
3672         tp->key[1] = TCAM_V4KEY1_NOPORT;
3673         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
3674         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
3675                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
3676         err = tcam_write(np, index, tp->key, tp->key_mask);
3677         if (err)
3678                 return err;
3679         err = tcam_assoc_write(np, index, tp->assoc_data);
3680         if (err)
3681                 return err;
3682
3683         return 0;
3684 }
3685
3686 static int niu_init_classifier_hw(struct niu *np)
3687 {
3688         struct niu_parent *parent = np->parent;
3689         struct niu_classifier *cp = &np->clas;
3690         int i, err;
3691
3692         nw64(H1POLY, cp->h1_init);
3693         nw64(H2POLY, cp->h2_init);
3694
3695         err = niu_init_hostinfo(np);
3696         if (err)
3697                 return err;
3698
3699         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
3700                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
3701
3702                 vlan_tbl_write(np, i, np->port,
3703                                vp->vlan_pref, vp->rdc_num);
3704         }
3705
3706         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
3707                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
3708
3709                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
3710                                                 ap->rdc_num, ap->mac_pref);
3711                 if (err)
3712                         return err;
3713         }
3714
3715         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
3716                 int index = i - CLASS_CODE_USER_PROG1;
3717
3718                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
3719                 if (err)
3720                         return err;
3721                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
3722                 if (err)
3723                         return err;
3724         }
3725
3726         err = niu_set_ip_frag_rule(np);
3727         if (err)
3728                 return err;
3729
3730         tcam_enable(np, 1);
3731
3732         return 0;
3733 }
3734
3735 static int niu_zcp_write(struct niu *np, int index, u64 *data)
3736 {
3737         nw64(ZCP_RAM_DATA0, data[0]);
3738         nw64(ZCP_RAM_DATA1, data[1]);
3739         nw64(ZCP_RAM_DATA2, data[2]);
3740         nw64(ZCP_RAM_DATA3, data[3]);
3741         nw64(ZCP_RAM_DATA4, data[4]);
3742         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
3743         nw64(ZCP_RAM_ACC,
3744              (ZCP_RAM_ACC_WRITE |
3745               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3746               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3747
3748         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3749                                    1000, 100);
3750 }
3751
3752 static int niu_zcp_read(struct niu *np, int index, u64 *data)
3753 {
3754         int err;
3755
3756         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3757                                   1000, 100);
3758         if (err) {
3759                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
3760                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3761                         (unsigned long long) nr64(ZCP_RAM_ACC));
3762                 return err;
3763         }
3764
3765         nw64(ZCP_RAM_ACC,
3766              (ZCP_RAM_ACC_READ |
3767               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3768               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3769
3770         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3771                                   1000, 100);
3772         if (err) {
3773                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
3774                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3775                         (unsigned long long) nr64(ZCP_RAM_ACC));
3776                 return err;
3777         }
3778
3779         data[0] = nr64(ZCP_RAM_DATA0);
3780         data[1] = nr64(ZCP_RAM_DATA1);
3781         data[2] = nr64(ZCP_RAM_DATA2);
3782         data[3] = nr64(ZCP_RAM_DATA3);
3783         data[4] = nr64(ZCP_RAM_DATA4);
3784
3785         return 0;
3786 }
3787
3788 static void niu_zcp_cfifo_reset(struct niu *np)
3789 {
3790         u64 val = nr64(RESET_CFIFO);
3791
3792         val |= RESET_CFIFO_RST(np->port);
3793         nw64(RESET_CFIFO, val);
3794         udelay(10);
3795
3796         val &= ~RESET_CFIFO_RST(np->port);
3797         nw64(RESET_CFIFO, val);
3798 }
3799
3800 static int niu_init_zcp(struct niu *np)
3801 {
3802         u64 data[5], rbuf[5];
3803         int i, max, err;
3804
3805         if (np->parent->plat_type != PLAT_TYPE_NIU) {
3806                 if (np->port == 0 || np->port == 1)
3807                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
3808                 else
3809                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
3810         } else
3811                 max = NIU_CFIFO_ENTRIES;
3812
3813         data[0] = 0;
3814         data[1] = 0;
3815         data[2] = 0;
3816         data[3] = 0;
3817         data[4] = 0;
3818
3819         for (i = 0; i < max; i++) {
3820                 err = niu_zcp_write(np, i, data);
3821                 if (err)
3822                         return err;
3823                 err = niu_zcp_read(np, i, rbuf);
3824                 if (err)
3825                         return err;
3826         }
3827
3828         niu_zcp_cfifo_reset(np);
3829         nw64(CFIFO_ECC(np->port), 0);
3830         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
3831         (void) nr64(ZCP_INT_STAT);
3832         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
3833
3834         return 0;
3835 }
3836
3837 static void niu_ipp_write(struct niu *np, int index, u64 *data)
3838 {
3839         u64 val = nr64_ipp(IPP_CFIG);
3840
3841         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
3842         nw64_ipp(IPP_DFIFO_WR_PTR, index);
3843         nw64_ipp(IPP_DFIFO_WR0, data[0]);
3844         nw64_ipp(IPP_DFIFO_WR1, data[1]);
3845         nw64_ipp(IPP_DFIFO_WR2, data[2]);
3846         nw64_ipp(IPP_DFIFO_WR3, data[3]);
3847         nw64_ipp(IPP_DFIFO_WR4, data[4]);
3848         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
3849 }
3850
3851 static void niu_ipp_read(struct niu *np, int index, u64 *data)
3852 {
3853         nw64_ipp(IPP_DFIFO_RD_PTR, index);
3854         data[0] = nr64_ipp(IPP_DFIFO_RD0);
3855         data[1] = nr64_ipp(IPP_DFIFO_RD1);
3856         data[2] = nr64_ipp(IPP_DFIFO_RD2);
3857         data[3] = nr64_ipp(IPP_DFIFO_RD3);
3858         data[4] = nr64_ipp(IPP_DFIFO_RD4);
3859 }
3860
3861 static int niu_ipp_reset(struct niu *np)
3862 {
3863         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
3864                                           1000, 100, "IPP_CFIG");
3865 }
3866
3867 static int niu_init_ipp(struct niu *np)
3868 {
3869         u64 data[5], rbuf[5], val;
3870         int i, max, err;
3871
3872         if (np->parent->plat_type != PLAT_TYPE_NIU) {
3873                 if (np->port == 0 || np->port == 1)
3874                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
3875                 else
3876                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
3877         } else
3878                 max = NIU_DFIFO_ENTRIES;
3879
3880         data[0] = 0;
3881         data[1] = 0;
3882         data[2] = 0;
3883         data[3] = 0;
3884         data[4] = 0;
3885
3886         for (i = 0; i < max; i++) {
3887                 niu_ipp_write(np, i, data);
3888                 niu_ipp_read(np, i, rbuf);
3889         }
3890
3891         (void) nr64_ipp(IPP_INT_STAT);
3892         (void) nr64_ipp(IPP_INT_STAT);
3893
3894         err = niu_ipp_reset(np);
3895         if (err)
3896                 return err;
3897
3898         (void) nr64_ipp(IPP_PKT_DIS);
3899         (void) nr64_ipp(IPP_BAD_CS_CNT);
3900         (void) nr64_ipp(IPP_ECC);
3901
3902         (void) nr64_ipp(IPP_INT_STAT);
3903
3904         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
3905
3906         val = nr64_ipp(IPP_CFIG);
3907         val &= ~IPP_CFIG_IP_MAX_PKT;
3908         val |= (IPP_CFIG_IPP_ENABLE |
3909                 IPP_CFIG_DFIFO_ECC_EN |
3910                 IPP_CFIG_DROP_BAD_CRC |
3911                 IPP_CFIG_CKSUM_EN |
3912                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
3913         nw64_ipp(IPP_CFIG, val);
3914
3915         return 0;
3916 }
3917
3918 static void niu_init_xif_xmac(struct niu *np)
3919 {
3920         struct niu_link_config *lp = &np->link_config;
3921         u64 val;
3922
3923         val = nr64_mac(XMAC_CONFIG);
3924
3925         if ((np->flags & NIU_FLAGS_10G) != 0 &&
3926             (np->flags & NIU_FLAGS_FIBER) != 0) {
3927                 if (netif_carrier_ok(np->dev)) {
3928                         val |= XMAC_CONFIG_LED_POLARITY;
3929                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
3930                 } else {
3931                         val |= XMAC_CONFIG_FORCE_LED_ON;
3932                         val &= ~XMAC_CONFIG_LED_POLARITY;
3933                 }
3934         }
3935
3936         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3937
3938         val |= XMAC_CONFIG_TX_OUTPUT_EN;
3939
3940         if (lp->loopback_mode == LOOPBACK_MAC) {
3941                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3942                 val |= XMAC_CONFIG_LOOPBACK;
3943         } else {
3944                 val &= ~XMAC_CONFIG_LOOPBACK;
3945         }
3946
3947         if (np->flags & NIU_FLAGS_10G) {
3948                 val &= ~XMAC_CONFIG_LFS_DISABLE;
3949         } else {
3950                 val |= XMAC_CONFIG_LFS_DISABLE;
3951                 if (!(np->flags & NIU_FLAGS_FIBER))
3952                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
3953                 else
3954                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
3955         }
3956
3957         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
3958
3959         if (lp->active_speed == SPEED_100)
3960                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
3961         else
3962                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
3963
3964         nw64_mac(XMAC_CONFIG, val);
3965
3966         val = nr64_mac(XMAC_CONFIG);
3967         val &= ~XMAC_CONFIG_MODE_MASK;
3968         if (np->flags & NIU_FLAGS_10G) {
3969                 val |= XMAC_CONFIG_MODE_XGMII;
3970         } else {
3971                 if (lp->active_speed == SPEED_100)
3972                         val |= XMAC_CONFIG_MODE_MII;
3973                 else
3974                         val |= XMAC_CONFIG_MODE_GMII;
3975         }
3976
3977         nw64_mac(XMAC_CONFIG, val);
3978 }
3979
3980 static void niu_init_xif_bmac(struct niu *np)
3981 {
3982         struct niu_link_config *lp = &np->link_config;
3983         u64 val;
3984
3985         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
3986
3987         if (lp->loopback_mode == LOOPBACK_MAC)
3988                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
3989         else
3990                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
3991
3992         if (lp->active_speed == SPEED_1000)
3993                 val |= BMAC_XIF_CONFIG_GMII_MODE;
3994         else
3995                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
3996
3997         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
3998                  BMAC_XIF_CONFIG_LED_POLARITY);
3999
4000         if (!(np->flags & NIU_FLAGS_10G) &&
4001             !(np->flags & NIU_FLAGS_FIBER) &&
4002             lp->active_speed == SPEED_100)
4003                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4004         else
4005                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4006
4007         nw64_mac(BMAC_XIF_CONFIG, val);
4008 }
4009
4010 static void niu_init_xif(struct niu *np)
4011 {
4012         if (np->flags & NIU_FLAGS_XMAC)
4013                 niu_init_xif_xmac(np);
4014         else
4015                 niu_init_xif_bmac(np);
4016 }
4017
4018 static void niu_pcs_mii_reset(struct niu *np)
4019 {
4020         u64 val = nr64_pcs(PCS_MII_CTL);
4021         val |= PCS_MII_CTL_RST;
4022         nw64_pcs(PCS_MII_CTL, val);
4023 }
4024
4025 static void niu_xpcs_reset(struct niu *np)
4026 {
4027         u64 val = nr64_xpcs(XPCS_CONTROL1);
4028         val |= XPCS_CONTROL1_RESET;
4029         nw64_xpcs(XPCS_CONTROL1, val);
4030 }
4031
4032 static int niu_init_pcs(struct niu *np)
4033 {
4034         struct niu_link_config *lp = &np->link_config;
4035         u64 val;
4036
4037         switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
4038         case NIU_FLAGS_FIBER:
4039                 /* 1G fiber */
4040                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4041                 nw64_pcs(PCS_DPATH_MODE, 0);
4042                 niu_pcs_mii_reset(np);
4043                 break;
4044
4045         case NIU_FLAGS_10G:
4046         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4047                 if (!(np->flags & NIU_FLAGS_XMAC))
4048                         return -EINVAL;
4049
4050                 /* 10G copper or fiber */
4051                 val = nr64_mac(XMAC_CONFIG);
4052                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4053                 nw64_mac(XMAC_CONFIG, val);
4054
4055                 niu_xpcs_reset(np);
4056
4057                 val = nr64_xpcs(XPCS_CONTROL1);
4058                 if (lp->loopback_mode == LOOPBACK_PHY)
4059                         val |= XPCS_CONTROL1_LOOPBACK;
4060                 else
4061                         val &= ~XPCS_CONTROL1_LOOPBACK;
4062                 nw64_xpcs(XPCS_CONTROL1, val);
4063
4064                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4065                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4066                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4067                 break;
4068
4069         case 0:
4070                 /* 1G copper */
4071                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4072                 niu_pcs_mii_reset(np);
4073                 break;
4074
4075         default:
4076                 return -EINVAL;
4077         }
4078
4079         return 0;
4080 }
4081
4082 static int niu_reset_tx_xmac(struct niu *np)
4083 {
4084         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4085                                           (XTXMAC_SW_RST_REG_RS |
4086                                            XTXMAC_SW_RST_SOFT_RST),
4087                                           1000, 100, "XTXMAC_SW_RST");
4088 }
4089
4090 static int niu_reset_tx_bmac(struct niu *np)
4091 {
4092         int limit;
4093
4094         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4095         limit = 1000;
4096         while (--limit >= 0) {
4097                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4098                         break;
4099                 udelay(100);
4100         }
4101         if (limit < 0) {
4102                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4103                         "BTXMAC_SW_RST[%llx]\n",
4104                         np->port,
4105                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4106                 return -ENODEV;
4107         }
4108
4109         return 0;
4110 }
4111
4112 static int niu_reset_tx_mac(struct niu *np)
4113 {
4114         if (np->flags & NIU_FLAGS_XMAC)
4115                 return niu_reset_tx_xmac(np);
4116         else
4117                 return niu_reset_tx_bmac(np);
4118 }
4119
4120 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4121 {
4122         u64 val;
4123
4124         val = nr64_mac(XMAC_MIN);
4125         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4126                  XMAC_MIN_RX_MIN_PKT_SIZE);
4127         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4128         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4129         nw64_mac(XMAC_MIN, val);
4130
4131         nw64_mac(XMAC_MAX, max);
4132
4133         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4134
4135         val = nr64_mac(XMAC_IPG);
4136         if (np->flags & NIU_FLAGS_10G) {
4137                 val &= ~XMAC_IPG_IPG_XGMII;
4138                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4139         } else {
4140                 val &= ~XMAC_IPG_IPG_MII_GMII;
4141                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4142         }
4143         nw64_mac(XMAC_IPG, val);
4144
4145         val = nr64_mac(XMAC_CONFIG);
4146         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4147                  XMAC_CONFIG_STRETCH_MODE |
4148                  XMAC_CONFIG_VAR_MIN_IPG_EN |
4149                  XMAC_CONFIG_TX_ENABLE);
4150         nw64_mac(XMAC_CONFIG, val);
4151
4152         nw64_mac(TXMAC_FRM_CNT, 0);
4153         nw64_mac(TXMAC_BYTE_CNT, 0);
4154 }
4155
4156 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4157 {
4158         u64 val;
4159
4160         nw64_mac(BMAC_MIN_FRAME, min);
4161         nw64_mac(BMAC_MAX_FRAME, max);
4162
4163         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4164         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4165         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4166
4167         val = nr64_mac(BTXMAC_CONFIG);
4168         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4169                  BTXMAC_CONFIG_ENABLE);
4170         nw64_mac(BTXMAC_CONFIG, val);
4171 }
4172
4173 static void niu_init_tx_mac(struct niu *np)
4174 {
4175         u64 min, max;
4176
4177         min = 64;
4178         if (np->dev->mtu > ETH_DATA_LEN)
4179                 max = 9216;
4180         else
4181                 max = 1522;
4182
4183         /* The XMAC_MIN register only accepts values for TX min which
4184          * have the low 3 bits cleared.
4185          */
4186         BUILD_BUG_ON(min & 0x7);
4187
4188         if (np->flags & NIU_FLAGS_XMAC)
4189                 niu_init_tx_xmac(np, min, max);
4190         else
4191                 niu_init_tx_bmac(np, min, max);
4192 }
4193
4194 static int niu_reset_rx_xmac(struct niu *np)
4195 {
4196         int limit;
4197
4198         nw64_mac(XRXMAC_SW_RST,
4199                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4200         limit = 1000;
4201         while (--limit >= 0) {
4202                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4203                                                  XRXMAC_SW_RST_SOFT_RST)))
4204                     break;
4205                 udelay(100);
4206         }
4207         if (limit < 0) {
4208                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4209                         "XRXMAC_SW_RST[%llx]\n",
4210                         np->port,
4211                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4212                 return -ENODEV;
4213         }
4214
4215         return 0;
4216 }
4217
4218 static int niu_reset_rx_bmac(struct niu *np)
4219 {
4220         int limit;
4221
4222         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4223         limit = 1000;
4224         while (--limit >= 0) {
4225                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4226                         break;
4227                 udelay(100);
4228         }
4229         if (limit < 0) {
4230                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4231                         "BRXMAC_SW_RST[%llx]\n",
4232                         np->port,
4233                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4234                 return -ENODEV;
4235         }
4236
4237         return 0;
4238 }
4239
4240 static int niu_reset_rx_mac(struct niu *np)
4241 {
4242         if (np->flags & NIU_FLAGS_XMAC)
4243                 return niu_reset_rx_xmac(np);
4244         else
4245                 return niu_reset_rx_bmac(np);
4246 }
4247
4248 static void niu_init_rx_xmac(struct niu *np)
4249 {
4250         struct niu_parent *parent = np->parent;
4251         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4252         int first_rdc_table = tp->first_table_num;
4253         unsigned long i;
4254         u64 val;
4255
4256         nw64_mac(XMAC_ADD_FILT0, 0);
4257         nw64_mac(XMAC_ADD_FILT1, 0);
4258         nw64_mac(XMAC_ADD_FILT2, 0);
4259         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4260         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4261         for (i = 0; i < MAC_NUM_HASH; i++)
4262                 nw64_mac(XMAC_HASH_TBL(i), 0);
4263         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4264         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4265         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4266
4267         val = nr64_mac(XMAC_CONFIG);
4268         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4269                  XMAC_CONFIG_PROMISCUOUS |
4270                  XMAC_CONFIG_PROMISC_GROUP |
4271                  XMAC_CONFIG_ERR_CHK_DIS |
4272                  XMAC_CONFIG_RX_CRC_CHK_DIS |
4273                  XMAC_CONFIG_RESERVED_MULTICAST |
4274                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
4275                  XMAC_CONFIG_ADDR_FILTER_EN |
4276                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
4277                  XMAC_CONFIG_STRIP_CRC |
4278                  XMAC_CONFIG_PASS_FLOW_CTRL |
4279                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
4280         val |= (XMAC_CONFIG_HASH_FILTER_EN);
4281         nw64_mac(XMAC_CONFIG, val);
4282
4283         nw64_mac(RXMAC_BT_CNT, 0);
4284         nw64_mac(RXMAC_BC_FRM_CNT, 0);
4285         nw64_mac(RXMAC_MC_FRM_CNT, 0);
4286         nw64_mac(RXMAC_FRAG_CNT, 0);
4287         nw64_mac(RXMAC_HIST_CNT1, 0);
4288         nw64_mac(RXMAC_HIST_CNT2, 0);
4289         nw64_mac(RXMAC_HIST_CNT3, 0);
4290         nw64_mac(RXMAC_HIST_CNT4, 0);
4291         nw64_mac(RXMAC_HIST_CNT5, 0);
4292         nw64_mac(RXMAC_HIST_CNT6, 0);
4293         nw64_mac(RXMAC_HIST_CNT7, 0);
4294         nw64_mac(RXMAC_MPSZER_CNT, 0);
4295         nw64_mac(RXMAC_CRC_ER_CNT, 0);
4296         nw64_mac(RXMAC_CD_VIO_CNT, 0);
4297         nw64_mac(LINK_FAULT_CNT, 0);
4298 }
4299
4300 static void niu_init_rx_bmac(struct niu *np)
4301 {
4302         struct niu_parent *parent = np->parent;
4303         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4304         int first_rdc_table = tp->first_table_num;
4305         unsigned long i;
4306         u64 val;
4307
4308         nw64_mac(BMAC_ADD_FILT0, 0);
4309         nw64_mac(BMAC_ADD_FILT1, 0);
4310         nw64_mac(BMAC_ADD_FILT2, 0);
4311         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
4312         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
4313         for (i = 0; i < MAC_NUM_HASH; i++)
4314                 nw64_mac(BMAC_HASH_TBL(i), 0);
4315         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4316         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4317         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
4318
4319         val = nr64_mac(BRXMAC_CONFIG);
4320         val &= ~(BRXMAC_CONFIG_ENABLE |
4321                  BRXMAC_CONFIG_STRIP_PAD |
4322                  BRXMAC_CONFIG_STRIP_FCS |
4323                  BRXMAC_CONFIG_PROMISC |
4324                  BRXMAC_CONFIG_PROMISC_GRP |
4325                  BRXMAC_CONFIG_ADDR_FILT_EN |
4326                  BRXMAC_CONFIG_DISCARD_DIS);
4327         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
4328         nw64_mac(BRXMAC_CONFIG, val);
4329
4330         val = nr64_mac(BMAC_ADDR_CMPEN);
4331         val |= BMAC_ADDR_CMPEN_EN0;
4332         nw64_mac(BMAC_ADDR_CMPEN, val);
4333 }
4334
4335 static void niu_init_rx_mac(struct niu *np)
4336 {
4337         niu_set_primary_mac(np, np->dev->dev_addr);
4338
4339         if (np->flags & NIU_FLAGS_XMAC)
4340                 niu_init_rx_xmac(np);
4341         else
4342                 niu_init_rx_bmac(np);
4343 }
4344
4345 static void niu_enable_tx_xmac(struct niu *np, int on)
4346 {
4347         u64 val = nr64_mac(XMAC_CONFIG);
4348
4349         if (on)
4350                 val |= XMAC_CONFIG_TX_ENABLE;
4351         else
4352                 val &= ~XMAC_CONFIG_TX_ENABLE;
4353         nw64_mac(XMAC_CONFIG, val);
4354 }
4355
4356 static void niu_enable_tx_bmac(struct niu *np, int on)
4357 {
4358         u64 val = nr64_mac(BTXMAC_CONFIG);
4359
4360         if (on)
4361                 val |= BTXMAC_CONFIG_ENABLE;
4362         else
4363                 val &= ~BTXMAC_CONFIG_ENABLE;
4364         nw64_mac(BTXMAC_CONFIG, val);
4365 }
4366
4367 static void niu_enable_tx_mac(struct niu *np, int on)
4368 {
4369         if (np->flags & NIU_FLAGS_XMAC)
4370                 niu_enable_tx_xmac(np, on);
4371         else
4372                 niu_enable_tx_bmac(np, on);
4373 }
4374
4375 static void niu_enable_rx_xmac(struct niu *np, int on)
4376 {
4377         u64 val = nr64_mac(XMAC_CONFIG);
4378
4379         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
4380                  XMAC_CONFIG_PROMISCUOUS);
4381
4382         if (np->flags & NIU_FLAGS_MCAST)
4383                 val |= XMAC_CONFIG_HASH_FILTER_EN;
4384         if (np->flags & NIU_FLAGS_PROMISC)
4385                 val |= XMAC_CONFIG_PROMISCUOUS;
4386
4387         if (on)
4388                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
4389         else
4390                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
4391         nw64_mac(XMAC_CONFIG, val);
4392 }
4393
4394 static void niu_enable_rx_bmac(struct niu *np, int on)
4395 {
4396         u64 val = nr64_mac(BRXMAC_CONFIG);
4397
4398         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
4399                  BRXMAC_CONFIG_PROMISC);
4400
4401         if (np->flags & NIU_FLAGS_MCAST)
4402                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
4403         if (np->flags & NIU_FLAGS_PROMISC)
4404                 val |= BRXMAC_CONFIG_PROMISC;
4405
4406         if (on)
4407                 val |= BRXMAC_CONFIG_ENABLE;
4408         else
4409                 val &= ~BRXMAC_CONFIG_ENABLE;
4410         nw64_mac(BRXMAC_CONFIG, val);
4411 }
4412
4413 static void niu_enable_rx_mac(struct niu *np, int on)
4414 {
4415         if (np->flags & NIU_FLAGS_XMAC)
4416                 niu_enable_rx_xmac(np, on);
4417         else
4418                 niu_enable_rx_bmac(np, on);
4419 }
4420
4421 static int niu_init_mac(struct niu *np)
4422 {
4423         int err;
4424
4425         niu_init_xif(np);
4426         err = niu_init_pcs(np);
4427         if (err)
4428                 return err;
4429
4430         err = niu_reset_tx_mac(np);
4431         if (err)
4432                 return err;
4433         niu_init_tx_mac(np);
4434         err = niu_reset_rx_mac(np);
4435         if (err)
4436                 return err;
4437         niu_init_rx_mac(np);
4438
4439         /* This looks hookey but the RX MAC reset we just did will
4440          * undo some of the state we setup in niu_init_tx_mac() so we
4441          * have to call it again.  In particular, the RX MAC reset will
4442          * set the XMAC_MAX register back to it's default value.
4443          */
4444         niu_init_tx_mac(np);
4445         niu_enable_tx_mac(np, 1);
4446
4447         niu_enable_rx_mac(np, 1);
4448
4449         return 0;
4450 }
4451
4452 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4453 {
4454         (void) niu_tx_channel_stop(np, rp->tx_channel);
4455 }
4456
4457 static void niu_stop_tx_channels(struct niu *np)
4458 {
4459         int i;
4460
4461         for (i = 0; i < np->num_tx_rings; i++) {
4462                 struct tx_ring_info *rp = &np->tx_rings[i];
4463
4464                 niu_stop_one_tx_channel(np, rp);
4465         }
4466 }
4467
4468 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4469 {
4470         (void) niu_tx_channel_reset(np, rp->tx_channel);
4471 }
4472
4473 static void niu_reset_tx_channels(struct niu *np)
4474 {
4475         int i;
4476
4477         for (i = 0; i < np->num_tx_rings; i++) {
4478                 struct tx_ring_info *rp = &np->tx_rings[i];
4479
4480                 niu_reset_one_tx_channel(np, rp);
4481         }
4482 }
4483
4484 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4485 {
4486         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
4487 }
4488
4489 static void niu_stop_rx_channels(struct niu *np)
4490 {
4491         int i;
4492
4493         for (i = 0; i < np->num_rx_rings; i++) {
4494                 struct rx_ring_info *rp = &np->rx_rings[i];
4495
4496                 niu_stop_one_rx_channel(np, rp);
4497         }
4498 }
4499
4500 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4501 {
4502         int channel = rp->rx_channel;
4503
4504         (void) niu_rx_channel_reset(np, channel);
4505         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
4506         nw64(RX_DMA_CTL_STAT(channel), 0);
4507         (void) niu_enable_rx_channel(np, channel, 0);
4508 }
4509
4510 static void niu_reset_rx_channels(struct niu *np)
4511 {
4512         int i;
4513
4514         for (i = 0; i < np->num_rx_rings; i++) {
4515                 struct rx_ring_info *rp = &np->rx_rings[i];
4516
4517                 niu_reset_one_rx_channel(np, rp);
4518         }
4519 }
4520
4521 static void niu_disable_ipp(struct niu *np)
4522 {
4523         u64 rd, wr, val;
4524         int limit;
4525
4526         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4527         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4528         limit = 100;
4529         while (--limit >= 0 && (rd != wr)) {
4530                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4531                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4532         }
4533         if (limit < 0 &&
4534             (rd != 0 && wr != 1)) {
4535                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
4536                         "rd_ptr[%llx] wr_ptr[%llx]\n",
4537                         np->dev->name,
4538                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
4539                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
4540         }
4541
4542         val = nr64_ipp(IPP_CFIG);
4543         val &= ~(IPP_CFIG_IPP_ENABLE |
4544                  IPP_CFIG_DFIFO_ECC_EN |
4545                  IPP_CFIG_DROP_BAD_CRC |
4546                  IPP_CFIG_CKSUM_EN);
4547         nw64_ipp(IPP_CFIG, val);
4548
4549         (void) niu_ipp_reset(np);
4550 }
4551
4552 static int niu_init_hw(struct niu *np)
4553 {
4554         int i, err;
4555
4556         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
4557         niu_txc_enable_port(np, 1);
4558         niu_txc_port_dma_enable(np, 1);
4559         niu_txc_set_imask(np, 0);
4560
4561         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
4562         for (i = 0; i < np->num_tx_rings; i++) {
4563                 struct tx_ring_info *rp = &np->tx_rings[i];
4564
4565                 err = niu_init_one_tx_channel(np, rp);
4566                 if (err)
4567                         return err;
4568         }
4569
4570         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
4571         err = niu_init_rx_channels(np);
4572         if (err)
4573                 goto out_uninit_tx_channels;
4574
4575         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
4576         err = niu_init_classifier_hw(np);
4577         if (err)
4578                 goto out_uninit_rx_channels;
4579
4580         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
4581         err = niu_init_zcp(np);
4582         if (err)
4583                 goto out_uninit_rx_channels;
4584
4585         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
4586         err = niu_init_ipp(np);
4587         if (err)
4588                 goto out_uninit_rx_channels;
4589
4590         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
4591         err = niu_init_mac(np);
4592         if (err)
4593                 goto out_uninit_ipp;
4594
4595         return 0;
4596
4597 out_uninit_ipp:
4598         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
4599         niu_disable_ipp(np);
4600
4601 out_uninit_rx_channels:
4602         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
4603         niu_stop_rx_channels(np);
4604         niu_reset_rx_channels(np);
4605
4606 out_uninit_tx_channels:
4607         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
4608         niu_stop_tx_channels(np);
4609         niu_reset_tx_channels(np);
4610
4611         return err;
4612 }
4613
4614 static void niu_stop_hw(struct niu *np)
4615 {
4616         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
4617         niu_enable_interrupts(np, 0);
4618
4619         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
4620         niu_enable_rx_mac(np, 0);
4621
4622         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
4623         niu_disable_ipp(np);
4624
4625         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
4626         niu_stop_tx_channels(np);
4627
4628         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
4629         niu_stop_rx_channels(np);
4630
4631         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
4632         niu_reset_tx_channels(np);
4633
4634         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
4635         niu_reset_rx_channels(np);
4636 }
4637
4638 static int niu_request_irq(struct niu *np)
4639 {
4640         int i, j, err;
4641
4642         err = 0;
4643         for (i = 0; i < np->num_ldg; i++) {
4644                 struct niu_ldg *lp = &np->ldg[i];
4645
4646                 err = request_irq(lp->irq, niu_interrupt,
4647                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
4648                                   np->dev->name, lp);
4649                 if (err)
4650                         goto out_free_irqs;
4651
4652         }
4653
4654         return 0;
4655
4656 out_free_irqs:
4657         for (j = 0; j < i; j++) {
4658                 struct niu_ldg *lp = &np->ldg[j];
4659
4660                 free_irq(lp->irq, lp);
4661         }
4662         return err;
4663 }
4664
4665 static void niu_free_irq(struct niu *np)
4666 {
4667         int i;
4668
4669         for (i = 0; i < np->num_ldg; i++) {
4670                 struct niu_ldg *lp = &np->ldg[i];
4671
4672                 free_irq(lp->irq, lp);
4673         }
4674 }
4675
4676 static void niu_enable_napi(struct niu *np)
4677 {
4678         int i;
4679
4680         for (i = 0; i < np->num_ldg; i++)
4681                 napi_enable(&np->ldg[i].napi);
4682 }
4683
4684 static void niu_disable_napi(struct niu *np)
4685 {
4686         int i;
4687
4688         for (i = 0; i < np->num_ldg; i++)
4689                 napi_disable(&np->ldg[i].napi);
4690 }
4691
4692 static int niu_open(struct net_device *dev)
4693 {
4694         struct niu *np = netdev_priv(dev);
4695         int err;
4696
4697         netif_carrier_off(dev);
4698
4699         err = niu_alloc_channels(np);
4700         if (err)
4701                 goto out_err;
4702
4703         err = niu_enable_interrupts(np, 0);
4704         if (err)
4705                 goto out_free_channels;
4706
4707         err = niu_request_irq(np);
4708         if (err)
4709                 goto out_free_channels;
4710
4711         niu_enable_napi(np);
4712
4713         spin_lock_irq(&np->lock);
4714
4715         err = niu_init_hw(np);
4716         if (!err) {
4717                 init_timer(&np->timer);
4718                 np->timer.expires = jiffies + HZ;
4719                 np->timer.data = (unsigned long) np;
4720                 np->timer.function = niu_timer;
4721
4722                 err = niu_enable_interrupts(np, 1);
4723                 if (err)
4724                         niu_stop_hw(np);
4725         }
4726
4727         spin_unlock_irq(&np->lock);
4728
4729         if (err) {
4730                 niu_disable_napi(np);
4731                 goto out_free_irq;
4732         }
4733
4734         netif_start_queue(dev);
4735
4736         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
4737                 netif_carrier_on(dev);
4738
4739         add_timer(&np->timer);
4740
4741         return 0;
4742
4743 out_free_irq:
4744         niu_free_irq(np);
4745
4746 out_free_channels:
4747         niu_free_channels(np);
4748
4749 out_err:
4750         return err;
4751 }
4752
4753 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
4754 {
4755         cancel_work_sync(&np->reset_task);
4756
4757         niu_disable_napi(np);
4758         netif_stop_queue(dev);
4759
4760         del_timer_sync(&np->timer);
4761
4762         spin_lock_irq(&np->lock);
4763
4764         niu_stop_hw(np);
4765
4766         spin_unlock_irq(&np->lock);
4767 }
4768
4769 static int niu_close(struct net_device *dev)
4770 {
4771         struct niu *np = netdev_priv(dev);
4772
4773         niu_full_shutdown(np, dev);
4774
4775         niu_free_irq(np);
4776
4777         niu_free_channels(np);
4778
4779         return 0;
4780 }
4781
4782 static void niu_sync_xmac_stats(struct niu *np)
4783 {
4784         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
4785
4786         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
4787         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
4788
4789         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
4790         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
4791         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
4792         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
4793         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
4794         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
4795         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
4796         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
4797         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
4798         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
4799         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
4800         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
4801         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
4802         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
4803         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
4804         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
4805 }
4806
4807 static void niu_sync_bmac_stats(struct niu *np)
4808 {
4809         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4810
4811         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
4812         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
4813
4814         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
4815         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4816         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4817         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
4818 }
4819
4820 static void niu_sync_mac_stats(struct niu *np)
4821 {
4822         if (np->flags & NIU_FLAGS_XMAC)
4823                 niu_sync_xmac_stats(np);
4824         else
4825                 niu_sync_bmac_stats(np);
4826 }
4827
4828 static void niu_get_rx_stats(struct niu *np)
4829 {
4830         unsigned long pkts, dropped, errors, bytes;
4831         int i;
4832
4833         pkts = dropped = errors = bytes = 0;
4834         for (i = 0; i < np->num_rx_rings; i++) {
4835                 struct rx_ring_info *rp = &np->rx_rings[i];
4836
4837                 pkts += rp->rx_packets;
4838                 bytes += rp->rx_bytes;
4839                 dropped += rp->rx_dropped;
4840                 errors += rp->rx_errors;
4841         }
4842         np->net_stats.rx_packets = pkts;
4843         np->net_stats.rx_bytes = bytes;
4844         np->net_stats.rx_dropped = dropped;
4845         np->net_stats.rx_errors = errors;
4846 }
4847
4848 static void niu_get_tx_stats(struct niu *np)
4849 {
4850         unsigned long pkts, errors, bytes;
4851         int i;
4852
4853         pkts = errors = bytes = 0;
4854         for (i = 0; i < np->num_tx_rings; i++) {
4855                 struct tx_ring_info *rp = &np->tx_rings[i];
4856
4857                 pkts += rp->tx_packets;
4858                 bytes += rp->tx_bytes;
4859                 errors += rp->tx_errors;
4860         }
4861         np->net_stats.tx_packets = pkts;
4862         np->net_stats.tx_bytes = bytes;
4863         np->net_stats.tx_errors = errors;
4864 }
4865
4866 static struct net_device_stats *niu_get_stats(struct net_device *dev)
4867 {
4868         struct niu *np = netdev_priv(dev);
4869
4870         niu_get_rx_stats(np);
4871         niu_get_tx_stats(np);
4872
4873         return &np->net_stats;
4874 }
4875
4876 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
4877 {
4878         int i;
4879
4880         for (i = 0; i < 16; i++)
4881                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
4882 }
4883
4884 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
4885 {
4886         int i;
4887
4888         for (i = 0; i < 16; i++)
4889                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
4890 }
4891
4892 static void niu_load_hash(struct niu *np, u16 *hash)
4893 {
4894         if (np->flags & NIU_FLAGS_XMAC)
4895                 niu_load_hash_xmac(np, hash);
4896         else
4897                 niu_load_hash_bmac(np, hash);
4898 }
4899
4900 static void niu_set_rx_mode(struct net_device *dev)
4901 {
4902         struct niu *np = netdev_priv(dev);
4903         int i, alt_cnt, err;
4904         struct dev_addr_list *addr;
4905         unsigned long flags;
4906         u16 hash[16] = { 0, };
4907
4908         spin_lock_irqsave(&np->lock, flags);
4909         niu_enable_rx_mac(np, 0);
4910
4911         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
4912         if (dev->flags & IFF_PROMISC)
4913                 np->flags |= NIU_FLAGS_PROMISC;
4914         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
4915                 np->flags |= NIU_FLAGS_MCAST;
4916
4917         alt_cnt = dev->uc_count;
4918         if (alt_cnt > niu_num_alt_addr(np)) {
4919                 alt_cnt = 0;
4920                 np->flags |= NIU_FLAGS_PROMISC;
4921         }
4922
4923         if (alt_cnt) {
4924                 int index = 0;
4925
4926                 for (addr = dev->uc_list; addr; addr = addr->next) {
4927                         err = niu_set_alt_mac(np, index,
4928                                               addr->da_addr);
4929                         if (err)
4930                                 printk(KERN_WARNING PFX "%s: Error %d "
4931                                        "adding alt mac %d\n",
4932                                        dev->name, err, index);
4933                         err = niu_enable_alt_mac(np, index, 1);
4934                         if (err)
4935                                 printk(KERN_WARNING PFX "%s: Error %d "
4936                                        "enabling alt mac %d\n",
4937                                        dev->name, err, index);
4938
4939                         index++;
4940                 }
4941         } else {
4942                 for (i = 0; i < niu_num_alt_addr(np); i++) {
4943                         err = niu_enable_alt_mac(np, i, 0);
4944                         if (err)
4945                                 printk(KERN_WARNING PFX "%s: Error %d "
4946                                        "disabling alt mac %d\n",
4947                                        dev->name, err, i);
4948                 }
4949         }
4950         if (dev->flags & IFF_ALLMULTI) {
4951                 for (i = 0; i < 16; i++)
4952                         hash[i] = 0xffff;
4953         } else if (dev->mc_count > 0) {
4954                 for (addr = dev->mc_list; addr; addr = addr->next) {
4955                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
4956
4957                         crc >>= 24;
4958                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
4959                 }
4960         }
4961
4962         if (np->flags & NIU_FLAGS_MCAST)
4963                 niu_load_hash(np, hash);
4964
4965         niu_enable_rx_mac(np, 1);
4966         spin_unlock_irqrestore(&np->lock, flags);
4967 }
4968
4969 static int niu_set_mac_addr(struct net_device *dev, void *p)
4970 {
4971         struct niu *np = netdev_priv(dev);
4972         struct sockaddr *addr = p;
4973         unsigned long flags;
4974
4975         if (!is_valid_ether_addr(addr->sa_data))
4976                 return -EINVAL;
4977
4978         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
4979
4980         if (!netif_running(dev))
4981                 return 0;
4982
4983         spin_lock_irqsave(&np->lock, flags);
4984         niu_enable_rx_mac(np, 0);
4985         niu_set_primary_mac(np, dev->dev_addr);
4986         niu_enable_rx_mac(np, 1);
4987         spin_unlock_irqrestore(&np->lock, flags);
4988
4989         return 0;
4990 }
4991
4992 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4993 {
4994         return -EOPNOTSUPP;
4995 }
4996
4997 static void niu_netif_stop(struct niu *np)
4998 {
4999         np->dev->trans_start = jiffies; /* prevent tx timeout */
5000
5001         niu_disable_napi(np);
5002
5003         netif_tx_disable(np->dev);
5004 }
5005
5006 static void niu_netif_start(struct niu *np)
5007 {
5008         /* NOTE: unconditional netif_wake_queue is only appropriate
5009          * so long as all callers are assured to have free tx slots
5010          * (such as after niu_init_hw).
5011          */
5012         netif_wake_queue(np->dev);
5013
5014         niu_enable_napi(np);
5015
5016         niu_enable_interrupts(np, 1);
5017 }
5018
5019 static void niu_reset_task(struct work_struct *work)
5020 {
5021         struct niu *np = container_of(work, struct niu, reset_task);
5022         unsigned long flags;
5023         int err;
5024
5025         spin_lock_irqsave(&np->lock, flags);
5026         if (!netif_running(np->dev)) {
5027                 spin_unlock_irqrestore(&np->lock, flags);
5028                 return;
5029         }
5030
5031         spin_unlock_irqrestore(&np->lock, flags);
5032
5033         del_timer_sync(&np->timer);
5034
5035         niu_netif_stop(np);
5036
5037         spin_lock_irqsave(&np->lock, flags);
5038
5039         niu_stop_hw(np);
5040
5041         err = niu_init_hw(np);
5042         if (!err) {
5043                 np->timer.expires = jiffies + HZ;
5044                 add_timer(&np->timer);
5045                 niu_netif_start(np);
5046         }
5047
5048         spin_unlock_irqrestore(&np->lock, flags);
5049 }
5050
5051 static void niu_tx_timeout(struct net_device *dev)
5052 {
5053         struct niu *np = netdev_priv(dev);
5054
5055         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5056                 dev->name);
5057
5058         schedule_work(&np->reset_task);
5059 }
5060
5061 static void niu_set_txd(struct tx_ring_info *rp, int index,
5062                         u64 mapping, u64 len, u64 mark,
5063                         u64 n_frags)
5064 {
5065         __le64 *desc = &rp->descr[index];
5066
5067         *desc = cpu_to_le64(mark |
5068                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5069                             (len << TX_DESC_TR_LEN_SHIFT) |
5070                             (mapping & TX_DESC_SAD));
5071 }
5072
5073 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5074                                 u64 pad_bytes, u64 len)
5075 {
5076         u16 eth_proto, eth_proto_inner;
5077         u64 csum_bits, l3off, ihl, ret;
5078         u8 ip_proto;
5079         int ipv6;
5080
5081         eth_proto = be16_to_cpu(ehdr->h_proto);
5082         eth_proto_inner = eth_proto;
5083         if (eth_proto == ETH_P_8021Q) {
5084                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5085                 __be16 val = vp->h_vlan_encapsulated_proto;
5086
5087                 eth_proto_inner = be16_to_cpu(val);
5088         }
5089
5090         ipv6 = ihl = 0;
5091         switch (skb->protocol) {
5092         case __constant_htons(ETH_P_IP):
5093                 ip_proto = ip_hdr(skb)->protocol;
5094                 ihl = ip_hdr(skb)->ihl;
5095                 break;
5096         case __constant_htons(ETH_P_IPV6):
5097                 ip_proto = ipv6_hdr(skb)->nexthdr;
5098                 ihl = (40 >> 2);
5099                 ipv6 = 1;
5100                 break;
5101         default:
5102                 ip_proto = ihl = 0;
5103                 break;
5104         }
5105
5106         csum_bits = TXHDR_CSUM_NONE;
5107         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5108                 u64 start, stuff;
5109
5110                 csum_bits = (ip_proto == IPPROTO_TCP ?
5111                              TXHDR_CSUM_TCP :
5112                              (ip_proto == IPPROTO_UDP ?
5113                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5114
5115                 start = skb_transport_offset(skb) -
5116                         (pad_bytes + sizeof(struct tx_pkt_hdr));
5117                 stuff = start + skb->csum_offset;
5118
5119                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5120                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5121         }
5122
5123         l3off = skb_network_offset(skb) -
5124                 (pad_bytes + sizeof(struct tx_pkt_hdr));
5125
5126         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5127                (len << TXHDR_LEN_SHIFT) |
5128                ((l3off / 2) << TXHDR_L3START_SHIFT) |
5129                (ihl << TXHDR_IHL_SHIFT) |
5130                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5131                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5132                (ipv6 ? TXHDR_IP_VER : 0) |
5133                csum_bits);
5134
5135         return ret;
5136 }
5137
5138 static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5139 {
5140         return &np->tx_rings[0];
5141 }
5142
5143 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5144 {
5145         struct niu *np = netdev_priv(dev);
5146         unsigned long align, headroom;
5147         struct tx_ring_info *rp;
5148         struct tx_pkt_hdr *tp;
5149         unsigned int len, nfg;
5150         struct ethhdr *ehdr;
5151         int prod, i, tlen;
5152         u64 mapping, mrk;
5153
5154         rp = tx_ring_select(np, skb);
5155
5156         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5157                 netif_stop_queue(dev);
5158                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5159                         "queue awake!\n", dev->name);
5160                 rp->tx_errors++;
5161                 return NETDEV_TX_BUSY;
5162         }
5163
5164         if (skb->len < ETH_ZLEN) {
5165                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5166
5167                 if (skb_pad(skb, pad_bytes))
5168                         goto out;
5169                 skb_put(skb, pad_bytes);
5170         }
5171
5172         len = sizeof(struct tx_pkt_hdr) + 15;
5173         if (skb_headroom(skb) < len) {
5174                 struct sk_buff *skb_new;
5175
5176                 skb_new = skb_realloc_headroom(skb, len);
5177                 if (!skb_new) {
5178                         rp->tx_errors++;
5179                         goto out_drop;
5180                 }
5181                 kfree_skb(skb);
5182                 skb = skb_new;
5183         }
5184
5185         align = ((unsigned long) skb->data & (16 - 1));
5186         headroom = align + sizeof(struct tx_pkt_hdr);
5187
5188         ehdr = (struct ethhdr *) skb->data;
5189         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5190
5191         len = skb->len - sizeof(struct tx_pkt_hdr);
5192         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5193         tp->resv = 0;
5194
5195         len = skb_headlen(skb);
5196         mapping = np->ops->map_single(np->device, skb->data,
5197                                       len, DMA_TO_DEVICE);
5198
5199         prod = rp->prod;
5200
5201         rp->tx_buffs[prod].skb = skb;
5202         rp->tx_buffs[prod].mapping = mapping;
5203
5204         mrk = TX_DESC_SOP;
5205         if (++rp->mark_counter == rp->mark_freq) {
5206                 rp->mark_counter = 0;
5207                 mrk |= TX_DESC_MARK;
5208                 rp->mark_pending++;
5209         }
5210
5211         tlen = len;
5212         nfg = skb_shinfo(skb)->nr_frags;
5213         while (tlen > 0) {
5214                 tlen -= MAX_TX_DESC_LEN;
5215                 nfg++;
5216         }
5217
5218         while (len > 0) {
5219                 unsigned int this_len = len;
5220
5221                 if (this_len > MAX_TX_DESC_LEN)
5222                         this_len = MAX_TX_DESC_LEN;
5223
5224                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5225                 mrk = nfg = 0;
5226
5227                 prod = NEXT_TX(rp, prod);
5228                 mapping += this_len;
5229                 len -= this_len;
5230         }
5231
5232         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
5233                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5234
5235                 len = frag->size;
5236                 mapping = np->ops->map_page(np->device, frag->page,
5237                                             frag->page_offset, len,
5238                                             DMA_TO_DEVICE);
5239
5240                 rp->tx_buffs[prod].skb = NULL;
5241                 rp->tx_buffs[prod].mapping = mapping;
5242
5243                 niu_set_txd(rp, prod, mapping, len, 0, 0);
5244
5245                 prod = NEXT_TX(rp, prod);
5246         }
5247
5248         if (prod < rp->prod)
5249                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5250         rp->prod = prod;
5251
5252         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5253
5254         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5255                 netif_stop_queue(dev);
5256                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5257                         netif_wake_queue(dev);
5258         }
5259
5260         dev->trans_start = jiffies;
5261
5262 out:
5263         return NETDEV_TX_OK;
5264
5265 out_drop:
5266         rp->tx_errors++;
5267         kfree_skb(skb);
5268         goto out;
5269 }
5270
5271 static int niu_change_mtu(struct net_device *dev, int new_mtu)
5272 {
5273         struct niu *np = netdev_priv(dev);
5274         int err, orig_jumbo, new_jumbo;
5275
5276         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
5277                 return -EINVAL;
5278
5279         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
5280         new_jumbo = (new_mtu > ETH_DATA_LEN);
5281
5282         dev->mtu = new_mtu;
5283
5284         if (!netif_running(dev) ||
5285             (orig_jumbo == new_jumbo))
5286                 return 0;
5287
5288         niu_full_shutdown(np, dev);
5289
5290         niu_free_channels(np);
5291
5292         niu_enable_napi(np);
5293
5294         err = niu_alloc_channels(np);
5295         if (err)
5296                 return err;
5297
5298         spin_lock_irq(&np->lock);
5299
5300         err = niu_init_hw(np);
5301         if (!err) {
5302                 init_timer(&np->timer);
5303                 np->timer.expires = jiffies + HZ;
5304                 np->timer.data = (unsigned long) np;
5305                 np->timer.function = niu_timer;
5306
5307                 err = niu_enable_interrupts(np, 1);
5308                 if (err)
5309                         niu_stop_hw(np);
5310         }
5311
5312         spin_unlock_irq(&np->lock);
5313
5314         if (!err) {
5315                 netif_start_queue(dev);
5316                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5317                         netif_carrier_on(dev);
5318
5319                 add_timer(&np->timer);
5320         }
5321
5322         return err;
5323 }
5324
5325 static void niu_get_drvinfo(struct net_device *dev,
5326                             struct ethtool_drvinfo *info)
5327 {
5328         struct niu *np = netdev_priv(dev);
5329         struct niu_vpd *vpd = &np->vpd;
5330
5331         strcpy(info->driver, DRV_MODULE_NAME);
5332         strcpy(info->version, DRV_MODULE_VERSION);
5333         sprintf(info->fw_version, "%d.%d",
5334                 vpd->fcode_major, vpd->fcode_minor);
5335         if (np->parent->plat_type != PLAT_TYPE_NIU)
5336                 strcpy(info->bus_info, pci_name(np->pdev));
5337 }
5338
5339 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5340 {
5341         struct niu *np = netdev_priv(dev);
5342         struct niu_link_config *lp;
5343
5344         lp = &np->link_config;
5345
5346         memset(cmd, 0, sizeof(*cmd));
5347         cmd->phy_address = np->phy_addr;
5348         cmd->supported = lp->supported;
5349         cmd->advertising = lp->advertising;
5350         cmd->autoneg = lp->autoneg;
5351         cmd->speed = lp->active_speed;
5352         cmd->duplex = lp->active_duplex;
5353
5354         return 0;
5355 }
5356
5357 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5358 {
5359         return -EINVAL;
5360 }
5361
5362 static u32 niu_get_msglevel(struct net_device *dev)
5363 {
5364         struct niu *np = netdev_priv(dev);
5365         return np->msg_enable;
5366 }
5367
5368 static void niu_set_msglevel(struct net_device *dev, u32 value)
5369 {
5370         struct niu *np = netdev_priv(dev);
5371         np->msg_enable = value;
5372 }
5373
5374 static int niu_get_eeprom_len(struct net_device *dev)
5375 {
5376         struct niu *np = netdev_priv(dev);
5377
5378         return np->eeprom_len;
5379 }
5380
5381 static int niu_get_eeprom(struct net_device *dev,
5382                           struct ethtool_eeprom *eeprom, u8 *data)
5383 {
5384         struct niu *np = netdev_priv(dev);
5385         u32 offset, len, val;
5386
5387         offset = eeprom->offset;
5388         len = eeprom->len;
5389
5390         if (offset + len < offset)
5391                 return -EINVAL;
5392         if (offset >= np->eeprom_len)
5393                 return -EINVAL;
5394         if (offset + len > np->eeprom_len)
5395                 len = eeprom->len = np->eeprom_len - offset;
5396
5397         if (offset & 3) {
5398                 u32 b_offset, b_count;
5399
5400                 b_offset = offset & 3;
5401                 b_count = 4 - b_offset;
5402                 if (b_count > len)
5403                         b_count = len;
5404
5405                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
5406                 memcpy(data, ((char *)&val) + b_offset, b_count);
5407                 data += b_count;
5408                 len -= b_count;
5409                 offset += b_count;
5410         }
5411         while (len >= 4) {
5412                 val = nr64(ESPC_NCR(offset / 4));
5413                 memcpy(data, &val, 4);
5414                 data += 4;
5415                 len -= 4;
5416                 offset += 4;
5417         }
5418         if (len) {
5419                 val = nr64(ESPC_NCR(offset / 4));
5420                 memcpy(data, &val, len);
5421         }
5422         return 0;
5423 }
5424
5425 static const struct {
5426         const char string[ETH_GSTRING_LEN];
5427 } niu_xmac_stat_keys[] = {
5428         { "tx_frames" },
5429         { "tx_bytes" },
5430         { "tx_fifo_errors" },
5431         { "tx_overflow_errors" },
5432         { "tx_max_pkt_size_errors" },
5433         { "tx_underflow_errors" },
5434         { "rx_local_faults" },
5435         { "rx_remote_faults" },
5436         { "rx_link_faults" },
5437         { "rx_align_errors" },
5438         { "rx_frags" },
5439         { "rx_mcasts" },
5440         { "rx_bcasts" },
5441         { "rx_hist_cnt1" },
5442         { "rx_hist_cnt2" },
5443         { "rx_hist_cnt3" },
5444         { "rx_hist_cnt4" },
5445         { "rx_hist_cnt5" },
5446         { "rx_hist_cnt6" },
5447         { "rx_hist_cnt7" },
5448         { "rx_octets" },
5449         { "rx_code_violations" },
5450         { "rx_len_errors" },
5451         { "rx_crc_errors" },
5452         { "rx_underflows" },
5453         { "rx_overflows" },
5454         { "pause_off_state" },
5455         { "pause_on_state" },
5456         { "pause_received" },
5457 };
5458
5459 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
5460
5461 static const struct {
5462         const char string[ETH_GSTRING_LEN];
5463 } niu_bmac_stat_keys[] = {
5464         { "tx_underflow_errors" },
5465         { "tx_max_pkt_size_errors" },
5466         { "tx_bytes" },
5467         { "tx_frames" },
5468         { "rx_overflows" },
5469         { "rx_frames" },
5470         { "rx_align_errors" },
5471         { "rx_crc_errors" },
5472         { "rx_len_errors" },
5473         { "pause_off_state" },
5474         { "pause_on_state" },
5475         { "pause_received" },
5476 };
5477
5478 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
5479
5480 static const struct {
5481         const char string[ETH_GSTRING_LEN];
5482 } niu_rxchan_stat_keys[] = {
5483         { "rx_channel" },
5484         { "rx_packets" },
5485         { "rx_bytes" },
5486         { "rx_dropped" },
5487         { "rx_errors" },
5488 };
5489
5490 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
5491
5492 static const struct {
5493         const char string[ETH_GSTRING_LEN];
5494 } niu_txchan_stat_keys[] = {
5495         { "tx_channel" },
5496         { "tx_packets" },
5497         { "tx_bytes" },
5498         { "tx_errors" },
5499 };
5500
5501 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
5502
5503 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5504 {
5505         struct niu *np = netdev_priv(dev);
5506         int i;
5507
5508         if (stringset != ETH_SS_STATS)
5509                 return;
5510
5511         if (np->flags & NIU_FLAGS_XMAC) {
5512                 memcpy(data, niu_xmac_stat_keys,
5513                        sizeof(niu_xmac_stat_keys));
5514                 data += sizeof(niu_xmac_stat_keys);
5515         } else {
5516                 memcpy(data, niu_bmac_stat_keys,
5517                        sizeof(niu_bmac_stat_keys));
5518                 data += sizeof(niu_bmac_stat_keys);
5519         }
5520         for (i = 0; i < np->num_rx_rings; i++) {
5521                 memcpy(data, niu_rxchan_stat_keys,
5522                        sizeof(niu_rxchan_stat_keys));
5523                 data += sizeof(niu_rxchan_stat_keys);
5524         }
5525         for (i = 0; i < np->num_tx_rings; i++) {
5526                 memcpy(data, niu_txchan_stat_keys,
5527                        sizeof(niu_txchan_stat_keys));
5528                 data += sizeof(niu_txchan_stat_keys);
5529         }
5530 }
5531
5532 static int niu_get_stats_count(struct net_device *dev)
5533 {
5534         struct niu *np = netdev_priv(dev);
5535
5536         return ((np->flags & NIU_FLAGS_XMAC ?
5537                  NUM_XMAC_STAT_KEYS :
5538                  NUM_BMAC_STAT_KEYS) +
5539                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
5540                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
5541 }
5542
5543 static void niu_get_ethtool_stats(struct net_device *dev,
5544                                   struct ethtool_stats *stats, u64 *data)
5545 {
5546         struct niu *np = netdev_priv(dev);
5547         int i;
5548
5549         niu_sync_mac_stats(np);
5550         if (np->flags & NIU_FLAGS_XMAC) {
5551                 memcpy(data, &np->mac_stats.xmac,
5552                        sizeof(struct niu_xmac_stats));
5553                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
5554         } else {
5555                 memcpy(data, &np->mac_stats.bmac,
5556                        sizeof(struct niu_bmac_stats));
5557                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
5558         }
5559         for (i = 0; i < np->num_rx_rings; i++) {
5560                 struct rx_ring_info *rp = &np->rx_rings[i];
5561
5562                 data[0] = rp->rx_channel;
5563                 data[1] = rp->rx_packets;
5564                 data[2] = rp->rx_bytes;
5565                 data[3] = rp->rx_dropped;
5566                 data[4] = rp->rx_errors;
5567                 data += 5;
5568         }
5569         for (i = 0; i < np->num_tx_rings; i++) {
5570                 struct tx_ring_info *rp = &np->tx_rings[i];
5571
5572                 data[0] = rp->tx_channel;
5573                 data[1] = rp->tx_packets;
5574                 data[2] = rp->tx_bytes;
5575                 data[3] = rp->tx_errors;
5576                 data += 4;
5577         }
5578 }
5579
5580 static u64 niu_led_state_save(struct niu *np)
5581 {
5582         if (np->flags & NIU_FLAGS_XMAC)
5583                 return nr64_mac(XMAC_CONFIG);
5584         else
5585                 return nr64_mac(BMAC_XIF_CONFIG);
5586 }
5587
5588 static void niu_led_state_restore(struct niu *np, u64 val)
5589 {
5590         if (np->flags & NIU_FLAGS_XMAC)
5591                 nw64_mac(XMAC_CONFIG, val);
5592         else
5593                 nw64_mac(BMAC_XIF_CONFIG, val);
5594 }
5595
5596 static void niu_force_led(struct niu *np, int on)
5597 {
5598         u64 val, reg, bit;
5599
5600         if (np->flags & NIU_FLAGS_XMAC) {
5601                 reg = XMAC_CONFIG;
5602                 bit = XMAC_CONFIG_FORCE_LED_ON;
5603         } else {
5604                 reg = BMAC_XIF_CONFIG;
5605                 bit = BMAC_XIF_CONFIG_LINK_LED;
5606         }
5607
5608         val = nr64_mac(reg);
5609         if (on)
5610                 val |= bit;
5611         else
5612                 val &= ~bit;
5613         nw64_mac(reg, val);
5614 }
5615
5616 static int niu_phys_id(struct net_device *dev, u32 data)
5617 {
5618         struct niu *np = netdev_priv(dev);
5619         u64 orig_led_state;
5620         int i;
5621
5622         if (!netif_running(dev))
5623                 return -EAGAIN;
5624
5625         if (data == 0)
5626                 data = 2;
5627
5628         orig_led_state = niu_led_state_save(np);
5629         for (i = 0; i < (data * 2); i++) {
5630                 int on = ((i % 2) == 0);
5631
5632                 niu_force_led(np, on);
5633
5634                 if (msleep_interruptible(500))
5635                         break;
5636         }
5637         niu_led_state_restore(np, orig_led_state);
5638
5639         return 0;
5640 }
5641
5642 static const struct ethtool_ops niu_ethtool_ops = {
5643         .get_drvinfo            = niu_get_drvinfo,
5644         .get_link               = ethtool_op_get_link,
5645         .get_msglevel           = niu_get_msglevel,
5646         .set_msglevel           = niu_set_msglevel,
5647         .get_eeprom_len         = niu_get_eeprom_len,
5648         .get_eeprom             = niu_get_eeprom,
5649         .get_settings           = niu_get_settings,
5650         .set_settings           = niu_set_settings,
5651         .get_strings            = niu_get_strings,
5652         .get_stats_count        = niu_get_stats_count,
5653         .get_ethtool_stats      = niu_get_ethtool_stats,
5654         .phys_id                = niu_phys_id,
5655 };
5656
5657 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
5658                               int ldg, int ldn)
5659 {
5660         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
5661                 return -EINVAL;
5662         if (ldn < 0 || ldn > LDN_MAX)
5663                 return -EINVAL;
5664
5665         parent->ldg_map[ldn] = ldg;
5666
5667         if (np->parent->plat_type == PLAT_TYPE_NIU) {
5668                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
5669                  * the firmware, and we're not supposed to change them.
5670                  * Validate the mapping, because if it's wrong we probably
5671                  * won't get any interrupts and that's painful to debug.
5672                  */
5673                 if (nr64(LDG_NUM(ldn)) != ldg) {
5674                         dev_err(np->device, PFX "Port %u, mis-matched "
5675                                 "LDG assignment "
5676                                 "for ldn %d, should be %d is %llu\n",
5677                                 np->port, ldn, ldg,
5678                                 (unsigned long long) nr64(LDG_NUM(ldn)));
5679                         return -EINVAL;
5680                 }
5681         } else
5682                 nw64(LDG_NUM(ldn), ldg);
5683
5684         return 0;
5685 }
5686
5687 static int niu_set_ldg_timer_res(struct niu *np, int res)
5688 {
5689         if (res < 0 || res > LDG_TIMER_RES_VAL)
5690                 return -EINVAL;
5691
5692
5693         nw64(LDG_TIMER_RES, res);
5694
5695         return 0;
5696 }
5697
5698 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
5699 {
5700         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
5701             (func < 0 || func > 3) ||
5702             (vector < 0 || vector > 0x1f))
5703                 return -EINVAL;
5704
5705         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
5706
5707         return 0;
5708 }
5709
5710 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
5711 {
5712         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
5713                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
5714         int limit;
5715
5716         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
5717                 return -EINVAL;
5718
5719         frame = frame_base;
5720         nw64(ESPC_PIO_STAT, frame);
5721         limit = 64;
5722         do {
5723                 udelay(5);
5724                 frame = nr64(ESPC_PIO_STAT);
5725                 if (frame & ESPC_PIO_STAT_READ_END)
5726                         break;
5727         } while (limit--);
5728         if (!(frame & ESPC_PIO_STAT_READ_END)) {
5729                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5730                         (unsigned long long) frame);
5731                 return -ENODEV;
5732         }
5733
5734         frame = frame_base;
5735         nw64(ESPC_PIO_STAT, frame);
5736         limit = 64;
5737         do {
5738                 udelay(5);
5739                 frame = nr64(ESPC_PIO_STAT);
5740                 if (frame & ESPC_PIO_STAT_READ_END)
5741                         break;
5742         } while (limit--);
5743         if (!(frame & ESPC_PIO_STAT_READ_END)) {
5744                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5745                         (unsigned long long) frame);
5746                 return -ENODEV;
5747         }
5748
5749         frame = nr64(ESPC_PIO_STAT);
5750         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
5751 }
5752
5753 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
5754 {
5755         int err = niu_pci_eeprom_read(np, off);
5756         u16 val;
5757
5758         if (err < 0)
5759                 return err;
5760         val = (err << 8);
5761         err = niu_pci_eeprom_read(np, off + 1);
5762         if (err < 0)
5763                 return err;
5764         val |= (err & 0xff);
5765
5766         return val;
5767 }
5768
5769 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
5770 {
5771         int err = niu_pci_eeprom_read(np, off);
5772         u16 val;
5773
5774         if (err < 0)
5775                 return err;
5776
5777         val = (err & 0xff);
5778         err = niu_pci_eeprom_read(np, off + 1);
5779         if (err < 0)
5780                 return err;
5781
5782         val |= (err & 0xff) << 8;
5783
5784         return val;
5785 }
5786
5787 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
5788                                               u32 off,
5789                                               char *namebuf,
5790                                               int namebuf_len)
5791 {
5792         int i;
5793
5794         for (i = 0; i < namebuf_len; i++) {
5795                 int err = niu_pci_eeprom_read(np, off + i);
5796                 if (err < 0)
5797                         return err;
5798                 *namebuf++ = err;
5799                 if (!err)
5800                         break;
5801         }
5802         if (i >= namebuf_len)
5803                 return -EINVAL;
5804
5805         return i + 1;
5806 }
5807
5808 static void __devinit niu_vpd_parse_version(struct niu *np)
5809 {
5810         struct niu_vpd *vpd = &np->vpd;
5811         int len = strlen(vpd->version) + 1;
5812         const char *s = vpd->version;
5813         int i;
5814
5815         for (i = 0; i < len - 5; i++) {
5816                 if (!strncmp(s + i, "FCode ", 5))
5817                         break;
5818         }
5819         if (i >= len - 5)
5820                 return;
5821
5822         s += i + 5;
5823         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
5824
5825         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
5826                vpd->fcode_major, vpd->fcode_minor);
5827         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
5828             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
5829              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
5830                 np->flags |= NIU_FLAGS_VPD_VALID;
5831 }
5832
5833 /* ESPC_PIO_EN_ENABLE must be set */
5834 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
5835                                             u32 start, u32 end)
5836 {
5837         unsigned int found_mask = 0;
5838 #define FOUND_MASK_MODEL        0x00000001
5839 #define FOUND_MASK_BMODEL       0x00000002
5840 #define FOUND_MASK_VERS         0x00000004
5841 #define FOUND_MASK_MAC          0x00000008
5842 #define FOUND_MASK_NMAC         0x00000010
5843 #define FOUND_MASK_PHY          0x00000020
5844 #define FOUND_MASK_ALL          0x0000003f
5845
5846         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
5847                start, end);
5848         while (start < end) {
5849                 int len, err, instance, type, prop_len;
5850                 char namebuf[64];
5851                 u8 *prop_buf;
5852                 int max_len;
5853
5854                 if (found_mask == FOUND_MASK_ALL) {
5855                         niu_vpd_parse_version(np);
5856                         return 1;
5857                 }
5858
5859                 err = niu_pci_eeprom_read(np, start + 2);
5860                 if (err < 0)
5861                         return err;
5862                 len = err;
5863                 start += 3;
5864
5865                 instance = niu_pci_eeprom_read(np, start);
5866                 type = niu_pci_eeprom_read(np, start + 3);
5867                 prop_len = niu_pci_eeprom_read(np, start + 4);
5868                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
5869                 if (err < 0)
5870                         return err;
5871
5872                 prop_buf = NULL;
5873                 max_len = 0;
5874                 if (!strcmp(namebuf, "model")) {
5875                         prop_buf = np->vpd.model;
5876                         max_len = NIU_VPD_MODEL_MAX;
5877                         found_mask |= FOUND_MASK_MODEL;
5878                 } else if (!strcmp(namebuf, "board-model")) {
5879                         prop_buf = np->vpd.board_model;
5880                         max_len = NIU_VPD_BD_MODEL_MAX;
5881                         found_mask |= FOUND_MASK_BMODEL;
5882                 } else if (!strcmp(namebuf, "version")) {
5883                         prop_buf = np->vpd.version;
5884                         max_len = NIU_VPD_VERSION_MAX;
5885                         found_mask |= FOUND_MASK_VERS;
5886                 } else if (!strcmp(namebuf, "local-mac-address")) {
5887                         prop_buf = np->vpd.local_mac;
5888                         max_len = ETH_ALEN;
5889                         found_mask |= FOUND_MASK_MAC;
5890                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
5891                         prop_buf = &np->vpd.mac_num;
5892                         max_len = 1;
5893                         found_mask |= FOUND_MASK_NMAC;
5894                 } else if (!strcmp(namebuf, "phy-type")) {
5895                         prop_buf = np->vpd.phy_type;
5896                         max_len = NIU_VPD_PHY_TYPE_MAX;
5897                         found_mask |= FOUND_MASK_PHY;
5898                 }
5899
5900                 if (max_len && prop_len > max_len) {
5901                         dev_err(np->device, PFX "Property '%s' length (%d) is "
5902                                 "too long.\n", namebuf, prop_len);
5903                         return -EINVAL;
5904                 }
5905
5906                 if (prop_buf) {
5907                         u32 off = start + 5 + err;
5908                         int i;
5909
5910                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
5911                                "len[%d]\n", namebuf, prop_len);
5912                         for (i = 0; i < prop_len; i++)
5913                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
5914                 }
5915
5916                 start += len;
5917         }
5918
5919         return 0;
5920 }
5921
5922 /* ESPC_PIO_EN_ENABLE must be set */
5923 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
5924 {
5925         u32 offset;
5926         int err;
5927
5928         err = niu_pci_eeprom_read16_swp(np, start + 1);
5929         if (err < 0)
5930                 return;
5931
5932         offset = err + 3;
5933
5934         while (start + offset < ESPC_EEPROM_SIZE) {
5935                 u32 here = start + offset;
5936                 u32 end;
5937
5938                 err = niu_pci_eeprom_read(np, here);
5939                 if (err != 0x90)
5940                         return;
5941
5942                 err = niu_pci_eeprom_read16_swp(np, here + 1);
5943                 if (err < 0)
5944                         return;
5945
5946                 here = start + offset + 3;
5947                 end = start + offset + err;
5948
5949                 offset += err;
5950
5951                 err = niu_pci_vpd_scan_props(np, here, end);
5952                 if (err < 0 || err == 1)
5953                         return;
5954         }
5955 }
5956
5957 /* ESPC_PIO_EN_ENABLE must be set */
5958 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
5959 {
5960         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
5961         int err;
5962
5963         while (start < end) {
5964                 ret = start;
5965
5966                 /* ROM header signature?  */
5967                 err = niu_pci_eeprom_read16(np, start +  0);
5968                 if (err != 0x55aa)
5969                         return 0;
5970
5971                 /* Apply offset to PCI data structure.  */
5972                 err = niu_pci_eeprom_read16(np, start + 23);
5973                 if (err < 0)
5974                         return 0;
5975                 start += err;
5976
5977                 /* Check for "PCIR" signature.  */
5978                 err = niu_pci_eeprom_read16(np, start +  0);
5979                 if (err != 0x5043)
5980                         return 0;
5981                 err = niu_pci_eeprom_read16(np, start +  2);
5982                 if (err != 0x4952)
5983                         return 0;
5984
5985                 /* Check for OBP image type.  */
5986                 err = niu_pci_eeprom_read(np, start + 20);
5987                 if (err < 0)
5988                         return 0;
5989                 if (err != 0x01) {
5990                         err = niu_pci_eeprom_read(np, ret + 2);
5991                         if (err < 0)
5992                                 return 0;
5993
5994                         start = ret + (err * 512);
5995                         continue;
5996                 }
5997
5998                 err = niu_pci_eeprom_read16_swp(np, start + 8);
5999                 if (err < 0)
6000                         return err;
6001                 ret += err;
6002
6003                 err = niu_pci_eeprom_read(np, ret + 0);
6004                 if (err != 0x82)
6005                         return 0;
6006
6007                 return ret;
6008         }
6009
6010         return 0;
6011 }
6012
6013 static int __devinit niu_phy_type_prop_decode(struct niu *np,
6014                                               const char *phy_prop)
6015 {
6016         if (!strcmp(phy_prop, "mif")) {
6017                 /* 1G copper, MII */
6018                 np->flags &= ~(NIU_FLAGS_FIBER |
6019                                NIU_FLAGS_10G);
6020                 np->mac_xcvr = MAC_XCVR_MII;
6021         } else if (!strcmp(phy_prop, "xgf")) {
6022                 /* 10G fiber, XPCS */
6023                 np->flags |= (NIU_FLAGS_10G |
6024                               NIU_FLAGS_FIBER);
6025                 np->mac_xcvr = MAC_XCVR_XPCS;
6026         } else if (!strcmp(phy_prop, "pcs")) {
6027                 /* 1G fiber, PCS */
6028                 np->flags &= ~NIU_FLAGS_10G;
6029                 np->flags |= NIU_FLAGS_FIBER;
6030                 np->mac_xcvr = MAC_XCVR_PCS;
6031         } else if (!strcmp(phy_prop, "xgc")) {
6032                 /* 10G copper, XPCS */
6033                 np->flags |= NIU_FLAGS_10G;
6034                 np->flags &= ~NIU_FLAGS_FIBER;
6035                 np->mac_xcvr = MAC_XCVR_XPCS;
6036         } else {
6037                 return -EINVAL;
6038         }
6039         return 0;
6040 }
6041
6042 static void __devinit niu_pci_vpd_validate(struct niu *np)
6043 {
6044         struct net_device *dev = np->dev;
6045         struct niu_vpd *vpd = &np->vpd;
6046         u8 val8;
6047
6048         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6049                 dev_err(np->device, PFX "VPD MAC invalid, "
6050                         "falling back to SPROM.\n");
6051
6052                 np->flags &= ~NIU_FLAGS_VPD_VALID;
6053                 return;
6054         }
6055
6056         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6057                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6058                         np->vpd.phy_type);
6059                 dev_err(np->device, PFX "Falling back to SPROM.\n");
6060                 np->flags &= ~NIU_FLAGS_VPD_VALID;
6061                 return;
6062         }
6063
6064         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6065
6066         val8 = dev->perm_addr[5];
6067         dev->perm_addr[5] += np->port;
6068         if (dev->perm_addr[5] < val8)
6069                 dev->perm_addr[4]++;
6070
6071         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6072 }
6073
6074 static int __devinit niu_pci_probe_sprom(struct niu *np)
6075 {
6076         struct net_device *dev = np->dev;
6077         int len, i;
6078         u64 val, sum;
6079         u8 val8;
6080
6081         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6082         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6083         len = val / 4;
6084
6085         np->eeprom_len = len;
6086
6087         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6088
6089         sum = 0;
6090         for (i = 0; i < len; i++) {
6091                 val = nr64(ESPC_NCR(i));
6092                 sum += (val >>  0) & 0xff;
6093                 sum += (val >>  8) & 0xff;
6094                 sum += (val >> 16) & 0xff;
6095                 sum += (val >> 24) & 0xff;
6096         }
6097         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6098         if ((sum & 0xff) != 0xab) {
6099                 dev_err(np->device, PFX "Bad SPROM checksum "
6100                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
6101                 return -EINVAL;
6102         }
6103
6104         val = nr64(ESPC_PHY_TYPE);
6105         switch (np->port) {
6106         case 0:
6107                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
6108                         ESPC_PHY_TYPE_PORT0_SHIFT;
6109                 break;
6110         case 1:
6111                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
6112                         ESPC_PHY_TYPE_PORT1_SHIFT;
6113                 break;
6114         case 2:
6115                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
6116                         ESPC_PHY_TYPE_PORT2_SHIFT;
6117                 break;
6118         case 3:
6119                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
6120                         ESPC_PHY_TYPE_PORT3_SHIFT;
6121                 break;
6122         default:
6123                 dev_err(np->device, PFX "Bogus port number %u\n",
6124                         np->port);
6125                 return -EINVAL;
6126         }
6127         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
6128
6129         switch (val8) {
6130         case ESPC_PHY_TYPE_1G_COPPER:
6131                 /* 1G copper, MII */
6132                 np->flags &= ~(NIU_FLAGS_FIBER |
6133                                NIU_FLAGS_10G);
6134                 np->mac_xcvr = MAC_XCVR_MII;
6135                 break;
6136
6137         case ESPC_PHY_TYPE_1G_FIBER:
6138                 /* 1G fiber, PCS */
6139                 np->flags &= ~NIU_FLAGS_10G;
6140                 np->flags |= NIU_FLAGS_FIBER;
6141                 np->mac_xcvr = MAC_XCVR_PCS;
6142                 break;
6143
6144         case ESPC_PHY_TYPE_10G_COPPER:
6145                 /* 10G copper, XPCS */
6146                 np->flags |= NIU_FLAGS_10G;
6147                 np->flags &= ~NIU_FLAGS_FIBER;
6148                 np->mac_xcvr = MAC_XCVR_XPCS;
6149                 break;
6150
6151         case ESPC_PHY_TYPE_10G_FIBER:
6152                 /* 10G fiber, XPCS */
6153                 np->flags |= (NIU_FLAGS_10G |
6154                               NIU_FLAGS_FIBER);
6155                 np->mac_xcvr = MAC_XCVR_XPCS;
6156                 break;
6157
6158         default:
6159                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
6160                 return -EINVAL;
6161         }
6162
6163         val = nr64(ESPC_MAC_ADDR0);
6164         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6165                (unsigned long long) val);
6166         dev->perm_addr[0] = (val >>  0) & 0xff;
6167         dev->perm_addr[1] = (val >>  8) & 0xff;
6168         dev->perm_addr[2] = (val >> 16) & 0xff;
6169         dev->perm_addr[3] = (val >> 24) & 0xff;
6170
6171         val = nr64(ESPC_MAC_ADDR1);
6172         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6173                (unsigned long long) val);
6174         dev->perm_addr[4] = (val >>  0) & 0xff;
6175         dev->perm_addr[5] = (val >>  8) & 0xff;
6176
6177         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6178                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6179                 dev_err(np->device, PFX "[ \n");
6180                 for (i = 0; i < 6; i++)
6181                         printk("%02x ", dev->perm_addr[i]);
6182                 printk("]\n");
6183                 return -EINVAL;
6184         }
6185
6186         val8 = dev->perm_addr[5];
6187         dev->perm_addr[5] += np->port;
6188         if (dev->perm_addr[5] < val8)
6189                 dev->perm_addr[4]++;
6190
6191         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6192
6193         val = nr64(ESPC_MOD_STR_LEN);
6194         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6195                (unsigned long long) val);
6196         if (val >= 8 * 4)
6197                 return -EINVAL;
6198
6199         for (i = 0; i < val; i += 4) {
6200                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6201
6202                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
6203                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
6204                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6205                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6206         }
6207         np->vpd.model[val] = '\0';
6208
6209         val = nr64(ESPC_BD_MOD_STR_LEN);
6210         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6211                (unsigned long long) val);
6212         if (val >= 4 * 4)
6213                 return -EINVAL;
6214
6215         for (i = 0; i < val; i += 4) {
6216                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6217
6218                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
6219                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
6220                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6221                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6222         }
6223         np->vpd.board_model[val] = '\0';
6224
6225         np->vpd.mac_num =
6226                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
6227         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
6228                np->vpd.mac_num);
6229
6230         return 0;
6231 }
6232
6233 static int __devinit niu_get_and_validate_port(struct niu *np)
6234 {
6235         struct niu_parent *parent = np->parent;
6236
6237         if (np->port <= 1)
6238                 np->flags |= NIU_FLAGS_XMAC;
6239
6240         if (!parent->num_ports) {
6241                 if (parent->plat_type == PLAT_TYPE_NIU) {
6242                         parent->num_ports = 2;
6243                 } else {
6244                         parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
6245                                 ESPC_NUM_PORTS_MACS_VAL;
6246
6247                         if (!parent->num_ports)
6248                                 parent->num_ports = 4;
6249                 }
6250         }
6251
6252         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
6253                np->port, parent->num_ports);
6254         if (np->port >= parent->num_ports)
6255                 return -ENODEV;
6256
6257         return 0;
6258 }
6259
6260 static int __devinit phy_record(struct niu_parent *parent,
6261                                 struct phy_probe_info *p,
6262                                 int dev_id_1, int dev_id_2, u8 phy_port,
6263                                 int type)
6264 {
6265         u32 id = (dev_id_1 << 16) | dev_id_2;
6266         u8 idx;
6267
6268         if (dev_id_1 < 0 || dev_id_2 < 0)
6269                 return 0;
6270         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
6271                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704)
6272                         return 0;
6273         } else {
6274                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
6275                         return 0;
6276         }
6277
6278         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
6279                 parent->index, id,
6280                 (type == PHY_TYPE_PMA_PMD ?
6281                  "PMA/PMD" :
6282                  (type == PHY_TYPE_PCS ?
6283                   "PCS" : "MII")),
6284                 phy_port);
6285
6286         if (p->cur[type] >= NIU_MAX_PORTS) {
6287                 printk(KERN_ERR PFX "Too many PHY ports.\n");
6288                 return -EINVAL;
6289         }
6290         idx = p->cur[type];
6291         p->phy_id[type][idx] = id;
6292         p->phy_port[type][idx] = phy_port;
6293         p->cur[type] = idx + 1;
6294         return 0;
6295 }
6296
6297 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
6298 {
6299         int i;
6300
6301         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
6302                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
6303                         return 1;
6304         }
6305         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
6306                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
6307                         return 1;
6308         }
6309
6310         return 0;
6311 }
6312
6313 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
6314 {
6315         int port, cnt;
6316
6317         cnt = 0;
6318         *lowest = 32;
6319         for (port = 8; port < 32; port++) {
6320                 if (port_has_10g(p, port)) {
6321                         if (!cnt)
6322                                 *lowest = port;
6323                         cnt++;
6324                 }
6325         }
6326
6327         return cnt;
6328 }
6329
6330 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
6331 {
6332         *lowest = 32;
6333         if (p->cur[PHY_TYPE_MII])
6334                 *lowest = p->phy_port[PHY_TYPE_MII][0];
6335
6336         return p->cur[PHY_TYPE_MII];
6337 }
6338
6339 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
6340 {
6341         int num_ports = parent->num_ports;
6342         int i;
6343
6344         for (i = 0; i < num_ports; i++) {
6345                 parent->rxchan_per_port[i] = (16 / num_ports);
6346                 parent->txchan_per_port[i] = (16 / num_ports);
6347
6348                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6349                         "[%u TX chans]\n",
6350                         parent->index, i,
6351                         parent->rxchan_per_port[i],
6352                         parent->txchan_per_port[i]);
6353         }
6354 }
6355
6356 static void __devinit niu_divide_channels(struct niu_parent *parent,
6357                                           int num_10g, int num_1g)
6358 {
6359         int num_ports = parent->num_ports;
6360         int rx_chans_per_10g, rx_chans_per_1g;
6361         int tx_chans_per_10g, tx_chans_per_1g;
6362         int i, tot_rx, tot_tx;
6363
6364         if (!num_10g || !num_1g) {
6365                 rx_chans_per_10g = rx_chans_per_1g =
6366                         (NIU_NUM_RXCHAN / num_ports);
6367                 tx_chans_per_10g = tx_chans_per_1g =
6368                         (NIU_NUM_TXCHAN / num_ports);
6369         } else {
6370                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
6371                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
6372                                     (rx_chans_per_1g * num_1g)) /
6373                         num_10g;
6374
6375                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
6376                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
6377                                     (tx_chans_per_1g * num_1g)) /
6378                         num_10g;
6379         }
6380
6381         tot_rx = tot_tx = 0;
6382         for (i = 0; i < num_ports; i++) {
6383                 int type = phy_decode(parent->port_phy, i);
6384
6385                 if (type == PORT_TYPE_10G) {
6386                         parent->rxchan_per_port[i] = rx_chans_per_10g;
6387                         parent->txchan_per_port[i] = tx_chans_per_10g;
6388                 } else {
6389                         parent->rxchan_per_port[i] = rx_chans_per_1g;
6390                         parent->txchan_per_port[i] = tx_chans_per_1g;
6391                 }
6392                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6393                         "[%u TX chans]\n",
6394                         parent->index, i,
6395                         parent->rxchan_per_port[i],
6396                         parent->txchan_per_port[i]);
6397                 tot_rx += parent->rxchan_per_port[i];
6398                 tot_tx += parent->txchan_per_port[i];
6399         }
6400
6401         if (tot_rx > NIU_NUM_RXCHAN) {
6402                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
6403                        "resetting to one per port.\n",
6404                        parent->index, tot_rx);
6405                 for (i = 0; i < num_ports; i++)
6406                         parent->rxchan_per_port[i] = 1;
6407         }
6408         if (tot_tx > NIU_NUM_TXCHAN) {
6409                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
6410                        "resetting to one per port.\n",
6411                        parent->index, tot_tx);
6412                 for (i = 0; i < num_ports; i++)
6413                         parent->txchan_per_port[i] = 1;
6414         }
6415         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
6416                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
6417                        "RX[%d] TX[%d]\n",
6418                        parent->index, tot_rx, tot_tx);
6419         }
6420 }
6421
6422 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
6423                                             int num_10g, int num_1g)
6424 {
6425         int i, num_ports = parent->num_ports;
6426         int rdc_group, rdc_groups_per_port;
6427         int rdc_channel_base;
6428
6429         rdc_group = 0;
6430         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
6431
6432         rdc_channel_base = 0;
6433
6434         for (i = 0; i < num_ports; i++) {
6435                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
6436                 int grp, num_channels = parent->rxchan_per_port[i];
6437                 int this_channel_offset;
6438
6439                 tp->first_table_num = rdc_group;
6440                 tp->num_tables = rdc_groups_per_port;
6441                 this_channel_offset = 0;
6442                 for (grp = 0; grp < tp->num_tables; grp++) {
6443                         struct rdc_table *rt = &tp->tables[grp];
6444                         int slot;
6445
6446                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
6447                                 parent->index, i, tp->first_table_num + grp);
6448                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
6449                                 rt->rxdma_channel[slot] =
6450                                         rdc_channel_base + this_channel_offset;
6451
6452                                 printk("%d ", rt->rxdma_channel[slot]);
6453
6454                                 if (++this_channel_offset == num_channels)
6455                                         this_channel_offset = 0;
6456                         }
6457                         printk("]\n");
6458                 }
6459
6460                 parent->rdc_default[i] = rdc_channel_base;
6461
6462                 rdc_channel_base += num_channels;
6463                 rdc_group += rdc_groups_per_port;
6464         }
6465 }
6466
6467 static int __devinit fill_phy_probe_info(struct niu *np,
6468                                          struct niu_parent *parent,
6469                                          struct phy_probe_info *info)
6470 {
6471         unsigned long flags;
6472         int port, err;
6473
6474         memset(info, 0, sizeof(*info));
6475
6476         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
6477         niu_lock_parent(np, flags);
6478         err = 0;
6479         for (port = 8; port < 32; port++) {
6480                 int dev_id_1, dev_id_2;
6481
6482                 dev_id_1 = mdio_read(np, port,
6483                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
6484                 dev_id_2 = mdio_read(np, port,
6485                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
6486                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6487                                  PHY_TYPE_PMA_PMD);
6488                 if (err)
6489                         break;
6490                 dev_id_1 = mdio_read(np, port,
6491                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
6492                 dev_id_2 = mdio_read(np, port,
6493                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
6494                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6495                                  PHY_TYPE_PCS);
6496                 if (err)
6497                         break;
6498                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
6499                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
6500                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6501                                  PHY_TYPE_MII);
6502                 if (err)
6503                         break;
6504         }
6505         niu_unlock_parent(np, flags);
6506
6507         return err;
6508 }
6509
6510 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
6511 {
6512         struct phy_probe_info *info = &parent->phy_probe_info;
6513         int lowest_10g, lowest_1g;
6514         int num_10g, num_1g;
6515         u32 val;
6516         int err;
6517
6518         err = fill_phy_probe_info(np, parent, info);
6519         if (err)
6520                 return err;
6521
6522         num_10g = count_10g_ports(info, &lowest_10g);
6523         num_1g = count_1g_ports(info, &lowest_1g);
6524
6525         switch ((num_10g << 4) | num_1g) {
6526         case 0x24:
6527                 if (lowest_1g == 10)
6528                         parent->plat_type = PLAT_TYPE_VF_P0;
6529                 else if (lowest_1g == 26)
6530                         parent->plat_type = PLAT_TYPE_VF_P1;
6531                 else
6532                         goto unknown_vg_1g_port;
6533
6534                 /* fallthru */
6535         case 0x22:
6536                 val = (phy_encode(PORT_TYPE_10G, 0) |
6537                        phy_encode(PORT_TYPE_10G, 1) |
6538                        phy_encode(PORT_TYPE_1G, 2) |
6539                        phy_encode(PORT_TYPE_1G, 3));
6540                 break;
6541
6542         case 0x20:
6543                 val = (phy_encode(PORT_TYPE_10G, 0) |
6544                        phy_encode(PORT_TYPE_10G, 1));
6545                 break;
6546
6547         case 0x10:
6548                 val = phy_encode(PORT_TYPE_10G, np->port);
6549                 break;
6550
6551         case 0x14:
6552                 if (lowest_1g == 10)
6553                         parent->plat_type = PLAT_TYPE_VF_P0;
6554                 else if (lowest_1g == 26)
6555                         parent->plat_type = PLAT_TYPE_VF_P1;
6556                 else
6557                         goto unknown_vg_1g_port;
6558
6559                 /* fallthru */
6560         case 0x13:
6561                 if ((lowest_10g & 0x7) == 0)
6562                         val = (phy_encode(PORT_TYPE_10G, 0) |
6563                                phy_encode(PORT_TYPE_1G, 1) |
6564                                phy_encode(PORT_TYPE_1G, 2) |
6565                                phy_encode(PORT_TYPE_1G, 3));
6566                 else
6567                         val = (phy_encode(PORT_TYPE_1G, 0) |
6568                                phy_encode(PORT_TYPE_10G, 1) |
6569                                phy_encode(PORT_TYPE_1G, 2) |
6570                                phy_encode(PORT_TYPE_1G, 3));
6571                 break;
6572
6573         case 0x04:
6574                 if (lowest_1g == 10)
6575                         parent->plat_type = PLAT_TYPE_VF_P0;
6576                 else if (lowest_1g == 26)
6577                         parent->plat_type = PLAT_TYPE_VF_P1;
6578                 else
6579                         goto unknown_vg_1g_port;
6580
6581                 val = (phy_encode(PORT_TYPE_1G, 0) |
6582                        phy_encode(PORT_TYPE_1G, 1) |
6583                        phy_encode(PORT_TYPE_1G, 2) |
6584                        phy_encode(PORT_TYPE_1G, 3));
6585                 break;
6586
6587         default:
6588                 printk(KERN_ERR PFX "Unsupported port config "
6589                        "10G[%d] 1G[%d]\n",
6590                        num_10g, num_1g);
6591                 return -EINVAL;
6592         }
6593
6594         parent->port_phy = val;
6595
6596         if (parent->plat_type == PLAT_TYPE_NIU)
6597                 niu_n2_divide_channels(parent);
6598         else
6599                 niu_divide_channels(parent, num_10g, num_1g);
6600
6601         niu_divide_rdc_groups(parent, num_10g, num_1g);
6602
6603         return 0;
6604
6605 unknown_vg_1g_port:
6606         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
6607                lowest_1g);
6608         return -EINVAL;
6609 }
6610
6611 static int __devinit niu_probe_ports(struct niu *np)
6612 {
6613         struct niu_parent *parent = np->parent;
6614         int err, i;
6615
6616         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
6617                parent->port_phy);
6618
6619         if (parent->port_phy == PORT_PHY_UNKNOWN) {
6620                 err = walk_phys(np, parent);
6621                 if (err)
6622                         return err;
6623
6624                 niu_set_ldg_timer_res(np, 2);
6625                 for (i = 0; i <= LDN_MAX; i++)
6626                         niu_ldn_irq_enable(np, i, 0);
6627         }
6628
6629         if (parent->port_phy == PORT_PHY_INVALID)
6630                 return -EINVAL;
6631
6632         return 0;
6633 }
6634
6635 static int __devinit niu_classifier_swstate_init(struct niu *np)
6636 {
6637         struct niu_classifier *cp = &np->clas;
6638
6639         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
6640                np->parent->tcam_num_entries);
6641
6642         cp->tcam_index = (u16) np->port;
6643         cp->h1_init = 0xffffffff;
6644         cp->h2_init = 0xffff;
6645
6646         return fflp_early_init(np);
6647 }
6648
6649 static void __devinit niu_link_config_init(struct niu *np)
6650 {
6651         struct niu_link_config *lp = &np->link_config;
6652
6653         lp->advertising = (ADVERTISED_10baseT_Half |
6654                            ADVERTISED_10baseT_Full |
6655                            ADVERTISED_100baseT_Half |
6656                            ADVERTISED_100baseT_Full |
6657                            ADVERTISED_1000baseT_Half |
6658                            ADVERTISED_1000baseT_Full |
6659                            ADVERTISED_10000baseT_Full |
6660                            ADVERTISED_Autoneg);
6661         lp->speed = lp->active_speed = SPEED_INVALID;
6662         lp->duplex = lp->active_duplex = DUPLEX_INVALID;
6663 #if 0
6664         lp->loopback_mode = LOOPBACK_MAC;
6665         lp->active_speed = SPEED_10000;
6666         lp->active_duplex = DUPLEX_FULL;
6667 #else
6668         lp->loopback_mode = LOOPBACK_DISABLED;
6669 #endif
6670 }
6671
6672 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
6673 {
6674         switch (np->port) {
6675         case 0:
6676                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
6677                 np->ipp_off  = 0x00000;
6678                 np->pcs_off  = 0x04000;
6679                 np->xpcs_off = 0x02000;
6680                 break;
6681
6682         case 1:
6683                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
6684                 np->ipp_off  = 0x08000;
6685                 np->pcs_off  = 0x0a000;
6686                 np->xpcs_off = 0x08000;
6687                 break;
6688
6689         case 2:
6690                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
6691                 np->ipp_off  = 0x04000;
6692                 np->pcs_off  = 0x0e000;
6693                 np->xpcs_off = ~0UL;
6694                 break;
6695
6696         case 3:
6697                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
6698                 np->ipp_off  = 0x0c000;
6699                 np->pcs_off  = 0x12000;
6700                 np->xpcs_off = ~0UL;
6701                 break;
6702
6703         default:
6704                 dev_err(np->device, PFX "Port %u is invalid, cannot "
6705                         "compute MAC block offset.\n", np->port);
6706                 return -EINVAL;
6707         }
6708
6709         return 0;
6710 }
6711
6712 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
6713 {
6714         struct msix_entry msi_vec[NIU_NUM_LDG];
6715         struct niu_parent *parent = np->parent;
6716         struct pci_dev *pdev = np->pdev;
6717         int i, num_irqs, err;
6718         u8 first_ldg;
6719
6720         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
6721         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
6722                 ldg_num_map[i] = first_ldg + i;
6723
6724         num_irqs = (parent->rxchan_per_port[np->port] +
6725                     parent->txchan_per_port[np->port] +
6726                     (np->port == 0 ? 3 : 1));
6727         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
6728
6729 retry:
6730         for (i = 0; i < num_irqs; i++) {
6731                 msi_vec[i].vector = 0;
6732                 msi_vec[i].entry = i;
6733         }
6734
6735         err = pci_enable_msix(pdev, msi_vec, num_irqs);
6736         if (err < 0) {
6737                 np->flags &= ~NIU_FLAGS_MSIX;
6738                 return;
6739         }
6740         if (err > 0) {
6741                 num_irqs = err;
6742                 goto retry;
6743         }
6744
6745         np->flags |= NIU_FLAGS_MSIX;
6746         for (i = 0; i < num_irqs; i++)
6747                 np->ldg[i].irq = msi_vec[i].vector;
6748         np->num_ldg = num_irqs;
6749 }
6750
6751 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
6752 {
6753 #ifdef CONFIG_SPARC64
6754         struct of_device *op = np->op;
6755         const u32 *int_prop;
6756         int i;
6757
6758         int_prop = of_get_property(op->node, "interrupts", NULL);
6759         if (!int_prop)
6760                 return -ENODEV;
6761
6762         for (i = 0; i < op->num_irqs; i++) {
6763                 ldg_num_map[i] = int_prop[i];
6764                 np->ldg[i].irq = op->irqs[i];
6765         }
6766
6767         np->num_ldg = op->num_irqs;
6768
6769         return 0;
6770 #else
6771         return -EINVAL;
6772 #endif
6773 }
6774
6775 static int __devinit niu_ldg_init(struct niu *np)
6776 {
6777         struct niu_parent *parent = np->parent;
6778         u8 ldg_num_map[NIU_NUM_LDG];
6779         int first_chan, num_chan;
6780         int i, err, ldg_rotor;
6781         u8 port;
6782
6783         np->num_ldg = 1;
6784         np->ldg[0].irq = np->dev->irq;
6785         if (parent->plat_type == PLAT_TYPE_NIU) {
6786                 err = niu_n2_irq_init(np, ldg_num_map);
6787                 if (err)
6788                         return err;
6789         } else
6790                 niu_try_msix(np, ldg_num_map);
6791
6792         port = np->port;
6793         for (i = 0; i < np->num_ldg; i++) {
6794                 struct niu_ldg *lp = &np->ldg[i];
6795
6796                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
6797
6798                 lp->np = np;
6799                 lp->ldg_num = ldg_num_map[i];
6800                 lp->timer = 2; /* XXX */
6801
6802                 /* On N2 NIU the firmware has setup the SID mappings so they go
6803                  * to the correct values that will route the LDG to the proper
6804                  * interrupt in the NCU interrupt table.
6805                  */
6806                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
6807                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
6808                         if (err)
6809                                 return err;
6810                 }
6811         }
6812
6813         /* We adopt the LDG assignment ordering used by the N2 NIU
6814          * 'interrupt' properties because that simplifies a lot of
6815          * things.  This ordering is:
6816          *
6817          *      MAC
6818          *      MIF     (if port zero)
6819          *      SYSERR  (if port zero)
6820          *      RX channels
6821          *      TX channels
6822          */
6823
6824         ldg_rotor = 0;
6825
6826         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
6827                                   LDN_MAC(port));
6828         if (err)
6829                 return err;
6830
6831         ldg_rotor++;
6832         if (ldg_rotor == np->num_ldg)
6833                 ldg_rotor = 0;
6834
6835         if (port == 0) {
6836                 err = niu_ldg_assign_ldn(np, parent,
6837                                          ldg_num_map[ldg_rotor],
6838                                          LDN_MIF);
6839                 if (err)
6840                         return err;
6841
6842                 ldg_rotor++;
6843                 if (ldg_rotor == np->num_ldg)
6844                         ldg_rotor = 0;
6845
6846                 err = niu_ldg_assign_ldn(np, parent,
6847                                          ldg_num_map[ldg_rotor],
6848                                          LDN_DEVICE_ERROR);
6849                 if (err)
6850                         return err;
6851
6852                 ldg_rotor++;
6853                 if (ldg_rotor == np->num_ldg)
6854                         ldg_rotor = 0;
6855
6856         }
6857
6858         first_chan = 0;
6859         for (i = 0; i < port; i++)
6860                 first_chan += parent->rxchan_per_port[port];
6861         num_chan = parent->rxchan_per_port[port];
6862
6863         for (i = first_chan; i < (first_chan + num_chan); i++) {
6864                 err = niu_ldg_assign_ldn(np, parent,
6865                                          ldg_num_map[ldg_rotor],
6866                                          LDN_RXDMA(i));
6867                 if (err)
6868                         return err;
6869                 ldg_rotor++;
6870                 if (ldg_rotor == np->num_ldg)
6871                         ldg_rotor = 0;
6872         }
6873
6874         first_chan = 0;
6875         for (i = 0; i < port; i++)
6876                 first_chan += parent->txchan_per_port[port];
6877         num_chan = parent->txchan_per_port[port];
6878         for (i = first_chan; i < (first_chan + num_chan); i++) {
6879                 err = niu_ldg_assign_ldn(np, parent,
6880                                          ldg_num_map[ldg_rotor],
6881                                          LDN_TXDMA(i));
6882                 if (err)
6883                         return err;
6884                 ldg_rotor++;
6885                 if (ldg_rotor == np->num_ldg)
6886                         ldg_rotor = 0;
6887         }
6888
6889         return 0;
6890 }
6891
6892 static void __devexit niu_ldg_free(struct niu *np)
6893 {
6894         if (np->flags & NIU_FLAGS_MSIX)
6895                 pci_disable_msix(np->pdev);
6896 }
6897
6898 static int __devinit niu_get_of_props(struct niu *np)
6899 {
6900 #ifdef CONFIG_SPARC64
6901         struct net_device *dev = np->dev;
6902         struct device_node *dp;
6903         const char *phy_type;
6904         const u8 *mac_addr;
6905         int prop_len;
6906
6907         if (np->parent->plat_type == PLAT_TYPE_NIU)
6908                 dp = np->op->node;
6909         else
6910                 dp = pci_device_to_OF_node(np->pdev);
6911
6912         phy_type = of_get_property(dp, "phy-type", &prop_len);
6913         if (!phy_type) {
6914                 dev_err(np->device, PFX "%s: OF node lacks "
6915                         "phy-type property\n",
6916                         dp->full_name);
6917                 return -EINVAL;
6918         }
6919
6920         if (!strcmp(phy_type, "none"))
6921                 return -ENODEV;
6922
6923         strcpy(np->vpd.phy_type, phy_type);
6924
6925         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6926                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
6927                         dp->full_name, np->vpd.phy_type);
6928                 return -EINVAL;
6929         }
6930
6931         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
6932         if (!mac_addr) {
6933                 dev_err(np->device, PFX "%s: OF node lacks "
6934                         "local-mac-address property\n",
6935                         dp->full_name);
6936                 return -EINVAL;
6937         }
6938         if (prop_len != dev->addr_len) {
6939                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
6940                         "is wrong.\n",
6941                         dp->full_name, prop_len);
6942         }
6943         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
6944         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6945                 int i;
6946
6947                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
6948                         dp->full_name);
6949                 dev_err(np->device, PFX "%s: [ \n",
6950                         dp->full_name);
6951                 for (i = 0; i < 6; i++)
6952                         printk("%02x ", dev->perm_addr[i]);
6953                 printk("]\n");
6954                 return -EINVAL;
6955         }
6956
6957         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6958
6959         return 0;
6960 #else
6961         return -EINVAL;
6962 #endif
6963 }
6964
6965 static int __devinit niu_get_invariants(struct niu *np)
6966 {
6967         int err, have_props;
6968         u32 offset;
6969
6970         err = niu_get_of_props(np);
6971         if (err == -ENODEV)
6972                 return err;
6973
6974         have_props = !err;
6975
6976         err = niu_get_and_validate_port(np);
6977         if (err)
6978                 return err;
6979
6980         err = niu_init_mac_ipp_pcs_base(np);
6981         if (err)
6982                 return err;
6983
6984         if (!have_props) {
6985                 if (np->parent->plat_type == PLAT_TYPE_NIU)
6986                         return -EINVAL;
6987
6988                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
6989                 offset = niu_pci_vpd_offset(np);
6990                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
6991                        offset);
6992                 if (offset)
6993                         niu_pci_vpd_fetch(np, offset);
6994                 nw64(ESPC_PIO_EN, 0);
6995
6996                 if (np->flags & NIU_FLAGS_VPD_VALID)
6997                         niu_pci_vpd_validate(np);
6998
6999                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7000                         err = niu_pci_probe_sprom(np);
7001                         if (err)
7002                                 return err;
7003                 }
7004         }
7005
7006         err = niu_probe_ports(np);
7007         if (err)
7008                 return err;
7009
7010         niu_ldg_init(np);
7011
7012         niu_classifier_swstate_init(np);
7013         niu_link_config_init(np);
7014
7015         err = niu_determine_phy_disposition(np);
7016         if (!err)
7017                 err = niu_init_link(np);
7018
7019         return err;
7020 }
7021
7022 static LIST_HEAD(niu_parent_list);
7023 static DEFINE_MUTEX(niu_parent_lock);
7024 static int niu_parent_index;
7025
7026 static ssize_t show_port_phy(struct device *dev,
7027                              struct device_attribute *attr, char *buf)
7028 {
7029         struct platform_device *plat_dev = to_platform_device(dev);
7030         struct niu_parent *p = plat_dev->dev.platform_data;
7031         u32 port_phy = p->port_phy;
7032         char *orig_buf = buf;
7033         int i;
7034
7035         if (port_phy == PORT_PHY_UNKNOWN ||
7036             port_phy == PORT_PHY_INVALID)
7037                 return 0;
7038
7039         for (i = 0; i < p->num_ports; i++) {
7040                 const char *type_str;
7041                 int type;
7042
7043                 type = phy_decode(port_phy, i);
7044                 if (type == PORT_TYPE_10G)
7045                         type_str = "10G";
7046                 else
7047                         type_str = "1G";
7048                 buf += sprintf(buf,
7049                                (i == 0) ? "%s" : " %s",
7050                                type_str);
7051         }
7052         buf += sprintf(buf, "\n");
7053         return buf - orig_buf;
7054 }
7055
7056 static ssize_t show_plat_type(struct device *dev,
7057                               struct device_attribute *attr, char *buf)
7058 {
7059         struct platform_device *plat_dev = to_platform_device(dev);
7060         struct niu_parent *p = plat_dev->dev.platform_data;
7061         const char *type_str;
7062
7063         switch (p->plat_type) {
7064         case PLAT_TYPE_ATLAS:
7065                 type_str = "atlas";
7066                 break;
7067         case PLAT_TYPE_NIU:
7068                 type_str = "niu";
7069                 break;
7070         case PLAT_TYPE_VF_P0:
7071                 type_str = "vf_p0";
7072                 break;
7073         case PLAT_TYPE_VF_P1:
7074                 type_str = "vf_p1";
7075                 break;
7076         default:
7077                 type_str = "unknown";
7078                 break;
7079         }
7080
7081         return sprintf(buf, "%s\n", type_str);
7082 }
7083
7084 static ssize_t __show_chan_per_port(struct device *dev,
7085                                     struct device_attribute *attr, char *buf,
7086                                     int rx)
7087 {
7088         struct platform_device *plat_dev = to_platform_device(dev);
7089         struct niu_parent *p = plat_dev->dev.platform_data;
7090         char *orig_buf = buf;
7091         u8 *arr;
7092         int i;
7093
7094         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7095
7096         for (i = 0; i < p->num_ports; i++) {
7097                 buf += sprintf(buf,
7098                                (i == 0) ? "%d" : " %d",
7099                                arr[i]);
7100         }
7101         buf += sprintf(buf, "\n");
7102
7103         return buf - orig_buf;
7104 }
7105
7106 static ssize_t show_rxchan_per_port(struct device *dev,
7107                                     struct device_attribute *attr, char *buf)
7108 {
7109         return __show_chan_per_port(dev, attr, buf, 1);
7110 }
7111
7112 static ssize_t show_txchan_per_port(struct device *dev,
7113                                     struct device_attribute *attr, char *buf)
7114 {
7115         return __show_chan_per_port(dev, attr, buf, 1);
7116 }
7117
7118 static ssize_t show_num_ports(struct device *dev,
7119                               struct device_attribute *attr, char *buf)
7120 {
7121         struct platform_device *plat_dev = to_platform_device(dev);
7122         struct niu_parent *p = plat_dev->dev.platform_data;
7123
7124         return sprintf(buf, "%d\n", p->num_ports);
7125 }
7126
7127 static struct device_attribute niu_parent_attributes[] = {
7128         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7129         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7130         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7131         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7132         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7133         {}
7134 };
7135
7136 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7137                                                     union niu_parent_id *id,
7138                                                     u8 ptype)
7139 {
7140         struct platform_device *plat_dev;
7141         struct niu_parent *p;
7142         int i;
7143
7144         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7145
7146         plat_dev = platform_device_register_simple("niu", niu_parent_index,
7147                                                    NULL, 0);
7148         if (!plat_dev)
7149                 return NULL;
7150
7151         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7152                 int err = device_create_file(&plat_dev->dev,
7153                                              &niu_parent_attributes[i]);
7154                 if (err)
7155                         goto fail_unregister;
7156         }
7157
7158         p = kzalloc(sizeof(*p), GFP_KERNEL);
7159         if (!p)
7160                 goto fail_unregister;
7161
7162         p->index = niu_parent_index++;
7163
7164         plat_dev->dev.platform_data = p;
7165         p->plat_dev = plat_dev;
7166
7167         memcpy(&p->id, id, sizeof(*id));
7168         p->plat_type = ptype;
7169         INIT_LIST_HEAD(&p->list);
7170         atomic_set(&p->refcnt, 0);
7171         list_add(&p->list, &niu_parent_list);
7172         spin_lock_init(&p->lock);
7173
7174         p->rxdma_clock_divider = 7500;
7175
7176         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7177         if (p->plat_type == PLAT_TYPE_NIU)
7178                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7179
7180         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7181                 int index = i - CLASS_CODE_USER_PROG1;
7182
7183                 p->tcam_key[index] = TCAM_KEY_TSEL;
7184                 p->flow_key[index] = (FLOW_KEY_IPSA |
7185                                       FLOW_KEY_IPDA |
7186                                       FLOW_KEY_PROTO |
7187                                       (FLOW_KEY_L4_BYTE12 <<
7188                                        FLOW_KEY_L4_0_SHIFT) |
7189                                       (FLOW_KEY_L4_BYTE12 <<
7190                                        FLOW_KEY_L4_1_SHIFT));
7191         }
7192
7193         for (i = 0; i < LDN_MAX + 1; i++)
7194                 p->ldg_map[i] = LDG_INVALID;
7195
7196         return p;
7197
7198 fail_unregister:
7199         platform_device_unregister(plat_dev);
7200         return NULL;
7201 }
7202
7203 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
7204                                                     union niu_parent_id *id,
7205                                                     u8 ptype)
7206 {
7207         struct niu_parent *p, *tmp;
7208         int port = np->port;
7209
7210         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
7211                ptype, port);
7212
7213         mutex_lock(&niu_parent_lock);
7214         p = NULL;
7215         list_for_each_entry(tmp, &niu_parent_list, list) {
7216                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
7217                         p = tmp;
7218                         break;
7219                 }
7220         }
7221         if (!p)
7222                 p = niu_new_parent(np, id, ptype);
7223
7224         if (p) {
7225                 char port_name[6];
7226                 int err;
7227
7228                 sprintf(port_name, "port%d", port);
7229                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
7230                                         &np->device->kobj,
7231                                         port_name);
7232                 if (!err) {
7233                         p->ports[port] = np;
7234                         atomic_inc(&p->refcnt);
7235                 }
7236         }
7237         mutex_unlock(&niu_parent_lock);
7238
7239         return p;
7240 }
7241
7242 static void niu_put_parent(struct niu *np)
7243 {
7244         struct niu_parent *p = np->parent;
7245         u8 port = np->port;
7246         char port_name[6];
7247
7248         BUG_ON(!p || p->ports[port] != np);
7249
7250         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
7251
7252         sprintf(port_name, "port%d", port);
7253
7254         mutex_lock(&niu_parent_lock);
7255
7256         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
7257
7258         p->ports[port] = NULL;
7259         np->parent = NULL;
7260
7261         if (atomic_dec_and_test(&p->refcnt)) {
7262                 list_del(&p->list);
7263                 platform_device_unregister(p->plat_dev);
7264         }
7265
7266         mutex_unlock(&niu_parent_lock);
7267 }
7268
7269 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
7270                                     u64 *handle, gfp_t flag)
7271 {
7272         dma_addr_t dh;
7273         void *ret;
7274
7275         ret = dma_alloc_coherent(dev, size, &dh, flag);
7276         if (ret)
7277                 *handle = dh;
7278         return ret;
7279 }
7280
7281 static void niu_pci_free_coherent(struct device *dev, size_t size,
7282                                   void *cpu_addr, u64 handle)
7283 {
7284         dma_free_coherent(dev, size, cpu_addr, handle);
7285 }
7286
7287 static u64 niu_pci_map_page(struct device *dev, struct page *page,
7288                             unsigned long offset, size_t size,
7289                             enum dma_data_direction direction)
7290 {
7291         return dma_map_page(dev, page, offset, size, direction);
7292 }
7293
7294 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
7295                                size_t size, enum dma_data_direction direction)
7296 {
7297         return dma_unmap_page(dev, dma_address, size, direction);
7298 }
7299
7300 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
7301                               size_t size,
7302                               enum dma_data_direction direction)
7303 {
7304         return dma_map_single(dev, cpu_addr, size, direction);
7305 }
7306
7307 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
7308                                  size_t size,
7309                                  enum dma_data_direction direction)
7310 {
7311         dma_unmap_single(dev, dma_address, size, direction);
7312 }
7313
7314 static const struct niu_ops niu_pci_ops = {
7315         .alloc_coherent = niu_pci_alloc_coherent,
7316         .free_coherent  = niu_pci_free_coherent,
7317         .map_page       = niu_pci_map_page,
7318         .unmap_page     = niu_pci_unmap_page,
7319         .map_single     = niu_pci_map_single,
7320         .unmap_single   = niu_pci_unmap_single,
7321 };
7322
7323 static void __devinit niu_driver_version(void)
7324 {
7325         static int niu_version_printed;
7326
7327         if (niu_version_printed++ == 0)
7328                 pr_info("%s", version);
7329 }
7330
7331 static struct net_device * __devinit niu_alloc_and_init(
7332         struct device *gen_dev, struct pci_dev *pdev,
7333         struct of_device *op, const struct niu_ops *ops,
7334         u8 port)
7335 {
7336         struct net_device *dev = alloc_etherdev(sizeof(struct niu));
7337         struct niu *np;
7338
7339         if (!dev) {
7340                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
7341                 return NULL;
7342         }
7343
7344         SET_NETDEV_DEV(dev, gen_dev);
7345
7346         np = netdev_priv(dev);
7347         np->dev = dev;
7348         np->pdev = pdev;
7349         np->op = op;
7350         np->device = gen_dev;
7351         np->ops = ops;
7352
7353         np->msg_enable = niu_debug;
7354
7355         spin_lock_init(&np->lock);
7356         INIT_WORK(&np->reset_task, niu_reset_task);
7357
7358         np->port = port;
7359
7360         return dev;
7361 }
7362
7363 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
7364 {
7365         dev->open = niu_open;
7366         dev->stop = niu_close;
7367         dev->get_stats = niu_get_stats;
7368         dev->set_multicast_list = niu_set_rx_mode;
7369         dev->set_mac_address = niu_set_mac_addr;
7370         dev->do_ioctl = niu_ioctl;
7371         dev->tx_timeout = niu_tx_timeout;
7372         dev->hard_start_xmit = niu_start_xmit;
7373         dev->ethtool_ops = &niu_ethtool_ops;
7374         dev->watchdog_timeo = NIU_TX_TIMEOUT;
7375         dev->change_mtu = niu_change_mtu;
7376 }
7377
7378 static void __devinit niu_device_announce(struct niu *np)
7379 {
7380         struct net_device *dev = np->dev;
7381         int i;
7382
7383         pr_info("%s: NIU Ethernet ", dev->name);
7384         for (i = 0; i < 6; i++)
7385                 printk("%2.2x%c", dev->dev_addr[i],
7386                        i == 5 ? '\n' : ':');
7387
7388         pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
7389                 dev->name,
7390                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
7391                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
7392                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
7393                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
7394                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
7395                 np->vpd.phy_type);
7396 }
7397
7398 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
7399                                       const struct pci_device_id *ent)
7400 {
7401         unsigned long niureg_base, niureg_len;
7402         union niu_parent_id parent_id;
7403         struct net_device *dev;
7404         struct niu *np;
7405         int err, pos;
7406         u64 dma_mask;
7407         u16 val16;
7408
7409         niu_driver_version();
7410
7411         err = pci_enable_device(pdev);
7412         if (err) {
7413                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
7414                         "aborting.\n");
7415                 return err;
7416         }
7417
7418         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
7419             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
7420                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
7421                         "base addresses, aborting.\n");
7422                 err = -ENODEV;
7423                 goto err_out_disable_pdev;
7424         }
7425
7426         err = pci_request_regions(pdev, DRV_MODULE_NAME);
7427         if (err) {
7428                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
7429                         "aborting.\n");
7430                 goto err_out_disable_pdev;
7431         }
7432
7433         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
7434         if (pos <= 0) {
7435                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
7436                         "aborting.\n");
7437                 goto err_out_free_res;
7438         }
7439
7440         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
7441                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
7442         if (!dev) {
7443                 err = -ENOMEM;
7444                 goto err_out_free_res;
7445         }
7446         np = netdev_priv(dev);
7447
7448         memset(&parent_id, 0, sizeof(parent_id));
7449         parent_id.pci.domain = pci_domain_nr(pdev->bus);
7450         parent_id.pci.bus = pdev->bus->number;
7451         parent_id.pci.device = PCI_SLOT(pdev->devfn);
7452
7453         np->parent = niu_get_parent(np, &parent_id,
7454                                     PLAT_TYPE_ATLAS);
7455         if (!np->parent) {
7456                 err = -ENOMEM;
7457                 goto err_out_free_dev;
7458         }
7459
7460         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
7461         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
7462         val16 |= (PCI_EXP_DEVCTL_CERE |
7463                   PCI_EXP_DEVCTL_NFERE |
7464                   PCI_EXP_DEVCTL_FERE |
7465                   PCI_EXP_DEVCTL_URRE |
7466                   PCI_EXP_DEVCTL_RELAX_EN);
7467         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
7468
7469         dma_mask = DMA_44BIT_MASK;
7470         err = pci_set_dma_mask(pdev, dma_mask);
7471         if (!err) {
7472                 dev->features |= NETIF_F_HIGHDMA;
7473                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
7474                 if (err) {
7475                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
7476                                 "DMA for consistent allocations, "
7477                                 "aborting.\n");
7478                         goto err_out_release_parent;
7479                 }
7480         }
7481         if (err || dma_mask == DMA_32BIT_MASK) {
7482                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7483                 if (err) {
7484                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
7485                                 "aborting.\n");
7486                         goto err_out_release_parent;
7487                 }
7488         }
7489
7490         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7491
7492         niureg_base = pci_resource_start(pdev, 0);
7493         niureg_len = pci_resource_len(pdev, 0);
7494
7495         np->regs = ioremap_nocache(niureg_base, niureg_len);
7496         if (!np->regs) {
7497                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
7498                         "aborting.\n");
7499                 err = -ENOMEM;
7500                 goto err_out_release_parent;
7501         }
7502
7503         pci_set_master(pdev);
7504         pci_save_state(pdev);
7505
7506         dev->irq = pdev->irq;
7507
7508         niu_assign_netdev_ops(dev);
7509
7510         err = niu_get_invariants(np);
7511         if (err) {
7512                 if (err != -ENODEV)
7513                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
7514                                 "of chip, aborting.\n");
7515                 goto err_out_iounmap;
7516         }
7517
7518         err = register_netdev(dev);
7519         if (err) {
7520                 dev_err(&pdev->dev, PFX "Cannot register net device, "
7521                         "aborting.\n");
7522                 goto err_out_iounmap;
7523         }
7524
7525         pci_set_drvdata(pdev, dev);
7526
7527         niu_device_announce(np);
7528
7529         return 0;
7530
7531 err_out_iounmap:
7532         if (np->regs) {
7533                 iounmap(np->regs);
7534                 np->regs = NULL;
7535         }
7536
7537 err_out_release_parent:
7538         niu_put_parent(np);
7539
7540 err_out_free_dev:
7541         free_netdev(dev);
7542
7543 err_out_free_res:
7544         pci_release_regions(pdev);
7545
7546 err_out_disable_pdev:
7547         pci_disable_device(pdev);
7548         pci_set_drvdata(pdev, NULL);
7549
7550         return err;
7551 }
7552
7553 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
7554 {
7555         struct net_device *dev = pci_get_drvdata(pdev);
7556
7557         if (dev) {
7558                 struct niu *np = netdev_priv(dev);
7559
7560                 unregister_netdev(dev);
7561                 if (np->regs) {
7562                         iounmap(np->regs);
7563                         np->regs = NULL;
7564                 }
7565
7566                 niu_ldg_free(np);
7567
7568                 niu_put_parent(np);
7569
7570                 free_netdev(dev);
7571                 pci_release_regions(pdev);
7572                 pci_disable_device(pdev);
7573                 pci_set_drvdata(pdev, NULL);
7574         }
7575 }
7576
7577 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
7578 {
7579         struct net_device *dev = pci_get_drvdata(pdev);
7580         struct niu *np = netdev_priv(dev);
7581         unsigned long flags;
7582
7583         if (!netif_running(dev))
7584                 return 0;
7585
7586         flush_scheduled_work();
7587         niu_netif_stop(np);
7588
7589         del_timer_sync(&np->timer);
7590
7591         spin_lock_irqsave(&np->lock, flags);
7592         niu_enable_interrupts(np, 0);
7593         spin_unlock_irqrestore(&np->lock, flags);
7594
7595         netif_device_detach(dev);
7596
7597         spin_lock_irqsave(&np->lock, flags);
7598         niu_stop_hw(np);
7599         spin_unlock_irqrestore(&np->lock, flags);
7600
7601         pci_save_state(pdev);
7602
7603         return 0;
7604 }
7605
7606 static int niu_resume(struct pci_dev *pdev)
7607 {
7608         struct net_device *dev = pci_get_drvdata(pdev);
7609         struct niu *np = netdev_priv(dev);
7610         unsigned long flags;
7611         int err;
7612
7613         if (!netif_running(dev))
7614                 return 0;
7615
7616         pci_restore_state(pdev);
7617
7618         netif_device_attach(dev);
7619
7620         spin_lock_irqsave(&np->lock, flags);
7621
7622         err = niu_init_hw(np);
7623         if (!err) {
7624                 np->timer.expires = jiffies + HZ;
7625                 add_timer(&np->timer);
7626                 niu_netif_start(np);
7627         }
7628
7629         spin_unlock_irqrestore(&np->lock, flags);
7630
7631         return err;
7632 }
7633
7634 static struct pci_driver niu_pci_driver = {
7635         .name           = DRV_MODULE_NAME,
7636         .id_table       = niu_pci_tbl,
7637         .probe          = niu_pci_init_one,
7638         .remove         = __devexit_p(niu_pci_remove_one),
7639         .suspend        = niu_suspend,
7640         .resume         = niu_resume,
7641 };
7642
7643 #ifdef CONFIG_SPARC64
7644 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
7645                                      u64 *dma_addr, gfp_t flag)
7646 {
7647         unsigned long order = get_order(size);
7648         unsigned long page = __get_free_pages(flag, order);
7649
7650         if (page == 0UL)
7651                 return NULL;
7652         memset((char *)page, 0, PAGE_SIZE << order);
7653         *dma_addr = __pa(page);
7654
7655         return (void *) page;
7656 }
7657
7658 static void niu_phys_free_coherent(struct device *dev, size_t size,
7659                                    void *cpu_addr, u64 handle)
7660 {
7661         unsigned long order = get_order(size);
7662
7663         free_pages((unsigned long) cpu_addr, order);
7664 }
7665
7666 static u64 niu_phys_map_page(struct device *dev, struct page *page,
7667                              unsigned long offset, size_t size,
7668                              enum dma_data_direction direction)
7669 {
7670         return page_to_phys(page) + offset;
7671 }
7672
7673 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
7674                                 size_t size, enum dma_data_direction direction)
7675 {
7676         /* Nothing to do.  */
7677 }
7678
7679 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
7680                                size_t size,
7681                                enum dma_data_direction direction)
7682 {
7683         return __pa(cpu_addr);
7684 }
7685
7686 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
7687                                   size_t size,
7688                                   enum dma_data_direction direction)
7689 {
7690         /* Nothing to do.  */
7691 }
7692
7693 static const struct niu_ops niu_phys_ops = {
7694         .alloc_coherent = niu_phys_alloc_coherent,
7695         .free_coherent  = niu_phys_free_coherent,
7696         .map_page       = niu_phys_map_page,
7697         .unmap_page     = niu_phys_unmap_page,
7698         .map_single     = niu_phys_map_single,
7699         .unmap_single   = niu_phys_unmap_single,
7700 };
7701
7702 static unsigned long res_size(struct resource *r)
7703 {
7704         return r->end - r->start + 1UL;
7705 }
7706
7707 static int __devinit niu_of_probe(struct of_device *op,
7708                                   const struct of_device_id *match)
7709 {
7710         union niu_parent_id parent_id;
7711         struct net_device *dev;
7712         struct niu *np;
7713         const u32 *reg;
7714         int err;
7715
7716         niu_driver_version();
7717
7718         reg = of_get_property(op->node, "reg", NULL);
7719         if (!reg) {
7720                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
7721                         op->node->full_name);
7722                 return -ENODEV;
7723         }
7724
7725         dev = niu_alloc_and_init(&op->dev, NULL, op,
7726                                  &niu_phys_ops, reg[0] & 0x1);
7727         if (!dev) {
7728                 err = -ENOMEM;
7729                 goto err_out;
7730         }
7731         np = netdev_priv(dev);
7732
7733         memset(&parent_id, 0, sizeof(parent_id));
7734         parent_id.of = of_get_parent(op->node);
7735
7736         np->parent = niu_get_parent(np, &parent_id,
7737                                     PLAT_TYPE_NIU);
7738         if (!np->parent) {
7739                 err = -ENOMEM;
7740                 goto err_out_free_dev;
7741         }
7742
7743         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7744
7745         np->regs = of_ioremap(&op->resource[1], 0,
7746                               res_size(&op->resource[1]),
7747                               "niu regs");
7748         if (!np->regs) {
7749                 dev_err(&op->dev, PFX "Cannot map device registers, "
7750                         "aborting.\n");
7751                 err = -ENOMEM;
7752                 goto err_out_release_parent;
7753         }
7754
7755         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
7756                                     res_size(&op->resource[2]),
7757                                     "niu vregs-1");
7758         if (!np->vir_regs_1) {
7759                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
7760                         "aborting.\n");
7761                 err = -ENOMEM;
7762                 goto err_out_iounmap;
7763         }
7764
7765         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
7766                                     res_size(&op->resource[3]),
7767                                     "niu vregs-2");
7768         if (!np->vir_regs_2) {
7769                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
7770                         "aborting.\n");
7771                 err = -ENOMEM;
7772                 goto err_out_iounmap;
7773         }
7774
7775         niu_assign_netdev_ops(dev);
7776
7777         err = niu_get_invariants(np);
7778         if (err) {
7779                 if (err != -ENODEV)
7780                         dev_err(&op->dev, PFX "Problem fetching invariants "
7781                                 "of chip, aborting.\n");
7782                 goto err_out_iounmap;
7783         }
7784
7785         err = register_netdev(dev);
7786         if (err) {
7787                 dev_err(&op->dev, PFX "Cannot register net device, "
7788                         "aborting.\n");
7789                 goto err_out_iounmap;
7790         }
7791
7792         dev_set_drvdata(&op->dev, dev);
7793
7794         niu_device_announce(np);
7795
7796         return 0;
7797
7798 err_out_iounmap:
7799         if (np->vir_regs_1) {
7800                 of_iounmap(&op->resource[2], np->vir_regs_1,
7801                            res_size(&op->resource[2]));
7802                 np->vir_regs_1 = NULL;
7803         }
7804
7805         if (np->vir_regs_2) {
7806                 of_iounmap(&op->resource[3], np->vir_regs_2,
7807                            res_size(&op->resource[3]));
7808                 np->vir_regs_2 = NULL;
7809         }
7810
7811         if (np->regs) {
7812                 of_iounmap(&op->resource[1], np->regs,
7813                            res_size(&op->resource[1]));
7814                 np->regs = NULL;
7815         }
7816
7817 err_out_release_parent:
7818         niu_put_parent(np);
7819
7820 err_out_free_dev:
7821         free_netdev(dev);
7822
7823 err_out:
7824         return err;
7825 }
7826
7827 static int __devexit niu_of_remove(struct of_device *op)
7828 {
7829         struct net_device *dev = dev_get_drvdata(&op->dev);
7830
7831         if (dev) {
7832                 struct niu *np = netdev_priv(dev);
7833
7834                 unregister_netdev(dev);
7835
7836                 if (np->vir_regs_1) {
7837                         of_iounmap(&op->resource[2], np->vir_regs_1,
7838                                    res_size(&op->resource[2]));
7839                         np->vir_regs_1 = NULL;
7840                 }
7841
7842                 if (np->vir_regs_2) {
7843                         of_iounmap(&op->resource[3], np->vir_regs_2,
7844                                    res_size(&op->resource[3]));
7845                         np->vir_regs_2 = NULL;
7846                 }
7847
7848                 if (np->regs) {
7849                         of_iounmap(&op->resource[1], np->regs,
7850                                    res_size(&op->resource[1]));
7851                         np->regs = NULL;
7852                 }
7853
7854                 niu_ldg_free(np);
7855
7856                 niu_put_parent(np);
7857
7858                 free_netdev(dev);
7859                 dev_set_drvdata(&op->dev, NULL);
7860         }
7861         return 0;
7862 }
7863
7864 static struct of_device_id niu_match[] = {
7865         {
7866                 .name = "network",
7867                 .compatible = "SUNW,niusl",
7868         },
7869         {},
7870 };
7871 MODULE_DEVICE_TABLE(of, niu_match);
7872
7873 static struct of_platform_driver niu_of_driver = {
7874         .name           = "niu",
7875         .match_table    = niu_match,
7876         .probe          = niu_of_probe,
7877         .remove         = __devexit_p(niu_of_remove),
7878 };
7879
7880 #endif /* CONFIG_SPARC64 */
7881
7882 static int __init niu_init(void)
7883 {
7884         int err = 0;
7885
7886         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
7887
7888         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
7889
7890 #ifdef CONFIG_SPARC64
7891         err = of_register_driver(&niu_of_driver, &of_bus_type);
7892 #endif
7893
7894         if (!err) {
7895                 err = pci_register_driver(&niu_pci_driver);
7896 #ifdef CONFIG_SPARC64
7897                 if (err)
7898                         of_unregister_driver(&niu_of_driver);
7899 #endif
7900         }
7901
7902         return err;
7903 }
7904
7905 static void __exit niu_exit(void)
7906 {
7907         pci_unregister_driver(&niu_pci_driver);
7908 #ifdef CONFIG_SPARC64
7909         of_unregister_driver(&niu_of_driver);
7910 #endif
7911 }
7912
7913 module_init(niu_init);
7914 module_exit(niu_exit);