2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
36 /* Maximum DPLL multiplier, divider values for OMAP3 */
37 #define OMAP3_MAX_DPLL_MULT 2048
38 #define OMAP3_MAX_DPLL_DIV 128
41 * DPLL1 supplies clock to the MPU.
42 * DPLL2 supplies clock to the IVA2.
43 * DPLL3 supplies CORE domain clocks.
44 * DPLL4 supplies peripheral clocks.
45 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
48 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
49 #define DPLL_LOW_POWER_STOP 0x1
50 #define DPLL_LOW_POWER_BYPASS 0x5
51 #define DPLL_LOCKED 0x7
55 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
56 static struct clk omap_32k_fck = {
57 .name = "omap_32k_fck",
59 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
61 .recalc = &propagate_rate,
64 static struct clk secure_32k_fck = {
65 .name = "secure_32k_fck",
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
69 .recalc = &propagate_rate,
72 /* Virtual source clocks for osc_sys_ck */
73 static struct clk virt_12m_ck = {
74 .name = "virt_12m_ck",
76 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
78 .recalc = &propagate_rate,
81 static struct clk virt_13m_ck = {
82 .name = "virt_13m_ck",
84 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
86 .recalc = &propagate_rate,
89 static struct clk virt_16_8m_ck = {
90 .name = "virt_16_8m_ck",
92 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
94 .recalc = &propagate_rate,
97 static struct clk virt_19_2m_ck = {
98 .name = "virt_19_2m_ck",
100 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
102 .recalc = &propagate_rate,
105 static struct clk virt_26m_ck = {
106 .name = "virt_26m_ck",
108 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
110 .recalc = &propagate_rate,
113 static struct clk virt_38_4m_ck = {
114 .name = "virt_38_4m_ck",
116 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
118 .recalc = &propagate_rate,
121 static const struct clksel_rate osc_sys_12m_rates[] = {
122 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
126 static const struct clksel_rate osc_sys_13m_rates[] = {
127 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
131 static const struct clksel_rate osc_sys_16_8m_rates[] = {
132 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
136 static const struct clksel_rate osc_sys_19_2m_rates[] = {
137 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
141 static const struct clksel_rate osc_sys_26m_rates[] = {
142 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
146 static const struct clksel_rate osc_sys_38_4m_rates[] = {
147 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
151 static const struct clksel osc_sys_clksel[] = {
152 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
153 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
154 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
155 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
156 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
157 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
161 /* Oscillator clock */
162 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
163 static struct clk osc_sys_ck = {
164 .name = "osc_sys_ck",
165 .init = &omap2_init_clksel_parent,
166 .clksel_reg = OMAP3430_PRM_CLKSEL,
167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
168 .clksel = osc_sys_clksel,
169 /* REVISIT: deal with autoextclkmode? */
170 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
172 .recalc = &omap2_clksel_recalc,
175 static const struct clksel_rate div2_rates[] = {
176 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
177 { .div = 2, .val = 2, .flags = RATE_IN_343X },
181 static const struct clksel sys_clksel[] = {
182 { .parent = &osc_sys_ck, .rates = div2_rates },
186 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
187 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
188 static struct clk sys_ck = {
190 .parent = &osc_sys_ck,
191 .init = &omap2_init_clksel_parent,
192 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
193 .clksel_mask = OMAP_SYSCLKDIV_MASK,
194 .clksel = sys_clksel,
195 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
196 .recalc = &omap2_clksel_recalc,
199 static struct clk sys_altclk = {
200 .name = "sys_altclk",
201 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
202 .recalc = &propagate_rate,
205 /* Optional external clock input for some McBSPs */
206 static struct clk mcbsp_clks = {
207 .name = "mcbsp_clks",
208 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
209 .recalc = &propagate_rate,
212 /* PRM EXTERNAL CLOCK OUTPUT */
214 static struct clk sys_clkout1 = {
215 .name = "sys_clkout1",
216 .parent = &osc_sys_ck,
217 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
218 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
219 .flags = CLOCK_IN_OMAP343X,
220 .recalc = &followparent_recalc,
227 static const struct clksel_rate dpll_bypass_rates[] = {
228 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
232 static const struct clksel_rate dpll_locked_rates[] = {
233 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
237 static const struct clksel_rate div16_dpll_rates[] = {
238 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
239 { .div = 2, .val = 2, .flags = RATE_IN_343X },
240 { .div = 3, .val = 3, .flags = RATE_IN_343X },
241 { .div = 4, .val = 4, .flags = RATE_IN_343X },
242 { .div = 5, .val = 5, .flags = RATE_IN_343X },
243 { .div = 6, .val = 6, .flags = RATE_IN_343X },
244 { .div = 7, .val = 7, .flags = RATE_IN_343X },
245 { .div = 8, .val = 8, .flags = RATE_IN_343X },
246 { .div = 9, .val = 9, .flags = RATE_IN_343X },
247 { .div = 10, .val = 10, .flags = RATE_IN_343X },
248 { .div = 11, .val = 11, .flags = RATE_IN_343X },
249 { .div = 12, .val = 12, .flags = RATE_IN_343X },
250 { .div = 13, .val = 13, .flags = RATE_IN_343X },
251 { .div = 14, .val = 14, .flags = RATE_IN_343X },
252 { .div = 15, .val = 15, .flags = RATE_IN_343X },
253 { .div = 16, .val = 16, .flags = RATE_IN_343X },
258 /* MPU clock source */
260 static struct dpll_data dpll1_dd = {
261 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
262 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
263 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
264 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
265 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
266 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
267 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
268 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
269 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
270 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
271 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
272 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
273 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT,
274 .max_multiplier = OMAP3_MAX_DPLL_MULT,
275 .max_divider = OMAP3_MAX_DPLL_DIV,
276 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
279 static struct clk dpll1_ck = {
282 .dpll_data = &dpll1_dd,
283 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
284 .round_rate = &omap2_dpll_round_rate,
285 .recalc = &omap3_dpll_recalc,
289 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
290 * DPLL isn't bypassed.
292 static struct clk dpll1_x2_ck = {
293 .name = "dpll1_x2_ck",
295 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
296 PARENT_CONTROLS_CLOCK,
297 .recalc = &omap3_clkoutx2_recalc,
300 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
301 static const struct clksel div16_dpll1_x2m2_clksel[] = {
302 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
307 * Does not exist in the TRM - needed to separate the M2 divider from
308 * bypass selection in mpu_ck
310 static struct clk dpll1_x2m2_ck = {
311 .name = "dpll1_x2m2_ck",
312 .parent = &dpll1_x2_ck,
313 .init = &omap2_init_clksel_parent,
314 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
315 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
316 .clksel = div16_dpll1_x2m2_clksel,
317 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
318 PARENT_CONTROLS_CLOCK,
319 .recalc = &omap2_clksel_recalc,
323 /* IVA2 clock source */
326 static struct dpll_data dpll2_dd = {
327 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
328 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
329 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
330 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
331 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
332 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
333 (1 << DPLL_LOW_POWER_BYPASS),
334 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
335 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
336 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
337 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
338 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
339 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
340 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT,
341 .max_multiplier = OMAP3_MAX_DPLL_MULT,
342 .max_divider = OMAP3_MAX_DPLL_DIV,
343 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
346 static struct clk dpll2_ck = {
348 .ops = &clkops_noncore_dpll_ops,
350 .dpll_data = &dpll2_dd,
351 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
352 .round_rate = &omap2_dpll_round_rate,
353 .recalc = &omap3_dpll_recalc,
356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
357 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
362 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
363 * or CLKOUTX2. CLKOUT seems most plausible.
365 static struct clk dpll2_m2_ck = {
366 .name = "dpll2_m2_ck",
368 .init = &omap2_init_clksel_parent,
369 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
370 OMAP3430_CM_CLKSEL2_PLL),
371 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
372 .clksel = div16_dpll2_m2x2_clksel,
373 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
374 PARENT_CONTROLS_CLOCK,
375 .recalc = &omap2_clksel_recalc,
380 * Source clock for all interfaces and for some device fclks
381 * REVISIT: Also supports fast relock bypass - not included below
383 static struct dpll_data dpll3_dd = {
384 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
385 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
386 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
387 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
388 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
389 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
390 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
391 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
392 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
393 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
394 .max_multiplier = OMAP3_MAX_DPLL_MULT,
395 .max_divider = OMAP3_MAX_DPLL_DIV,
396 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
399 static struct clk dpll3_ck = {
402 .dpll_data = &dpll3_dd,
403 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
404 .round_rate = &omap2_dpll_round_rate,
405 .recalc = &omap3_dpll_recalc,
409 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
410 * DPLL isn't bypassed
412 static struct clk dpll3_x2_ck = {
413 .name = "dpll3_x2_ck",
415 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
416 PARENT_CONTROLS_CLOCK,
417 .recalc = &omap3_clkoutx2_recalc,
420 static const struct clksel_rate div31_dpll3_rates[] = {
421 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
422 { .div = 2, .val = 2, .flags = RATE_IN_343X },
423 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
424 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
425 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
426 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
427 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
428 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
429 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
430 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
431 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
432 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
433 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
434 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
435 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
436 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
437 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
438 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
439 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
440 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
441 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
442 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
443 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
444 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
445 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
446 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
447 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
448 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
449 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
450 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
451 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
455 static const struct clksel div31_dpll3m2_clksel[] = {
456 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
462 * REVISIT: This DPLL output divider must be changed in SRAM, so until
463 * that code is ready, this should remain a 'read-only' clksel clock.
465 static struct clk dpll3_m2_ck = {
466 .name = "dpll3_m2_ck",
468 .init = &omap2_init_clksel_parent,
469 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
470 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
471 .clksel = div31_dpll3m2_clksel,
472 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
473 PARENT_CONTROLS_CLOCK,
474 .recalc = &omap2_clksel_recalc,
477 static const struct clksel core_ck_clksel[] = {
478 { .parent = &sys_ck, .rates = dpll_bypass_rates },
479 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
483 static struct clk core_ck = {
485 .init = &omap2_init_clksel_parent,
486 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
487 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
488 .clksel = core_ck_clksel,
489 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
490 PARENT_CONTROLS_CLOCK,
491 .recalc = &omap2_clksel_recalc,
494 static const struct clksel dpll3_m2x2_ck_clksel[] = {
495 { .parent = &sys_ck, .rates = dpll_bypass_rates },
496 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
500 static struct clk dpll3_m2x2_ck = {
501 .name = "dpll3_m2x2_ck",
502 .init = &omap2_init_clksel_parent,
503 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
504 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
505 .clksel = dpll3_m2x2_ck_clksel,
506 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
507 PARENT_CONTROLS_CLOCK,
508 .recalc = &omap2_clksel_recalc,
511 /* The PWRDN bit is apparently only available on 3430ES2 and above */
512 static const struct clksel div16_dpll3_clksel[] = {
513 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
517 /* This virtual clock is the source for dpll3_m3x2_ck */
518 static struct clk dpll3_m3_ck = {
519 .name = "dpll3_m3_ck",
521 .init = &omap2_init_clksel_parent,
522 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
523 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
524 .clksel = div16_dpll3_clksel,
525 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
526 PARENT_CONTROLS_CLOCK,
527 .recalc = &omap2_clksel_recalc,
530 /* The PWRDN bit is apparently only available on 3430ES2 and above */
531 static struct clk dpll3_m3x2_ck = {
532 .name = "dpll3_m3x2_ck",
533 .parent = &dpll3_m3_ck,
534 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
535 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
536 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
537 .recalc = &omap3_clkoutx2_recalc,
540 static const struct clksel emu_core_alwon_ck_clksel[] = {
541 { .parent = &sys_ck, .rates = dpll_bypass_rates },
542 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
546 static struct clk emu_core_alwon_ck = {
547 .name = "emu_core_alwon_ck",
548 .parent = &dpll3_m3x2_ck,
549 .init = &omap2_init_clksel_parent,
550 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
551 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
552 .clksel = emu_core_alwon_ck_clksel,
553 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
554 PARENT_CONTROLS_CLOCK,
555 .recalc = &omap2_clksel_recalc,
559 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
561 static struct dpll_data dpll4_dd = {
562 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
563 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
564 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
565 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
566 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
567 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
568 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
569 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
570 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
571 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
572 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
573 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
574 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT,
575 .max_multiplier = OMAP3_MAX_DPLL_MULT,
576 .max_divider = OMAP3_MAX_DPLL_DIV,
577 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
580 static struct clk dpll4_ck = {
582 .ops = &clkops_noncore_dpll_ops,
584 .dpll_data = &dpll4_dd,
585 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
586 .round_rate = &omap2_dpll_round_rate,
587 .recalc = &omap3_dpll_recalc,
591 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
592 * DPLL isn't bypassed --
593 * XXX does this serve any downstream clocks?
595 static struct clk dpll4_x2_ck = {
596 .name = "dpll4_x2_ck",
598 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
599 PARENT_CONTROLS_CLOCK,
600 .recalc = &omap3_clkoutx2_recalc,
603 static const struct clksel div16_dpll4_clksel[] = {
604 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
608 /* This virtual clock is the source for dpll4_m2x2_ck */
609 static struct clk dpll4_m2_ck = {
610 .name = "dpll4_m2_ck",
612 .init = &omap2_init_clksel_parent,
613 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
614 .clksel_mask = OMAP3430_DIV_96M_MASK,
615 .clksel = div16_dpll4_clksel,
616 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
617 PARENT_CONTROLS_CLOCK,
618 .recalc = &omap2_clksel_recalc,
621 /* The PWRDN bit is apparently only available on 3430ES2 and above */
622 static struct clk dpll4_m2x2_ck = {
623 .name = "dpll4_m2x2_ck",
624 .parent = &dpll4_m2_ck,
625 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
626 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
627 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
628 .recalc = &omap3_clkoutx2_recalc,
631 static const struct clksel omap_96m_alwon_fck_clksel[] = {
632 { .parent = &sys_ck, .rates = dpll_bypass_rates },
633 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
637 static struct clk omap_96m_alwon_fck = {
638 .name = "omap_96m_alwon_fck",
639 .parent = &dpll4_m2x2_ck,
640 .init = &omap2_init_clksel_parent,
641 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
642 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
643 .clksel = omap_96m_alwon_fck_clksel,
644 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
645 PARENT_CONTROLS_CLOCK,
646 .recalc = &omap2_clksel_recalc,
649 static struct clk omap_96m_fck = {
650 .name = "omap_96m_fck",
651 .parent = &omap_96m_alwon_fck,
652 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
653 PARENT_CONTROLS_CLOCK,
654 .recalc = &followparent_recalc,
657 static const struct clksel cm_96m_fck_clksel[] = {
658 { .parent = &sys_ck, .rates = dpll_bypass_rates },
659 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
663 static struct clk cm_96m_fck = {
664 .name = "cm_96m_fck",
665 .parent = &dpll4_m2x2_ck,
666 .init = &omap2_init_clksel_parent,
667 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
668 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
669 .clksel = cm_96m_fck_clksel,
670 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
671 PARENT_CONTROLS_CLOCK,
672 .recalc = &omap2_clksel_recalc,
675 /* This virtual clock is the source for dpll4_m3x2_ck */
676 static struct clk dpll4_m3_ck = {
677 .name = "dpll4_m3_ck",
679 .init = &omap2_init_clksel_parent,
680 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
681 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
682 .clksel = div16_dpll4_clksel,
683 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
684 PARENT_CONTROLS_CLOCK,
685 .recalc = &omap2_clksel_recalc,
688 /* The PWRDN bit is apparently only available on 3430ES2 and above */
689 static struct clk dpll4_m3x2_ck = {
690 .name = "dpll4_m3x2_ck",
691 .parent = &dpll4_m3_ck,
692 .init = &omap2_init_clksel_parent,
693 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
694 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
695 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
696 .recalc = &omap3_clkoutx2_recalc,
699 static const struct clksel virt_omap_54m_fck_clksel[] = {
700 { .parent = &sys_ck, .rates = dpll_bypass_rates },
701 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
705 static struct clk virt_omap_54m_fck = {
706 .name = "virt_omap_54m_fck",
707 .parent = &dpll4_m3x2_ck,
708 .init = &omap2_init_clksel_parent,
709 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
710 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
711 .clksel = virt_omap_54m_fck_clksel,
712 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
713 PARENT_CONTROLS_CLOCK,
714 .recalc = &omap2_clksel_recalc,
717 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
718 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
722 static const struct clksel_rate omap_54m_alt_rates[] = {
723 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
727 static const struct clksel omap_54m_clksel[] = {
728 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
729 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
733 static struct clk omap_54m_fck = {
734 .name = "omap_54m_fck",
735 .init = &omap2_init_clksel_parent,
736 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
737 .clksel_mask = OMAP3430_SOURCE_54M,
738 .clksel = omap_54m_clksel,
739 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
740 PARENT_CONTROLS_CLOCK,
741 .recalc = &omap2_clksel_recalc,
744 static const struct clksel_rate omap_48m_96md2_rates[] = {
745 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
749 static const struct clksel_rate omap_48m_alt_rates[] = {
750 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
754 static const struct clksel omap_48m_clksel[] = {
755 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
756 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
760 static struct clk omap_48m_fck = {
761 .name = "omap_48m_fck",
762 .init = &omap2_init_clksel_parent,
763 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
764 .clksel_mask = OMAP3430_SOURCE_48M,
765 .clksel = omap_48m_clksel,
766 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
767 PARENT_CONTROLS_CLOCK,
768 .recalc = &omap2_clksel_recalc,
771 static struct clk omap_12m_fck = {
772 .name = "omap_12m_fck",
773 .parent = &omap_48m_fck,
775 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
776 PARENT_CONTROLS_CLOCK,
777 .recalc = &omap2_fixed_divisor_recalc,
780 /* This virstual clock is the source for dpll4_m4x2_ck */
781 static struct clk dpll4_m4_ck = {
782 .name = "dpll4_m4_ck",
784 .init = &omap2_init_clksel_parent,
785 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
786 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
787 .clksel = div16_dpll4_clksel,
788 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
789 PARENT_CONTROLS_CLOCK,
790 .recalc = &omap2_clksel_recalc,
793 /* The PWRDN bit is apparently only available on 3430ES2 and above */
794 static struct clk dpll4_m4x2_ck = {
795 .name = "dpll4_m4x2_ck",
796 .parent = &dpll4_m4_ck,
797 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
798 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
799 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
800 .recalc = &omap3_clkoutx2_recalc,
803 /* This virtual clock is the source for dpll4_m5x2_ck */
804 static struct clk dpll4_m5_ck = {
805 .name = "dpll4_m5_ck",
807 .init = &omap2_init_clksel_parent,
808 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
809 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
810 .clksel = div16_dpll4_clksel,
811 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
812 PARENT_CONTROLS_CLOCK,
813 .recalc = &omap2_clksel_recalc,
816 /* The PWRDN bit is apparently only available on 3430ES2 and above */
817 static struct clk dpll4_m5x2_ck = {
818 .name = "dpll4_m5x2_ck",
819 .parent = &dpll4_m5_ck,
820 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
821 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
822 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
823 .recalc = &omap3_clkoutx2_recalc,
826 /* This virtual clock is the source for dpll4_m6x2_ck */
827 static struct clk dpll4_m6_ck = {
828 .name = "dpll4_m6_ck",
830 .init = &omap2_init_clksel_parent,
831 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
832 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
833 .clksel = div16_dpll4_clksel,
834 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
835 PARENT_CONTROLS_CLOCK,
836 .recalc = &omap2_clksel_recalc,
839 /* The PWRDN bit is apparently only available on 3430ES2 and above */
840 static struct clk dpll4_m6x2_ck = {
841 .name = "dpll4_m6x2_ck",
842 .parent = &dpll4_m6_ck,
843 .init = &omap2_init_clksel_parent,
844 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
845 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
846 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
847 .recalc = &omap3_clkoutx2_recalc,
850 static struct clk emu_per_alwon_ck = {
851 .name = "emu_per_alwon_ck",
852 .parent = &dpll4_m6x2_ck,
853 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
854 PARENT_CONTROLS_CLOCK,
855 .recalc = &followparent_recalc,
859 /* Supplies 120MHz clock, USIM source clock */
862 static struct dpll_data dpll5_dd = {
863 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
864 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
865 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
866 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
867 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
868 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
869 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
870 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
871 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
872 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
873 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
874 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
875 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
876 .max_multiplier = OMAP3_MAX_DPLL_MULT,
877 .max_divider = OMAP3_MAX_DPLL_DIV,
878 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
881 static struct clk dpll5_ck = {
883 .ops = &clkops_noncore_dpll_ops,
885 .dpll_data = &dpll5_dd,
886 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
887 .round_rate = &omap2_dpll_round_rate,
888 .recalc = &omap3_dpll_recalc,
891 static const struct clksel div16_dpll5_clksel[] = {
892 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
896 static struct clk dpll5_m2_ck = {
897 .name = "dpll5_m2_ck",
899 .init = &omap2_init_clksel_parent,
900 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
901 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
902 .clksel = div16_dpll5_clksel,
903 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
904 PARENT_CONTROLS_CLOCK,
905 .recalc = &omap2_clksel_recalc,
908 static const struct clksel omap_120m_fck_clksel[] = {
909 { .parent = &sys_ck, .rates = dpll_bypass_rates },
910 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
914 static struct clk omap_120m_fck = {
915 .name = "omap_120m_fck",
916 .parent = &dpll5_m2_ck,
917 .init = &omap2_init_clksel_parent,
918 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
919 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
920 .clksel = omap_120m_fck_clksel,
921 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
922 PARENT_CONTROLS_CLOCK,
923 .recalc = &omap2_clksel_recalc,
926 /* CM EXTERNAL CLOCK OUTPUTS */
928 static const struct clksel_rate clkout2_src_core_rates[] = {
929 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
933 static const struct clksel_rate clkout2_src_sys_rates[] = {
934 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
938 static const struct clksel_rate clkout2_src_96m_rates[] = {
939 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
943 static const struct clksel_rate clkout2_src_54m_rates[] = {
944 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
948 static const struct clksel clkout2_src_clksel[] = {
949 { .parent = &core_ck, .rates = clkout2_src_core_rates },
950 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
951 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
952 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
956 static struct clk clkout2_src_ck = {
957 .name = "clkout2_src_ck",
958 .init = &omap2_init_clksel_parent,
959 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
960 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
961 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
962 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
963 .clksel = clkout2_src_clksel,
964 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
965 .recalc = &omap2_clksel_recalc,
968 static const struct clksel_rate sys_clkout2_rates[] = {
969 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
970 { .div = 2, .val = 1, .flags = RATE_IN_343X },
971 { .div = 4, .val = 2, .flags = RATE_IN_343X },
972 { .div = 8, .val = 3, .flags = RATE_IN_343X },
973 { .div = 16, .val = 4, .flags = RATE_IN_343X },
977 static const struct clksel sys_clkout2_clksel[] = {
978 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
982 static struct clk sys_clkout2 = {
983 .name = "sys_clkout2",
984 .init = &omap2_init_clksel_parent,
985 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
986 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
987 .clksel = sys_clkout2_clksel,
988 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
989 .recalc = &omap2_clksel_recalc,
992 /* CM OUTPUT CLOCKS */
994 static struct clk corex2_fck = {
995 .name = "corex2_fck",
996 .parent = &dpll3_m2x2_ck,
997 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
998 PARENT_CONTROLS_CLOCK,
999 .recalc = &followparent_recalc,
1002 /* DPLL power domain clock controls */
1004 static const struct clksel div2_core_clksel[] = {
1005 { .parent = &core_ck, .rates = div2_rates },
1010 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1011 * may be inconsistent here?
1013 static struct clk dpll1_fck = {
1014 .name = "dpll1_fck",
1016 .init = &omap2_init_clksel_parent,
1017 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1018 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1019 .clksel = div2_core_clksel,
1020 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1021 PARENT_CONTROLS_CLOCK,
1022 .recalc = &omap2_clksel_recalc,
1027 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1028 * derives from the high-frequency bypass clock originating from DPLL3,
1029 * called 'dpll1_fck'
1031 static const struct clksel mpu_clksel[] = {
1032 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1033 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1037 static struct clk mpu_ck = {
1039 .parent = &dpll1_x2m2_ck,
1040 .init = &omap2_init_clksel_parent,
1041 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1042 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1043 .clksel = mpu_clksel,
1044 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1045 PARENT_CONTROLS_CLOCK,
1046 .clkdm_name = "mpu_clkdm",
1047 .recalc = &omap2_clksel_recalc,
1050 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1051 static const struct clksel_rate arm_fck_rates[] = {
1052 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1053 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1057 static const struct clksel arm_fck_clksel[] = {
1058 { .parent = &mpu_ck, .rates = arm_fck_rates },
1062 static struct clk arm_fck = {
1065 .init = &omap2_init_clksel_parent,
1066 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1067 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1068 .clksel = arm_fck_clksel,
1069 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1070 PARENT_CONTROLS_CLOCK,
1071 .recalc = &omap2_clksel_recalc,
1074 /* XXX What about neon_clkdm ? */
1077 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1078 * although it is referenced - so this is a guess
1080 static struct clk emu_mpu_alwon_ck = {
1081 .name = "emu_mpu_alwon_ck",
1083 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1084 PARENT_CONTROLS_CLOCK,
1085 .recalc = &followparent_recalc,
1088 static struct clk dpll2_fck = {
1089 .name = "dpll2_fck",
1091 .init = &omap2_init_clksel_parent,
1092 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1093 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1094 .clksel = div2_core_clksel,
1095 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1096 PARENT_CONTROLS_CLOCK,
1097 .recalc = &omap2_clksel_recalc,
1102 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1103 * derives from the high-frequency bypass clock originating from DPLL3,
1104 * called 'dpll2_fck'
1107 static const struct clksel iva2_clksel[] = {
1108 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1109 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1113 static struct clk iva2_ck = {
1115 .parent = &dpll2_m2_ck,
1116 .init = &omap2_init_clksel_parent,
1117 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1118 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1119 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1120 OMAP3430_CM_IDLEST_PLL),
1121 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1122 .clksel = iva2_clksel,
1123 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1124 .clkdm_name = "iva2_clkdm",
1125 .recalc = &omap2_clksel_recalc,
1128 /* Common interface clocks */
1130 static struct clk l3_ick = {
1133 .init = &omap2_init_clksel_parent,
1134 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1135 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1136 .clksel = div2_core_clksel,
1137 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1138 PARENT_CONTROLS_CLOCK,
1139 .clkdm_name = "core_l3_clkdm",
1140 .recalc = &omap2_clksel_recalc,
1143 static const struct clksel div2_l3_clksel[] = {
1144 { .parent = &l3_ick, .rates = div2_rates },
1148 static struct clk l4_ick = {
1151 .init = &omap2_init_clksel_parent,
1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1153 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1154 .clksel = div2_l3_clksel,
1155 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1156 PARENT_CONTROLS_CLOCK,
1157 .clkdm_name = "core_l4_clkdm",
1158 .recalc = &omap2_clksel_recalc,
1162 static const struct clksel div2_l4_clksel[] = {
1163 { .parent = &l4_ick, .rates = div2_rates },
1167 static struct clk rm_ick = {
1170 .init = &omap2_init_clksel_parent,
1171 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1172 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1173 .clksel = div2_l4_clksel,
1174 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1175 .recalc = &omap2_clksel_recalc,
1178 /* GFX power domain */
1180 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1182 static const struct clksel gfx_l3_clksel[] = {
1183 { .parent = &l3_ick, .rates = gfx_l3_rates },
1187 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1188 static struct clk gfx_l3_ck = {
1189 .name = "gfx_l3_ck",
1191 .init = &omap2_init_clksel_parent,
1192 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1193 .enable_bit = OMAP_EN_GFX_SHIFT,
1194 .flags = CLOCK_IN_OMAP3430ES1,
1195 .recalc = &followparent_recalc,
1198 static struct clk gfx_l3_fck = {
1199 .name = "gfx_l3_fck",
1200 .parent = &gfx_l3_ck,
1201 .init = &omap2_init_clksel_parent,
1202 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1203 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1204 .clksel = gfx_l3_clksel,
1205 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1206 PARENT_CONTROLS_CLOCK,
1207 .clkdm_name = "gfx_3430es1_clkdm",
1208 .recalc = &omap2_clksel_recalc,
1211 static struct clk gfx_l3_ick = {
1212 .name = "gfx_l3_ick",
1213 .parent = &gfx_l3_ck,
1214 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1215 .clkdm_name = "gfx_3430es1_clkdm",
1216 .recalc = &followparent_recalc,
1219 static struct clk gfx_cg1_ck = {
1220 .name = "gfx_cg1_ck",
1221 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1222 .init = &omap2_init_clk_clkdm,
1223 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1224 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1225 .flags = CLOCK_IN_OMAP3430ES1,
1226 .clkdm_name = "gfx_3430es1_clkdm",
1227 .recalc = &followparent_recalc,
1230 static struct clk gfx_cg2_ck = {
1231 .name = "gfx_cg2_ck",
1232 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1233 .init = &omap2_init_clk_clkdm,
1234 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1235 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1236 .flags = CLOCK_IN_OMAP3430ES1,
1237 .clkdm_name = "gfx_3430es1_clkdm",
1238 .recalc = &followparent_recalc,
1241 /* SGX power domain - 3430ES2 only */
1243 static const struct clksel_rate sgx_core_rates[] = {
1244 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1245 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1246 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1250 static const struct clksel_rate sgx_96m_rates[] = {
1251 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1255 static const struct clksel sgx_clksel[] = {
1256 { .parent = &core_ck, .rates = sgx_core_rates },
1257 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1261 static struct clk sgx_fck = {
1263 .init = &omap2_init_clksel_parent,
1264 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1265 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1266 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1267 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1268 .clksel = sgx_clksel,
1269 .flags = CLOCK_IN_OMAP3430ES2,
1270 .clkdm_name = "sgx_clkdm",
1271 .recalc = &omap2_clksel_recalc,
1274 static struct clk sgx_ick = {
1277 .init = &omap2_init_clk_clkdm,
1278 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1279 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1280 .flags = CLOCK_IN_OMAP3430ES2,
1281 .clkdm_name = "sgx_clkdm",
1282 .recalc = &followparent_recalc,
1285 /* CORE power domain */
1287 static struct clk d2d_26m_fck = {
1288 .name = "d2d_26m_fck",
1290 .init = &omap2_init_clk_clkdm,
1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1292 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1293 .flags = CLOCK_IN_OMAP3430ES1,
1294 .clkdm_name = "d2d_clkdm",
1295 .recalc = &followparent_recalc,
1298 static const struct clksel omap343x_gpt_clksel[] = {
1299 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1300 { .parent = &sys_ck, .rates = gpt_sys_rates },
1304 static struct clk gpt10_fck = {
1305 .name = "gpt10_fck",
1307 .init = &omap2_init_clksel_parent,
1308 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1309 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1310 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1311 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1312 .clksel = omap343x_gpt_clksel,
1313 .flags = CLOCK_IN_OMAP343X,
1314 .clkdm_name = "core_l4_clkdm",
1315 .recalc = &omap2_clksel_recalc,
1318 static struct clk gpt11_fck = {
1319 .name = "gpt11_fck",
1321 .init = &omap2_init_clksel_parent,
1322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1323 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1324 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1325 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1326 .clksel = omap343x_gpt_clksel,
1327 .flags = CLOCK_IN_OMAP343X,
1328 .clkdm_name = "core_l4_clkdm",
1329 .recalc = &omap2_clksel_recalc,
1332 static struct clk cpefuse_fck = {
1333 .name = "cpefuse_fck",
1335 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1336 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1337 .flags = CLOCK_IN_OMAP3430ES2,
1338 .recalc = &followparent_recalc,
1341 static struct clk ts_fck = {
1343 .parent = &omap_32k_fck,
1344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1345 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1346 .flags = CLOCK_IN_OMAP3430ES2,
1347 .recalc = &followparent_recalc,
1350 static struct clk usbtll_fck = {
1351 .name = "usbtll_fck",
1352 .parent = &omap_120m_fck,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1354 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1355 .flags = CLOCK_IN_OMAP3430ES2,
1356 .recalc = &followparent_recalc,
1359 /* CORE 96M FCLK-derived clocks */
1361 static struct clk core_96m_fck = {
1362 .name = "core_96m_fck",
1363 .parent = &omap_96m_fck,
1364 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1365 PARENT_CONTROLS_CLOCK,
1366 .clkdm_name = "core_l4_clkdm",
1367 .recalc = &followparent_recalc,
1370 static struct clk mmchs3_fck = {
1371 .name = "mmchs_fck",
1373 .parent = &core_96m_fck,
1374 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1375 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1376 .flags = CLOCK_IN_OMAP3430ES2,
1377 .clkdm_name = "core_l4_clkdm",
1378 .recalc = &followparent_recalc,
1381 static struct clk mmchs2_fck = {
1382 .name = "mmchs_fck",
1384 .parent = &core_96m_fck,
1385 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1386 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1387 .flags = CLOCK_IN_OMAP343X,
1388 .clkdm_name = "core_l4_clkdm",
1389 .recalc = &followparent_recalc,
1392 static struct clk mspro_fck = {
1393 .name = "mspro_fck",
1394 .parent = &core_96m_fck,
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1396 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1397 .flags = CLOCK_IN_OMAP343X,
1398 .clkdm_name = "core_l4_clkdm",
1399 .recalc = &followparent_recalc,
1402 static struct clk mmchs1_fck = {
1403 .name = "mmchs_fck",
1404 .parent = &core_96m_fck,
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1407 .flags = CLOCK_IN_OMAP343X,
1408 .clkdm_name = "core_l4_clkdm",
1409 .recalc = &followparent_recalc,
1412 static struct clk i2c3_fck = {
1415 .parent = &core_96m_fck,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1418 .flags = CLOCK_IN_OMAP343X,
1419 .clkdm_name = "core_l4_clkdm",
1420 .recalc = &followparent_recalc,
1423 static struct clk i2c2_fck = {
1426 .parent = &core_96m_fck,
1427 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1428 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1429 .flags = CLOCK_IN_OMAP343X,
1430 .clkdm_name = "core_l4_clkdm",
1431 .recalc = &followparent_recalc,
1434 static struct clk i2c1_fck = {
1437 .parent = &core_96m_fck,
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1439 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1440 .flags = CLOCK_IN_OMAP343X,
1441 .clkdm_name = "core_l4_clkdm",
1442 .recalc = &followparent_recalc,
1446 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1447 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1449 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1450 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1454 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1455 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1459 static const struct clksel mcbsp_15_clksel[] = {
1460 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1461 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1465 static struct clk mcbsp5_fck = {
1466 .name = "mcbsp_fck",
1468 .init = &omap2_init_clksel_parent,
1469 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1470 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1471 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1472 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1473 .clksel = mcbsp_15_clksel,
1474 .flags = CLOCK_IN_OMAP343X,
1475 .clkdm_name = "core_l4_clkdm",
1476 .recalc = &omap2_clksel_recalc,
1479 static struct clk mcbsp1_fck = {
1480 .name = "mcbsp_fck",
1482 .init = &omap2_init_clksel_parent,
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1485 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1486 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1487 .clksel = mcbsp_15_clksel,
1488 .flags = CLOCK_IN_OMAP343X,
1489 .clkdm_name = "core_l4_clkdm",
1490 .recalc = &omap2_clksel_recalc,
1493 /* CORE_48M_FCK-derived clocks */
1495 static struct clk core_48m_fck = {
1496 .name = "core_48m_fck",
1497 .parent = &omap_48m_fck,
1498 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1499 PARENT_CONTROLS_CLOCK,
1500 .clkdm_name = "core_l4_clkdm",
1501 .recalc = &followparent_recalc,
1504 static struct clk mcspi4_fck = {
1505 .name = "mcspi_fck",
1507 .parent = &core_48m_fck,
1508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1509 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1510 .flags = CLOCK_IN_OMAP343X,
1511 .recalc = &followparent_recalc,
1514 static struct clk mcspi3_fck = {
1515 .name = "mcspi_fck",
1517 .parent = &core_48m_fck,
1518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1519 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1520 .flags = CLOCK_IN_OMAP343X,
1521 .recalc = &followparent_recalc,
1524 static struct clk mcspi2_fck = {
1525 .name = "mcspi_fck",
1527 .parent = &core_48m_fck,
1528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1529 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1530 .flags = CLOCK_IN_OMAP343X,
1531 .recalc = &followparent_recalc,
1534 static struct clk mcspi1_fck = {
1535 .name = "mcspi_fck",
1537 .parent = &core_48m_fck,
1538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1539 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1540 .flags = CLOCK_IN_OMAP343X,
1541 .recalc = &followparent_recalc,
1544 static struct clk uart2_fck = {
1545 .name = "uart2_fck",
1546 .parent = &core_48m_fck,
1547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1549 .flags = CLOCK_IN_OMAP343X,
1550 .recalc = &followparent_recalc,
1553 static struct clk uart1_fck = {
1554 .name = "uart1_fck",
1555 .parent = &core_48m_fck,
1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1558 .flags = CLOCK_IN_OMAP343X,
1559 .recalc = &followparent_recalc,
1562 static struct clk fshostusb_fck = {
1563 .name = "fshostusb_fck",
1564 .parent = &core_48m_fck,
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1567 .flags = CLOCK_IN_OMAP3430ES1,
1568 .recalc = &followparent_recalc,
1571 /* CORE_12M_FCK based clocks */
1573 static struct clk core_12m_fck = {
1574 .name = "core_12m_fck",
1575 .parent = &omap_12m_fck,
1576 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1577 PARENT_CONTROLS_CLOCK,
1578 .clkdm_name = "core_l4_clkdm",
1579 .recalc = &followparent_recalc,
1582 static struct clk hdq_fck = {
1584 .parent = &core_12m_fck,
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1587 .flags = CLOCK_IN_OMAP343X,
1588 .recalc = &followparent_recalc,
1591 /* DPLL3-derived clock */
1593 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1594 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1595 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1596 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1597 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1598 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1599 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1603 static const struct clksel ssi_ssr_clksel[] = {
1604 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1608 static struct clk ssi_ssr_fck = {
1609 .name = "ssi_ssr_fck",
1610 .init = &omap2_init_clksel_parent,
1611 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1612 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1613 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1614 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1615 .clksel = ssi_ssr_clksel,
1616 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1617 .clkdm_name = "core_l4_clkdm",
1618 .recalc = &omap2_clksel_recalc,
1621 static struct clk ssi_sst_fck = {
1622 .name = "ssi_sst_fck",
1623 .parent = &ssi_ssr_fck,
1625 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1626 .recalc = &omap2_fixed_divisor_recalc,
1631 /* CORE_L3_ICK based clocks */
1634 * XXX must add clk_enable/clk_disable for these if standard code won't
1637 static struct clk core_l3_ick = {
1638 .name = "core_l3_ick",
1640 .init = &omap2_init_clk_clkdm,
1641 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1642 PARENT_CONTROLS_CLOCK,
1643 .clkdm_name = "core_l3_clkdm",
1644 .recalc = &followparent_recalc,
1647 static struct clk hsotgusb_ick = {
1648 .name = "hsotgusb_ick",
1649 .parent = &core_l3_ick,
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1652 .flags = CLOCK_IN_OMAP343X,
1653 .clkdm_name = "core_l3_clkdm",
1654 .recalc = &followparent_recalc,
1657 static struct clk sdrc_ick = {
1659 .parent = &core_l3_ick,
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1661 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1662 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1663 .clkdm_name = "core_l3_clkdm",
1664 .recalc = &followparent_recalc,
1667 static struct clk gpmc_fck = {
1669 .parent = &core_l3_ick,
1670 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1672 .clkdm_name = "core_l3_clkdm",
1673 .recalc = &followparent_recalc,
1676 /* SECURITY_L3_ICK based clocks */
1678 static struct clk security_l3_ick = {
1679 .name = "security_l3_ick",
1681 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1682 PARENT_CONTROLS_CLOCK,
1683 .recalc = &followparent_recalc,
1686 static struct clk pka_ick = {
1688 .parent = &security_l3_ick,
1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1690 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1691 .flags = CLOCK_IN_OMAP343X,
1692 .recalc = &followparent_recalc,
1695 /* CORE_L4_ICK based clocks */
1697 static struct clk core_l4_ick = {
1698 .name = "core_l4_ick",
1700 .init = &omap2_init_clk_clkdm,
1701 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1702 PARENT_CONTROLS_CLOCK,
1703 .clkdm_name = "core_l4_clkdm",
1704 .recalc = &followparent_recalc,
1707 static struct clk usbtll_ick = {
1708 .name = "usbtll_ick",
1709 .parent = &core_l4_ick,
1710 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1711 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1712 .flags = CLOCK_IN_OMAP3430ES2,
1713 .clkdm_name = "core_l4_clkdm",
1714 .recalc = &followparent_recalc,
1717 static struct clk mmchs3_ick = {
1718 .name = "mmchs_ick",
1720 .parent = &core_l4_ick,
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1722 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1723 .flags = CLOCK_IN_OMAP3430ES2,
1724 .clkdm_name = "core_l4_clkdm",
1725 .recalc = &followparent_recalc,
1728 /* Intersystem Communication Registers - chassis mode only */
1729 static struct clk icr_ick = {
1731 .parent = &core_l4_ick,
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1734 .flags = CLOCK_IN_OMAP343X,
1735 .clkdm_name = "core_l4_clkdm",
1736 .recalc = &followparent_recalc,
1739 static struct clk aes2_ick = {
1741 .parent = &core_l4_ick,
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1743 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1744 .flags = CLOCK_IN_OMAP343X,
1745 .clkdm_name = "core_l4_clkdm",
1746 .recalc = &followparent_recalc,
1749 static struct clk sha12_ick = {
1750 .name = "sha12_ick",
1751 .parent = &core_l4_ick,
1752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1753 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1754 .flags = CLOCK_IN_OMAP343X,
1755 .clkdm_name = "core_l4_clkdm",
1756 .recalc = &followparent_recalc,
1759 static struct clk des2_ick = {
1761 .parent = &core_l4_ick,
1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1763 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1764 .flags = CLOCK_IN_OMAP343X,
1765 .clkdm_name = "core_l4_clkdm",
1766 .recalc = &followparent_recalc,
1769 static struct clk mmchs2_ick = {
1770 .name = "mmchs_ick",
1772 .parent = &core_l4_ick,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1774 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1775 .flags = CLOCK_IN_OMAP343X,
1776 .clkdm_name = "core_l4_clkdm",
1777 .recalc = &followparent_recalc,
1780 static struct clk mmchs1_ick = {
1781 .name = "mmchs_ick",
1782 .parent = &core_l4_ick,
1783 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1785 .flags = CLOCK_IN_OMAP343X,
1786 .clkdm_name = "core_l4_clkdm",
1787 .recalc = &followparent_recalc,
1790 static struct clk mspro_ick = {
1791 .name = "mspro_ick",
1792 .parent = &core_l4_ick,
1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1795 .flags = CLOCK_IN_OMAP343X,
1796 .clkdm_name = "core_l4_clkdm",
1797 .recalc = &followparent_recalc,
1800 static struct clk hdq_ick = {
1802 .parent = &core_l4_ick,
1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1805 .flags = CLOCK_IN_OMAP343X,
1806 .clkdm_name = "core_l4_clkdm",
1807 .recalc = &followparent_recalc,
1810 static struct clk mcspi4_ick = {
1811 .name = "mcspi_ick",
1813 .parent = &core_l4_ick,
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1816 .flags = CLOCK_IN_OMAP343X,
1817 .clkdm_name = "core_l4_clkdm",
1818 .recalc = &followparent_recalc,
1821 static struct clk mcspi3_ick = {
1822 .name = "mcspi_ick",
1824 .parent = &core_l4_ick,
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1826 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1827 .flags = CLOCK_IN_OMAP343X,
1828 .clkdm_name = "core_l4_clkdm",
1829 .recalc = &followparent_recalc,
1832 static struct clk mcspi2_ick = {
1833 .name = "mcspi_ick",
1835 .parent = &core_l4_ick,
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1838 .flags = CLOCK_IN_OMAP343X,
1839 .clkdm_name = "core_l4_clkdm",
1840 .recalc = &followparent_recalc,
1843 static struct clk mcspi1_ick = {
1844 .name = "mcspi_ick",
1846 .parent = &core_l4_ick,
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1849 .flags = CLOCK_IN_OMAP343X,
1850 .clkdm_name = "core_l4_clkdm",
1851 .recalc = &followparent_recalc,
1854 static struct clk i2c3_ick = {
1857 .parent = &core_l4_ick,
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1860 .flags = CLOCK_IN_OMAP343X,
1861 .clkdm_name = "core_l4_clkdm",
1862 .recalc = &followparent_recalc,
1865 static struct clk i2c2_ick = {
1868 .parent = &core_l4_ick,
1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1871 .flags = CLOCK_IN_OMAP343X,
1872 .clkdm_name = "core_l4_clkdm",
1873 .recalc = &followparent_recalc,
1876 static struct clk i2c1_ick = {
1879 .parent = &core_l4_ick,
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1882 .flags = CLOCK_IN_OMAP343X,
1883 .clkdm_name = "core_l4_clkdm",
1884 .recalc = &followparent_recalc,
1887 static struct clk uart2_ick = {
1888 .name = "uart2_ick",
1889 .parent = &core_l4_ick,
1890 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1892 .flags = CLOCK_IN_OMAP343X,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1897 static struct clk uart1_ick = {
1898 .name = "uart1_ick",
1899 .parent = &core_l4_ick,
1900 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1902 .flags = CLOCK_IN_OMAP343X,
1903 .clkdm_name = "core_l4_clkdm",
1904 .recalc = &followparent_recalc,
1907 static struct clk gpt11_ick = {
1908 .name = "gpt11_ick",
1909 .parent = &core_l4_ick,
1910 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1911 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1912 .flags = CLOCK_IN_OMAP343X,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1917 static struct clk gpt10_ick = {
1918 .name = "gpt10_ick",
1919 .parent = &core_l4_ick,
1920 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1922 .flags = CLOCK_IN_OMAP343X,
1923 .clkdm_name = "core_l4_clkdm",
1924 .recalc = &followparent_recalc,
1927 static struct clk mcbsp5_ick = {
1928 .name = "mcbsp_ick",
1930 .parent = &core_l4_ick,
1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1933 .flags = CLOCK_IN_OMAP343X,
1934 .clkdm_name = "core_l4_clkdm",
1935 .recalc = &followparent_recalc,
1938 static struct clk mcbsp1_ick = {
1939 .name = "mcbsp_ick",
1941 .parent = &core_l4_ick,
1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1944 .flags = CLOCK_IN_OMAP343X,
1945 .clkdm_name = "core_l4_clkdm",
1946 .recalc = &followparent_recalc,
1949 static struct clk fac_ick = {
1951 .parent = &core_l4_ick,
1952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1954 .flags = CLOCK_IN_OMAP3430ES1,
1955 .clkdm_name = "core_l4_clkdm",
1956 .recalc = &followparent_recalc,
1959 static struct clk mailboxes_ick = {
1960 .name = "mailboxes_ick",
1961 .parent = &core_l4_ick,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1964 .flags = CLOCK_IN_OMAP343X,
1965 .clkdm_name = "core_l4_clkdm",
1966 .recalc = &followparent_recalc,
1969 static struct clk omapctrl_ick = {
1970 .name = "omapctrl_ick",
1971 .parent = &core_l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1974 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1975 .recalc = &followparent_recalc,
1978 /* SSI_L4_ICK based clocks */
1980 static struct clk ssi_l4_ick = {
1981 .name = "ssi_l4_ick",
1983 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1984 PARENT_CONTROLS_CLOCK,
1985 .clkdm_name = "core_l4_clkdm",
1986 .recalc = &followparent_recalc,
1989 static struct clk ssi_ick = {
1991 .parent = &ssi_l4_ick,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1994 .flags = CLOCK_IN_OMAP343X,
1995 .clkdm_name = "core_l4_clkdm",
1996 .recalc = &followparent_recalc,
1999 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2000 * but l4_ick makes more sense to me */
2002 static const struct clksel usb_l4_clksel[] = {
2003 { .parent = &l4_ick, .rates = div2_rates },
2007 static struct clk usb_l4_ick = {
2008 .name = "usb_l4_ick",
2010 .init = &omap2_init_clksel_parent,
2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2012 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2013 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2014 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2015 .clksel = usb_l4_clksel,
2016 .flags = CLOCK_IN_OMAP3430ES1,
2017 .recalc = &omap2_clksel_recalc,
2020 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2022 /* SECURITY_L4_ICK2 based clocks */
2024 static struct clk security_l4_ick2 = {
2025 .name = "security_l4_ick2",
2027 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2028 PARENT_CONTROLS_CLOCK,
2029 .recalc = &followparent_recalc,
2032 static struct clk aes1_ick = {
2034 .parent = &security_l4_ick2,
2035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2036 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2037 .flags = CLOCK_IN_OMAP343X,
2038 .recalc = &followparent_recalc,
2041 static struct clk rng_ick = {
2043 .parent = &security_l4_ick2,
2044 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2045 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2046 .flags = CLOCK_IN_OMAP343X,
2047 .recalc = &followparent_recalc,
2050 static struct clk sha11_ick = {
2051 .name = "sha11_ick",
2052 .parent = &security_l4_ick2,
2053 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2054 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2055 .flags = CLOCK_IN_OMAP343X,
2056 .recalc = &followparent_recalc,
2059 static struct clk des1_ick = {
2061 .parent = &security_l4_ick2,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2063 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2064 .flags = CLOCK_IN_OMAP343X,
2065 .recalc = &followparent_recalc,
2069 static const struct clksel dss1_alwon_fck_clksel[] = {
2070 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2071 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2075 static struct clk dss1_alwon_fck = {
2076 .name = "dss1_alwon_fck",
2077 .parent = &dpll4_m4x2_ck,
2078 .init = &omap2_init_clksel_parent,
2079 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2080 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2081 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2082 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2083 .clksel = dss1_alwon_fck_clksel,
2084 .flags = CLOCK_IN_OMAP343X,
2085 .clkdm_name = "dss_clkdm",
2086 .recalc = &omap2_clksel_recalc,
2089 static struct clk dss_tv_fck = {
2090 .name = "dss_tv_fck",
2091 .parent = &omap_54m_fck,
2092 .init = &omap2_init_clk_clkdm,
2093 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2094 .enable_bit = OMAP3430_EN_TV_SHIFT,
2095 .flags = CLOCK_IN_OMAP343X,
2096 .clkdm_name = "dss_clkdm",
2097 .recalc = &followparent_recalc,
2100 static struct clk dss_96m_fck = {
2101 .name = "dss_96m_fck",
2102 .parent = &omap_96m_fck,
2103 .init = &omap2_init_clk_clkdm,
2104 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2105 .enable_bit = OMAP3430_EN_TV_SHIFT,
2106 .flags = CLOCK_IN_OMAP343X,
2107 .clkdm_name = "dss_clkdm",
2108 .recalc = &followparent_recalc,
2111 static struct clk dss2_alwon_fck = {
2112 .name = "dss2_alwon_fck",
2114 .init = &omap2_init_clk_clkdm,
2115 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2116 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2117 .flags = CLOCK_IN_OMAP343X,
2118 .clkdm_name = "dss_clkdm",
2119 .recalc = &followparent_recalc,
2122 static struct clk dss_ick = {
2123 /* Handles both L3 and L4 clocks */
2126 .init = &omap2_init_clk_clkdm,
2127 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2128 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2129 .flags = CLOCK_IN_OMAP343X,
2130 .clkdm_name = "dss_clkdm",
2131 .recalc = &followparent_recalc,
2136 static const struct clksel cam_mclk_clksel[] = {
2137 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2138 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2142 static struct clk cam_mclk = {
2144 .parent = &dpll4_m5x2_ck,
2145 .init = &omap2_init_clksel_parent,
2146 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2147 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2148 .clksel = cam_mclk_clksel,
2149 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2150 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2151 .flags = CLOCK_IN_OMAP343X,
2152 .clkdm_name = "cam_clkdm",
2153 .recalc = &omap2_clksel_recalc,
2156 static struct clk cam_ick = {
2157 /* Handles both L3 and L4 clocks */
2160 .init = &omap2_init_clk_clkdm,
2161 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2162 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2163 .flags = CLOCK_IN_OMAP343X,
2164 .clkdm_name = "cam_clkdm",
2165 .recalc = &followparent_recalc,
2168 /* USBHOST - 3430ES2 only */
2170 static struct clk usbhost_120m_fck = {
2171 .name = "usbhost_120m_fck",
2172 .parent = &omap_120m_fck,
2173 .init = &omap2_init_clk_clkdm,
2174 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2175 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2176 .flags = CLOCK_IN_OMAP3430ES2,
2177 .clkdm_name = "usbhost_clkdm",
2178 .recalc = &followparent_recalc,
2181 static struct clk usbhost_48m_fck = {
2182 .name = "usbhost_48m_fck",
2183 .parent = &omap_48m_fck,
2184 .init = &omap2_init_clk_clkdm,
2185 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2186 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2187 .flags = CLOCK_IN_OMAP3430ES2,
2188 .clkdm_name = "usbhost_clkdm",
2189 .recalc = &followparent_recalc,
2192 static struct clk usbhost_ick = {
2193 /* Handles both L3 and L4 clocks */
2194 .name = "usbhost_ick",
2196 .init = &omap2_init_clk_clkdm,
2197 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2198 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2199 .flags = CLOCK_IN_OMAP3430ES2,
2200 .clkdm_name = "usbhost_clkdm",
2201 .recalc = &followparent_recalc,
2204 static struct clk usbhost_sar_fck = {
2205 .name = "usbhost_sar_fck",
2206 .parent = &osc_sys_ck,
2207 .init = &omap2_init_clk_clkdm,
2208 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2209 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2210 .flags = CLOCK_IN_OMAP3430ES2,
2211 .clkdm_name = "usbhost_clkdm",
2212 .recalc = &followparent_recalc,
2217 static const struct clksel_rate usim_96m_rates[] = {
2218 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2219 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2220 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2221 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2225 static const struct clksel_rate usim_120m_rates[] = {
2226 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2227 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2228 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2229 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2233 static const struct clksel usim_clksel[] = {
2234 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2235 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2236 { .parent = &sys_ck, .rates = div2_rates },
2241 static struct clk usim_fck = {
2243 .init = &omap2_init_clksel_parent,
2244 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2245 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2246 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2247 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2248 .clksel = usim_clksel,
2249 .flags = CLOCK_IN_OMAP3430ES2,
2250 .recalc = &omap2_clksel_recalc,
2253 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2254 static struct clk gpt1_fck = {
2256 .init = &omap2_init_clksel_parent,
2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2258 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2259 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2260 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2261 .clksel = omap343x_gpt_clksel,
2262 .flags = CLOCK_IN_OMAP343X,
2263 .clkdm_name = "wkup_clkdm",
2264 .recalc = &omap2_clksel_recalc,
2267 static struct clk wkup_32k_fck = {
2268 .name = "wkup_32k_fck",
2269 .init = &omap2_init_clk_clkdm,
2270 .parent = &omap_32k_fck,
2271 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2272 .clkdm_name = "wkup_clkdm",
2273 .recalc = &followparent_recalc,
2276 static struct clk gpio1_dbck = {
2277 .name = "gpio1_dbck",
2278 .parent = &wkup_32k_fck,
2279 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2280 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2281 .flags = CLOCK_IN_OMAP343X,
2282 .clkdm_name = "wkup_clkdm",
2283 .recalc = &followparent_recalc,
2286 static struct clk wdt2_fck = {
2288 .parent = &wkup_32k_fck,
2289 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2290 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2291 .flags = CLOCK_IN_OMAP343X,
2292 .clkdm_name = "wkup_clkdm",
2293 .recalc = &followparent_recalc,
2296 static struct clk wkup_l4_ick = {
2297 .name = "wkup_l4_ick",
2299 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2300 .clkdm_name = "wkup_clkdm",
2301 .recalc = &followparent_recalc,
2305 /* Never specifically named in the TRM, so we have to infer a likely name */
2306 static struct clk usim_ick = {
2308 .parent = &wkup_l4_ick,
2309 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2310 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2311 .flags = CLOCK_IN_OMAP3430ES2,
2312 .clkdm_name = "wkup_clkdm",
2313 .recalc = &followparent_recalc,
2316 static struct clk wdt2_ick = {
2318 .parent = &wkup_l4_ick,
2319 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2320 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2321 .flags = CLOCK_IN_OMAP343X,
2322 .clkdm_name = "wkup_clkdm",
2323 .recalc = &followparent_recalc,
2326 static struct clk wdt1_ick = {
2328 .parent = &wkup_l4_ick,
2329 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2330 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2331 .flags = CLOCK_IN_OMAP343X,
2332 .clkdm_name = "wkup_clkdm",
2333 .recalc = &followparent_recalc,
2336 static struct clk gpio1_ick = {
2337 .name = "gpio1_ick",
2338 .parent = &wkup_l4_ick,
2339 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2340 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2341 .flags = CLOCK_IN_OMAP343X,
2342 .clkdm_name = "wkup_clkdm",
2343 .recalc = &followparent_recalc,
2346 static struct clk omap_32ksync_ick = {
2347 .name = "omap_32ksync_ick",
2348 .parent = &wkup_l4_ick,
2349 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2350 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2351 .flags = CLOCK_IN_OMAP343X,
2352 .clkdm_name = "wkup_clkdm",
2353 .recalc = &followparent_recalc,
2356 /* XXX This clock no longer exists in 3430 TRM rev F */
2357 static struct clk gpt12_ick = {
2358 .name = "gpt12_ick",
2359 .parent = &wkup_l4_ick,
2360 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2361 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2362 .flags = CLOCK_IN_OMAP343X,
2363 .clkdm_name = "wkup_clkdm",
2364 .recalc = &followparent_recalc,
2367 static struct clk gpt1_ick = {
2369 .parent = &wkup_l4_ick,
2370 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2371 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2372 .flags = CLOCK_IN_OMAP343X,
2373 .clkdm_name = "wkup_clkdm",
2374 .recalc = &followparent_recalc,
2379 /* PER clock domain */
2381 static struct clk per_96m_fck = {
2382 .name = "per_96m_fck",
2383 .parent = &omap_96m_alwon_fck,
2384 .init = &omap2_init_clk_clkdm,
2385 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2386 PARENT_CONTROLS_CLOCK,
2387 .clkdm_name = "per_clkdm",
2388 .recalc = &followparent_recalc,
2391 static struct clk per_48m_fck = {
2392 .name = "per_48m_fck",
2393 .parent = &omap_48m_fck,
2394 .init = &omap2_init_clk_clkdm,
2395 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2396 PARENT_CONTROLS_CLOCK,
2397 .clkdm_name = "per_clkdm",
2398 .recalc = &followparent_recalc,
2401 static struct clk uart3_fck = {
2402 .name = "uart3_fck",
2403 .parent = &per_48m_fck,
2404 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2405 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2406 .flags = CLOCK_IN_OMAP343X,
2407 .clkdm_name = "per_clkdm",
2408 .recalc = &followparent_recalc,
2411 static struct clk gpt2_fck = {
2413 .init = &omap2_init_clksel_parent,
2414 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2415 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2416 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2417 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2418 .clksel = omap343x_gpt_clksel,
2419 .flags = CLOCK_IN_OMAP343X,
2420 .clkdm_name = "per_clkdm",
2421 .recalc = &omap2_clksel_recalc,
2424 static struct clk gpt3_fck = {
2426 .init = &omap2_init_clksel_parent,
2427 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2428 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2429 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2430 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2431 .clksel = omap343x_gpt_clksel,
2432 .flags = CLOCK_IN_OMAP343X,
2433 .clkdm_name = "per_clkdm",
2434 .recalc = &omap2_clksel_recalc,
2437 static struct clk gpt4_fck = {
2439 .init = &omap2_init_clksel_parent,
2440 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2442 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2443 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2444 .clksel = omap343x_gpt_clksel,
2445 .flags = CLOCK_IN_OMAP343X,
2446 .clkdm_name = "per_clkdm",
2447 .recalc = &omap2_clksel_recalc,
2450 static struct clk gpt5_fck = {
2452 .init = &omap2_init_clksel_parent,
2453 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2454 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2455 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2456 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2457 .clksel = omap343x_gpt_clksel,
2458 .flags = CLOCK_IN_OMAP343X,
2459 .clkdm_name = "per_clkdm",
2460 .recalc = &omap2_clksel_recalc,
2463 static struct clk gpt6_fck = {
2465 .init = &omap2_init_clksel_parent,
2466 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2467 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2468 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2469 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2470 .clksel = omap343x_gpt_clksel,
2471 .flags = CLOCK_IN_OMAP343X,
2472 .clkdm_name = "per_clkdm",
2473 .recalc = &omap2_clksel_recalc,
2476 static struct clk gpt7_fck = {
2478 .init = &omap2_init_clksel_parent,
2479 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2480 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2481 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2482 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2483 .clksel = omap343x_gpt_clksel,
2484 .flags = CLOCK_IN_OMAP343X,
2485 .clkdm_name = "per_clkdm",
2486 .recalc = &omap2_clksel_recalc,
2489 static struct clk gpt8_fck = {
2491 .init = &omap2_init_clksel_parent,
2492 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2493 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2494 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2495 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2496 .clksel = omap343x_gpt_clksel,
2497 .flags = CLOCK_IN_OMAP343X,
2498 .clkdm_name = "per_clkdm",
2499 .recalc = &omap2_clksel_recalc,
2502 static struct clk gpt9_fck = {
2504 .init = &omap2_init_clksel_parent,
2505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2506 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2508 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2509 .clksel = omap343x_gpt_clksel,
2510 .flags = CLOCK_IN_OMAP343X,
2511 .clkdm_name = "per_clkdm",
2512 .recalc = &omap2_clksel_recalc,
2515 static struct clk per_32k_alwon_fck = {
2516 .name = "per_32k_alwon_fck",
2517 .parent = &omap_32k_fck,
2518 .clkdm_name = "per_clkdm",
2519 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2520 .recalc = &followparent_recalc,
2523 static struct clk gpio6_dbck = {
2524 .name = "gpio6_dbck",
2525 .parent = &per_32k_alwon_fck,
2526 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2527 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2528 .flags = CLOCK_IN_OMAP343X,
2529 .clkdm_name = "per_clkdm",
2530 .recalc = &followparent_recalc,
2533 static struct clk gpio5_dbck = {
2534 .name = "gpio5_dbck",
2535 .parent = &per_32k_alwon_fck,
2536 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2537 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2538 .flags = CLOCK_IN_OMAP343X,
2539 .clkdm_name = "per_clkdm",
2540 .recalc = &followparent_recalc,
2543 static struct clk gpio4_dbck = {
2544 .name = "gpio4_dbck",
2545 .parent = &per_32k_alwon_fck,
2546 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2547 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2548 .flags = CLOCK_IN_OMAP343X,
2549 .clkdm_name = "per_clkdm",
2550 .recalc = &followparent_recalc,
2553 static struct clk gpio3_dbck = {
2554 .name = "gpio3_dbck",
2555 .parent = &per_32k_alwon_fck,
2556 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2557 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2558 .flags = CLOCK_IN_OMAP343X,
2559 .clkdm_name = "per_clkdm",
2560 .recalc = &followparent_recalc,
2563 static struct clk gpio2_dbck = {
2564 .name = "gpio2_dbck",
2565 .parent = &per_32k_alwon_fck,
2566 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2567 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2568 .flags = CLOCK_IN_OMAP343X,
2569 .clkdm_name = "per_clkdm",
2570 .recalc = &followparent_recalc,
2573 static struct clk wdt3_fck = {
2575 .parent = &per_32k_alwon_fck,
2576 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2578 .flags = CLOCK_IN_OMAP343X,
2579 .clkdm_name = "per_clkdm",
2580 .recalc = &followparent_recalc,
2583 static struct clk per_l4_ick = {
2584 .name = "per_l4_ick",
2586 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2587 PARENT_CONTROLS_CLOCK,
2588 .clkdm_name = "per_clkdm",
2589 .recalc = &followparent_recalc,
2592 static struct clk gpio6_ick = {
2593 .name = "gpio6_ick",
2594 .parent = &per_l4_ick,
2595 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2596 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2597 .flags = CLOCK_IN_OMAP343X,
2598 .clkdm_name = "per_clkdm",
2599 .recalc = &followparent_recalc,
2602 static struct clk gpio5_ick = {
2603 .name = "gpio5_ick",
2604 .parent = &per_l4_ick,
2605 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2606 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2607 .flags = CLOCK_IN_OMAP343X,
2608 .clkdm_name = "per_clkdm",
2609 .recalc = &followparent_recalc,
2612 static struct clk gpio4_ick = {
2613 .name = "gpio4_ick",
2614 .parent = &per_l4_ick,
2615 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2616 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2617 .flags = CLOCK_IN_OMAP343X,
2618 .clkdm_name = "per_clkdm",
2619 .recalc = &followparent_recalc,
2622 static struct clk gpio3_ick = {
2623 .name = "gpio3_ick",
2624 .parent = &per_l4_ick,
2625 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2626 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2627 .flags = CLOCK_IN_OMAP343X,
2628 .clkdm_name = "per_clkdm",
2629 .recalc = &followparent_recalc,
2632 static struct clk gpio2_ick = {
2633 .name = "gpio2_ick",
2634 .parent = &per_l4_ick,
2635 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2636 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2637 .flags = CLOCK_IN_OMAP343X,
2638 .clkdm_name = "per_clkdm",
2639 .recalc = &followparent_recalc,
2642 static struct clk wdt3_ick = {
2644 .parent = &per_l4_ick,
2645 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2646 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2647 .flags = CLOCK_IN_OMAP343X,
2648 .clkdm_name = "per_clkdm",
2649 .recalc = &followparent_recalc,
2652 static struct clk uart3_ick = {
2653 .name = "uart3_ick",
2654 .parent = &per_l4_ick,
2655 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2656 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2657 .flags = CLOCK_IN_OMAP343X,
2658 .clkdm_name = "per_clkdm",
2659 .recalc = &followparent_recalc,
2662 static struct clk gpt9_ick = {
2664 .parent = &per_l4_ick,
2665 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2666 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2667 .flags = CLOCK_IN_OMAP343X,
2668 .clkdm_name = "per_clkdm",
2669 .recalc = &followparent_recalc,
2672 static struct clk gpt8_ick = {
2674 .parent = &per_l4_ick,
2675 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2676 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2677 .flags = CLOCK_IN_OMAP343X,
2678 .clkdm_name = "per_clkdm",
2679 .recalc = &followparent_recalc,
2682 static struct clk gpt7_ick = {
2684 .parent = &per_l4_ick,
2685 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2686 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2687 .flags = CLOCK_IN_OMAP343X,
2688 .clkdm_name = "per_clkdm",
2689 .recalc = &followparent_recalc,
2692 static struct clk gpt6_ick = {
2694 .parent = &per_l4_ick,
2695 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2696 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2697 .flags = CLOCK_IN_OMAP343X,
2698 .clkdm_name = "per_clkdm",
2699 .recalc = &followparent_recalc,
2702 static struct clk gpt5_ick = {
2704 .parent = &per_l4_ick,
2705 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2706 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2707 .flags = CLOCK_IN_OMAP343X,
2708 .clkdm_name = "per_clkdm",
2709 .recalc = &followparent_recalc,
2712 static struct clk gpt4_ick = {
2714 .parent = &per_l4_ick,
2715 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2716 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2717 .flags = CLOCK_IN_OMAP343X,
2718 .clkdm_name = "per_clkdm",
2719 .recalc = &followparent_recalc,
2722 static struct clk gpt3_ick = {
2724 .parent = &per_l4_ick,
2725 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2726 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2727 .flags = CLOCK_IN_OMAP343X,
2728 .clkdm_name = "per_clkdm",
2729 .recalc = &followparent_recalc,
2732 static struct clk gpt2_ick = {
2734 .parent = &per_l4_ick,
2735 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2736 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2737 .flags = CLOCK_IN_OMAP343X,
2738 .clkdm_name = "per_clkdm",
2739 .recalc = &followparent_recalc,
2742 static struct clk mcbsp2_ick = {
2743 .name = "mcbsp_ick",
2745 .parent = &per_l4_ick,
2746 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2748 .flags = CLOCK_IN_OMAP343X,
2749 .clkdm_name = "per_clkdm",
2750 .recalc = &followparent_recalc,
2753 static struct clk mcbsp3_ick = {
2754 .name = "mcbsp_ick",
2756 .parent = &per_l4_ick,
2757 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2758 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2759 .flags = CLOCK_IN_OMAP343X,
2760 .clkdm_name = "per_clkdm",
2761 .recalc = &followparent_recalc,
2764 static struct clk mcbsp4_ick = {
2765 .name = "mcbsp_ick",
2767 .parent = &per_l4_ick,
2768 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2770 .flags = CLOCK_IN_OMAP343X,
2771 .clkdm_name = "per_clkdm",
2772 .recalc = &followparent_recalc,
2775 static const struct clksel mcbsp_234_clksel[] = {
2776 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2777 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2781 static struct clk mcbsp2_fck = {
2782 .name = "mcbsp_fck",
2784 .init = &omap2_init_clksel_parent,
2785 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2786 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2787 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2788 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2789 .clksel = mcbsp_234_clksel,
2790 .flags = CLOCK_IN_OMAP343X,
2791 .clkdm_name = "per_clkdm",
2792 .recalc = &omap2_clksel_recalc,
2795 static struct clk mcbsp3_fck = {
2796 .name = "mcbsp_fck",
2798 .init = &omap2_init_clksel_parent,
2799 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2800 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2801 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2802 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2803 .clksel = mcbsp_234_clksel,
2804 .flags = CLOCK_IN_OMAP343X,
2805 .clkdm_name = "per_clkdm",
2806 .recalc = &omap2_clksel_recalc,
2809 static struct clk mcbsp4_fck = {
2810 .name = "mcbsp_fck",
2812 .init = &omap2_init_clksel_parent,
2813 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2814 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2815 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2816 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2817 .clksel = mcbsp_234_clksel,
2818 .flags = CLOCK_IN_OMAP343X,
2819 .clkdm_name = "per_clkdm",
2820 .recalc = &omap2_clksel_recalc,
2825 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2827 static const struct clksel_rate emu_src_sys_rates[] = {
2828 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2832 static const struct clksel_rate emu_src_core_rates[] = {
2833 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2837 static const struct clksel_rate emu_src_per_rates[] = {
2838 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2842 static const struct clksel_rate emu_src_mpu_rates[] = {
2843 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2847 static const struct clksel emu_src_clksel[] = {
2848 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2849 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2850 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2851 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2856 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2857 * to switch the source of some of the EMU clocks.
2858 * XXX Are there CLKEN bits for these EMU clks?
2860 static struct clk emu_src_ck = {
2861 .name = "emu_src_ck",
2862 .init = &omap2_init_clksel_parent,
2863 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2864 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2865 .clksel = emu_src_clksel,
2866 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2867 .clkdm_name = "emu_clkdm",
2868 .recalc = &omap2_clksel_recalc,
2871 static const struct clksel_rate pclk_emu_rates[] = {
2872 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2873 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2874 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2875 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2879 static const struct clksel pclk_emu_clksel[] = {
2880 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2884 static struct clk pclk_fck = {
2886 .init = &omap2_init_clksel_parent,
2887 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2888 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2889 .clksel = pclk_emu_clksel,
2890 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2891 .clkdm_name = "emu_clkdm",
2892 .recalc = &omap2_clksel_recalc,
2895 static const struct clksel_rate pclkx2_emu_rates[] = {
2896 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2897 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2898 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2902 static const struct clksel pclkx2_emu_clksel[] = {
2903 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2907 static struct clk pclkx2_fck = {
2908 .name = "pclkx2_fck",
2909 .init = &omap2_init_clksel_parent,
2910 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2911 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2912 .clksel = pclkx2_emu_clksel,
2913 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2914 .clkdm_name = "emu_clkdm",
2915 .recalc = &omap2_clksel_recalc,
2918 static const struct clksel atclk_emu_clksel[] = {
2919 { .parent = &emu_src_ck, .rates = div2_rates },
2923 static struct clk atclk_fck = {
2924 .name = "atclk_fck",
2925 .init = &omap2_init_clksel_parent,
2926 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2927 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2928 .clksel = atclk_emu_clksel,
2929 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2930 .clkdm_name = "emu_clkdm",
2931 .recalc = &omap2_clksel_recalc,
2934 static struct clk traceclk_src_fck = {
2935 .name = "traceclk_src_fck",
2936 .init = &omap2_init_clksel_parent,
2937 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2938 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2939 .clksel = emu_src_clksel,
2940 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2941 .clkdm_name = "emu_clkdm",
2942 .recalc = &omap2_clksel_recalc,
2945 static const struct clksel_rate traceclk_rates[] = {
2946 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2947 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2948 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2952 static const struct clksel traceclk_clksel[] = {
2953 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2957 static struct clk traceclk_fck = {
2958 .name = "traceclk_fck",
2959 .init = &omap2_init_clksel_parent,
2960 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2961 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2962 .clksel = traceclk_clksel,
2963 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2964 .clkdm_name = "emu_clkdm",
2965 .recalc = &omap2_clksel_recalc,
2970 /* SmartReflex fclk (VDD1) */
2971 static struct clk sr1_fck = {
2974 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2975 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2976 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2977 .recalc = &followparent_recalc,
2980 /* SmartReflex fclk (VDD2) */
2981 static struct clk sr2_fck = {
2984 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2985 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2986 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2987 .recalc = &followparent_recalc,
2990 static struct clk sr_l4_ick = {
2991 .name = "sr_l4_ick",
2993 .flags = CLOCK_IN_OMAP343X,
2994 .clkdm_name = "core_l4_clkdm",
2995 .recalc = &followparent_recalc,
2998 /* SECURE_32K_FCK clocks */
3000 /* XXX This clock no longer exists in 3430 TRM rev F */
3001 static struct clk gpt12_fck = {
3002 .name = "gpt12_fck",
3003 .parent = &secure_32k_fck,
3004 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3005 .recalc = &followparent_recalc,
3008 static struct clk wdt1_fck = {
3010 .parent = &secure_32k_fck,
3011 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3012 .recalc = &followparent_recalc,
3015 static struct clk *onchip_34xx_clks[] __initdata = {
3043 &omap_96m_alwon_fck,