1 /* linux/arch/arm/plat-s3c24xx/pm.c
3 * Copyright (c) 2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Power Manager (Suspend-To-RAM) support
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Parts based on arch/arm/mach-pxa/pm.c
26 * Thanks to Dimitry Andric for debugging
29 #include <linux/init.h>
30 #include <linux/suspend.h>
31 #include <linux/errno.h>
32 #include <linux/time.h>
33 #include <linux/interrupt.h>
34 #include <linux/serial_core.h>
37 #include <asm/cacheflush.h>
38 #include <mach/hardware.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
43 #include <mach/regs-mem.h>
44 #include <mach/regs-irq.h>
46 #include <asm/mach/time.h>
51 #define PFX "s3c24xx-pm: "
53 static struct sleep_save core_save[] = {
54 SAVE_ITEM(S3C2410_LOCKTIME),
55 SAVE_ITEM(S3C2410_CLKCON),
57 /* we restore the timings here, with the proviso that the board
58 * brings the system up in an slower, or equal frequency setting
59 * to the original system.
61 * if we cannot guarantee this, then things are going to go very
62 * wrong here, as we modify the refresh and both pll settings.
65 SAVE_ITEM(S3C2410_BWSCON),
66 SAVE_ITEM(S3C2410_BANKCON0),
67 SAVE_ITEM(S3C2410_BANKCON1),
68 SAVE_ITEM(S3C2410_BANKCON2),
69 SAVE_ITEM(S3C2410_BANKCON3),
70 SAVE_ITEM(S3C2410_BANKCON4),
71 SAVE_ITEM(S3C2410_BANKCON5),
73 #ifndef CONFIG_CPU_FREQ
74 SAVE_ITEM(S3C2410_CLKDIVN),
75 SAVE_ITEM(S3C2410_MPLLCON),
76 SAVE_ITEM(S3C2410_REFRESH),
78 SAVE_ITEM(S3C2410_UPLLCON),
79 SAVE_ITEM(S3C2410_CLKSLOW),
82 static struct gpio_sleep {
89 .base = S3C2410_GPACON,
92 .base = S3C2410_GPBCON,
95 .base = S3C2410_GPCCON,
98 .base = S3C2410_GPDCON,
101 .base = S3C2410_GPECON,
104 .base = S3C2410_GPFCON,
107 .base = S3C2410_GPGCON,
110 .base = S3C2410_GPHCON,
114 static struct sleep_save misc_save[] = {
115 SAVE_ITEM(S3C2410_DCLKCON),
118 #ifdef CONFIG_S3C2410_PM_DEBUG
120 #define SAVE_UART(va) \
121 SAVE_ITEM((va) + S3C2410_ULCON), \
122 SAVE_ITEM((va) + S3C2410_UCON), \
123 SAVE_ITEM((va) + S3C2410_UFCON), \
124 SAVE_ITEM((va) + S3C2410_UMCON), \
125 SAVE_ITEM((va) + S3C2410_UBRDIV)
127 static struct sleep_save uart_save[] = {
128 SAVE_UART(S3C24XX_VA_UART0),
129 SAVE_UART(S3C24XX_VA_UART1),
130 #ifndef CONFIG_CPU_S3C2400
131 SAVE_UART(S3C24XX_VA_UART2),
137 * we send the debug to printascii() to allow it to be seen if the
138 * system never wakes up from the sleep
141 static void s3c2410_pm_debug_init(void)
143 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
145 /* re-start uart clocks */
146 tmp |= S3C2410_CLKCON_UART0;
147 tmp |= S3C2410_CLKCON_UART1;
148 tmp |= S3C2410_CLKCON_UART2;
150 __raw_writel(tmp, S3C2410_CLKCON);
155 #define s3c2410_pm_debug_init() do { } while(0)
157 static struct sleep_save uart_save[] = {};
160 /* s3c2410_pm_show_resume_irqs
162 * print any IRQs asserted at resume time (ie, we woke from)
165 static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
172 for (i = 0; i <= 31; i++) {
173 if ((which) & (1L<<i)) {
174 S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
179 /* s3c_pm_check_resume_pin
181 * check to see if the pin is configured correctly for sleep mode, and
182 * make any necessary adjustments if it is not
185 static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
187 unsigned long irqstate;
188 unsigned long pinstate;
189 int irq = s3c2410_gpio_getirq(pin);
192 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
194 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
196 pinstate = s3c2410_gpio_getcfg(pin);
199 if (pinstate == S3C2410_GPIO_IRQ)
200 S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
202 if (pinstate == S3C2410_GPIO_IRQ) {
203 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
204 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
209 /* s3c2410_pm_configure_extint
211 * configure all external interrupt pins
214 static void s3c2410_pm_configure_extint(void)
218 /* for each of the external interrupts (EINT0..EINT15) we
219 * need to check wether it is an external interrupt source,
220 * and then configure it as an input if it is not
223 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
224 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
227 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
228 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
232 /* offsets for CON/DAT/UP registers */
234 #define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
235 #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
236 #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
238 /* s3c2410_pm_save_gpios()
240 * Save the state of the GPIOs
243 static void s3c2410_pm_save_gpios(void)
245 struct gpio_sleep *gps = gpio_save;
248 for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
249 void __iomem *base = gps->base;
251 gps->gpcon = __raw_readl(base + OFFS_CON);
252 gps->gpdat = __raw_readl(base + OFFS_DAT);
255 gps->gpup = __raw_readl(base + OFFS_UP);
260 /* Test whether the given masked+shifted bits of an GPIO configuration
261 * are one of the SFN (special function) modes. */
263 static inline int is_sfn(unsigned long con)
265 return (con == 2 || con == 3);
268 /* Test if the given masked+shifted GPIO configuration is an input */
270 static inline int is_in(unsigned long con)
275 /* Test if the given masked+shifted GPIO configuration is an output */
277 static inline int is_out(unsigned long con)
282 /* s3c2410_pm_restore_gpio()
284 * Restore one of the GPIO banks that was saved during suspend. This is
285 * not as simple as once thought, due to the possibility of glitches
286 * from the order that the CON and DAT registers are set in.
288 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
289 * combinations of changes to check. Three of these, if the pin stays
290 * in the same configuration can be discounted. This leaves us with
293 * { IN => OUT } Change DAT first
294 * { IN => SFN } Change CON first
295 * { OUT => SFN } Change CON first, so new data will not glitch
296 * { OUT => IN } Change CON first, so new data will not glitch
297 * { SFN => IN } Change CON first
298 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
300 * We do not currently deal with the UP registers as these control
301 * weak resistors, so a small delay in change should not need to bring
302 * these into the calculations.
304 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
305 * state for when it is next output.
308 static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
310 void __iomem *base = gps->base;
311 unsigned long gps_gpcon = gps->gpcon;
312 unsigned long gps_gpdat = gps->gpdat;
313 unsigned long old_gpcon;
314 unsigned long old_gpdat;
315 unsigned long old_gpup = 0x0;
319 old_gpcon = __raw_readl(base + OFFS_CON);
320 old_gpdat = __raw_readl(base + OFFS_DAT);
322 if (base == S3C2410_GPACON) {
323 /* GPACON only has one bit per control / data and no PULLUPs.
324 * GPACON[x] = 0 => Output, 1 => SFN */
326 /* first set all SFN bits to SFN */
328 gpcon = old_gpcon | gps->gpcon;
329 __raw_writel(gpcon, base + OFFS_CON);
331 /* now set all the other bits */
333 __raw_writel(gps_gpdat, base + OFFS_DAT);
334 __raw_writel(gps_gpcon, base + OFFS_CON);
336 unsigned long old, new, mask;
337 unsigned long change_mask = 0x0;
339 old_gpup = __raw_readl(base + OFFS_UP);
341 /* Create a change_mask of all the items that need to have
342 * their CON value changed before their DAT value, so that
343 * we minimise the work between the two settings.
346 for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
347 old = (old_gpcon & mask) >> nr;
348 new = (gps_gpcon & mask) >> nr;
350 /* If there is no change, then skip */
355 /* If both are special function, then skip */
357 if (is_sfn(old) && is_sfn(new))
360 /* Change is IN => OUT, do not change now */
362 if (is_in(old) && is_out(new))
365 /* Change is SFN => OUT, do not change now */
367 if (is_sfn(old) && is_out(new))
370 /* We should now be at the case of IN=>SFN,
371 * OUT=>SFN, OUT=>IN, SFN=>IN. */
376 /* Write the new CON settings */
378 gpcon = old_gpcon & ~change_mask;
379 gpcon |= gps_gpcon & change_mask;
381 __raw_writel(gpcon, base + OFFS_CON);
383 /* Now change any items that require DAT,CON */
385 __raw_writel(gps_gpdat, base + OFFS_DAT);
386 __raw_writel(gps_gpcon, base + OFFS_CON);
387 __raw_writel(gps->gpup, base + OFFS_UP);
390 S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
391 index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
395 /** s3c2410_pm_restore_gpios()
397 * Restore the state of the GPIOs
400 static void s3c2410_pm_restore_gpios(void)
402 struct gpio_sleep *gps = gpio_save;
405 for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
406 s3c2410_pm_restore_gpio(gpio, gps);
410 void (*pm_cpu_prep)(void);
411 void (*pm_cpu_sleep)(void);
413 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
417 * central control for sleep/resume process
420 static int s3c2410_pm_enter(suspend_state_t state)
422 unsigned long regs_save[16];
424 /* ensure the debug is initialised (if enabled) */
426 s3c2410_pm_debug_init();
428 S3C_PMDBG("s3c2410_pm_enter(%d)\n", state);
430 if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
431 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
435 /* check if we have anything to wake-up with... bad things seem
436 * to happen if you suspend with no wakeup (system will often
437 * require a full power-cycle)
440 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
441 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
442 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
443 printk(KERN_ERR PFX "Aborting sleep\n");
447 /* prepare check area if configured */
449 s3c_pm_check_prepare();
451 /* store the physical address of the register recovery block */
453 s3c_sleep_save_phys = virt_to_phys(regs_save);
455 S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
457 /* save all necessary core registers not covered by the drivers */
459 s3c2410_pm_save_gpios();
460 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
461 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
462 s3c_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
464 /* set the irq configuration for wake */
466 s3c2410_pm_configure_extint();
468 S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
469 s3c_irqwake_intmask, s3c_irqwake_eintmask);
471 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
472 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
474 /* ack any outstanding external interrupts before we go to sleep */
476 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
477 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
478 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
480 /* call cpu specific preparation */
484 /* flush cache back to ram */
488 s3c_pm_check_store();
490 /* send the cpu to sleep... */
492 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
494 /* s3c2410_cpu_save will also act as our return point from when
495 * we resume as it saves its own register state, so use the return
496 * code to differentiate return from save and return from sleep */
498 if (s3c2410_cpu_save(regs_save) == 0) {
503 /* restore the cpu state */
507 /* restore the system state */
509 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
510 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
511 s3c_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
512 s3c2410_pm_restore_gpios();
514 s3c2410_pm_debug_init();
516 /* check what irq (if any) restored the system */
518 S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
519 __raw_readl(S3C2410_SRCPND),
520 __raw_readl(S3C2410_EINTPEND));
522 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
523 s3c_irqwake_intmask);
525 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
526 s3c_irqwake_eintmask);
528 S3C_PMDBG("post sleep, preparing to return\n");
530 s3c_pm_check_restore();
532 /* ok, let's return from sleep */
534 S3C_PMDBG("S3C2410 PM Resume (post-restore)\n");
538 static struct platform_suspend_ops s3c2410_pm_ops = {
539 .enter = s3c2410_pm_enter,
540 .valid = suspend_valid_only_mem,
545 * Attach the power management functions. This should be called
546 * from the board specific initialisation if the board supports
550 int __init s3c2410_pm_init(void)
552 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
554 suspend_set_ops(&s3c2410_pm_ops);