2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
45 #define DRV_NAME "sata_nv"
46 #define DRV_VERSION "2.0"
53 NV_PORT0_SCR_REG_OFFSET = 0x00,
54 NV_PORT1_SCR_REG_OFFSET = 0x40,
56 /* INT_STATUS/ENABLE */
59 NV_INT_STATUS_CK804 = 0x440,
60 NV_INT_ENABLE_CK804 = 0x441,
62 /* INT_STATUS/ENABLE bits */
66 NV_INT_REMOVED = 0x08,
68 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
71 NV_INT_MASK = NV_INT_DEV |
72 NV_INT_ADDED | NV_INT_REMOVED,
76 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
78 // For PCI config register 20
79 NV_MCP_SATA_CFG_20 = 0x50,
80 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
83 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void nv_ck804_host_stop(struct ata_host *host);
85 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
86 struct pt_regs *regs);
87 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
88 struct pt_regs *regs);
89 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
90 struct pt_regs *regs);
91 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
92 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
94 static void nv_nf2_freeze(struct ata_port *ap);
95 static void nv_nf2_thaw(struct ata_port *ap);
96 static void nv_ck804_freeze(struct ata_port *ap);
97 static void nv_ck804_thaw(struct ata_port *ap);
98 static void nv_error_handler(struct ata_port *ap);
104 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
108 static const struct pci_device_id nv_pci_tbl[] = {
109 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
110 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
111 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
112 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
113 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
114 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
115 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
116 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
117 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
118 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
119 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
120 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
121 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
122 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
123 { PCI_VDEVICE(NVIDIA, 0x045c), GENERIC },
124 { PCI_VDEVICE(NVIDIA, 0x045d), GENERIC },
125 { PCI_VDEVICE(NVIDIA, 0x045e), GENERIC },
126 { PCI_VDEVICE(NVIDIA, 0x045f), GENERIC },
127 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
128 PCI_ANY_ID, PCI_ANY_ID,
129 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
130 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
131 PCI_ANY_ID, PCI_ANY_ID,
132 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
133 { 0, } /* terminate list */
136 static struct pci_driver nv_pci_driver = {
138 .id_table = nv_pci_tbl,
139 .probe = nv_init_one,
140 .remove = ata_pci_remove_one,
143 static struct scsi_host_template nv_sht = {
144 .module = THIS_MODULE,
146 .ioctl = ata_scsi_ioctl,
147 .queuecommand = ata_scsi_queuecmd,
148 .can_queue = ATA_DEF_QUEUE,
149 .this_id = ATA_SHT_THIS_ID,
150 .sg_tablesize = LIBATA_MAX_PRD,
151 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
152 .emulated = ATA_SHT_EMULATED,
153 .use_clustering = ATA_SHT_USE_CLUSTERING,
154 .proc_name = DRV_NAME,
155 .dma_boundary = ATA_DMA_BOUNDARY,
156 .slave_configure = ata_scsi_slave_config,
157 .slave_destroy = ata_scsi_slave_destroy,
158 .bios_param = ata_std_bios_param,
161 static const struct ata_port_operations nv_generic_ops = {
162 .port_disable = ata_port_disable,
163 .tf_load = ata_tf_load,
164 .tf_read = ata_tf_read,
165 .exec_command = ata_exec_command,
166 .check_status = ata_check_status,
167 .dev_select = ata_std_dev_select,
168 .bmdma_setup = ata_bmdma_setup,
169 .bmdma_start = ata_bmdma_start,
170 .bmdma_stop = ata_bmdma_stop,
171 .bmdma_status = ata_bmdma_status,
172 .qc_prep = ata_qc_prep,
173 .qc_issue = ata_qc_issue_prot,
174 .freeze = ata_bmdma_freeze,
175 .thaw = ata_bmdma_thaw,
176 .error_handler = nv_error_handler,
177 .post_internal_cmd = ata_bmdma_post_internal_cmd,
178 .data_xfer = ata_pio_data_xfer,
179 .irq_handler = nv_generic_interrupt,
180 .irq_clear = ata_bmdma_irq_clear,
181 .scr_read = nv_scr_read,
182 .scr_write = nv_scr_write,
183 .port_start = ata_port_start,
184 .port_stop = ata_port_stop,
185 .host_stop = ata_pci_host_stop,
188 static const struct ata_port_operations nv_nf2_ops = {
189 .port_disable = ata_port_disable,
190 .tf_load = ata_tf_load,
191 .tf_read = ata_tf_read,
192 .exec_command = ata_exec_command,
193 .check_status = ata_check_status,
194 .dev_select = ata_std_dev_select,
195 .bmdma_setup = ata_bmdma_setup,
196 .bmdma_start = ata_bmdma_start,
197 .bmdma_stop = ata_bmdma_stop,
198 .bmdma_status = ata_bmdma_status,
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
201 .freeze = nv_nf2_freeze,
203 .error_handler = nv_error_handler,
204 .post_internal_cmd = ata_bmdma_post_internal_cmd,
205 .data_xfer = ata_pio_data_xfer,
206 .irq_handler = nv_nf2_interrupt,
207 .irq_clear = ata_bmdma_irq_clear,
208 .scr_read = nv_scr_read,
209 .scr_write = nv_scr_write,
210 .port_start = ata_port_start,
211 .port_stop = ata_port_stop,
212 .host_stop = ata_pci_host_stop,
215 static const struct ata_port_operations nv_ck804_ops = {
216 .port_disable = ata_port_disable,
217 .tf_load = ata_tf_load,
218 .tf_read = ata_tf_read,
219 .exec_command = ata_exec_command,
220 .check_status = ata_check_status,
221 .dev_select = ata_std_dev_select,
222 .bmdma_setup = ata_bmdma_setup,
223 .bmdma_start = ata_bmdma_start,
224 .bmdma_stop = ata_bmdma_stop,
225 .bmdma_status = ata_bmdma_status,
226 .qc_prep = ata_qc_prep,
227 .qc_issue = ata_qc_issue_prot,
228 .freeze = nv_ck804_freeze,
229 .thaw = nv_ck804_thaw,
230 .error_handler = nv_error_handler,
231 .post_internal_cmd = ata_bmdma_post_internal_cmd,
232 .data_xfer = ata_pio_data_xfer,
233 .irq_handler = nv_ck804_interrupt,
234 .irq_clear = ata_bmdma_irq_clear,
235 .scr_read = nv_scr_read,
236 .scr_write = nv_scr_write,
237 .port_start = ata_port_start,
238 .port_stop = ata_port_stop,
239 .host_stop = nv_ck804_host_stop,
242 static struct ata_port_info nv_port_info[] = {
246 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
247 .pio_mask = NV_PIO_MASK,
248 .mwdma_mask = NV_MWDMA_MASK,
249 .udma_mask = NV_UDMA_MASK,
250 .port_ops = &nv_generic_ops,
255 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
256 .pio_mask = NV_PIO_MASK,
257 .mwdma_mask = NV_MWDMA_MASK,
258 .udma_mask = NV_UDMA_MASK,
259 .port_ops = &nv_nf2_ops,
264 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
265 .pio_mask = NV_PIO_MASK,
266 .mwdma_mask = NV_MWDMA_MASK,
267 .udma_mask = NV_UDMA_MASK,
268 .port_ops = &nv_ck804_ops,
272 MODULE_AUTHOR("NVIDIA");
273 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
274 MODULE_LICENSE("GPL");
275 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
276 MODULE_VERSION(DRV_VERSION);
278 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
279 struct pt_regs *regs)
281 struct ata_host *host = dev_instance;
283 unsigned int handled = 0;
286 spin_lock_irqsave(&host->lock, flags);
288 for (i = 0; i < host->n_ports; i++) {
293 !(ap->flags & ATA_FLAG_DISABLED)) {
294 struct ata_queued_cmd *qc;
296 qc = ata_qc_from_tag(ap, ap->active_tag);
297 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
298 handled += ata_host_intr(ap, qc);
300 // No request pending? Clear interrupt status
301 // anyway, in case there's one pending.
302 ap->ops->check_status(ap);
307 spin_unlock_irqrestore(&host->lock, flags);
309 return IRQ_RETVAL(handled);
312 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
314 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
317 /* freeze if hotplugged */
318 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
323 /* bail out if not our interrupt */
324 if (!(irq_stat & NV_INT_DEV))
327 /* DEV interrupt w/ no active qc? */
328 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
329 ata_check_status(ap);
333 /* handle interrupt */
334 handled = ata_host_intr(ap, qc);
335 if (unlikely(!handled)) {
336 /* spurious, clear it */
337 ata_check_status(ap);
343 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
347 for (i = 0; i < host->n_ports; i++) {
348 struct ata_port *ap = host->ports[i];
350 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
351 handled += nv_host_intr(ap, irq_stat);
353 irq_stat >>= NV_INT_PORT_SHIFT;
356 return IRQ_RETVAL(handled);
359 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
360 struct pt_regs *regs)
362 struct ata_host *host = dev_instance;
366 spin_lock(&host->lock);
367 irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
368 ret = nv_do_interrupt(host, irq_stat);
369 spin_unlock(&host->lock);
374 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
375 struct pt_regs *regs)
377 struct ata_host *host = dev_instance;
381 spin_lock(&host->lock);
382 irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804);
383 ret = nv_do_interrupt(host, irq_stat);
384 spin_unlock(&host->lock);
389 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
391 if (sc_reg > SCR_CONTROL)
394 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
397 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
399 if (sc_reg > SCR_CONTROL)
402 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
405 static void nv_nf2_freeze(struct ata_port *ap)
407 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
408 int shift = ap->port_no * NV_INT_PORT_SHIFT;
411 mask = inb(scr_addr + NV_INT_ENABLE);
412 mask &= ~(NV_INT_ALL << shift);
413 outb(mask, scr_addr + NV_INT_ENABLE);
416 static void nv_nf2_thaw(struct ata_port *ap)
418 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
419 int shift = ap->port_no * NV_INT_PORT_SHIFT;
422 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
424 mask = inb(scr_addr + NV_INT_ENABLE);
425 mask |= (NV_INT_MASK << shift);
426 outb(mask, scr_addr + NV_INT_ENABLE);
429 static void nv_ck804_freeze(struct ata_port *ap)
431 void __iomem *mmio_base = ap->host->mmio_base;
432 int shift = ap->port_no * NV_INT_PORT_SHIFT;
435 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
436 mask &= ~(NV_INT_ALL << shift);
437 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
440 static void nv_ck804_thaw(struct ata_port *ap)
442 void __iomem *mmio_base = ap->host->mmio_base;
443 int shift = ap->port_no * NV_INT_PORT_SHIFT;
446 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
448 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
449 mask |= (NV_INT_MASK << shift);
450 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
453 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
457 /* SATA hardreset fails to retrieve proper device signature on
458 * some controllers. Don't classify on hardreset. For more
459 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
461 return sata_std_hardreset(ap, &dummy);
464 static void nv_error_handler(struct ata_port *ap)
466 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
467 nv_hardreset, ata_std_postreset);
470 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
472 static int printed_version = 0;
473 struct ata_port_info *ppi[2];
474 struct ata_probe_ent *probe_ent;
475 int pci_dev_busy = 0;
480 // Make sure this is a SATA controller by counting the number of bars
481 // (NVIDIA SATA controllers will always have six bars). Otherwise,
482 // it's an IDE controller and we ignore it.
483 for (bar=0; bar<6; bar++)
484 if (pci_resource_start(pdev, bar) == 0)
487 if (!printed_version++)
488 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
490 rc = pci_enable_device(pdev);
494 rc = pci_request_regions(pdev, DRV_NAME);
497 goto err_out_disable;
500 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
502 goto err_out_regions;
503 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
505 goto err_out_regions;
509 ppi[0] = ppi[1] = &nv_port_info[ent->driver_data];
510 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
512 goto err_out_regions;
514 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
515 if (!probe_ent->mmio_base) {
517 goto err_out_free_ent;
520 base = (unsigned long)probe_ent->mmio_base;
522 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
523 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
525 /* enable SATA space for CK804 */
526 if (ent->driver_data == CK804) {
529 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
530 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
531 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
534 pci_set_master(pdev);
536 rc = ata_device_add(probe_ent);
538 goto err_out_iounmap;
545 pci_iounmap(pdev, probe_ent->mmio_base);
549 pci_release_regions(pdev);
552 pci_disable_device(pdev);
557 static void nv_ck804_host_stop(struct ata_host *host)
559 struct pci_dev *pdev = to_pci_dev(host->dev);
562 /* disable SATA space for CK804 */
563 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
564 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
565 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
567 ata_pci_host_stop(host);
570 static int __init nv_init(void)
572 return pci_register_driver(&nv_pci_driver);
575 static void __exit nv_exit(void)
577 pci_unregister_driver(&nv_pci_driver);
580 module_init(nv_init);
581 module_exit(nv_exit);