Merge branch 'linus' into sched/devel
[linux-2.6] / drivers / mmc / host / pxamci.c
1 /*
2  *  linux/drivers/mmc/host/pxa.c - PXA MMCI driver
3  *
4  *  Copyright (C) 2003 Russell King, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  *  This hardware is really sick:
11  *   - No way to clear interrupts.
12  *   - Have to turn off the clock whenever we touch the device.
13  *   - Doesn't tell you how many data blocks were transferred.
14  *  Yuck!
15  *
16  *      1 and 3 byte data transfers not supported
17  *      max block length up to 1023
18  */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/mmc/host.h>
29
30 #include <asm/dma.h>
31 #include <asm/io.h>
32 #include <asm/sizes.h>
33
34 #include <asm/arch/pxa-regs.h>
35 #include <asm/arch/mmc.h>
36
37 #include "pxamci.h"
38
39 #define DRIVER_NAME     "pxa2xx-mci"
40
41 #define NR_SG   1
42 #define CLKRT_OFF       (~0)
43
44 struct pxamci_host {
45         struct mmc_host         *mmc;
46         spinlock_t              lock;
47         struct resource         *res;
48         void __iomem            *base;
49         struct clk              *clk;
50         unsigned long           clkrate;
51         int                     irq;
52         int                     dma;
53         unsigned int            clkrt;
54         unsigned int            cmdat;
55         unsigned int            imask;
56         unsigned int            power_mode;
57         struct pxamci_platform_data *pdata;
58
59         struct mmc_request      *mrq;
60         struct mmc_command      *cmd;
61         struct mmc_data         *data;
62
63         dma_addr_t              sg_dma;
64         struct pxa_dma_desc     *sg_cpu;
65         unsigned int            dma_len;
66
67         unsigned int            dma_dir;
68         unsigned int            dma_drcmrrx;
69         unsigned int            dma_drcmrtx;
70 };
71
72 static void pxamci_stop_clock(struct pxamci_host *host)
73 {
74         if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
75                 unsigned long timeout = 10000;
76                 unsigned int v;
77
78                 writel(STOP_CLOCK, host->base + MMC_STRPCL);
79
80                 do {
81                         v = readl(host->base + MMC_STAT);
82                         if (!(v & STAT_CLK_EN))
83                                 break;
84                         udelay(1);
85                 } while (timeout--);
86
87                 if (v & STAT_CLK_EN)
88                         dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
89         }
90 }
91
92 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
93 {
94         unsigned long flags;
95
96         spin_lock_irqsave(&host->lock, flags);
97         host->imask &= ~mask;
98         writel(host->imask, host->base + MMC_I_MASK);
99         spin_unlock_irqrestore(&host->lock, flags);
100 }
101
102 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
103 {
104         unsigned long flags;
105
106         spin_lock_irqsave(&host->lock, flags);
107         host->imask |= mask;
108         writel(host->imask, host->base + MMC_I_MASK);
109         spin_unlock_irqrestore(&host->lock, flags);
110 }
111
112 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
113 {
114         unsigned int nob = data->blocks;
115         unsigned long long clks;
116         unsigned int timeout;
117         bool dalgn = 0;
118         u32 dcmd;
119         int i;
120
121         host->data = data;
122
123         if (data->flags & MMC_DATA_STREAM)
124                 nob = 0xffff;
125
126         writel(nob, host->base + MMC_NOB);
127         writel(data->blksz, host->base + MMC_BLKLEN);
128
129         clks = (unsigned long long)data->timeout_ns * host->clkrate;
130         do_div(clks, 1000000000UL);
131         timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
132         writel((timeout + 255) / 256, host->base + MMC_RDTO);
133
134         if (data->flags & MMC_DATA_READ) {
135                 host->dma_dir = DMA_FROM_DEVICE;
136                 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
137                 DRCMR(host->dma_drcmrtx) = 0;
138                 DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD;
139         } else {
140                 host->dma_dir = DMA_TO_DEVICE;
141                 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
142                 DRCMR(host->dma_drcmrrx) = 0;
143                 DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD;
144         }
145
146         dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
147
148         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
149                                    host->dma_dir);
150
151         for (i = 0; i < host->dma_len; i++) {
152                 unsigned int length = sg_dma_len(&data->sg[i]);
153                 host->sg_cpu[i].dcmd = dcmd | length;
154                 if (length & 31 && !(data->flags & MMC_DATA_READ))
155                         host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
156                 /* Not aligned to 8-byte boundary? */
157                 if (sg_dma_address(&data->sg[i]) & 0x7)
158                         dalgn = 1;
159                 if (data->flags & MMC_DATA_READ) {
160                         host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
161                         host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
162                 } else {
163                         host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
164                         host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
165                 }
166                 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
167                                         sizeof(struct pxa_dma_desc);
168         }
169         host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
170         wmb();
171
172         /*
173          * The PXA27x DMA controller encounters overhead when working with
174          * unaligned (to 8-byte boundaries) data, so switch on byte alignment
175          * mode only if we have unaligned data.
176          */
177         if (dalgn)
178                 DALGN |= (1 << host->dma);
179         else
180                 DALGN &= (1 << host->dma);
181         DDADR(host->dma) = host->sg_dma;
182         DCSR(host->dma) = DCSR_RUN;
183 }
184
185 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
186 {
187         WARN_ON(host->cmd != NULL);
188         host->cmd = cmd;
189
190         if (cmd->flags & MMC_RSP_BUSY)
191                 cmdat |= CMDAT_BUSY;
192
193 #define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
194         switch (RSP_TYPE(mmc_resp_type(cmd))) {
195         case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
196                 cmdat |= CMDAT_RESP_SHORT;
197                 break;
198         case RSP_TYPE(MMC_RSP_R3):
199                 cmdat |= CMDAT_RESP_R3;
200                 break;
201         case RSP_TYPE(MMC_RSP_R2):
202                 cmdat |= CMDAT_RESP_R2;
203                 break;
204         default:
205                 break;
206         }
207
208         writel(cmd->opcode, host->base + MMC_CMD);
209         writel(cmd->arg >> 16, host->base + MMC_ARGH);
210         writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
211         writel(cmdat, host->base + MMC_CMDAT);
212         writel(host->clkrt, host->base + MMC_CLKRT);
213
214         writel(START_CLOCK, host->base + MMC_STRPCL);
215
216         pxamci_enable_irq(host, END_CMD_RES);
217 }
218
219 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
220 {
221         host->mrq = NULL;
222         host->cmd = NULL;
223         host->data = NULL;
224         mmc_request_done(host->mmc, mrq);
225 }
226
227 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
228 {
229         struct mmc_command *cmd = host->cmd;
230         int i;
231         u32 v;
232
233         if (!cmd)
234                 return 0;
235
236         host->cmd = NULL;
237
238         /*
239          * Did I mention this is Sick.  We always need to
240          * discard the upper 8 bits of the first 16-bit word.
241          */
242         v = readl(host->base + MMC_RES) & 0xffff;
243         for (i = 0; i < 4; i++) {
244                 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
245                 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
246                 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
247                 v = w2;
248         }
249
250         if (stat & STAT_TIME_OUT_RESPONSE) {
251                 cmd->error = -ETIMEDOUT;
252         } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
253 #ifdef CONFIG_PXA27x
254                 /*
255                  * workaround for erratum #42:
256                  * Intel PXA27x Family Processor Specification Update Rev 001
257                  * A bogus CRC error can appear if the msb of a 136 bit
258                  * response is a one.
259                  */
260                 if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {
261                         pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
262                 } else
263 #endif
264                 cmd->error = -EILSEQ;
265         }
266
267         pxamci_disable_irq(host, END_CMD_RES);
268         if (host->data && !cmd->error) {
269                 pxamci_enable_irq(host, DATA_TRAN_DONE);
270         } else {
271                 pxamci_finish_request(host, host->mrq);
272         }
273
274         return 1;
275 }
276
277 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
278 {
279         struct mmc_data *data = host->data;
280
281         if (!data)
282                 return 0;
283
284         DCSR(host->dma) = 0;
285         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
286                      host->dma_dir);
287
288         if (stat & STAT_READ_TIME_OUT)
289                 data->error = -ETIMEDOUT;
290         else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
291                 data->error = -EILSEQ;
292
293         /*
294          * There appears to be a hardware design bug here.  There seems to
295          * be no way to find out how much data was transferred to the card.
296          * This means that if there was an error on any block, we mark all
297          * data blocks as being in error.
298          */
299         if (!data->error)
300                 data->bytes_xfered = data->blocks * data->blksz;
301         else
302                 data->bytes_xfered = 0;
303
304         pxamci_disable_irq(host, DATA_TRAN_DONE);
305
306         host->data = NULL;
307         if (host->mrq->stop) {
308                 pxamci_stop_clock(host);
309                 pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
310         } else {
311                 pxamci_finish_request(host, host->mrq);
312         }
313
314         return 1;
315 }
316
317 static irqreturn_t pxamci_irq(int irq, void *devid)
318 {
319         struct pxamci_host *host = devid;
320         unsigned int ireg;
321         int handled = 0;
322
323         ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
324
325         if (ireg) {
326                 unsigned stat = readl(host->base + MMC_STAT);
327
328                 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
329
330                 if (ireg & END_CMD_RES)
331                         handled |= pxamci_cmd_done(host, stat);
332                 if (ireg & DATA_TRAN_DONE)
333                         handled |= pxamci_data_done(host, stat);
334                 if (ireg & SDIO_INT) {
335                         mmc_signal_sdio_irq(host->mmc);
336                         handled = 1;
337                 }
338         }
339
340         return IRQ_RETVAL(handled);
341 }
342
343 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
344 {
345         struct pxamci_host *host = mmc_priv(mmc);
346         unsigned int cmdat;
347
348         WARN_ON(host->mrq != NULL);
349
350         host->mrq = mrq;
351
352         pxamci_stop_clock(host);
353
354         cmdat = host->cmdat;
355         host->cmdat &= ~CMDAT_INIT;
356
357         if (mrq->data) {
358                 pxamci_setup_data(host, mrq->data);
359
360                 cmdat &= ~CMDAT_BUSY;
361                 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
362                 if (mrq->data->flags & MMC_DATA_WRITE)
363                         cmdat |= CMDAT_WRITE;
364
365                 if (mrq->data->flags & MMC_DATA_STREAM)
366                         cmdat |= CMDAT_STREAM;
367         }
368
369         pxamci_start_cmd(host, mrq->cmd, cmdat);
370 }
371
372 static int pxamci_get_ro(struct mmc_host *mmc)
373 {
374         struct pxamci_host *host = mmc_priv(mmc);
375
376         if (host->pdata && host->pdata->get_ro)
377                 return host->pdata->get_ro(mmc_dev(mmc));
378         /* Host doesn't support read only detection so assume writeable */
379         return 0;
380 }
381
382 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
383 {
384         struct pxamci_host *host = mmc_priv(mmc);
385
386         if (ios->clock) {
387                 unsigned long rate = host->clkrate;
388                 unsigned int clk = rate / ios->clock;
389
390                 if (host->clkrt == CLKRT_OFF)
391                         clk_enable(host->clk);
392
393                 if (ios->clock == 26000000) {
394                         /* to support 26MHz on pxa300/pxa310 */
395                         host->clkrt = 7;
396                 } else {
397                         /* to handle (19.5MHz, 26MHz) */
398                         if (!clk)
399                                 clk = 1;
400
401                         /*
402                          * clk might result in a lower divisor than we
403                          * desire.  check for that condition and adjust
404                          * as appropriate.
405                          */
406                         if (rate / clk > ios->clock)
407                                 clk <<= 1;
408                         host->clkrt = fls(clk) - 1;
409                 }
410
411                 /*
412                  * we write clkrt on the next command
413                  */
414         } else {
415                 pxamci_stop_clock(host);
416                 if (host->clkrt != CLKRT_OFF) {
417                         host->clkrt = CLKRT_OFF;
418                         clk_disable(host->clk);
419                 }
420         }
421
422         if (host->power_mode != ios->power_mode) {
423                 host->power_mode = ios->power_mode;
424
425                 if (host->pdata && host->pdata->setpower)
426                         host->pdata->setpower(mmc_dev(mmc), ios->vdd);
427
428                 if (ios->power_mode == MMC_POWER_ON)
429                         host->cmdat |= CMDAT_INIT;
430         }
431
432         if (ios->bus_width == MMC_BUS_WIDTH_4)
433                 host->cmdat |= CMDAT_SD_4DAT;
434         else
435                 host->cmdat &= ~CMDAT_SD_4DAT;
436
437         pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
438                  host->clkrt, host->cmdat);
439 }
440
441 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
442 {
443         struct pxamci_host *pxa_host = mmc_priv(host);
444
445         if (enable)
446                 pxamci_enable_irq(pxa_host, SDIO_INT);
447         else
448                 pxamci_disable_irq(pxa_host, SDIO_INT);
449 }
450
451 static const struct mmc_host_ops pxamci_ops = {
452         .request                = pxamci_request,
453         .get_ro                 = pxamci_get_ro,
454         .set_ios                = pxamci_set_ios,
455         .enable_sdio_irq        = pxamci_enable_sdio_irq,
456 };
457
458 static void pxamci_dma_irq(int dma, void *devid)
459 {
460         struct pxamci_host *host = devid;
461         int dcsr = DCSR(dma);
462         DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;
463
464         if (dcsr & DCSR_ENDINTR) {
465                 writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
466         } else {
467                 printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",
468                        mmc_hostname(host->mmc), dma, dcsr);
469                 host->data->error = -EIO;
470                 pxamci_data_done(host, 0);
471         }
472 }
473
474 static irqreturn_t pxamci_detect_irq(int irq, void *devid)
475 {
476         struct pxamci_host *host = mmc_priv(devid);
477
478         mmc_detect_change(devid, host->pdata->detect_delay);
479         return IRQ_HANDLED;
480 }
481
482 static int pxamci_probe(struct platform_device *pdev)
483 {
484         struct mmc_host *mmc;
485         struct pxamci_host *host = NULL;
486         struct resource *r, *dmarx, *dmatx;
487         int ret, irq;
488
489         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
490         irq = platform_get_irq(pdev, 0);
491         if (!r || irq < 0)
492                 return -ENXIO;
493
494         r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
495         if (!r)
496                 return -EBUSY;
497
498         mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
499         if (!mmc) {
500                 ret = -ENOMEM;
501                 goto out;
502         }
503
504         mmc->ops = &pxamci_ops;
505
506         /*
507          * We can do SG-DMA, but we don't because we never know how much
508          * data we successfully wrote to the card.
509          */
510         mmc->max_phys_segs = NR_SG;
511
512         /*
513          * Our hardware DMA can handle a maximum of one page per SG entry.
514          */
515         mmc->max_seg_size = PAGE_SIZE;
516
517         /*
518          * Block length register is only 10 bits before PXA27x.
519          */
520         mmc->max_blk_size = (cpu_is_pxa21x() || cpu_is_pxa25x()) ? 1023 : 2048;
521
522         /*
523          * Block count register is 16 bits.
524          */
525         mmc->max_blk_count = 65535;
526
527         host = mmc_priv(mmc);
528         host->mmc = mmc;
529         host->dma = -1;
530         host->pdata = pdev->dev.platform_data;
531         host->clkrt = CLKRT_OFF;
532
533         host->clk = clk_get(&pdev->dev, "MMCCLK");
534         if (IS_ERR(host->clk)) {
535                 ret = PTR_ERR(host->clk);
536                 host->clk = NULL;
537                 goto out;
538         }
539
540         host->clkrate = clk_get_rate(host->clk);
541
542         /*
543          * Calculate minimum clock rate, rounding up.
544          */
545         mmc->f_min = (host->clkrate + 63) / 64;
546         mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000
547                                                           : host->clkrate;
548
549         mmc->ocr_avail = host->pdata ?
550                          host->pdata->ocr_mask :
551                          MMC_VDD_32_33|MMC_VDD_33_34;
552         mmc->caps = 0;
553         host->cmdat = 0;
554         if (!cpu_is_pxa21x() && !cpu_is_pxa25x()) {
555                 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
556                 host->cmdat |= CMDAT_SDIO_INT_EN;
557                 if (cpu_is_pxa300() || cpu_is_pxa310())
558                         mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
559                                      MMC_CAP_SD_HIGHSPEED;
560         }
561
562         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
563         if (!host->sg_cpu) {
564                 ret = -ENOMEM;
565                 goto out;
566         }
567
568         spin_lock_init(&host->lock);
569         host->res = r;
570         host->irq = irq;
571         host->imask = MMC_I_MASK_ALL;
572
573         host->base = ioremap(r->start, SZ_4K);
574         if (!host->base) {
575                 ret = -ENOMEM;
576                 goto out;
577         }
578
579         /*
580          * Ensure that the host controller is shut down, and setup
581          * with our defaults.
582          */
583         pxamci_stop_clock(host);
584         writel(0, host->base + MMC_SPI);
585         writel(64, host->base + MMC_RESTO);
586         writel(host->imask, host->base + MMC_I_MASK);
587
588         host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
589                                     pxamci_dma_irq, host);
590         if (host->dma < 0) {
591                 ret = -EBUSY;
592                 goto out;
593         }
594
595         ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
596         if (ret)
597                 goto out;
598
599         platform_set_drvdata(pdev, mmc);
600
601         dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
602         if (!dmarx) {
603                 ret = -ENXIO;
604                 goto out;
605         }
606         host->dma_drcmrrx = dmarx->start;
607
608         dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
609         if (!dmatx) {
610                 ret = -ENXIO;
611                 goto out;
612         }
613         host->dma_drcmrtx = dmatx->start;
614
615         if (host->pdata && host->pdata->init)
616                 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
617
618         mmc_add_host(mmc);
619
620         return 0;
621
622  out:
623         if (host) {
624                 if (host->dma >= 0)
625                         pxa_free_dma(host->dma);
626                 if (host->base)
627                         iounmap(host->base);
628                 if (host->sg_cpu)
629                         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
630                 if (host->clk)
631                         clk_put(host->clk);
632         }
633         if (mmc)
634                 mmc_free_host(mmc);
635         release_resource(r);
636         return ret;
637 }
638
639 static int pxamci_remove(struct platform_device *pdev)
640 {
641         struct mmc_host *mmc = platform_get_drvdata(pdev);
642
643         platform_set_drvdata(pdev, NULL);
644
645         if (mmc) {
646                 struct pxamci_host *host = mmc_priv(mmc);
647
648                 if (host->pdata && host->pdata->exit)
649                         host->pdata->exit(&pdev->dev, mmc);
650
651                 mmc_remove_host(mmc);
652
653                 pxamci_stop_clock(host);
654                 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
655                        END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
656                        host->base + MMC_I_MASK);
657
658                 DRCMR(host->dma_drcmrrx) = 0;
659                 DRCMR(host->dma_drcmrtx) = 0;
660
661                 free_irq(host->irq, host);
662                 pxa_free_dma(host->dma);
663                 iounmap(host->base);
664                 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
665
666                 clk_put(host->clk);
667
668                 release_resource(host->res);
669
670                 mmc_free_host(mmc);
671         }
672         return 0;
673 }
674
675 #ifdef CONFIG_PM
676 static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
677 {
678         struct mmc_host *mmc = platform_get_drvdata(dev);
679         int ret = 0;
680
681         if (mmc)
682                 ret = mmc_suspend_host(mmc, state);
683
684         return ret;
685 }
686
687 static int pxamci_resume(struct platform_device *dev)
688 {
689         struct mmc_host *mmc = platform_get_drvdata(dev);
690         int ret = 0;
691
692         if (mmc)
693                 ret = mmc_resume_host(mmc);
694
695         return ret;
696 }
697 #else
698 #define pxamci_suspend  NULL
699 #define pxamci_resume   NULL
700 #endif
701
702 static struct platform_driver pxamci_driver = {
703         .probe          = pxamci_probe,
704         .remove         = pxamci_remove,
705         .suspend        = pxamci_suspend,
706         .resume         = pxamci_resume,
707         .driver         = {
708                 .name   = DRIVER_NAME,
709                 .owner  = THIS_MODULE,
710         },
711 };
712
713 static int __init pxamci_init(void)
714 {
715         return platform_driver_register(&pxamci_driver);
716 }
717
718 static void __exit pxamci_exit(void)
719 {
720         platform_driver_unregister(&pxamci_driver);
721 }
722
723 module_init(pxamci_init);
724 module_exit(pxamci_exit);
725
726 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
727 MODULE_LICENSE("GPL");
728 MODULE_ALIAS("platform:pxa2xx-mci");