git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *
   3  *              Linux MegaRAID driver for SAS based RAID controllers
   4  *
   5  * Copyright (c) 2003-2005  LSI Corporation.
   6  *
   7  *              This program is free software; you can redistribute it and/or
   8  *              modify it under the terms of the GNU General Public License
   9  *              as published by the Free Software Foundation; either version
  10  *              2 of the License, or (at your option) any later version.
  11  *
  12  * FILE         : megaraid_sas.h
  13  */
  14
  15 #ifndef LSI_MEGARAID_SAS_H
  16 #define LSI_MEGARAID_SAS_H
  17
  18 /*
  19  * MegaRAID SAS Driver meta data
  20  */
  21 #define MEGASAS_VERSION                         "00.00.04.01"
  22 #define MEGASAS_RELDATE                         "July 24, 2008"
  23 #define MEGASAS_EXT_VERSION                     "Thu July 24 11:41:51 PST 2008"
  24
  25 /*
  26  * Device IDs
  27  */
  28 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  29 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  30 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  31 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  32 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  33
  34 /*
  35  * =====================================
  36  * MegaRAID SAS MFI firmware definitions
  37  * =====================================
  38  */
  39
  40 /*
  41  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
  42  * protocol between the software and firmware. Commands are issued using
  43  * "message frames"
  44  */
  45
  46 /*
  47  * FW posts its state in upper 4 bits of outbound_msg_0 register
  48  */
  49 #define MFI_STATE_MASK                          0xF0000000
  50 #define MFI_STATE_UNDEFINED                     0x00000000
  51 #define MFI_STATE_BB_INIT                       0x10000000
  52 #define MFI_STATE_FW_INIT                       0x40000000
  53 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
  54 #define MFI_STATE_FW_INIT_2                     0x70000000
  55 #define MFI_STATE_DEVICE_SCAN                   0x80000000
  56 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
  57 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
  58 #define MFI_STATE_READY                         0xB0000000
  59 #define MFI_STATE_OPERATIONAL                   0xC0000000
  60 #define MFI_STATE_FAULT                         0xF0000000
  61
  62 #define MEGAMFI_FRAME_SIZE                      64
  63
  64 /*
  65  * During FW init, clear pending cmds & reset state using inbound_msg_0
  66  *
  67  * ABORT        : Abort all pending cmds
  68  * READY        : Move from OPERATIONAL to READY state; discard queue info
  69  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
  70  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
  71  * HOTPLUG      : Resume from Hotplug
  72  * MFI_STOP_ADP : Send signal to FW to stop processing
  73  */
  74 #define MFI_INIT_ABORT                          0x00000001
  75 #define MFI_INIT_READY                          0x00000002
  76 #define MFI_INIT_MFIMODE                        0x00000004
  77 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
  78 #define MFI_INIT_HOTPLUG                        0x00000010
  79 #define MFI_STOP_ADP                            0x00000020
  80 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
  81                                                 MFI_INIT_MFIMODE| \
  82                                                 MFI_INIT_ABORT
  83
  84 /*
  85  * MFI frame flags
  86  */
  87 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
  88 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
  89 #define MFI_FRAME_SGL32                         0x0000
  90 #define MFI_FRAME_SGL64                         0x0002
  91 #define MFI_FRAME_SENSE32                       0x0000
  92 #define MFI_FRAME_SENSE64                       0x0004
  93 #define MFI_FRAME_DIR_NONE                      0x0000
  94 #define MFI_FRAME_DIR_WRITE                     0x0008
  95 #define MFI_FRAME_DIR_READ                      0x0010
  96 #define MFI_FRAME_DIR_BOTH                      0x0018
  97
  98 /*
  99  * Definition for cmd_status
 100  */
 101 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 102
 103 /*
 104  * MFI command opcodes
 105  */
 106 #define MFI_CMD_INIT                            0x00
 107 #define MFI_CMD_LD_READ                         0x01
 108 #define MFI_CMD_LD_WRITE                        0x02
 109 #define MFI_CMD_LD_SCSI_IO                      0x03
 110 #define MFI_CMD_PD_SCSI_IO                      0x04
 111 #define MFI_CMD_DCMD                            0x05
 112 #define MFI_CMD_ABORT                           0x06
 113 #define MFI_CMD_SMP                             0x07
 114 #define MFI_CMD_STP                             0x08
 115
 116 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 117
 118 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 119 #define MR_FLUSH_CTRL_CACHE                     0x01
 120 #define MR_FLUSH_DISK_CACHE                     0x02
 121
 122 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 123 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 124 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 125
 126 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 127 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 128 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 129 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 130
 131 #define MR_DCMD_CLUSTER                         0x08000000
 132 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 133 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 134
 135 /*
 136  * MFI command completion codes
 137  */
 138 enum MFI_STAT {
 139         MFI_STAT_OK = 0x00,
 140         MFI_STAT_INVALID_CMD = 0x01,
 141         MFI_STAT_INVALID_DCMD = 0x02,
 142         MFI_STAT_INVALID_PARAMETER = 0x03,
 143         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 144         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 145         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 146         MFI_STAT_APP_IN_USE = 0x07,
 147         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 148         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 149         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 150         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 151         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 152         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 153         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 154         MFI_STAT_FLASH_BUSY = 0x0f,
 155         MFI_STAT_FLASH_ERROR = 0x10,
 156         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 157         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 158         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 159         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 160         MFI_STAT_FLUSH_FAILED = 0x15,
 161         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 162         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 163         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 164         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 165         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 166         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 167         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 168         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 169         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 170         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 171         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 172         MFI_STAT_MFC_HW_ERROR = 0x21,
 173         MFI_STAT_NO_HW_PRESENT = 0x22,
 174         MFI_STAT_NOT_FOUND = 0x23,
 175         MFI_STAT_NOT_IN_ENCL = 0x24,
 176         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 177         MFI_STAT_PD_TYPE_WRONG = 0x26,
 178         MFI_STAT_PR_DISABLED = 0x27,
 179         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 180         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 181         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 182         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 183         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 184         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 185         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 186         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 187         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 188         MFI_STAT_TIME_NOT_SET = 0x31,
 189         MFI_STAT_WRONG_STATE = 0x32,
 190         MFI_STAT_LD_OFFLINE = 0x33,
 191         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 192         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 193         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 194         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 195         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 196
 197         MFI_STAT_INVALID_STATUS = 0xFF
 198 };
 199
 200 /*
 201  * Number of mailbox bytes in DCMD message frame
 202  */
 203 #define MFI_MBOX_SIZE                           12
 204
 205 enum MR_EVT_CLASS {
 206
 207         MR_EVT_CLASS_DEBUG = -2,
 208         MR_EVT_CLASS_PROGRESS = -1,
 209         MR_EVT_CLASS_INFO = 0,
 210         MR_EVT_CLASS_WARNING = 1,
 211         MR_EVT_CLASS_CRITICAL = 2,
 212         MR_EVT_CLASS_FATAL = 3,
 213         MR_EVT_CLASS_DEAD = 4,
 214
 215 };
 216
 217 enum MR_EVT_LOCALE {
 218
 219         MR_EVT_LOCALE_LD = 0x0001,
 220         MR_EVT_LOCALE_PD = 0x0002,
 221         MR_EVT_LOCALE_ENCL = 0x0004,
 222         MR_EVT_LOCALE_BBU = 0x0008,
 223         MR_EVT_LOCALE_SAS = 0x0010,
 224         MR_EVT_LOCALE_CTRL = 0x0020,
 225         MR_EVT_LOCALE_CONFIG = 0x0040,
 226         MR_EVT_LOCALE_CLUSTER = 0x0080,
 227         MR_EVT_LOCALE_ALL = 0xffff,
 228
 229 };
 230
 231 enum MR_EVT_ARGS {
 232
 233         MR_EVT_ARGS_NONE,
 234         MR_EVT_ARGS_CDB_SENSE,
 235         MR_EVT_ARGS_LD,
 236         MR_EVT_ARGS_LD_COUNT,
 237         MR_EVT_ARGS_LD_LBA,
 238         MR_EVT_ARGS_LD_OWNER,
 239         MR_EVT_ARGS_LD_LBA_PD_LBA,
 240         MR_EVT_ARGS_LD_PROG,
 241         MR_EVT_ARGS_LD_STATE,
 242         MR_EVT_ARGS_LD_STRIP,
 243         MR_EVT_ARGS_PD,
 244         MR_EVT_ARGS_PD_ERR,
 245         MR_EVT_ARGS_PD_LBA,
 246         MR_EVT_ARGS_PD_LBA_LD,
 247         MR_EVT_ARGS_PD_PROG,
 248         MR_EVT_ARGS_PD_STATE,
 249         MR_EVT_ARGS_PCI,
 250         MR_EVT_ARGS_RATE,
 251         MR_EVT_ARGS_STR,
 252         MR_EVT_ARGS_TIME,
 253         MR_EVT_ARGS_ECC,
 254
 255 };
 256
 257 /*
 258  * SAS controller properties
 259  */
 260 struct megasas_ctrl_prop {
 261
 262         u16 seq_num;
 263         u16 pred_fail_poll_interval;
 264         u16 intr_throttle_count;
 265         u16 intr_throttle_timeouts;
 266         u8 rebuild_rate;
 267         u8 patrol_read_rate;
 268         u8 bgi_rate;
 269         u8 cc_rate;
 270         u8 recon_rate;
 271         u8 cache_flush_interval;
 272         u8 spinup_drv_count;
 273         u8 spinup_delay;
 274         u8 cluster_enable;
 275         u8 coercion_mode;
 276         u8 alarm_enable;
 277         u8 disable_auto_rebuild;
 278         u8 disable_battery_warn;
 279         u8 ecc_bucket_size;
 280         u16 ecc_bucket_leak_rate;
 281         u8 restore_hotspare_on_insertion;
 282         u8 expose_encl_devices;
 283         u8 reserved[38];
 284
 285 } __attribute__ ((packed));
 286
 287 /*
 288  * SAS controller information
 289  */
 290 struct megasas_ctrl_info {
 291
 292         /*
 293          * PCI device information
 294          */
 295         struct {
 296
 297                 u16 vendor_id;
 298                 u16 device_id;
 299                 u16 sub_vendor_id;
 300                 u16 sub_device_id;
 301                 u8 reserved[24];
 302
 303         } __attribute__ ((packed)) pci;
 304
 305         /*
 306          * Host interface information
 307          */
 308         struct {
 309
 310                 u8 PCIX:1;
 311                 u8 PCIE:1;
 312                 u8 iSCSI:1;
 313                 u8 SAS_3G:1;
 314                 u8 reserved_0:4;
 315                 u8 reserved_1[6];
 316                 u8 port_count;
 317                 u64 port_addr[8];
 318
 319         } __attribute__ ((packed)) host_interface;
 320
 321         /*
 322          * Device (backend) interface information
 323          */
 324         struct {
 325
 326                 u8 SPI:1;
 327                 u8 SAS_3G:1;
 328                 u8 SATA_1_5G:1;
 329                 u8 SATA_3G:1;
 330                 u8 reserved_0:4;
 331                 u8 reserved_1[6];
 332                 u8 port_count;
 333                 u64 port_addr[8];
 334
 335         } __attribute__ ((packed)) device_interface;
 336
 337         /*
 338          * List of components residing in flash. All str are null terminated
 339          */
 340         u32 image_check_word;
 341         u32 image_component_count;
 342
 343         struct {
 344
 345                 char name[8];
 346                 char version[32];
 347                 char build_date[16];
 348                 char built_time[16];
 349
 350         } __attribute__ ((packed)) image_component[8];
 351
 352         /*
 353          * List of flash components that have been flashed on the card, but
 354          * are not in use, pending reset of the adapter. This list will be
 355          * empty if a flash operation has not occurred. All stings are null
 356          * terminated
 357          */
 358         u32 pending_image_component_count;
 359
 360         struct {
 361
 362                 char name[8];
 363                 char version[32];
 364                 char build_date[16];
 365                 char build_time[16];
 366
 367         } __attribute__ ((packed)) pending_image_component[8];
 368
 369         u8 max_arms;
 370         u8 max_spans;
 371         u8 max_arrays;
 372         u8 max_lds;
 373
 374         char product_name[80];
 375         char serial_no[32];
 376
 377         /*
 378          * Other physical/controller/operation information. Indicates the
 379          * presence of the hardware
 380          */
 381         struct {
 382
 383                 u32 bbu:1;
 384                 u32 alarm:1;
 385                 u32 nvram:1;
 386                 u32 uart:1;
 387                 u32 reserved:28;
 388
 389         } __attribute__ ((packed)) hw_present;
 390
 391         u32 current_fw_time;
 392
 393         /*
 394          * Maximum data transfer sizes
 395          */
 396         u16 max_concurrent_cmds;
 397         u16 max_sge_count;
 398         u32 max_request_size;
 399
 400         /*
 401          * Logical and physical device counts
 402          */
 403         u16 ld_present_count;
 404         u16 ld_degraded_count;
 405         u16 ld_offline_count;
 406
 407         u16 pd_present_count;
 408         u16 pd_disk_present_count;
 409         u16 pd_disk_pred_failure_count;
 410         u16 pd_disk_failed_count;
 411
 412         /*
 413          * Memory size information
 414          */
 415         u16 nvram_size;
 416         u16 memory_size;
 417         u16 flash_size;
 418
 419         /*
 420          * Error counters
 421          */
 422         u16 mem_correctable_error_count;
 423         u16 mem_uncorrectable_error_count;
 424
 425         /*
 426          * Cluster information
 427          */
 428         u8 cluster_permitted;
 429         u8 cluster_active;
 430
 431         /*
 432          * Additional max data transfer sizes
 433          */
 434         u16 max_strips_per_io;
 435
 436         /*
 437          * Controller capabilities structures
 438          */
 439         struct {
 440
 441                 u32 raid_level_0:1;
 442                 u32 raid_level_1:1;
 443                 u32 raid_level_5:1;
 444                 u32 raid_level_1E:1;
 445                 u32 raid_level_6:1;
 446                 u32 reserved:27;
 447
 448         } __attribute__ ((packed)) raid_levels;
 449
 450         struct {
 451
 452                 u32 rbld_rate:1;
 453                 u32 cc_rate:1;
 454                 u32 bgi_rate:1;
 455                 u32 recon_rate:1;
 456                 u32 patrol_rate:1;
 457                 u32 alarm_control:1;
 458                 u32 cluster_supported:1;
 459                 u32 bbu:1;
 460                 u32 spanning_allowed:1;
 461                 u32 dedicated_hotspares:1;
 462                 u32 revertible_hotspares:1;
 463                 u32 foreign_config_import:1;
 464                 u32 self_diagnostic:1;
 465                 u32 mixed_redundancy_arr:1;
 466                 u32 global_hot_spares:1;
 467                 u32 reserved:17;
 468
 469         } __attribute__ ((packed)) adapter_operations;
 470
 471         struct {
 472
 473                 u32 read_policy:1;
 474                 u32 write_policy:1;
 475                 u32 io_policy:1;
 476                 u32 access_policy:1;
 477                 u32 disk_cache_policy:1;
 478                 u32 reserved:27;
 479
 480         } __attribute__ ((packed)) ld_operations;
 481
 482         struct {
 483
 484                 u8 min;
 485                 u8 max;
 486                 u8 reserved[2];
 487
 488         } __attribute__ ((packed)) stripe_sz_ops;
 489
 490         struct {
 491
 492                 u32 force_online:1;
 493                 u32 force_offline:1;
 494                 u32 force_rebuild:1;
 495                 u32 reserved:29;
 496
 497         } __attribute__ ((packed)) pd_operations;
 498
 499         struct {
 500
 501                 u32 ctrl_supports_sas:1;
 502                 u32 ctrl_supports_sata:1;
 503                 u32 allow_mix_in_encl:1;
 504                 u32 allow_mix_in_ld:1;
 505                 u32 allow_sata_in_cluster:1;
 506                 u32 reserved:27;
 507
 508         } __attribute__ ((packed)) pd_mix_support;
 509
 510         /*
 511          * Define ECC single-bit-error bucket information
 512          */
 513         u8 ecc_bucket_count;
 514         u8 reserved_2[11];
 515
 516         /*
 517          * Include the controller properties (changeable items)
 518          */
 519         struct megasas_ctrl_prop properties;
 520
 521         /*
 522          * Define FW pkg version (set in envt v'bles on OEM basis)
 523          */
 524         char package_version[0x60];
 525
 526         u8 pad[0x800 - 0x6a0];
 527
 528 } __attribute__ ((packed));
 529
 530 /*
 531  * ===============================
 532  * MegaRAID SAS driver definitions
 533  * ===============================
 534  */
 535 #define MEGASAS_MAX_PD_CHANNELS                 2
 536 #define MEGASAS_MAX_LD_CHANNELS                 2
 537 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
 538                                                 MEGASAS_MAX_LD_CHANNELS)
 539 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
 540 #define MEGASAS_DEFAULT_INIT_ID                 -1
 541 #define MEGASAS_MAX_LUN                         8
 542 #define MEGASAS_MAX_LD                          64
 543
 544 #define MEGASAS_DBG_LVL                         1
 545
 546 #define MEGASAS_FW_BUSY                         1
 547
 548 /* Frame Type */
 549 #define IO_FRAME                                0
 550 #define PTHRU_FRAME                             1
 551
 552 /*
 553  * When SCSI mid-layer calls driver's reset routine, driver waits for
 554  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
 555  * that the driver cannot _actually_ abort or reset pending commands. While
 556  * it is waiting for the commands to complete, it prints a diagnostic message
 557  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
 558  */
 559 #define MEGASAS_RESET_WAIT_TIME                 180
 560 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
 561 #define MEGASAS_RESET_NOTICE_INTERVAL           5
 562 #define MEGASAS_IOCTL_CMD                       0
 563 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
 564
 565 /*
 566  * FW reports the maximum of number of commands that it can accept (maximum
 567  * commands that can be outstanding) at any time. The driver must report a
 568  * lower number to the mid layer because it can issue a few internal commands
 569  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
 570  * is shown below
 571  */
 572 #define MEGASAS_INT_CMDS                        32
 573
 574 /*
 575  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
 576  * SGLs based on the size of dma_addr_t
 577  */
 578 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
 579
 580 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
 581 #define MFI_POLL_TIMEOUT_SECS                   60
 582 #define MEGASAS_COMPLETION_TIMER_INTERVAL      (HZ/10)
 583
 584 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
 585 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
 586 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
 587
 588 /*
 589 * register set for both 1068 and 1078 controllers
 590 * structure extended for 1078 registers
 591 */
 592
 593 struct megasas_register_set {
 594         u32     reserved_0[4];                  /*0000h*/
 595
 596         u32     inbound_msg_0;                  /*0010h*/
 597         u32     inbound_msg_1;                  /*0014h*/
 598         u32     outbound_msg_0;                 /*0018h*/
 599         u32     outbound_msg_1;                 /*001Ch*/
 600
 601         u32     inbound_doorbell;               /*0020h*/
 602         u32     inbound_intr_status;            /*0024h*/
 603         u32     inbound_intr_mask;              /*0028h*/
 604
 605         u32     outbound_doorbell;              /*002Ch*/
 606         u32     outbound_intr_status;           /*0030h*/
 607         u32     outbound_intr_mask;             /*0034h*/
 608
 609         u32     reserved_1[2];                  /*0038h*/
 610
 611         u32     inbound_queue_port;             /*0040h*/
 612         u32     outbound_queue_port;            /*0044h*/
 613
 614         u32     reserved_2[22];                 /*0048h*/
 615
 616         u32     outbound_doorbell_clear;        /*00A0h*/
 617
 618         u32     reserved_3[3];                  /*00A4h*/
 619
 620         u32     outbound_scratch_pad ;          /*00B0h*/
 621
 622         u32     reserved_4[3];                  /*00B4h*/
 623
 624         u32     inbound_low_queue_port ;        /*00C0h*/
 625
 626         u32     inbound_high_queue_port ;       /*00C4h*/
 627
 628         u32     reserved_5;                     /*00C8h*/
 629         u32     index_registers[820];           /*00CCh*/
 630
 631 } __attribute__ ((packed));
 632
 633 struct megasas_sge32 {
 634
 635         u32 phys_addr;
 636         u32 length;
 637
 638 } __attribute__ ((packed));
 639
 640 struct megasas_sge64 {
 641
 642         u64 phys_addr;
 643         u32 length;
 644
 645 } __attribute__ ((packed));
 646
 647 union megasas_sgl {
 648
 649         struct megasas_sge32 sge32[1];
 650         struct megasas_sge64 sge64[1];
 651
 652 } __attribute__ ((packed));
 653
 654 struct megasas_header {
 655
 656         u8 cmd;                 /*00h */
 657         u8 sense_len;           /*01h */
 658         u8 cmd_status;          /*02h */
 659         u8 scsi_status;         /*03h */
 660
 661         u8 target_id;           /*04h */
 662         u8 lun;                 /*05h */
 663         u8 cdb_len;             /*06h */
 664         u8 sge_count;           /*07h */
 665
 666         u32 context;            /*08h */
 667         u32 pad_0;              /*0Ch */
 668
 669         u16 flags;              /*10h */
 670         u16 timeout;            /*12h */
 671         u32 data_xferlen;       /*14h */
 672
 673 } __attribute__ ((packed));
 674
 675 union megasas_sgl_frame {
 676
 677         struct megasas_sge32 sge32[8];
 678         struct megasas_sge64 sge64[5];
 679
 680 } __attribute__ ((packed));
 681
 682 struct megasas_init_frame {
 683
 684         u8 cmd;                 /*00h */
 685         u8 reserved_0;          /*01h */
 686         u8 cmd_status;          /*02h */
 687
 688         u8 reserved_1;          /*03h */
 689         u32 reserved_2;         /*04h */
 690
 691         u32 context;            /*08h */
 692         u32 pad_0;              /*0Ch */
 693
 694         u16 flags;              /*10h */
 695         u16 reserved_3;         /*12h */
 696         u32 data_xfer_len;      /*14h */
 697
 698         u32 queue_info_new_phys_addr_lo;        /*18h */
 699         u32 queue_info_new_phys_addr_hi;        /*1Ch */
 700         u32 queue_info_old_phys_addr_lo;        /*20h */
 701         u32 queue_info_old_phys_addr_hi;        /*24h */
 702
 703         u32 reserved_4[6];      /*28h */
 704
 705 } __attribute__ ((packed));
 706
 707 struct megasas_init_queue_info {
 708
 709         u32 init_flags;         /*00h */
 710         u32 reply_queue_entries;        /*04h */
 711
 712         u32 reply_queue_start_phys_addr_lo;     /*08h */
 713         u32 reply_queue_start_phys_addr_hi;     /*0Ch */
 714         u32 producer_index_phys_addr_lo;        /*10h */
 715         u32 producer_index_phys_addr_hi;        /*14h */
 716         u32 consumer_index_phys_addr_lo;        /*18h */
 717         u32 consumer_index_phys_addr_hi;        /*1Ch */
 718
 719 } __attribute__ ((packed));
 720
 721 struct megasas_io_frame {
 722
 723         u8 cmd;                 /*00h */
 724         u8 sense_len;           /*01h */
 725         u8 cmd_status;          /*02h */
 726         u8 scsi_status;         /*03h */
 727
 728         u8 target_id;           /*04h */
 729         u8 access_byte;         /*05h */
 730         u8 reserved_0;          /*06h */
 731         u8 sge_count;           /*07h */
 732
 733         u32 context;            /*08h */
 734         u32 pad_0;              /*0Ch */
 735
 736         u16 flags;              /*10h */
 737         u16 timeout;            /*12h */
 738         u32 lba_count;          /*14h */
 739
 740         u32 sense_buf_phys_addr_lo;     /*18h */
 741         u32 sense_buf_phys_addr_hi;     /*1Ch */
 742
 743         u32 start_lba_lo;       /*20h */
 744         u32 start_lba_hi;       /*24h */
 745
 746         union megasas_sgl sgl;  /*28h */
 747
 748 } __attribute__ ((packed));
 749
 750 struct megasas_pthru_frame {
 751
 752         u8 cmd;                 /*00h */
 753         u8 sense_len;           /*01h */
 754         u8 cmd_status;          /*02h */
 755         u8 scsi_status;         /*03h */
 756
 757         u8 target_id;           /*04h */
 758         u8 lun;                 /*05h */
 759         u8 cdb_len;             /*06h */
 760         u8 sge_count;           /*07h */
 761
 762         u32 context;            /*08h */
 763         u32 pad_0;              /*0Ch */
 764
 765         u16 flags;              /*10h */
 766         u16 timeout;            /*12h */
 767         u32 data_xfer_len;      /*14h */
 768
 769         u32 sense_buf_phys_addr_lo;     /*18h */
 770         u32 sense_buf_phys_addr_hi;     /*1Ch */
 771
 772         u8 cdb[16];             /*20h */
 773         union megasas_sgl sgl;  /*30h */
 774
 775 } __attribute__ ((packed));
 776
 777 struct megasas_dcmd_frame {
 778
 779         u8 cmd;                 /*00h */
 780         u8 reserved_0;          /*01h */
 781         u8 cmd_status;          /*02h */
 782         u8 reserved_1[4];       /*03h */
 783         u8 sge_count;           /*07h */
 784
 785         u32 context;            /*08h */
 786         u32 pad_0;              /*0Ch */
 787
 788         u16 flags;              /*10h */
 789         u16 timeout;            /*12h */
 790
 791         u32 data_xfer_len;      /*14h */
 792         u32 opcode;             /*18h */
 793
 794         union {                 /*1Ch */
 795                 u8 b[12];
 796                 u16 s[6];
 797                 u32 w[3];
 798         } mbox;
 799
 800         union megasas_sgl sgl;  /*28h */
 801
 802 } __attribute__ ((packed));
 803
 804 struct megasas_abort_frame {
 805
 806         u8 cmd;                 /*00h */
 807         u8 reserved_0;          /*01h */
 808         u8 cmd_status;          /*02h */
 809
 810         u8 reserved_1;          /*03h */
 811         u32 reserved_2;         /*04h */
 812
 813         u32 context;            /*08h */
 814         u32 pad_0;              /*0Ch */
 815
 816         u16 flags;              /*10h */
 817         u16 reserved_3;         /*12h */
 818         u32 reserved_4;         /*14h */
 819
 820         u32 abort_context;      /*18h */
 821         u32 pad_1;              /*1Ch */
 822
 823         u32 abort_mfi_phys_addr_lo;     /*20h */
 824         u32 abort_mfi_phys_addr_hi;     /*24h */
 825
 826         u32 reserved_5[6];      /*28h */
 827
 828 } __attribute__ ((packed));
 829
 830 struct megasas_smp_frame {
 831
 832         u8 cmd;                 /*00h */
 833         u8 reserved_1;          /*01h */
 834         u8 cmd_status;          /*02h */
 835         u8 connection_status;   /*03h */
 836
 837         u8 reserved_2[3];       /*04h */
 838         u8 sge_count;           /*07h */
 839
 840         u32 context;            /*08h */
 841         u32 pad_0;              /*0Ch */
 842
 843         u16 flags;              /*10h */
 844         u16 timeout;            /*12h */
 845
 846         u32 data_xfer_len;      /*14h */
 847         u64 sas_addr;           /*18h */
 848
 849         union {
 850                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
 851                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
 852         } sgl;
 853
 854 } __attribute__ ((packed));
 855
 856 struct megasas_stp_frame {
 857
 858         u8 cmd;                 /*00h */
 859         u8 reserved_1;          /*01h */
 860         u8 cmd_status;          /*02h */
 861         u8 reserved_2;          /*03h */
 862
 863         u8 target_id;           /*04h */
 864         u8 reserved_3[2];       /*05h */
 865         u8 sge_count;           /*07h */
 866
 867         u32 context;            /*08h */
 868         u32 pad_0;              /*0Ch */
 869
 870         u16 flags;              /*10h */
 871         u16 timeout;            /*12h */
 872
 873         u32 data_xfer_len;      /*14h */
 874
 875         u16 fis[10];            /*18h */
 876         u32 stp_flags;
 877
 878         union {
 879                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
 880                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
 881         } sgl;
 882
 883 } __attribute__ ((packed));
 884
 885 union megasas_frame {
 886
 887         struct megasas_header hdr;
 888         struct megasas_init_frame init;
 889         struct megasas_io_frame io;
 890         struct megasas_pthru_frame pthru;
 891         struct megasas_dcmd_frame dcmd;
 892         struct megasas_abort_frame abort;
 893         struct megasas_smp_frame smp;
 894         struct megasas_stp_frame stp;
 895
 896         u8 raw_bytes[64];
 897 };
 898
 899 struct megasas_cmd;
 900
 901 union megasas_evt_class_locale {
 902
 903         struct {
 904                 u16 locale;
 905                 u8 reserved;
 906                 s8 class;
 907         } __attribute__ ((packed)) members;
 908
 909         u32 word;
 910
 911 } __attribute__ ((packed));
 912
 913 struct megasas_evt_log_info {
 914         u32 newest_seq_num;
 915         u32 oldest_seq_num;
 916         u32 clear_seq_num;
 917         u32 shutdown_seq_num;
 918         u32 boot_seq_num;
 919
 920 } __attribute__ ((packed));
 921
 922 struct megasas_progress {
 923
 924         u16 progress;
 925         u16 elapsed_seconds;
 926
 927 } __attribute__ ((packed));
 928
 929 struct megasas_evtarg_ld {
 930
 931         u16 target_id;
 932         u8 ld_index;
 933         u8 reserved;
 934
 935 } __attribute__ ((packed));
 936
 937 struct megasas_evtarg_pd {
 938         u16 device_id;
 939         u8 encl_index;
 940         u8 slot_number;
 941
 942 } __attribute__ ((packed));
 943
 944 struct megasas_evt_detail {
 945
 946         u32 seq_num;
 947         u32 time_stamp;
 948         u32 code;
 949         union megasas_evt_class_locale cl;
 950         u8 arg_type;
 951         u8 reserved1[15];
 952
 953         union {
 954                 struct {
 955                         struct megasas_evtarg_pd pd;
 956                         u8 cdb_length;
 957                         u8 sense_length;
 958                         u8 reserved[2];
 959                         u8 cdb[16];
 960                         u8 sense[64];
 961                 } __attribute__ ((packed)) cdbSense;
 962
 963                 struct megasas_evtarg_ld ld;
 964
 965                 struct {
 966                         struct megasas_evtarg_ld ld;
 967                         u64 count;
 968                 } __attribute__ ((packed)) ld_count;
 969
 970                 struct {
 971                         u64 lba;
 972                         struct megasas_evtarg_ld ld;
 973                 } __attribute__ ((packed)) ld_lba;
 974
 975                 struct {
 976                         struct megasas_evtarg_ld ld;
 977                         u32 prevOwner;
 978                         u32 newOwner;
 979                 } __attribute__ ((packed)) ld_owner;
 980
 981                 struct {
 982                         u64 ld_lba;
 983                         u64 pd_lba;
 984                         struct megasas_evtarg_ld ld;
 985                         struct megasas_evtarg_pd pd;
 986                 } __attribute__ ((packed)) ld_lba_pd_lba;
 987
 988                 struct {
 989                         struct megasas_evtarg_ld ld;
 990                         struct megasas_progress prog;
 991                 } __attribute__ ((packed)) ld_prog;
 992
 993                 struct {
 994                         struct megasas_evtarg_ld ld;
 995                         u32 prev_state;
 996                         u32 new_state;
 997                 } __attribute__ ((packed)) ld_state;
 998
 999                 struct {
1000                         u64 strip;
1001                         struct megasas_evtarg_ld ld;
1002                 } __attribute__ ((packed)) ld_strip;
1003
1004                 struct megasas_evtarg_pd pd;
1005
1006                 struct {
1007                         struct megasas_evtarg_pd pd;
1008                         u32 err;
1009                 } __attribute__ ((packed)) pd_err;
1010
1011                 struct {
1012                         u64 lba;
1013                         struct megasas_evtarg_pd pd;
1014                 } __attribute__ ((packed)) pd_lba;
1015
1016                 struct {
1017                         u64 lba;
1018                         struct megasas_evtarg_pd pd;
1019                         struct megasas_evtarg_ld ld;
1020                 } __attribute__ ((packed)) pd_lba_ld;
1021
1022                 struct {
1023                         struct megasas_evtarg_pd pd;
1024                         struct megasas_progress prog;
1025                 } __attribute__ ((packed)) pd_prog;
1026
1027                 struct {
1028                         struct megasas_evtarg_pd pd;
1029                         u32 prevState;
1030                         u32 newState;
1031                 } __attribute__ ((packed)) pd_state;
1032
1033                 struct {
1034                         u16 vendorId;
1035                         u16 deviceId;
1036                         u16 subVendorId;
1037                         u16 subDeviceId;
1038                 } __attribute__ ((packed)) pci;
1039
1040                 u32 rate;
1041                 char str[96];
1042
1043                 struct {
1044                         u32 rtc;
1045                         u32 elapsedSeconds;
1046                 } __attribute__ ((packed)) time;
1047
1048                 struct {
1049                         u32 ecar;
1050                         u32 elog;
1051                         char str[64];
1052                 } __attribute__ ((packed)) ecc;
1053
1054                 u8 b[96];
1055                 u16 s[48];
1056                 u32 w[24];
1057                 u64 d[12];
1058         } args;
1059
1060         char description[128];
1061
1062 } __attribute__ ((packed));
1063
1064  struct megasas_instance_template {
1065         void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1066
1067         void (*enable_intr)(struct megasas_register_set __iomem *) ;
1068         void (*disable_intr)(struct megasas_register_set __iomem *);
1069
1070         int (*clear_intr)(struct megasas_register_set __iomem *);
1071
1072         u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1073  };
1074
1075 struct megasas_instance {
1076
1077         u32 *producer;
1078         dma_addr_t producer_h;
1079         u32 *consumer;
1080         dma_addr_t consumer_h;
1081
1082         u32 *reply_queue;
1083         dma_addr_t reply_queue_h;
1084
1085         unsigned long base_addr;
1086         struct megasas_register_set __iomem *reg_set;
1087
1088         s8 init_id;
1089
1090         u16 max_num_sge;
1091         u16 max_fw_cmds;
1092         u32 max_sectors_per_req;
1093
1094         struct megasas_cmd **cmd_list;
1095         struct list_head cmd_pool;
1096         spinlock_t cmd_pool_lock;
1097         /* used to synch producer, consumer ptrs in dpc */
1098         spinlock_t completion_lock;
1099         struct dma_pool *frame_dma_pool;
1100         struct dma_pool *sense_dma_pool;
1101
1102         struct megasas_evt_detail *evt_detail;
1103         dma_addr_t evt_detail_h;
1104         struct megasas_cmd *aen_cmd;
1105         struct mutex aen_mutex;
1106         struct semaphore ioctl_sem;
1107
1108         struct Scsi_Host *host;
1109
1110         wait_queue_head_t int_cmd_wait_q;
1111         wait_queue_head_t abort_cmd_wait_q;
1112
1113         struct pci_dev *pdev;
1114         u32 unique_id;
1115
1116         atomic_t fw_outstanding;
1117         u32 hw_crit_error;
1118
1119         struct megasas_instance_template *instancet;
1120         struct tasklet_struct isr_tasklet;
1121
1122         u8 flag;
1123         unsigned long last_time;
1124
1125         struct timer_list io_completion_timer;
1126 };
1127
1128 #define MEGASAS_IS_LOGICAL(scp)                                         \
1129         (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1130
1131 #define MEGASAS_DEV_INDEX(inst, scp)                                    \
1132         ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +    \
1133         scp->device->id
1134
1135 struct megasas_cmd {
1136
1137         union megasas_frame *frame;
1138         dma_addr_t frame_phys_addr;
1139         u8 *sense;
1140         dma_addr_t sense_phys_addr;
1141
1142         u32 index;
1143         u8 sync_cmd;
1144         u8 cmd_status;
1145         u16 abort_aen;
1146
1147         struct list_head list;
1148         struct scsi_cmnd *scmd;
1149         struct megasas_instance *instance;
1150         u32 frame_count;
1151 };
1152
1153 #define MAX_MGMT_ADAPTERS               1024
1154 #define MAX_IOCTL_SGE                   16
1155
1156 struct megasas_iocpacket {
1157
1158         u16 host_no;
1159         u16 __pad1;
1160         u32 sgl_off;
1161         u32 sge_count;
1162         u32 sense_off;
1163         u32 sense_len;
1164         union {
1165                 u8 raw[128];
1166                 struct megasas_header hdr;
1167         } frame;
1168
1169         struct iovec sgl[MAX_IOCTL_SGE];
1170
1171 } __attribute__ ((packed));
1172
1173 struct megasas_aen {
1174         u16 host_no;
1175         u16 __pad1;
1176         u32 seq_num;
1177         u32 class_locale_word;
1178 } __attribute__ ((packed));
1179
1180 #ifdef CONFIG_COMPAT
1181 struct compat_megasas_iocpacket {
1182         u16 host_no;
1183         u16 __pad1;
1184         u32 sgl_off;
1185         u32 sge_count;
1186         u32 sense_off;
1187         u32 sense_len;
1188         union {
1189                 u8 raw[128];
1190                 struct megasas_header hdr;
1191         } frame;
1192         struct compat_iovec sgl[MAX_IOCTL_SGE];
1193 } __attribute__ ((packed));
1194
1195 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
1196 #endif
1197
1198 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
1199 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
1200
1201 struct megasas_mgmt_info {
1202
1203         u16 count;
1204         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1205         int max_index;
1206 };
1207
1208 #endif                          /*LSI_MEGARAID_SAS_H */