git.oblomov.eu Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *
 101  * Known bugs:
 102  * We suspect that on some hardware no TX done interrupts are generated.
 103  * This means recovery from netif_stop_queue only happens if the hw timer
 104  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 105  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 106  * If your hardware reliably generates tx done interrupts, then you can remove
 107  * DEV_NEED_TIMERIRQ from the driver_data flags.
 108  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 109  * superfluous timer interrupts from the nic.
 110  */
 111 #define FORCEDETH_VERSION               "0.44"
 112 #define DRV_NAME                        "forcedeth"
 113
 114 #include <linux/module.h>
 115 #include <linux/types.h>
 116 #include <linux/pci.h>
 117 #include <linux/interrupt.h>
 118 #include <linux/netdevice.h>
 119 #include <linux/etherdevice.h>
 120 #include <linux/delay.h>
 121 #include <linux/spinlock.h>
 122 #include <linux/ethtool.h>
 123 #include <linux/timer.h>
 124 #include <linux/skbuff.h>
 125 #include <linux/mii.h>
 126 #include <linux/random.h>
 127 #include <linux/init.h>
 128 #include <linux/if_vlan.h>
 129
 130 #include <asm/irq.h>
 131 #include <asm/io.h>
 132 #include <asm/uaccess.h>
 133 #include <asm/system.h>
 134
 135 #if 0
 136 #define dprintk                 printk
 137 #else
 138 #define dprintk(x...)           do { } while (0)
 139 #endif
 140
 141
 142 /*
 143  * Hardware access:
 144  */
 145
 146 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 147 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 148 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 149 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 150 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 151
 152 enum {
 153         NvRegIrqStatus = 0x000,
 154 #define NVREG_IRQSTAT_MIIEVENT  0x040
 155 #define NVREG_IRQSTAT_MASK              0x1ff
 156         NvRegIrqMask = 0x004,
 157 #define NVREG_IRQ_RX_ERROR              0x0001
 158 #define NVREG_IRQ_RX                    0x0002
 159 #define NVREG_IRQ_RX_NOBUF              0x0004
 160 #define NVREG_IRQ_TX_ERR                0x0008
 161 #define NVREG_IRQ_TX_OK                 0x0010
 162 #define NVREG_IRQ_TIMER                 0x0020
 163 #define NVREG_IRQ_LINK                  0x0040
 164 #define NVREG_IRQ_TX_ERROR              0x0080
 165 #define NVREG_IRQ_TX1                   0x0100
 166 #define NVREG_IRQMASK_WANTED            0x00df
 167
 168 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 169                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 170                                         NVREG_IRQ_TX1))
 171
 172         NvRegUnknownSetupReg6 = 0x008,
 173 #define NVREG_UNKSETUP6_VAL             3
 174
 175 /*
 176  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 177  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 178  */
 179         NvRegPollingInterval = 0x00c,
 180 #define NVREG_POLL_DEFAULT      970
 181         NvRegMisc1 = 0x080,
 182 #define NVREG_MISC1_HD          0x02
 183 #define NVREG_MISC1_FORCE       0x3b0f3c
 184
 185         NvRegTransmitterControl = 0x084,
 186 #define NVREG_XMITCTL_START     0x01
 187         NvRegTransmitterStatus = 0x088,
 188 #define NVREG_XMITSTAT_BUSY     0x01
 189
 190         NvRegPacketFilterFlags = 0x8c,
 191 #define NVREG_PFF_ALWAYS        0x7F0008
 192 #define NVREG_PFF_PROMISC       0x80
 193 #define NVREG_PFF_MYADDR        0x20
 194
 195         NvRegOffloadConfig = 0x90,
 196 #define NVREG_OFFLOAD_HOMEPHY   0x601
 197 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 198         NvRegReceiverControl = 0x094,
 199 #define NVREG_RCVCTL_START      0x01
 200         NvRegReceiverStatus = 0x98,
 201 #define NVREG_RCVSTAT_BUSY      0x01
 202
 203         NvRegRandomSeed = 0x9c,
 204 #define NVREG_RNDSEED_MASK      0x00ff
 205 #define NVREG_RNDSEED_FORCE     0x7f00
 206 #define NVREG_RNDSEED_FORCE2    0x2d00
 207 #define NVREG_RNDSEED_FORCE3    0x7400
 208
 209         NvRegUnknownSetupReg1 = 0xA0,
 210 #define NVREG_UNKSETUP1_VAL     0x16070f
 211         NvRegUnknownSetupReg2 = 0xA4,
 212 #define NVREG_UNKSETUP2_VAL     0x16
 213         NvRegMacAddrA = 0xA8,
 214         NvRegMacAddrB = 0xAC,
 215         NvRegMulticastAddrA = 0xB0,
 216 #define NVREG_MCASTADDRA_FORCE  0x01
 217         NvRegMulticastAddrB = 0xB4,
 218         NvRegMulticastMaskA = 0xB8,
 219         NvRegMulticastMaskB = 0xBC,
 220
 221         NvRegPhyInterface = 0xC0,
 222 #define PHY_RGMII               0x10000000
 223
 224         NvRegTxRingPhysAddr = 0x100,
 225         NvRegRxRingPhysAddr = 0x104,
 226         NvRegRingSizes = 0x108,
 227 #define NVREG_RINGSZ_TXSHIFT 0
 228 #define NVREG_RINGSZ_RXSHIFT 16
 229         NvRegUnknownTransmitterReg = 0x10c,
 230         NvRegLinkSpeed = 0x110,
 231 #define NVREG_LINKSPEED_FORCE 0x10000
 232 #define NVREG_LINKSPEED_10      1000
 233 #define NVREG_LINKSPEED_100     100
 234 #define NVREG_LINKSPEED_1000    50
 235 #define NVREG_LINKSPEED_MASK    (0xFFF)
 236         NvRegUnknownSetupReg5 = 0x130,
 237 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 238         NvRegUnknownSetupReg3 = 0x13c,
 239 #define NVREG_UNKSETUP3_VAL1    0x200010
 240         NvRegTxRxControl = 0x144,
 241 #define NVREG_TXRXCTL_KICK      0x0001
 242 #define NVREG_TXRXCTL_BIT1      0x0002
 243 #define NVREG_TXRXCTL_BIT2      0x0004
 244 #define NVREG_TXRXCTL_IDLE      0x0008
 245 #define NVREG_TXRXCTL_RESET     0x0010
 246 #define NVREG_TXRXCTL_RXCHECK   0x0400
 247 #define NVREG_TXRXCTL_DESC_1    0
 248 #define NVREG_TXRXCTL_DESC_2    0x02100
 249 #define NVREG_TXRXCTL_DESC_3    0x02200
 250         NvRegMIIStatus = 0x180,
 251 #define NVREG_MIISTAT_ERROR             0x0001
 252 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 253 #define NVREG_MIISTAT_MASK              0x000f
 254 #define NVREG_MIISTAT_MASK2             0x000f
 255         NvRegUnknownSetupReg4 = 0x184,
 256 #define NVREG_UNKSETUP4_VAL     8
 257
 258         NvRegAdapterControl = 0x188,
 259 #define NVREG_ADAPTCTL_START    0x02
 260 #define NVREG_ADAPTCTL_LINKUP   0x04
 261 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 262 #define NVREG_ADAPTCTL_RUNNING  0x100000
 263 #define NVREG_ADAPTCTL_PHYSHIFT 24
 264         NvRegMIISpeed = 0x18c,
 265 #define NVREG_MIISPEED_BIT8     (1<<8)
 266 #define NVREG_MIIDELAY  5
 267         NvRegMIIControl = 0x190,
 268 #define NVREG_MIICTL_INUSE      0x08000
 269 #define NVREG_MIICTL_WRITE      0x00400
 270 #define NVREG_MIICTL_ADDRSHIFT  5
 271         NvRegMIIData = 0x194,
 272         NvRegWakeUpFlags = 0x200,
 273 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 274 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 275 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 276 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 277 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 278 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 279 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 280 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 281 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 282 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 283 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 284
 285         NvRegPatternCRC = 0x204,
 286         NvRegPatternMask = 0x208,
 287         NvRegPowerCap = 0x268,
 288 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 289 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 290 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 291         NvRegPowerState = 0x26c,
 292 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 293 #define NVREG_POWERSTATE_VALID          0x0100
 294 #define NVREG_POWERSTATE_MASK           0x0003
 295 #define NVREG_POWERSTATE_D0             0x0000
 296 #define NVREG_POWERSTATE_D1             0x0001
 297 #define NVREG_POWERSTATE_D2             0x0002
 298 #define NVREG_POWERSTATE_D3             0x0003
 299 };
 300
 301 /* Big endian: should work, but is untested */
 302 struct ring_desc {
 303         u32 PacketBuffer;
 304         u32 FlagLen;
 305 };
 306
 307 struct ring_desc_ex {
 308         u32 PacketBufferHigh;
 309         u32 PacketBufferLow;
 310         u32 Reserved;
 311         u32 FlagLen;
 312 };
 313
 314 typedef union _ring_type {
 315         struct ring_desc* orig;
 316         struct ring_desc_ex* ex;
 317 } ring_type;
 318
 319 #define FLAG_MASK_V1 0xffff0000
 320 #define FLAG_MASK_V2 0xffffc000
 321 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 322 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 323
 324 #define NV_TX_LASTPACKET        (1<<16)
 325 #define NV_TX_RETRYERROR        (1<<19)
 326 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 327 #define NV_TX_DEFERRED          (1<<26)
 328 #define NV_TX_CARRIERLOST       (1<<27)
 329 #define NV_TX_LATECOLLISION     (1<<28)
 330 #define NV_TX_UNDERFLOW         (1<<29)
 331 #define NV_TX_ERROR             (1<<30)
 332 #define NV_TX_VALID             (1<<31)
 333
 334 #define NV_TX2_LASTPACKET       (1<<29)
 335 #define NV_TX2_RETRYERROR       (1<<18)
 336 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 337 #define NV_TX2_DEFERRED         (1<<25)
 338 #define NV_TX2_CARRIERLOST      (1<<26)
 339 #define NV_TX2_LATECOLLISION    (1<<27)
 340 #define NV_TX2_UNDERFLOW        (1<<28)
 341 /* error and valid are the same for both */
 342 #define NV_TX2_ERROR            (1<<30)
 343 #define NV_TX2_VALID            (1<<31)
 344 #define NV_TX2_TSO              (1<<28)
 345 #define NV_TX2_TSO_SHIFT        14
 346 #define NV_TX2_CHECKSUM_L3      (1<<27)
 347 #define NV_TX2_CHECKSUM_L4      (1<<26)
 348
 349 #define NV_RX_DESCRIPTORVALID   (1<<16)
 350 #define NV_RX_MISSEDFRAME       (1<<17)
 351 #define NV_RX_SUBSTRACT1        (1<<18)
 352 #define NV_RX_ERROR1            (1<<23)
 353 #define NV_RX_ERROR2            (1<<24)
 354 #define NV_RX_ERROR3            (1<<25)
 355 #define NV_RX_ERROR4            (1<<26)
 356 #define NV_RX_CRCERR            (1<<27)
 357 #define NV_RX_OVERFLOW          (1<<28)
 358 #define NV_RX_FRAMINGERR        (1<<29)
 359 #define NV_RX_ERROR             (1<<30)
 360 #define NV_RX_AVAIL             (1<<31)
 361
 362 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 363 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 364 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 365 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 366 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 367 #define NV_RX2_SUBSTRACT1       (1<<25)
 368 #define NV_RX2_ERROR1           (1<<18)
 369 #define NV_RX2_ERROR2           (1<<19)
 370 #define NV_RX2_ERROR3           (1<<20)
 371 #define NV_RX2_ERROR4           (1<<21)
 372 #define NV_RX2_CRCERR           (1<<22)
 373 #define NV_RX2_OVERFLOW         (1<<23)
 374 #define NV_RX2_FRAMINGERR       (1<<24)
 375 /* error and avail are the same for both */
 376 #define NV_RX2_ERROR            (1<<30)
 377 #define NV_RX2_AVAIL            (1<<31)
 378
 379 /* Miscelaneous hardware related defines: */
 380 #define NV_PCI_REGSZ            0x270
 381
 382 /* various timeout delays: all in usec */
 383 #define NV_TXRX_RESET_DELAY     4
 384 #define NV_TXSTOP_DELAY1        10
 385 #define NV_TXSTOP_DELAY1MAX     500000
 386 #define NV_TXSTOP_DELAY2        100
 387 #define NV_RXSTOP_DELAY1        10
 388 #define NV_RXSTOP_DELAY1MAX     500000
 389 #define NV_RXSTOP_DELAY2        100
 390 #define NV_SETUP5_DELAY         5
 391 #define NV_SETUP5_DELAYMAX      50000
 392 #define NV_POWERUP_DELAY        5
 393 #define NV_POWERUP_DELAYMAX     5000
 394 #define NV_MIIBUSY_DELAY        50
 395 #define NV_MIIPHY_DELAY 10
 396 #define NV_MIIPHY_DELAYMAX      10000
 397
 398 #define NV_WAKEUPPATTERNS       5
 399 #define NV_WAKEUPMASKENTRIES    4
 400
 401 /* General driver defaults */
 402 #define NV_WATCHDOG_TIMEO       (5*HZ)
 403
 404 #define RX_RING         128
 405 #define TX_RING         64
 406 /*
 407  * If your nic mysteriously hangs then try to reduce the limits
 408  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 409  * last valid ring entry. But this would be impossible to
 410  * implement - probably a disassembly error.
 411  */
 412 #define TX_LIMIT_STOP   63
 413 #define TX_LIMIT_START  62
 414
 415 /* rx/tx mac addr + type + vlan + align + slack*/
 416 #define NV_RX_HEADERS           (64)
 417 /* even more slack. */
 418 #define NV_RX_ALLOC_PAD         (64)
 419
 420 /* maximum mtu size */
 421 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 422 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 423
 424 #define OOM_REFILL      (1+HZ/20)
 425 #define POLL_WAIT       (1+HZ/100)
 426 #define LINK_TIMEOUT    (3*HZ)
 427
 428 /*
 429  * desc_ver values:
 430  * The nic supports three different descriptor types:
 431  * - DESC_VER_1: Original
 432  * - DESC_VER_2: support for jumbo frames.
 433  * - DESC_VER_3: 64-bit format.
 434  */
 435 #define DESC_VER_1      1
 436 #define DESC_VER_2      2
 437 #define DESC_VER_3      3
 438
 439 /* PHY defines */
 440 #define PHY_OUI_MARVELL 0x5043
 441 #define PHY_OUI_CICADA  0x03f1
 442 #define PHYID1_OUI_MASK 0x03ff
 443 #define PHYID1_OUI_SHFT 6
 444 #define PHYID2_OUI_MASK 0xfc00
 445 #define PHYID2_OUI_SHFT 10
 446 #define PHY_INIT1       0x0f000
 447 #define PHY_INIT2       0x0e00
 448 #define PHY_INIT3       0x01000
 449 #define PHY_INIT4       0x0200
 450 #define PHY_INIT5       0x0004
 451 #define PHY_INIT6       0x02000
 452 #define PHY_GIGABIT     0x0100
 453
 454 #define PHY_TIMEOUT     0x1
 455 #define PHY_ERROR       0x2
 456
 457 #define PHY_100 0x1
 458 #define PHY_1000        0x2
 459 #define PHY_HALF        0x100
 460
 461 /* FIXME: MII defines that should be added to <linux/mii.h> */
 462 #define MII_1000BT_CR   0x09
 463 #define MII_1000BT_SR   0x0a
 464 #define ADVERTISE_1000FULL      0x0200
 465 #define ADVERTISE_1000HALF      0x0100
 466 #define LPA_1000FULL    0x0800
 467 #define LPA_1000HALF    0x0400
 468
 469
 470 /*
 471  * SMP locking:
 472  * All hardware access under dev->priv->lock, except the performance
 473  * critical parts:
 474  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 475  *      by the arch code for interrupts.
 476  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 477  *      needs dev->priv->lock :-(
 478  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 479  */
 480
 481 /* in dev: base, irq */
 482 struct fe_priv {
 483         spinlock_t lock;
 484
 485         /* General data:
 486          * Locking: spin_lock(&np->lock); */
 487         struct net_device_stats stats;
 488         int in_shutdown;
 489         u32 linkspeed;
 490         int duplex;
 491         int autoneg;
 492         int fixed_mode;
 493         int phyaddr;
 494         int wolenabled;
 495         unsigned int phy_oui;
 496         u16 gigabit;
 497
 498         /* General data: RO fields */
 499         dma_addr_t ring_addr;
 500         struct pci_dev *pci_dev;
 501         u32 orig_mac[2];
 502         u32 irqmask;
 503         u32 desc_ver;
 504         u32 txrxctl_bits;
 505
 506         void __iomem *base;
 507
 508         /* rx specific fields.
 509          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 510          */
 511         ring_type rx_ring;
 512         unsigned int cur_rx, refill_rx;
 513         struct sk_buff *rx_skbuff[RX_RING];
 514         dma_addr_t rx_dma[RX_RING];
 515         unsigned int rx_buf_sz;
 516         unsigned int pkt_limit;
 517         struct timer_list oom_kick;
 518         struct timer_list nic_poll;
 519
 520         /* media detection workaround.
 521          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 522          */
 523         int need_linktimer;
 524         unsigned long link_timeout;
 525         /*
 526          * tx specific fields.
 527          */
 528         ring_type tx_ring;
 529         unsigned int next_tx, nic_tx;
 530         struct sk_buff *tx_skbuff[TX_RING];
 531         dma_addr_t tx_dma[TX_RING];
 532         u32 tx_flags;
 533 };
 534
 535 /*
 536  * Maximum number of loops until we assume that a bit in the irq mask
 537  * is stuck. Overridable with module param.
 538  */
 539 static int max_interrupt_work = 5;
 540
 541 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 542 {
 543         return netdev_priv(dev);
 544 }
 545
 546 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 547 {
 548         return ((struct fe_priv *)netdev_priv(dev))->base;
 549 }
 550
 551 static inline void pci_push(u8 __iomem *base)
 552 {
 553         /* force out pending posted writes */
 554         readl(base);
 555 }
 556
 557 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 558 {
 559         return le32_to_cpu(prd->FlagLen)
 560                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 561 }
 562
 563 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 564 {
 565         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 566 }
 567
 568 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 569                                 int delay, int delaymax, const char *msg)
 570 {
 571         u8 __iomem *base = get_hwbase(dev);
 572
 573         pci_push(base);
 574         do {
 575                 udelay(delay);
 576                 delaymax -= delay;
 577                 if (delaymax < 0) {
 578                         if (msg)
 579                                 printk(msg);
 580                         return 1;
 581                 }
 582         } while ((readl(base + offset) & mask) != target);
 583         return 0;
 584 }
 585
 586 #define MII_READ        (-1)
 587 /* mii_rw: read/write a register on the PHY.
 588  *
 589  * Caller must guarantee serialization
 590  */
 591 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 592 {
 593         u8 __iomem *base = get_hwbase(dev);
 594         u32 reg;
 595         int retval;
 596
 597         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 598
 599         reg = readl(base + NvRegMIIControl);
 600         if (reg & NVREG_MIICTL_INUSE) {
 601                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 602                 udelay(NV_MIIBUSY_DELAY);
 603         }
 604
 605         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 606         if (value != MII_READ) {
 607                 writel(value, base + NvRegMIIData);
 608                 reg |= NVREG_MIICTL_WRITE;
 609         }
 610         writel(reg, base + NvRegMIIControl);
 611
 612         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 613                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 614                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 615                                 dev->name, miireg, addr);
 616                 retval = -1;
 617         } else if (value != MII_READ) {
 618                 /* it was a write operation - fewer failures are detectable */
 619                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 620                                 dev->name, value, miireg, addr);
 621                 retval = 0;
 622         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 623                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 624                                 dev->name, miireg, addr);
 625                 retval = -1;
 626         } else {
 627                 retval = readl(base + NvRegMIIData);
 628                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 629                                 dev->name, miireg, addr, retval);
 630         }
 631
 632         return retval;
 633 }
 634
 635 static int phy_reset(struct net_device *dev)
 636 {
 637         struct fe_priv *np = netdev_priv(dev);
 638         u32 miicontrol;
 639         unsigned int tries = 0;
 640
 641         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 642         miicontrol |= BMCR_RESET;
 643         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 644                 return -1;
 645         }
 646
 647         /* wait for 500ms */
 648         msleep(500);
 649
 650         /* must wait till reset is deasserted */
 651         while (miicontrol & BMCR_RESET) {
 652                 msleep(10);
 653                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 654                 /* FIXME: 100 tries seem excessive */
 655                 if (tries++ > 100)
 656                         return -1;
 657         }
 658         return 0;
 659 }
 660
 661 static int phy_init(struct net_device *dev)
 662 {
 663         struct fe_priv *np = get_nvpriv(dev);
 664         u8 __iomem *base = get_hwbase(dev);
 665         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 666
 667         /* set advertise register */
 668         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 669         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 670         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 671                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 672                 return PHY_ERROR;
 673         }
 674
 675         /* get phy interface type */
 676         phyinterface = readl(base + NvRegPhyInterface);
 677
 678         /* see if gigabit phy */
 679         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 680         if (mii_status & PHY_GIGABIT) {
 681                 np->gigabit = PHY_GIGABIT;
 682                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 683                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 684                 if (phyinterface & PHY_RGMII)
 685                         mii_control_1000 |= ADVERTISE_1000FULL;
 686                 else
 687                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 688
 689                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 690                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 691                         return PHY_ERROR;
 692                 }
 693         }
 694         else
 695                 np->gigabit = 0;
 696
 697         /* reset the phy */
 698         if (phy_reset(dev)) {
 699                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 700                 return PHY_ERROR;
 701         }
 702
 703         /* phy vendor specific configuration */
 704         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 705                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 706                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 707                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 708                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 709                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 710                         return PHY_ERROR;
 711                 }
 712                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 713                 phy_reserved |= PHY_INIT5;
 714                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 715                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 716                         return PHY_ERROR;
 717                 }
 718         }
 719         if (np->phy_oui == PHY_OUI_CICADA) {
 720                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 721                 phy_reserved |= PHY_INIT6;
 722                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 723                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 724                         return PHY_ERROR;
 725                 }
 726         }
 727
 728         /* restart auto negotiation */
 729         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 730         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 731         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 732                 return PHY_ERROR;
 733         }
 734
 735         return 0;
 736 }
 737
 738 static void nv_start_rx(struct net_device *dev)
 739 {
 740         struct fe_priv *np = netdev_priv(dev);
 741         u8 __iomem *base = get_hwbase(dev);
 742
 743         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 744         /* Already running? Stop it. */
 745         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 746                 writel(0, base + NvRegReceiverControl);
 747                 pci_push(base);
 748         }
 749         writel(np->linkspeed, base + NvRegLinkSpeed);
 750         pci_push(base);
 751         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 752         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 753                                 dev->name, np->duplex, np->linkspeed);
 754         pci_push(base);
 755 }
 756
 757 static void nv_stop_rx(struct net_device *dev)
 758 {
 759         u8 __iomem *base = get_hwbase(dev);
 760
 761         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 762         writel(0, base + NvRegReceiverControl);
 763         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 764                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 765                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 766
 767         udelay(NV_RXSTOP_DELAY2);
 768         writel(0, base + NvRegLinkSpeed);
 769 }
 770
 771 static void nv_start_tx(struct net_device *dev)
 772 {
 773         u8 __iomem *base = get_hwbase(dev);
 774
 775         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 776         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 777         pci_push(base);
 778 }
 779
 780 static void nv_stop_tx(struct net_device *dev)
 781 {
 782         u8 __iomem *base = get_hwbase(dev);
 783
 784         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 785         writel(0, base + NvRegTransmitterControl);
 786         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 787                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 788                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 789
 790         udelay(NV_TXSTOP_DELAY2);
 791         writel(0, base + NvRegUnknownTransmitterReg);
 792 }
 793
 794 static void nv_txrx_reset(struct net_device *dev)
 795 {
 796         struct fe_priv *np = netdev_priv(dev);
 797         u8 __iomem *base = get_hwbase(dev);
 798
 799         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 800         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
 801         pci_push(base);
 802         udelay(NV_TXRX_RESET_DELAY);
 803         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
 804         pci_push(base);
 805 }
 806
 807 /*
 808  * nv_get_stats: dev->get_stats function
 809  * Get latest stats value from the nic.
 810  * Called with read_lock(&dev_base_lock) held for read -
 811  * only synchronized against unregister_netdevice.
 812  */
 813 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 814 {
 815         struct fe_priv *np = netdev_priv(dev);
 816
 817         /* It seems that the nic always generates interrupts and doesn't
 818          * accumulate errors internally. Thus the current values in np->stats
 819          * are already up to date.
 820          */
 821         return &np->stats;
 822 }
 823
 824 /*
 825  * nv_alloc_rx: fill rx ring entries.
 826  * Return 1 if the allocations for the skbs failed and the
 827  * rx engine is without Available descriptors
 828  */
 829 static int nv_alloc_rx(struct net_device *dev)
 830 {
 831         struct fe_priv *np = netdev_priv(dev);
 832         unsigned int refill_rx = np->refill_rx;
 833         int nr;
 834
 835         while (np->cur_rx != refill_rx) {
 836                 struct sk_buff *skb;
 837
 838                 nr = refill_rx % RX_RING;
 839                 if (np->rx_skbuff[nr] == NULL) {
 840
 841                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 842                         if (!skb)
 843                                 break;
 844
 845                         skb->dev = dev;
 846                         np->rx_skbuff[nr] = skb;
 847                 } else {
 848                         skb = np->rx_skbuff[nr];
 849                 }
 850                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
 851                                                 PCI_DMA_FROMDEVICE);
 852                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 853                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 854                         wmb();
 855                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 856                 } else {
 857                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
 858                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
 859                         wmb();
 860                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
 861                 }
 862                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 863                                         dev->name, refill_rx);
 864                 refill_rx++;
 865         }
 866         np->refill_rx = refill_rx;
 867         if (np->cur_rx - refill_rx == RX_RING)
 868                 return 1;
 869         return 0;
 870 }
 871
 872 static void nv_do_rx_refill(unsigned long data)
 873 {
 874         struct net_device *dev = (struct net_device *) data;
 875         struct fe_priv *np = netdev_priv(dev);
 876
 877         disable_irq(dev->irq);
 878         if (nv_alloc_rx(dev)) {
 879                 spin_lock(&np->lock);
 880                 if (!np->in_shutdown)
 881                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 882                 spin_unlock(&np->lock);
 883         }
 884         enable_irq(dev->irq);
 885 }
 886
 887 static void nv_init_rx(struct net_device *dev)
 888 {
 889         struct fe_priv *np = netdev_priv(dev);
 890         int i;
 891
 892         np->cur_rx = RX_RING;
 893         np->refill_rx = 0;
 894         for (i = 0; i < RX_RING; i++)
 895                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 896                         np->rx_ring.orig[i].FlagLen = 0;
 897                 else
 898                         np->rx_ring.ex[i].FlagLen = 0;
 899 }
 900
 901 static void nv_init_tx(struct net_device *dev)
 902 {
 903         struct fe_priv *np = netdev_priv(dev);
 904         int i;
 905
 906         np->next_tx = np->nic_tx = 0;
 907         for (i = 0; i < TX_RING; i++) {
 908                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 909                         np->tx_ring.orig[i].FlagLen = 0;
 910                 else
 911                         np->tx_ring.ex[i].FlagLen = 0;
 912                 np->tx_skbuff[i] = NULL;
 913         }
 914 }
 915
 916 static int nv_init_ring(struct net_device *dev)
 917 {
 918         nv_init_tx(dev);
 919         nv_init_rx(dev);
 920         return nv_alloc_rx(dev);
 921 }
 922
 923 static void nv_release_txskb(struct net_device *dev, unsigned int skbnr)
 924 {
 925         struct fe_priv *np = netdev_priv(dev);
 926         struct sk_buff *skb = np->tx_skbuff[skbnr];
 927         unsigned int j, entry, fragments;
 928
 929         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n",
 930                 dev->name, skbnr, np->tx_skbuff[skbnr]);
 931
 932         entry = skbnr;
 933         if ((fragments = skb_shinfo(skb)->nr_frags) != 0) {
 934                 for (j = fragments; j >= 1; j--) {
 935                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1];
 936                         pci_unmap_page(np->pci_dev, np->tx_dma[entry],
 937                                        frag->size,
 938                                        PCI_DMA_TODEVICE);
 939                         entry = (entry - 1) % TX_RING;
 940                 }
 941         }
 942         pci_unmap_single(np->pci_dev, np->tx_dma[entry],
 943                          skb->len - skb->data_len,
 944                          PCI_DMA_TODEVICE);
 945         dev_kfree_skb_irq(skb);
 946         np->tx_skbuff[skbnr] = NULL;
 947 }
 948
 949 static void nv_drain_tx(struct net_device *dev)
 950 {
 951         struct fe_priv *np = netdev_priv(dev);
 952         unsigned int i;
 953
 954         for (i = 0; i < TX_RING; i++) {
 955                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 956                         np->tx_ring.orig[i].FlagLen = 0;
 957                 else
 958                         np->tx_ring.ex[i].FlagLen = 0;
 959                 if (np->tx_skbuff[i]) {
 960                         nv_release_txskb(dev, i);
 961                         np->stats.tx_dropped++;
 962                 }
 963         }
 964 }
 965
 966 static void nv_drain_rx(struct net_device *dev)
 967 {
 968         struct fe_priv *np = netdev_priv(dev);
 969         int i;
 970         for (i = 0; i < RX_RING; i++) {
 971                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 972                         np->rx_ring.orig[i].FlagLen = 0;
 973                 else
 974                         np->rx_ring.ex[i].FlagLen = 0;
 975                 wmb();
 976                 if (np->rx_skbuff[i]) {
 977                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
 978                                                 np->rx_skbuff[i]->len,
 979                                                 PCI_DMA_FROMDEVICE);
 980                         dev_kfree_skb(np->rx_skbuff[i]);
 981                         np->rx_skbuff[i] = NULL;
 982                 }
 983         }
 984 }
 985
 986 static void drain_ring(struct net_device *dev)
 987 {
 988         nv_drain_tx(dev);
 989         nv_drain_rx(dev);
 990 }
 991
 992 /*
 993  * nv_start_xmit: dev->hard_start_xmit function
 994  * Called with dev->xmit_lock held.
 995  */
 996 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
 997 {
 998         struct fe_priv *np = netdev_priv(dev);
 999         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1000         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1001         unsigned int nr = (np->next_tx + fragments) % TX_RING;
1002         unsigned int i;
1003
1004         spin_lock_irq(&np->lock);
1005
1006         if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) {
1007                 spin_unlock_irq(&np->lock);
1008                 netif_stop_queue(dev);
1009                 return NETDEV_TX_BUSY;
1010         }
1011
1012         np->tx_skbuff[nr] = skb;
1013
1014         if (fragments) {
1015                 dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments);
1016                 /* setup descriptors in reverse order */
1017                 for (i = fragments; i >= 1; i--) {
1018                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1];
1019                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size,
1020                                                         PCI_DMA_TODEVICE);
1021
1022                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1023                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1024                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1025                         } else {
1026                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1027                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1028                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1029                         }
1030
1031                         nr = (nr - 1) % TX_RING;
1032
1033                         if (np->desc_ver == DESC_VER_1)
1034                                 tx_flags_extra &= ~NV_TX_LASTPACKET;
1035                         else
1036                                 tx_flags_extra &= ~NV_TX2_LASTPACKET;
1037                 }
1038         }
1039
1040 #ifdef NETIF_F_TSO
1041         if (skb_shinfo(skb)->tso_size)
1042                 tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1043         else
1044 #endif
1045         tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1046
1047         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len,
1048                                         PCI_DMA_TODEVICE);
1049
1050         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1051                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1052                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1053         } else {
1054                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1055                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1056                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1057         }
1058
1059         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n",
1060                                 dev->name, np->next_tx, tx_flags_extra);
1061         {
1062                 int j;
1063                 for (j=0; j<64; j++) {
1064                         if ((j%16) == 0)
1065                                 dprintk("\n%03x:", j);
1066                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1067                 }
1068                 dprintk("\n");
1069         }
1070
1071         np->next_tx += 1 + fragments;
1072
1073         dev->trans_start = jiffies;
1074         spin_unlock_irq(&np->lock);
1075         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1076         pci_push(get_hwbase(dev));
1077         return NETDEV_TX_OK;
1078 }
1079
1080 /*
1081  * nv_tx_done: check for completed packets, release the skbs.
1082  *
1083  * Caller must own np->lock.
1084  */
1085 static void nv_tx_done(struct net_device *dev)
1086 {
1087         struct fe_priv *np = netdev_priv(dev);
1088         u32 Flags;
1089         unsigned int i;
1090         struct sk_buff *skb;
1091
1092         while (np->nic_tx != np->next_tx) {
1093                 i = np->nic_tx % TX_RING;
1094
1095                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1096                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1097                 else
1098                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1099
1100                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1101                                         dev->name, np->nic_tx, Flags);
1102                 if (Flags & NV_TX_VALID)
1103                         break;
1104                 if (np->desc_ver == DESC_VER_1) {
1105                         if (Flags & NV_TX_LASTPACKET) {
1106                                 skb = np->tx_skbuff[i];
1107                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1108                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1109                                         if (Flags & NV_TX_UNDERFLOW)
1110                                                 np->stats.tx_fifo_errors++;
1111                                         if (Flags & NV_TX_CARRIERLOST)
1112                                                 np->stats.tx_carrier_errors++;
1113                                         np->stats.tx_errors++;
1114                                 } else {
1115                                         np->stats.tx_packets++;
1116                                         np->stats.tx_bytes += skb->len;
1117                                 }
1118                                 nv_release_txskb(dev, i);
1119                         }
1120                 } else {
1121                         if (Flags & NV_TX2_LASTPACKET) {
1122                                 skb = np->tx_skbuff[i];
1123                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1124                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1125                                         if (Flags & NV_TX2_UNDERFLOW)
1126                                                 np->stats.tx_fifo_errors++;
1127                                         if (Flags & NV_TX2_CARRIERLOST)
1128                                                 np->stats.tx_carrier_errors++;
1129                                         np->stats.tx_errors++;
1130                                 } else {
1131                                         np->stats.tx_packets++;
1132                                         np->stats.tx_bytes += skb->len;
1133                                 }
1134                                 nv_release_txskb(dev, i);
1135                         }
1136                 }
1137                 np->nic_tx++;
1138         }
1139         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1140                 netif_wake_queue(dev);
1141 }
1142
1143 /*
1144  * nv_tx_timeout: dev->tx_timeout function
1145  * Called with dev->xmit_lock held.
1146  */
1147 static void nv_tx_timeout(struct net_device *dev)
1148 {
1149         struct fe_priv *np = netdev_priv(dev);
1150         u8 __iomem *base = get_hwbase(dev);
1151
1152         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1153                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1154
1155         {
1156                 int i;
1157
1158                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1159                                 dev->name, (unsigned long)np->ring_addr,
1160                                 np->next_tx, np->nic_tx);
1161                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1162                 for (i=0;i<0x400;i+= 32) {
1163                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1164                                         i,
1165                                         readl(base + i + 0), readl(base + i + 4),
1166                                         readl(base + i + 8), readl(base + i + 12),
1167                                         readl(base + i + 16), readl(base + i + 20),
1168                                         readl(base + i + 24), readl(base + i + 28));
1169                 }
1170                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1171                 for (i=0;i<TX_RING;i+= 4) {
1172                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1173                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1174                                        i,
1175                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1176                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1177                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1178                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1179                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1180                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1181                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1182                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1183                         } else {
1184                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1185                                        i,
1186                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1187                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1188                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1189                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1190                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1191                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1192                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1193                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1194                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1195                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1196                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1197                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1198                         }
1199                 }
1200         }
1201
1202         spin_lock_irq(&np->lock);
1203
1204         /* 1) stop tx engine */
1205         nv_stop_tx(dev);
1206
1207         /* 2) check that the packets were not sent already: */
1208         nv_tx_done(dev);
1209
1210         /* 3) if there are dead entries: clear everything */
1211         if (np->next_tx != np->nic_tx) {
1212                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1213                 nv_drain_tx(dev);
1214                 np->next_tx = np->nic_tx = 0;
1215                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1216                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1217                 else
1218                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1219                 netif_wake_queue(dev);
1220         }
1221
1222         /* 4) restart tx engine */
1223         nv_start_tx(dev);
1224         spin_unlock_irq(&np->lock);
1225 }
1226
1227 /*
1228  * Called when the nic notices a mismatch between the actual data len on the
1229  * wire and the len indicated in the 802 header
1230  */
1231 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1232 {
1233         int hdrlen;     /* length of the 802 header */
1234         int protolen;   /* length as stored in the proto field */
1235
1236         /* 1) calculate len according to header */
1237         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1238                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1239                 hdrlen = VLAN_HLEN;
1240         } else {
1241                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1242                 hdrlen = ETH_HLEN;
1243         }
1244         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1245                                 dev->name, datalen, protolen, hdrlen);
1246         if (protolen > ETH_DATA_LEN)
1247                 return datalen; /* Value in proto field not a len, no checks possible */
1248
1249         protolen += hdrlen;
1250         /* consistency checks: */
1251         if (datalen > ETH_ZLEN) {
1252                 if (datalen >= protolen) {
1253                         /* more data on wire than in 802 header, trim of
1254                          * additional data.
1255                          */
1256                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1257                                         dev->name, protolen);
1258                         return protolen;
1259                 } else {
1260                         /* less data on wire than mentioned in header.
1261                          * Discard the packet.
1262                          */
1263                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1264                                         dev->name);
1265                         return -1;
1266                 }
1267         } else {
1268                 /* short packet. Accept only if 802 values are also short */
1269                 if (protolen > ETH_ZLEN) {
1270                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1271                                         dev->name);
1272                         return -1;
1273                 }
1274                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1275                                 dev->name, datalen);
1276                 return datalen;
1277         }
1278 }
1279
1280 static void nv_rx_process(struct net_device *dev)
1281 {
1282         struct fe_priv *np = netdev_priv(dev);
1283         u32 Flags;
1284
1285         for (;;) {
1286                 struct sk_buff *skb;
1287                 int len;
1288                 int i;
1289                 if (np->cur_rx - np->refill_rx >= RX_RING)
1290                         break;  /* we scanned the whole ring - do not continue */
1291
1292                 i = np->cur_rx % RX_RING;
1293                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1294                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1295                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1296                 } else {
1297                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1298                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1299                 }
1300
1301                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1302                                         dev->name, np->cur_rx, Flags);
1303
1304                 if (Flags & NV_RX_AVAIL)
1305                         break;  /* still owned by hardware, */
1306
1307                 /*
1308                  * the packet is for us - immediately tear down the pci mapping.
1309                  * TODO: check if a prefetch of the first cacheline improves
1310                  * the performance.
1311                  */
1312                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1313                                 np->rx_skbuff[i]->len,
1314                                 PCI_DMA_FROMDEVICE);
1315
1316                 {
1317                         int j;
1318                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1319                         for (j=0; j<64; j++) {
1320                                 if ((j%16) == 0)
1321                                         dprintk("\n%03x:", j);
1322                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1323                         }
1324                         dprintk("\n");
1325                 }
1326                 /* look at what we actually got: */
1327                 if (np->desc_ver == DESC_VER_1) {
1328                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1329                                 goto next_pkt;
1330
1331                         if (Flags & NV_RX_MISSEDFRAME) {
1332                                 np->stats.rx_missed_errors++;
1333                                 np->stats.rx_errors++;
1334                                 goto next_pkt;
1335                         }
1336                         if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1337                                 np->stats.rx_errors++;
1338                                 goto next_pkt;
1339                         }
1340                         if (Flags & NV_RX_CRCERR) {
1341                                 np->stats.rx_crc_errors++;
1342                                 np->stats.rx_errors++;
1343                                 goto next_pkt;
1344                         }
1345                         if (Flags & NV_RX_OVERFLOW) {
1346                                 np->stats.rx_over_errors++;
1347                                 np->stats.rx_errors++;
1348                                 goto next_pkt;
1349                         }
1350                         if (Flags & NV_RX_ERROR4) {
1351                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1352                                 if (len < 0) {
1353                                         np->stats.rx_errors++;
1354                                         goto next_pkt;
1355                                 }
1356                         }
1357                         /* framing errors are soft errors. */
1358                         if (Flags & NV_RX_FRAMINGERR) {
1359                                 if (Flags & NV_RX_SUBSTRACT1) {
1360                                         len--;
1361                                 }
1362                         }
1363                 } else {
1364                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1365                                 goto next_pkt;
1366
1367                         if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1368                                 np->stats.rx_errors++;
1369                                 goto next_pkt;
1370                         }
1371                         if (Flags & NV_RX2_CRCERR) {
1372                                 np->stats.rx_crc_errors++;
1373                                 np->stats.rx_errors++;
1374                                 goto next_pkt;
1375                         }
1376                         if (Flags & NV_RX2_OVERFLOW) {
1377                                 np->stats.rx_over_errors++;
1378                                 np->stats.rx_errors++;
1379                                 goto next_pkt;
1380                         }
1381                         if (Flags & NV_RX2_ERROR4) {
1382                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1383                                 if (len < 0) {
1384                                         np->stats.rx_errors++;
1385                                         goto next_pkt;
1386                                 }
1387                         }
1388                         /* framing errors are soft errors */
1389                         if (Flags & NV_RX2_FRAMINGERR) {
1390                                 if (Flags & NV_RX2_SUBSTRACT1) {
1391                                         len--;
1392                                 }
1393                         }
1394                         Flags &= NV_RX2_CHECKSUMMASK;
1395                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1396                                         Flags == NV_RX2_CHECKSUMOK2 ||
1397                                         Flags == NV_RX2_CHECKSUMOK3) {
1398                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1399                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1400                         } else {
1401                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1402                         }
1403                 }
1404                 /* got a valid packet - forward it to the network core */
1405                 skb = np->rx_skbuff[i];
1406                 np->rx_skbuff[i] = NULL;
1407
1408                 skb_put(skb, len);
1409                 skb->protocol = eth_type_trans(skb, dev);
1410                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1411                                         dev->name, np->cur_rx, len, skb->protocol);
1412                 netif_rx(skb);
1413                 dev->last_rx = jiffies;
1414                 np->stats.rx_packets++;
1415                 np->stats.rx_bytes += len;
1416 next_pkt:
1417                 np->cur_rx++;
1418         }
1419 }
1420
1421 static void set_bufsize(struct net_device *dev)
1422 {
1423         struct fe_priv *np = netdev_priv(dev);
1424
1425         if (dev->mtu <= ETH_DATA_LEN)
1426                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1427         else
1428                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1429 }
1430
1431 /*
1432  * nv_change_mtu: dev->change_mtu function
1433  * Called with dev_base_lock held for read.
1434  */
1435 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1436 {
1437         struct fe_priv *np = netdev_priv(dev);
1438         int old_mtu;
1439
1440         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1441                 return -EINVAL;
1442
1443         old_mtu = dev->mtu;
1444         dev->mtu = new_mtu;
1445
1446         /* return early if the buffer sizes will not change */
1447         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1448                 return 0;
1449         if (old_mtu == new_mtu)
1450                 return 0;
1451
1452         /* synchronized against open : rtnl_lock() held by caller */
1453         if (netif_running(dev)) {
1454                 u8 __iomem *base = get_hwbase(dev);
1455                 /*
1456                  * It seems that the nic preloads valid ring entries into an
1457                  * internal buffer. The procedure for flushing everything is
1458                  * guessed, there is probably a simpler approach.
1459                  * Changing the MTU is a rare event, it shouldn't matter.
1460                  */
1461                 disable_irq(dev->irq);
1462                 spin_lock_bh(&dev->xmit_lock);
1463                 spin_lock(&np->lock);
1464                 /* stop engines */
1465                 nv_stop_rx(dev);
1466                 nv_stop_tx(dev);
1467                 nv_txrx_reset(dev);
1468                 /* drain rx queue */
1469                 nv_drain_rx(dev);
1470                 nv_drain_tx(dev);
1471                 /* reinit driver view of the rx queue */
1472                 nv_init_rx(dev);
1473                 nv_init_tx(dev);
1474                 /* alloc new rx buffers */
1475                 set_bufsize(dev);
1476                 if (nv_alloc_rx(dev)) {
1477                         if (!np->in_shutdown)
1478                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1479                 }
1480                 /* reinit nic view of the rx queue */
1481                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1482                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1483                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1484                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1485                 else
1486                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1487                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1488                         base + NvRegRingSizes);
1489                 pci_push(base);
1490                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1491                 pci_push(base);
1492
1493                 /* restart rx engine */
1494                 nv_start_rx(dev);
1495                 nv_start_tx(dev);
1496                 spin_unlock(&np->lock);
1497                 spin_unlock_bh(&dev->xmit_lock);
1498                 enable_irq(dev->irq);
1499         }
1500         return 0;
1501 }
1502
1503 static void nv_copy_mac_to_hw(struct net_device *dev)
1504 {
1505         u8 __iomem *base = get_hwbase(dev);
1506         u32 mac[2];
1507
1508         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1509                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1510         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1511
1512         writel(mac[0], base + NvRegMacAddrA);
1513         writel(mac[1], base + NvRegMacAddrB);
1514 }
1515
1516 /*
1517  * nv_set_mac_address: dev->set_mac_address function
1518  * Called with rtnl_lock() held.
1519  */
1520 static int nv_set_mac_address(struct net_device *dev, void *addr)
1521 {
1522         struct fe_priv *np = netdev_priv(dev);
1523         struct sockaddr *macaddr = (struct sockaddr*)addr;
1524
1525         if(!is_valid_ether_addr(macaddr->sa_data))
1526                 return -EADDRNOTAVAIL;
1527
1528         /* synchronized against open : rtnl_lock() held by caller */
1529         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1530
1531         if (netif_running(dev)) {
1532                 spin_lock_bh(&dev->xmit_lock);
1533                 spin_lock_irq(&np->lock);
1534
1535                 /* stop rx engine */
1536                 nv_stop_rx(dev);
1537
1538                 /* set mac address */
1539                 nv_copy_mac_to_hw(dev);
1540
1541                 /* restart rx engine */
1542                 nv_start_rx(dev);
1543                 spin_unlock_irq(&np->lock);
1544                 spin_unlock_bh(&dev->xmit_lock);
1545         } else {
1546                 nv_copy_mac_to_hw(dev);
1547         }
1548         return 0;
1549 }
1550
1551 /*
1552  * nv_set_multicast: dev->set_multicast function
1553  * Called with dev->xmit_lock held.
1554  */
1555 static void nv_set_multicast(struct net_device *dev)
1556 {
1557         struct fe_priv *np = netdev_priv(dev);
1558         u8 __iomem *base = get_hwbase(dev);
1559         u32 addr[2];
1560         u32 mask[2];
1561         u32 pff;
1562
1563         memset(addr, 0, sizeof(addr));
1564         memset(mask, 0, sizeof(mask));
1565
1566         if (dev->flags & IFF_PROMISC) {
1567                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1568                 pff = NVREG_PFF_PROMISC;
1569         } else {
1570                 pff = NVREG_PFF_MYADDR;
1571
1572                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1573                         u32 alwaysOff[2];
1574                         u32 alwaysOn[2];
1575
1576                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1577                         if (dev->flags & IFF_ALLMULTI) {
1578                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1579                         } else {
1580                                 struct dev_mc_list *walk;
1581
1582                                 walk = dev->mc_list;
1583                                 while (walk != NULL) {
1584                                         u32 a, b;
1585                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1586                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1587                                         alwaysOn[0] &= a;
1588                                         alwaysOff[0] &= ~a;
1589                                         alwaysOn[1] &= b;
1590                                         alwaysOff[1] &= ~b;
1591                                         walk = walk->next;
1592                                 }
1593                         }
1594                         addr[0] = alwaysOn[0];
1595                         addr[1] = alwaysOn[1];
1596                         mask[0] = alwaysOn[0] | alwaysOff[0];
1597                         mask[1] = alwaysOn[1] | alwaysOff[1];
1598                 }
1599         }
1600         addr[0] |= NVREG_MCASTADDRA_FORCE;
1601         pff |= NVREG_PFF_ALWAYS;
1602         spin_lock_irq(&np->lock);
1603         nv_stop_rx(dev);
1604         writel(addr[0], base + NvRegMulticastAddrA);
1605         writel(addr[1], base + NvRegMulticastAddrB);
1606         writel(mask[0], base + NvRegMulticastMaskA);
1607         writel(mask[1], base + NvRegMulticastMaskB);
1608         writel(pff, base + NvRegPacketFilterFlags);
1609         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1610                 dev->name);
1611         nv_start_rx(dev);
1612         spin_unlock_irq(&np->lock);
1613 }
1614
1615 static int nv_update_linkspeed(struct net_device *dev)
1616 {
1617         struct fe_priv *np = netdev_priv(dev);
1618         u8 __iomem *base = get_hwbase(dev);
1619         int adv, lpa;
1620         int newls = np->linkspeed;
1621         int newdup = np->duplex;
1622         int mii_status;
1623         int retval = 0;
1624         u32 control_1000, status_1000, phyreg;
1625
1626         /* BMSR_LSTATUS is latched, read it twice:
1627          * we want the current value.
1628          */
1629         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1630         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1631
1632         if (!(mii_status & BMSR_LSTATUS)) {
1633                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1634                                 dev->name);
1635                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1636                 newdup = 0;
1637                 retval = 0;
1638                 goto set_speed;
1639         }
1640
1641         if (np->autoneg == 0) {
1642                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1643                                 dev->name, np->fixed_mode);
1644                 if (np->fixed_mode & LPA_100FULL) {
1645                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1646                         newdup = 1;
1647                 } else if (np->fixed_mode & LPA_100HALF) {
1648                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1649                         newdup = 0;
1650                 } else if (np->fixed_mode & LPA_10FULL) {
1651                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1652                         newdup = 1;
1653                 } else {
1654                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1655                         newdup = 0;
1656                 }
1657                 retval = 1;
1658                 goto set_speed;
1659         }
1660         /* check auto negotiation is complete */
1661         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1662                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1663                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1664                 newdup = 0;
1665                 retval = 0;
1666                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1667                 goto set_speed;
1668         }
1669
1670         retval = 1;
1671         if (np->gigabit == PHY_GIGABIT) {
1672                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1673                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1674
1675                 if ((control_1000 & ADVERTISE_1000FULL) &&
1676                         (status_1000 & LPA_1000FULL)) {
1677                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1678                                 dev->name);
1679                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1680                         newdup = 1;
1681                         goto set_speed;
1682                 }
1683         }
1684
1685         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1686         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1687         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1688                                 dev->name, adv, lpa);
1689
1690         /* FIXME: handle parallel detection properly */
1691         lpa = lpa & adv;
1692         if (lpa & LPA_100FULL) {
1693                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1694                 newdup = 1;
1695         } else if (lpa & LPA_100HALF) {
1696                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1697                 newdup = 0;
1698         } else if (lpa & LPA_10FULL) {
1699                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1700                 newdup = 1;
1701         } else if (lpa & LPA_10HALF) {
1702                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1703                 newdup = 0;
1704         } else {
1705                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1706                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1707                 newdup = 0;
1708         }
1709
1710 set_speed:
1711         if (np->duplex == newdup && np->linkspeed == newls)
1712                 return retval;
1713
1714         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1715                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1716
1717         np->duplex = newdup;
1718         np->linkspeed = newls;
1719
1720         if (np->gigabit == PHY_GIGABIT) {
1721                 phyreg = readl(base + NvRegRandomSeed);
1722                 phyreg &= ~(0x3FF00);
1723                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1724                         phyreg |= NVREG_RNDSEED_FORCE3;
1725                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1726                         phyreg |= NVREG_RNDSEED_FORCE2;
1727                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1728                         phyreg |= NVREG_RNDSEED_FORCE;
1729                 writel(phyreg, base + NvRegRandomSeed);
1730         }
1731
1732         phyreg = readl(base + NvRegPhyInterface);
1733         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1734         if (np->duplex == 0)
1735                 phyreg |= PHY_HALF;
1736         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1737                 phyreg |= PHY_100;
1738         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1739                 phyreg |= PHY_1000;
1740         writel(phyreg, base + NvRegPhyInterface);
1741
1742         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1743                 base + NvRegMisc1);
1744         pci_push(base);
1745         writel(np->linkspeed, base + NvRegLinkSpeed);
1746         pci_push(base);
1747
1748         return retval;
1749 }
1750
1751 static void nv_linkchange(struct net_device *dev)
1752 {
1753         if (nv_update_linkspeed(dev)) {
1754                 if (netif_carrier_ok(dev)) {
1755                         nv_stop_rx(dev);
1756                 } else {
1757                         netif_carrier_on(dev);
1758                         printk(KERN_INFO "%s: link up.\n", dev->name);
1759                 }
1760                 nv_start_rx(dev);
1761         } else {
1762                 if (netif_carrier_ok(dev)) {
1763                         netif_carrier_off(dev);
1764                         printk(KERN_INFO "%s: link down.\n", dev->name);
1765                         nv_stop_rx(dev);
1766                 }
1767         }
1768 }
1769
1770 static void nv_link_irq(struct net_device *dev)
1771 {
1772         u8 __iomem *base = get_hwbase(dev);
1773         u32 miistat;
1774
1775         miistat = readl(base + NvRegMIIStatus);
1776         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1777         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1778
1779         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1780                 nv_linkchange(dev);
1781         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1782 }
1783
1784 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1785 {
1786         struct net_device *dev = (struct net_device *) data;
1787         struct fe_priv *np = netdev_priv(dev);
1788         u8 __iomem *base = get_hwbase(dev);
1789         u32 events;
1790         int i;
1791
1792         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1793
1794         for (i=0; ; i++) {
1795                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1796                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1797                 pci_push(base);
1798                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1799                 if (!(events & np->irqmask))
1800                         break;
1801
1802                 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
1803                         spin_lock(&np->lock);
1804                         nv_tx_done(dev);
1805                         spin_unlock(&np->lock);
1806                 }
1807
1808                 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1809                         nv_rx_process(dev);
1810                         if (nv_alloc_rx(dev)) {
1811                                 spin_lock(&np->lock);
1812                                 if (!np->in_shutdown)
1813                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1814                                 spin_unlock(&np->lock);
1815                         }
1816                 }
1817
1818                 if (events & NVREG_IRQ_LINK) {
1819                         spin_lock(&np->lock);
1820                         nv_link_irq(dev);
1821                         spin_unlock(&np->lock);
1822                 }
1823                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1824                         spin_lock(&np->lock);
1825                         nv_linkchange(dev);
1826                         spin_unlock(&np->lock);
1827                         np->link_timeout = jiffies + LINK_TIMEOUT;
1828                 }
1829                 if (events & (NVREG_IRQ_TX_ERR)) {
1830                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1831                                                 dev->name, events);
1832                 }
1833                 if (events & (NVREG_IRQ_UNKNOWN)) {
1834                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1835                                                 dev->name, events);
1836                 }
1837                 if (i > max_interrupt_work) {
1838                         spin_lock(&np->lock);
1839                         /* disable interrupts on the nic */
1840                         writel(0, base + NvRegIrqMask);
1841                         pci_push(base);
1842
1843                         if (!np->in_shutdown)
1844                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1845                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1846                         spin_unlock(&np->lock);
1847                         break;
1848                 }
1849
1850         }
1851         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1852
1853         return IRQ_RETVAL(i);
1854 }
1855
1856 static void nv_do_nic_poll(unsigned long data)
1857 {
1858         struct net_device *dev = (struct net_device *) data;
1859         struct fe_priv *np = netdev_priv(dev);
1860         u8 __iomem *base = get_hwbase(dev);
1861
1862         disable_irq(dev->irq);
1863         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1864         /*
1865          * reenable interrupts on the nic, we have to do this before calling
1866          * nv_nic_irq because that may decide to do otherwise
1867          */
1868         writel(np->irqmask, base + NvRegIrqMask);
1869         pci_push(base);
1870         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1871         enable_irq(dev->irq);
1872 }
1873
1874 #ifdef CONFIG_NET_POLL_CONTROLLER
1875 static void nv_poll_controller(struct net_device *dev)
1876 {
1877         nv_do_nic_poll((unsigned long) dev);
1878 }
1879 #endif
1880
1881 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1882 {
1883         struct fe_priv *np = netdev_priv(dev);
1884         strcpy(info->driver, "forcedeth");
1885         strcpy(info->version, FORCEDETH_VERSION);
1886         strcpy(info->bus_info, pci_name(np->pci_dev));
1887 }
1888
1889 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1890 {
1891         struct fe_priv *np = netdev_priv(dev);
1892         wolinfo->supported = WAKE_MAGIC;
1893
1894         spin_lock_irq(&np->lock);
1895         if (np->wolenabled)
1896                 wolinfo->wolopts = WAKE_MAGIC;
1897         spin_unlock_irq(&np->lock);
1898 }
1899
1900 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1901 {
1902         struct fe_priv *np = netdev_priv(dev);
1903         u8 __iomem *base = get_hwbase(dev);
1904
1905         spin_lock_irq(&np->lock);
1906         if (wolinfo->wolopts == 0) {
1907                 writel(0, base + NvRegWakeUpFlags);
1908                 np->wolenabled = 0;
1909         }
1910         if (wolinfo->wolopts & WAKE_MAGIC) {
1911                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1912                 np->wolenabled = 1;
1913         }
1914         spin_unlock_irq(&np->lock);
1915         return 0;
1916 }
1917
1918 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1919 {
1920         struct fe_priv *np = netdev_priv(dev);
1921         int adv;
1922
1923         spin_lock_irq(&np->lock);
1924         ecmd->port = PORT_MII;
1925         if (!netif_running(dev)) {
1926                 /* We do not track link speed / duplex setting if the
1927                  * interface is disabled. Force a link check */
1928                 nv_update_linkspeed(dev);
1929         }
1930         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1931                 case NVREG_LINKSPEED_10:
1932                         ecmd->speed = SPEED_10;
1933                         break;
1934                 case NVREG_LINKSPEED_100:
1935                         ecmd->speed = SPEED_100;
1936                         break;
1937                 case NVREG_LINKSPEED_1000:
1938                         ecmd->speed = SPEED_1000;
1939                         break;
1940         }
1941         ecmd->duplex = DUPLEX_HALF;
1942         if (np->duplex)
1943                 ecmd->duplex = DUPLEX_FULL;
1944
1945         ecmd->autoneg = np->autoneg;
1946
1947         ecmd->advertising = ADVERTISED_MII;
1948         if (np->autoneg) {
1949                 ecmd->advertising |= ADVERTISED_Autoneg;
1950                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1951         } else {
1952                 adv = np->fixed_mode;
1953         }
1954         if (adv & ADVERTISE_10HALF)
1955                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1956         if (adv & ADVERTISE_10FULL)
1957                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1958         if (adv & ADVERTISE_100HALF)
1959                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1960         if (adv & ADVERTISE_100FULL)
1961                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1962         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1963                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1964                 if (adv & ADVERTISE_1000FULL)
1965                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
1966         }
1967
1968         ecmd->supported = (SUPPORTED_Autoneg |
1969                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1970                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1971                 SUPPORTED_MII);
1972         if (np->gigabit == PHY_GIGABIT)
1973                 ecmd->supported |= SUPPORTED_1000baseT_Full;
1974
1975         ecmd->phy_address = np->phyaddr;
1976         ecmd->transceiver = XCVR_EXTERNAL;
1977
1978         /* ignore maxtxpkt, maxrxpkt for now */
1979         spin_unlock_irq(&np->lock);
1980         return 0;
1981 }
1982
1983 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1984 {
1985         struct fe_priv *np = netdev_priv(dev);
1986
1987         if (ecmd->port != PORT_MII)
1988                 return -EINVAL;
1989         if (ecmd->transceiver != XCVR_EXTERNAL)
1990                 return -EINVAL;
1991         if (ecmd->phy_address != np->phyaddr) {
1992                 /* TODO: support switching between multiple phys. Should be
1993                  * trivial, but not enabled due to lack of test hardware. */
1994                 return -EINVAL;
1995         }
1996         if (ecmd->autoneg == AUTONEG_ENABLE) {
1997                 u32 mask;
1998
1999                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2000                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2001                 if (np->gigabit == PHY_GIGABIT)
2002                         mask |= ADVERTISED_1000baseT_Full;
2003
2004                 if ((ecmd->advertising & mask) == 0)
2005                         return -EINVAL;
2006
2007         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2008                 /* Note: autonegotiation disable, speed 1000 intentionally
2009                  * forbidden - noone should need that. */
2010
2011                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2012                         return -EINVAL;
2013                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2014                         return -EINVAL;
2015         } else {
2016                 return -EINVAL;
2017         }
2018
2019         spin_lock_irq(&np->lock);
2020         if (ecmd->autoneg == AUTONEG_ENABLE) {
2021                 int adv, bmcr;
2022
2023                 np->autoneg = 1;
2024
2025                 /* advertise only what has been requested */
2026                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2027                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2028                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2029                         adv |= ADVERTISE_10HALF;
2030                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2031                         adv |= ADVERTISE_10FULL;
2032                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2033                         adv |= ADVERTISE_100HALF;
2034                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2035                         adv |= ADVERTISE_100FULL;
2036                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2037
2038                 if (np->gigabit == PHY_GIGABIT) {
2039                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2040                         adv &= ~ADVERTISE_1000FULL;
2041                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2042                                 adv |= ADVERTISE_1000FULL;
2043                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2044                 }
2045
2046                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2047                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2048                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2049
2050         } else {
2051                 int adv, bmcr;
2052
2053                 np->autoneg = 0;
2054
2055                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2056                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2057                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2058                         adv |= ADVERTISE_10HALF;
2059                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2060                         adv |= ADVERTISE_10FULL;
2061                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2062                         adv |= ADVERTISE_100HALF;
2063                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2064                         adv |= ADVERTISE_100FULL;
2065                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2066                 np->fixed_mode = adv;
2067
2068                 if (np->gigabit == PHY_GIGABIT) {
2069                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2070                         adv &= ~ADVERTISE_1000FULL;
2071                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2072                 }
2073
2074                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2075                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2076                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2077                         bmcr |= BMCR_FULLDPLX;
2078                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2079                         bmcr |= BMCR_SPEED100;
2080                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2081
2082                 if (netif_running(dev)) {
2083                         /* Wait a bit and then reconfigure the nic. */
2084                         udelay(10);
2085                         nv_linkchange(dev);
2086                 }
2087         }
2088         spin_unlock_irq(&np->lock);
2089
2090         return 0;
2091 }
2092
2093 #define FORCEDETH_REGS_VER      1
2094 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
2095
2096 static int nv_get_regs_len(struct net_device *dev)
2097 {
2098         return FORCEDETH_REGS_SIZE;
2099 }
2100
2101 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2102 {
2103         struct fe_priv *np = netdev_priv(dev);
2104         u8 __iomem *base = get_hwbase(dev);
2105         u32 *rbuf = buf;
2106         int i;
2107
2108         regs->version = FORCEDETH_REGS_VER;
2109         spin_lock_irq(&np->lock);
2110         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2111                 rbuf[i] = readl(base + i*sizeof(u32));
2112         spin_unlock_irq(&np->lock);
2113 }
2114
2115 static int nv_nway_reset(struct net_device *dev)
2116 {
2117         struct fe_priv *np = netdev_priv(dev);
2118         int ret;
2119
2120         spin_lock_irq(&np->lock);
2121         if (np->autoneg) {
2122                 int bmcr;
2123
2124                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2125                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2126                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2127
2128                 ret = 0;
2129         } else {
2130                 ret = -EINVAL;
2131         }
2132         spin_unlock_irq(&np->lock);
2133
2134         return ret;
2135 }
2136
2137 static struct ethtool_ops ops = {
2138         .get_drvinfo = nv_get_drvinfo,
2139         .get_link = ethtool_op_get_link,
2140         .get_wol = nv_get_wol,
2141         .set_wol = nv_set_wol,
2142         .get_settings = nv_get_settings,
2143         .set_settings = nv_set_settings,
2144         .get_regs_len = nv_get_regs_len,
2145         .get_regs = nv_get_regs,
2146         .nway_reset = nv_nway_reset,
2147         .get_perm_addr = ethtool_op_get_perm_addr,
2148 };
2149
2150 static int nv_open(struct net_device *dev)
2151 {
2152         struct fe_priv *np = netdev_priv(dev);
2153         u8 __iomem *base = get_hwbase(dev);
2154         int ret, oom, i;
2155
2156         dprintk(KERN_DEBUG "nv_open: begin\n");
2157
2158         /* 1) erase previous misconfiguration */
2159         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2160         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2161         writel(0, base + NvRegMulticastAddrB);
2162         writel(0, base + NvRegMulticastMaskA);
2163         writel(0, base + NvRegMulticastMaskB);
2164         writel(0, base + NvRegPacketFilterFlags);
2165
2166         writel(0, base + NvRegTransmitterControl);
2167         writel(0, base + NvRegReceiverControl);
2168
2169         writel(0, base + NvRegAdapterControl);
2170
2171         /* 2) initialize descriptor rings */
2172         set_bufsize(dev);
2173         oom = nv_init_ring(dev);
2174
2175         writel(0, base + NvRegLinkSpeed);
2176         writel(0, base + NvRegUnknownTransmitterReg);
2177         nv_txrx_reset(dev);
2178         writel(0, base + NvRegUnknownSetupReg6);
2179
2180         np->in_shutdown = 0;
2181
2182         /* 3) set mac address */
2183         nv_copy_mac_to_hw(dev);
2184
2185         /* 4) give hw rings */
2186         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2187         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2188                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2189         else
2190                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2191         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2192                 base + NvRegRingSizes);
2193
2194         /* 5) continue setup */
2195         writel(np->linkspeed, base + NvRegLinkSpeed);
2196         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2197         writel(np->txrxctl_bits, base + NvRegTxRxControl);
2198         pci_push(base);
2199         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2200         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2201                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2202                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2203
2204         writel(0, base + NvRegUnknownSetupReg4);
2205         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2206         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2207
2208         /* 6) continue setup */
2209         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2210         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2211         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2212         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2213
2214         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2215         get_random_bytes(&i, sizeof(i));
2216         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2217         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2218         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2219         writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2220         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2221         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2222                         base + NvRegAdapterControl);
2223         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2224         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2225         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2226
2227         i = readl(base + NvRegPowerState);
2228         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2229                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2230
2231         pci_push(base);
2232         udelay(10);
2233         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2234
2235         writel(0, base + NvRegIrqMask);
2236         pci_push(base);
2237         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2238         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2239         pci_push(base);
2240
2241         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2242         if (ret)
2243                 goto out_drain;
2244
2245         /* ask for interrupts */
2246         writel(np->irqmask, base + NvRegIrqMask);
2247
2248         spin_lock_irq(&np->lock);
2249         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2250         writel(0, base + NvRegMulticastAddrB);
2251         writel(0, base + NvRegMulticastMaskA);
2252         writel(0, base + NvRegMulticastMaskB);
2253         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2254         /* One manual link speed update: Interrupts are enabled, future link
2255          * speed changes cause interrupts and are handled by nv_link_irq().
2256          */
2257         {
2258                 u32 miistat;
2259                 miistat = readl(base + NvRegMIIStatus);
2260                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2261                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2262         }
2263         /* set linkspeed to invalid value, thus force nv_update_linkspeed
2264          * to init hw */
2265         np->linkspeed = 0;
2266         ret = nv_update_linkspeed(dev);
2267         nv_start_rx(dev);
2268         nv_start_tx(dev);
2269         netif_start_queue(dev);
2270         if (ret) {
2271                 netif_carrier_on(dev);
2272         } else {
2273                 printk("%s: no link during initialization.\n", dev->name);
2274                 netif_carrier_off(dev);
2275         }
2276         if (oom)
2277                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2278         spin_unlock_irq(&np->lock);
2279
2280         return 0;
2281 out_drain:
2282         drain_ring(dev);
2283         return ret;
2284 }
2285
2286 static int nv_close(struct net_device *dev)
2287 {
2288         struct fe_priv *np = netdev_priv(dev);
2289         u8 __iomem *base;
2290
2291         spin_lock_irq(&np->lock);
2292         np->in_shutdown = 1;
2293         spin_unlock_irq(&np->lock);
2294         synchronize_irq(dev->irq);
2295
2296         del_timer_sync(&np->oom_kick);
2297         del_timer_sync(&np->nic_poll);
2298
2299         netif_stop_queue(dev);
2300         spin_lock_irq(&np->lock);
2301         nv_stop_tx(dev);
2302         nv_stop_rx(dev);
2303         nv_txrx_reset(dev);
2304
2305         /* disable interrupts on the nic or we will lock up */
2306         base = get_hwbase(dev);
2307         writel(0, base + NvRegIrqMask);
2308         pci_push(base);
2309         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2310
2311         spin_unlock_irq(&np->lock);
2312
2313         free_irq(dev->irq, dev);
2314
2315         drain_ring(dev);
2316
2317         if (np->wolenabled)
2318                 nv_start_rx(dev);
2319
2320         /* special op: write back the misordered MAC address - otherwise
2321          * the next nv_probe would see a wrong address.
2322          */
2323         writel(np->orig_mac[0], base + NvRegMacAddrA);
2324         writel(np->orig_mac[1], base + NvRegMacAddrB);
2325
2326         /* FIXME: power down nic */
2327
2328         return 0;
2329 }
2330
2331 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2332 {
2333         struct net_device *dev;
2334         struct fe_priv *np;
2335         unsigned long addr;
2336         u8 __iomem *base;
2337         int err, i;
2338
2339         dev = alloc_etherdev(sizeof(struct fe_priv));
2340         err = -ENOMEM;
2341         if (!dev)
2342                 goto out;
2343
2344         np = netdev_priv(dev);
2345         np->pci_dev = pci_dev;
2346         spin_lock_init(&np->lock);
2347         SET_MODULE_OWNER(dev);
2348         SET_NETDEV_DEV(dev, &pci_dev->dev);
2349
2350         init_timer(&np->oom_kick);
2351         np->oom_kick.data = (unsigned long) dev;
2352         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2353         init_timer(&np->nic_poll);
2354         np->nic_poll.data = (unsigned long) dev;
2355         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2356
2357         err = pci_enable_device(pci_dev);
2358         if (err) {
2359                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2360                                 err, pci_name(pci_dev));
2361                 goto out_free;
2362         }
2363
2364         pci_set_master(pci_dev);
2365
2366         err = pci_request_regions(pci_dev, DRV_NAME);
2367         if (err < 0)
2368                 goto out_disable;
2369
2370         err = -EINVAL;
2371         addr = 0;
2372         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2373                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2374                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2375                                 pci_resource_len(pci_dev, i),
2376                                 pci_resource_flags(pci_dev, i));
2377                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2378                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2379                         addr = pci_resource_start(pci_dev, i);
2380                         break;
2381                 }
2382         }
2383         if (i == DEVICE_COUNT_RESOURCE) {
2384                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2385                                         pci_name(pci_dev));
2386                 goto out_relreg;
2387         }
2388
2389         /* handle different descriptor versions */
2390         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2391                 /* packet format 3: supports 40-bit addressing */
2392                 np->desc_ver = DESC_VER_3;
2393                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2394                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2395                                         pci_name(pci_dev));
2396                 } else {
2397                         dev->features |= NETIF_F_HIGHDMA;
2398                 }
2399                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2400         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2401                 /* packet format 2: supports jumbo frames */
2402                 np->desc_ver = DESC_VER_2;
2403                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2404         } else {
2405                 /* original packet format */
2406                 np->desc_ver = DESC_VER_1;
2407                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2408         }
2409
2410         np->pkt_limit = NV_PKTLIMIT_1;
2411         if (id->driver_data & DEV_HAS_LARGEDESC)
2412                 np->pkt_limit = NV_PKTLIMIT_2;
2413
2414         if (id->driver_data & DEV_HAS_CHECKSUM) {
2415                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2416                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2417 #ifdef NETIF_F_TSO
2418                 dev->features |= NETIF_F_TSO;
2419 #endif
2420         }
2421
2422         err = -ENOMEM;
2423         np->base = ioremap(addr, NV_PCI_REGSZ);
2424         if (!np->base)
2425                 goto out_relreg;
2426         dev->base_addr = (unsigned long)np->base;
2427
2428         dev->irq = pci_dev->irq;
2429
2430         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2431                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2432                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2433                                         &np->ring_addr);
2434                 if (!np->rx_ring.orig)
2435                         goto out_unmap;
2436                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2437         } else {
2438                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2439                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2440                                         &np->ring_addr);
2441                 if (!np->rx_ring.ex)
2442                         goto out_unmap;
2443                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2444         }
2445
2446         dev->open = nv_open;
2447         dev->stop = nv_close;
2448         dev->hard_start_xmit = nv_start_xmit;
2449         dev->get_stats = nv_get_stats;
2450         dev->change_mtu = nv_change_mtu;
2451         dev->set_mac_address = nv_set_mac_address;
2452         dev->set_multicast_list = nv_set_multicast;
2453 #ifdef CONFIG_NET_POLL_CONTROLLER
2454         dev->poll_controller = nv_poll_controller;
2455 #endif
2456         SET_ETHTOOL_OPS(dev, &ops);
2457         dev->tx_timeout = nv_tx_timeout;
2458         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2459
2460         pci_set_drvdata(pci_dev, dev);
2461
2462         /* read the mac address */
2463         base = get_hwbase(dev);
2464         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2465         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2466
2467         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2468         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2469         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2470         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2471         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2472         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2473         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2474
2475         if (!is_valid_ether_addr(dev->perm_addr)) {
2476                 /*
2477                  * Bad mac address. At least one bios sets the mac address
2478                  * to 01:23:45:67:89:ab
2479                  */
2480                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2481                         pci_name(pci_dev),
2482                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2483                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2484                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2485                 dev->dev_addr[0] = 0x00;
2486                 dev->dev_addr[1] = 0x00;
2487                 dev->dev_addr[2] = 0x6c;
2488                 get_random_bytes(&dev->dev_addr[3], 3);
2489         }
2490
2491         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2492                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2493                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2494
2495         /* disable WOL */
2496         writel(0, base + NvRegWakeUpFlags);
2497         np->wolenabled = 0;
2498
2499         if (np->desc_ver == DESC_VER_1) {
2500                 np->tx_flags = NV_TX_VALID;
2501         } else {
2502                 np->tx_flags = NV_TX2_VALID;
2503         }
2504         np->irqmask = NVREG_IRQMASK_WANTED;
2505         if (id->driver_data & DEV_NEED_TIMERIRQ)
2506                 np->irqmask |= NVREG_IRQ_TIMER;
2507         if (id->driver_data & DEV_NEED_LINKTIMER) {
2508                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2509                 np->need_linktimer = 1;
2510                 np->link_timeout = jiffies + LINK_TIMEOUT;
2511         } else {
2512                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2513                 np->need_linktimer = 0;
2514         }
2515
2516         /* find a suitable phy */
2517         for (i = 1; i < 32; i++) {
2518                 int id1, id2;
2519
2520                 spin_lock_irq(&np->lock);
2521                 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2522                 spin_unlock_irq(&np->lock);
2523                 if (id1 < 0 || id1 == 0xffff)
2524                         continue;
2525                 spin_lock_irq(&np->lock);
2526                 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2527                 spin_unlock_irq(&np->lock);
2528                 if (id2 < 0 || id2 == 0xffff)
2529                         continue;
2530
2531                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2532                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2533                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2534                                 pci_name(pci_dev), id1, id2, i);
2535                 np->phyaddr = i;
2536                 np->phy_oui = id1 | id2;
2537                 break;
2538         }
2539         if (i == 32) {
2540                 /* PHY in isolate mode? No phy attached and user wants to
2541                  * test loopback? Very odd, but can be correct.
2542                  */
2543                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2544                                 pci_name(pci_dev));
2545         }
2546
2547         if (i != 32) {
2548                 /* reset it */
2549                 phy_init(dev);
2550         }
2551
2552         /* set default link speed settings */
2553         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2554         np->duplex = 0;
2555         np->autoneg = 1;
2556
2557         err = register_netdev(dev);
2558         if (err) {
2559                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2560                 goto out_freering;
2561         }
2562         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2563                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2564                         pci_name(pci_dev));
2565
2566         return 0;
2567
2568 out_freering:
2569         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2570                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2571                                     np->rx_ring.orig, np->ring_addr);
2572         else
2573                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2574                                     np->rx_ring.ex, np->ring_addr);
2575         pci_set_drvdata(pci_dev, NULL);
2576 out_unmap:
2577         iounmap(get_hwbase(dev));
2578 out_relreg:
2579         pci_release_regions(pci_dev);
2580 out_disable:
2581         pci_disable_device(pci_dev);
2582 out_free:
2583         free_netdev(dev);
2584 out:
2585         return err;
2586 }
2587
2588 static void __devexit nv_remove(struct pci_dev *pci_dev)
2589 {
2590         struct net_device *dev = pci_get_drvdata(pci_dev);
2591         struct fe_priv *np = netdev_priv(dev);
2592
2593         unregister_netdev(dev);
2594
2595         /* free all structures */
2596         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2597                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2598         else
2599                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2600         iounmap(get_hwbase(dev));
2601         pci_release_regions(pci_dev);
2602         pci_disable_device(pci_dev);
2603         free_netdev(dev);
2604         pci_set_drvdata(pci_dev, NULL);
2605 }
2606
2607 static struct pci_device_id pci_tbl[] = {
2608         {       /* nForce Ethernet Controller */
2609                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2610                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2611         },
2612         {       /* nForce2 Ethernet Controller */
2613                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2614                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2615         },
2616         {       /* nForce3 Ethernet Controller */
2617                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2618                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2619         },
2620         {       /* nForce3 Ethernet Controller */
2621                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2622                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2623         },
2624         {       /* nForce3 Ethernet Controller */
2625                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2626                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2627         },
2628         {       /* nForce3 Ethernet Controller */
2629                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2630                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2631         },
2632         {       /* nForce3 Ethernet Controller */
2633                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2634                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2635         },
2636         {       /* CK804 Ethernet Controller */
2637                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2638                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2639         },
2640         {       /* CK804 Ethernet Controller */
2641                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2642                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2643         },
2644         {       /* MCP04 Ethernet Controller */
2645                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2646                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2647         },
2648         {       /* MCP04 Ethernet Controller */
2649                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2650                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2651         },
2652         {       /* MCP51 Ethernet Controller */
2653                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2654                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2655         },
2656         {       /* MCP51 Ethernet Controller */
2657                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2658                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2659         },
2660         {       /* MCP55 Ethernet Controller */
2661                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2662                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2663         },
2664         {       /* MCP55 Ethernet Controller */
2665                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2666                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2667         },
2668         {0,},
2669 };
2670
2671 static struct pci_driver driver = {
2672         .name = "forcedeth",
2673         .id_table = pci_tbl,
2674         .probe = nv_probe,
2675         .remove = __devexit_p(nv_remove),
2676 };
2677
2678
2679 static int __init init_nic(void)
2680 {
2681         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2682         return pci_module_init(&driver);
2683 }
2684
2685 static void __exit exit_nic(void)
2686 {
2687         pci_unregister_driver(&driver);
2688 }
2689
2690 module_param(max_interrupt_work, int, 0);
2691 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2692
2693 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2694 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2695 MODULE_LICENSE("GPL");
2696
2697 MODULE_DEVICE_TABLE(pci, pci_tbl);
2698
2699 module_init(init_nic);
2700 module_exit(exit_nic);