git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define DR7_GD_MASK (1 << 13)
  42 #define DR6_BD_MASK (1 << 13)
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50
  51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  52
  53 /* Turn on to get debugging output*/
  54 /* #define NESTED_DEBUG */
  55
  56 #ifdef NESTED_DEBUG
  57 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  58 #else
  59 #define nsvm_printk(fmt, args...) do {} while(0)
  60 #endif
  61
  62 /* enable NPT for AMD64 and X86 with PAE */
  63 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  64 static bool npt_enabled = true;
  65 #else
  66 static bool npt_enabled = false;
  67 #endif
  68 static int npt = 1;
  69
  70 module_param(npt, int, S_IRUGO);
  71
  72 static void kvm_reput_irq(struct vcpu_svm *svm);
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  76 {
  77         return container_of(vcpu, struct vcpu_svm, vcpu);
  78 }
  79
  80 static unsigned long iopm_base;
  81
  82 struct kvm_ldttss_desc {
  83         u16 limit0;
  84         u16 base0;
  85         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  86         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  87         u32 base3;
  88         u32 zero1;
  89 } __attribute__((packed));
  90
  91 struct svm_cpu_data {
  92         int cpu;
  93
  94         u64 asid_generation;
  95         u32 max_asid;
  96         u32 next_asid;
  97         struct kvm_ldttss_desc *tss_desc;
  98
  99         struct page *save_area;
 100 };
 101
 102 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 103 static uint32_t svm_features;
 104
 105 struct svm_init_data {
 106         int cpu;
 107         int r;
 108 };
 109
 110 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 111
 112 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 113 #define MSRS_RANGE_SIZE 2048
 114 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 115
 116 #define MAX_INST_SIZE 15
 117
 118 static inline u32 svm_has(u32 feat)
 119 {
 120         return svm_features & feat;
 121 }
 122
 123 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 124 {
 125         int word_index = __ffs(vcpu->arch.irq_summary);
 126         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 127         int irq = word_index * BITS_PER_LONG + bit_index;
 128
 129         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 130         if (!vcpu->arch.irq_pending[word_index])
 131                 clear_bit(word_index, &vcpu->arch.irq_summary);
 132         return irq;
 133 }
 134
 135 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 136 {
 137         set_bit(irq, vcpu->arch.irq_pending);
 138         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 139 }
 140
 141 static inline void clgi(void)
 142 {
 143         asm volatile (__ex(SVM_CLGI));
 144 }
 145
 146 static inline void stgi(void)
 147 {
 148         asm volatile (__ex(SVM_STGI));
 149 }
 150
 151 static inline void invlpga(unsigned long addr, u32 asid)
 152 {
 153         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 154 }
 155
 156 static inline unsigned long kvm_read_cr2(void)
 157 {
 158         unsigned long cr2;
 159
 160         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 161         return cr2;
 162 }
 163
 164 static inline void kvm_write_cr2(unsigned long val)
 165 {
 166         asm volatile ("mov %0, %%cr2" :: "r" (val));
 167 }
 168
 169 static inline unsigned long read_dr6(void)
 170 {
 171         unsigned long dr6;
 172
 173         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 174         return dr6;
 175 }
 176
 177 static inline void write_dr6(unsigned long val)
 178 {
 179         asm volatile ("mov %0, %%dr6" :: "r" (val));
 180 }
 181
 182 static inline unsigned long read_dr7(void)
 183 {
 184         unsigned long dr7;
 185
 186         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 187         return dr7;
 188 }
 189
 190 static inline void write_dr7(unsigned long val)
 191 {
 192         asm volatile ("mov %0, %%dr7" :: "r" (val));
 193 }
 194
 195 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 196 {
 197         to_svm(vcpu)->asid_generation--;
 198 }
 199
 200 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 201 {
 202         force_new_asid(vcpu);
 203 }
 204
 205 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 206 {
 207         if (!npt_enabled && !(efer & EFER_LMA))
 208                 efer &= ~EFER_LME;
 209
 210         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 211         vcpu->arch.shadow_efer = efer;
 212 }
 213
 214 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 215                                 bool has_error_code, u32 error_code)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         svm->vmcb->control.event_inj = nr
 220                 | SVM_EVTINJ_VALID
 221                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 222                 | SVM_EVTINJ_TYPE_EXEPT;
 223         svm->vmcb->control.event_inj_err = error_code;
 224 }
 225
 226 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_svm *svm = to_svm(vcpu);
 229
 230         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 231 }
 232
 233 static int is_external_interrupt(u32 info)
 234 {
 235         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 236         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 237 }
 238
 239 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 240 {
 241         struct vcpu_svm *svm = to_svm(vcpu);
 242
 243         if (!svm->next_rip) {
 244                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 245                 return;
 246         }
 247         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 248                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 249                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 250
 251         kvm_rip_write(vcpu, svm->next_rip);
 252         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 253
 254         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 255 }
 256
 257 static int has_svm(void)
 258 {
 259         const char *msg;
 260
 261         if (!cpu_has_svm(&msg)) {
 262                 printk(KERN_INFO "has_svn: %s\n", msg);
 263                 return 0;
 264         }
 265
 266         return 1;
 267 }
 268
 269 static void svm_hardware_disable(void *garbage)
 270 {
 271         cpu_svm_disable();
 272 }
 273
 274 static void svm_hardware_enable(void *garbage)
 275 {
 276
 277         struct svm_cpu_data *svm_data;
 278         uint64_t efer;
 279         struct desc_ptr gdt_descr;
 280         struct desc_struct *gdt;
 281         int me = raw_smp_processor_id();
 282
 283         if (!has_svm()) {
 284                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 285                 return;
 286         }
 287         svm_data = per_cpu(svm_data, me);
 288
 289         if (!svm_data) {
 290                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 291                        me);
 292                 return;
 293         }
 294
 295         svm_data->asid_generation = 1;
 296         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 297         svm_data->next_asid = svm_data->max_asid + 1;
 298
 299         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 300         gdt = (struct desc_struct *)gdt_descr.address;
 301         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 302
 303         rdmsrl(MSR_EFER, efer);
 304         wrmsrl(MSR_EFER, efer | EFER_SVME);
 305
 306         wrmsrl(MSR_VM_HSAVE_PA,
 307                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 308 }
 309
 310 static void svm_cpu_uninit(int cpu)
 311 {
 312         struct svm_cpu_data *svm_data
 313                 = per_cpu(svm_data, raw_smp_processor_id());
 314
 315         if (!svm_data)
 316                 return;
 317
 318         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 319         __free_page(svm_data->save_area);
 320         kfree(svm_data);
 321 }
 322
 323 static int svm_cpu_init(int cpu)
 324 {
 325         struct svm_cpu_data *svm_data;
 326         int r;
 327
 328         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 329         if (!svm_data)
 330                 return -ENOMEM;
 331         svm_data->cpu = cpu;
 332         svm_data->save_area = alloc_page(GFP_KERNEL);
 333         r = -ENOMEM;
 334         if (!svm_data->save_area)
 335                 goto err_1;
 336
 337         per_cpu(svm_data, cpu) = svm_data;
 338
 339         return 0;
 340
 341 err_1:
 342         kfree(svm_data);
 343         return r;
 344
 345 }
 346
 347 static void set_msr_interception(u32 *msrpm, unsigned msr,
 348                                  int read, int write)
 349 {
 350         int i;
 351
 352         for (i = 0; i < NUM_MSR_MAPS; i++) {
 353                 if (msr >= msrpm_ranges[i] &&
 354                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 355                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 356                                           msrpm_ranges[i]) * 2;
 357
 358                         u32 *base = msrpm + (msr_offset / 32);
 359                         u32 msr_shift = msr_offset % 32;
 360                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 361                         *base = (*base & ~(0x3 << msr_shift)) |
 362                                 (mask << msr_shift);
 363                         return;
 364                 }
 365         }
 366         BUG();
 367 }
 368
 369 static void svm_vcpu_init_msrpm(u32 *msrpm)
 370 {
 371         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 372
 373 #ifdef CONFIG_X86_64
 374         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 375         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 376         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 377         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 378         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 379         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 380 #endif
 381         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 382         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 383         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 385 }
 386
 387 static void svm_enable_lbrv(struct vcpu_svm *svm)
 388 {
 389         u32 *msrpm = svm->msrpm;
 390
 391         svm->vmcb->control.lbr_ctl = 1;
 392         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 393         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 394         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 395         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 396 }
 397
 398 static void svm_disable_lbrv(struct vcpu_svm *svm)
 399 {
 400         u32 *msrpm = svm->msrpm;
 401
 402         svm->vmcb->control.lbr_ctl = 0;
 403         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 404         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 405         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 406         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 407 }
 408
 409 static __init int svm_hardware_setup(void)
 410 {
 411         int cpu;
 412         struct page *iopm_pages;
 413         void *iopm_va;
 414         int r;
 415
 416         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 417
 418         if (!iopm_pages)
 419                 return -ENOMEM;
 420
 421         iopm_va = page_address(iopm_pages);
 422         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 423         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 424         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 425
 426         if (boot_cpu_has(X86_FEATURE_NX))
 427                 kvm_enable_efer_bits(EFER_NX);
 428
 429         for_each_online_cpu(cpu) {
 430                 r = svm_cpu_init(cpu);
 431                 if (r)
 432                         goto err;
 433         }
 434
 435         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 436
 437         if (!svm_has(SVM_FEATURE_NPT))
 438                 npt_enabled = false;
 439
 440         if (npt_enabled && !npt) {
 441                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 442                 npt_enabled = false;
 443         }
 444
 445         if (npt_enabled) {
 446                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 447                 kvm_enable_tdp();
 448         } else
 449                 kvm_disable_tdp();
 450
 451         return 0;
 452
 453 err:
 454         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 455         iopm_base = 0;
 456         return r;
 457 }
 458
 459 static __exit void svm_hardware_unsetup(void)
 460 {
 461         int cpu;
 462
 463         for_each_online_cpu(cpu)
 464                 svm_cpu_uninit(cpu);
 465
 466         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 467         iopm_base = 0;
 468 }
 469
 470 static void init_seg(struct vmcb_seg *seg)
 471 {
 472         seg->selector = 0;
 473         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 474                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 475         seg->limit = 0xffff;
 476         seg->base = 0;
 477 }
 478
 479 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 480 {
 481         seg->selector = 0;
 482         seg->attrib = SVM_SELECTOR_P_MASK | type;
 483         seg->limit = 0xffff;
 484         seg->base = 0;
 485 }
 486
 487 static void init_vmcb(struct vcpu_svm *svm)
 488 {
 489         struct vmcb_control_area *control = &svm->vmcb->control;
 490         struct vmcb_save_area *save = &svm->vmcb->save;
 491
 492         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 493                                         INTERCEPT_CR3_MASK |
 494                                         INTERCEPT_CR4_MASK;
 495
 496         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 497                                         INTERCEPT_CR3_MASK |
 498                                         INTERCEPT_CR4_MASK |
 499                                         INTERCEPT_CR8_MASK;
 500
 501         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 502                                         INTERCEPT_DR1_MASK |
 503                                         INTERCEPT_DR2_MASK |
 504                                         INTERCEPT_DR3_MASK;
 505
 506         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 507                                         INTERCEPT_DR1_MASK |
 508                                         INTERCEPT_DR2_MASK |
 509                                         INTERCEPT_DR3_MASK |
 510                                         INTERCEPT_DR5_MASK |
 511                                         INTERCEPT_DR7_MASK;
 512
 513         control->intercept_exceptions = (1 << PF_VECTOR) |
 514                                         (1 << UD_VECTOR) |
 515                                         (1 << MC_VECTOR);
 516
 517
 518         control->intercept =    (1ULL << INTERCEPT_INTR) |
 519                                 (1ULL << INTERCEPT_NMI) |
 520                                 (1ULL << INTERCEPT_SMI) |
 521                                 (1ULL << INTERCEPT_CPUID) |
 522                                 (1ULL << INTERCEPT_INVD) |
 523                                 (1ULL << INTERCEPT_HLT) |
 524                                 (1ULL << INTERCEPT_INVLPG) |
 525                                 (1ULL << INTERCEPT_INVLPGA) |
 526                                 (1ULL << INTERCEPT_IOIO_PROT) |
 527                                 (1ULL << INTERCEPT_MSR_PROT) |
 528                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 529                                 (1ULL << INTERCEPT_SHUTDOWN) |
 530                                 (1ULL << INTERCEPT_VMRUN) |
 531                                 (1ULL << INTERCEPT_VMMCALL) |
 532                                 (1ULL << INTERCEPT_VMLOAD) |
 533                                 (1ULL << INTERCEPT_VMSAVE) |
 534                                 (1ULL << INTERCEPT_STGI) |
 535                                 (1ULL << INTERCEPT_CLGI) |
 536                                 (1ULL << INTERCEPT_SKINIT) |
 537                                 (1ULL << INTERCEPT_WBINVD) |
 538                                 (1ULL << INTERCEPT_MONITOR) |
 539                                 (1ULL << INTERCEPT_MWAIT);
 540
 541         control->iopm_base_pa = iopm_base;
 542         control->msrpm_base_pa = __pa(svm->msrpm);
 543         control->tsc_offset = 0;
 544         control->int_ctl = V_INTR_MASKING_MASK;
 545
 546         init_seg(&save->es);
 547         init_seg(&save->ss);
 548         init_seg(&save->ds);
 549         init_seg(&save->fs);
 550         init_seg(&save->gs);
 551
 552         save->cs.selector = 0xf000;
 553         /* Executable/Readable Code Segment */
 554         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 555                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 556         save->cs.limit = 0xffff;
 557         /*
 558          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 559          * be consistent with it.
 560          *
 561          * Replace when we have real mode working for vmx.
 562          */
 563         save->cs.base = 0xf0000;
 564
 565         save->gdtr.limit = 0xffff;
 566         save->idtr.limit = 0xffff;
 567
 568         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 569         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 570
 571         save->efer = EFER_SVME;
 572         save->dr6 = 0xffff0ff0;
 573         save->dr7 = 0x400;
 574         save->rflags = 2;
 575         save->rip = 0x0000fff0;
 576         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 577
 578         /*
 579          * cr0 val on cpu init should be 0x60000010, we enable cpu
 580          * cache by default. the orderly way is to enable cache in bios.
 581          */
 582         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 583         save->cr4 = X86_CR4_PAE;
 584         /* rdx = ?? */
 585
 586         if (npt_enabled) {
 587                 /* Setup VMCB for Nested Paging */
 588                 control->nested_ctl = 1;
 589                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 590                                         (1ULL << INTERCEPT_INVLPG));
 591                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 592                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 593                                                 INTERCEPT_CR3_MASK);
 594                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 595                                                  INTERCEPT_CR3_MASK);
 596                 save->g_pat = 0x0007040600070406ULL;
 597                 /* enable caching because the QEMU Bios doesn't enable it */
 598                 save->cr0 = X86_CR0_ET;
 599                 save->cr3 = 0;
 600                 save->cr4 = 0;
 601         }
 602         force_new_asid(&svm->vcpu);
 603
 604         svm->vcpu.arch.hflags = HF_GIF_MASK;
 605 }
 606
 607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 608 {
 609         struct vcpu_svm *svm = to_svm(vcpu);
 610
 611         init_vmcb(svm);
 612
 613         if (vcpu->vcpu_id != 0) {
 614                 kvm_rip_write(vcpu, 0);
 615                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 616                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 617         }
 618         vcpu->arch.regs_avail = ~0;
 619         vcpu->arch.regs_dirty = ~0;
 620
 621         return 0;
 622 }
 623
 624 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 625 {
 626         struct vcpu_svm *svm;
 627         struct page *page;
 628         struct page *msrpm_pages;
 629         struct page *hsave_page;
 630         int err;
 631
 632         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 633         if (!svm) {
 634                 err = -ENOMEM;
 635                 goto out;
 636         }
 637
 638         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 639         if (err)
 640                 goto free_svm;
 641
 642         page = alloc_page(GFP_KERNEL);
 643         if (!page) {
 644                 err = -ENOMEM;
 645                 goto uninit;
 646         }
 647
 648         err = -ENOMEM;
 649         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 650         if (!msrpm_pages)
 651                 goto uninit;
 652         svm->msrpm = page_address(msrpm_pages);
 653         svm_vcpu_init_msrpm(svm->msrpm);
 654
 655         hsave_page = alloc_page(GFP_KERNEL);
 656         if (!hsave_page)
 657                 goto uninit;
 658         svm->hsave = page_address(hsave_page);
 659
 660         svm->vmcb = page_address(page);
 661         clear_page(svm->vmcb);
 662         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 663         svm->asid_generation = 0;
 664         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 665         init_vmcb(svm);
 666
 667         fx_init(&svm->vcpu);
 668         svm->vcpu.fpu_active = 1;
 669         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 670         if (svm->vcpu.vcpu_id == 0)
 671                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 672
 673         return &svm->vcpu;
 674
 675 uninit:
 676         kvm_vcpu_uninit(&svm->vcpu);
 677 free_svm:
 678         kmem_cache_free(kvm_vcpu_cache, svm);
 679 out:
 680         return ERR_PTR(err);
 681 }
 682
 683 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 684 {
 685         struct vcpu_svm *svm = to_svm(vcpu);
 686
 687         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 688         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 689         __free_page(virt_to_page(svm->hsave));
 690         kvm_vcpu_uninit(vcpu);
 691         kmem_cache_free(kvm_vcpu_cache, svm);
 692 }
 693
 694 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 695 {
 696         struct vcpu_svm *svm = to_svm(vcpu);
 697         int i;
 698
 699         if (unlikely(cpu != vcpu->cpu)) {
 700                 u64 tsc_this, delta;
 701
 702                 /*
 703                  * Make sure that the guest sees a monotonically
 704                  * increasing TSC.
 705                  */
 706                 rdtscll(tsc_this);
 707                 delta = vcpu->arch.host_tsc - tsc_this;
 708                 svm->vmcb->control.tsc_offset += delta;
 709                 vcpu->cpu = cpu;
 710                 kvm_migrate_timers(vcpu);
 711         }
 712
 713         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 714                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 715 }
 716
 717 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 718 {
 719         struct vcpu_svm *svm = to_svm(vcpu);
 720         int i;
 721
 722         ++vcpu->stat.host_state_reload;
 723         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 724                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 725
 726         rdtscll(vcpu->arch.host_tsc);
 727 }
 728
 729 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 730 {
 731         return to_svm(vcpu)->vmcb->save.rflags;
 732 }
 733
 734 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 735 {
 736         to_svm(vcpu)->vmcb->save.rflags = rflags;
 737 }
 738
 739 static void svm_set_vintr(struct vcpu_svm *svm)
 740 {
 741         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 742 }
 743
 744 static void svm_clear_vintr(struct vcpu_svm *svm)
 745 {
 746         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 747 }
 748
 749 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 750 {
 751         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 752
 753         switch (seg) {
 754         case VCPU_SREG_CS: return &save->cs;
 755         case VCPU_SREG_DS: return &save->ds;
 756         case VCPU_SREG_ES: return &save->es;
 757         case VCPU_SREG_FS: return &save->fs;
 758         case VCPU_SREG_GS: return &save->gs;
 759         case VCPU_SREG_SS: return &save->ss;
 760         case VCPU_SREG_TR: return &save->tr;
 761         case VCPU_SREG_LDTR: return &save->ldtr;
 762         }
 763         BUG();
 764         return NULL;
 765 }
 766
 767 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 768 {
 769         struct vmcb_seg *s = svm_seg(vcpu, seg);
 770
 771         return s->base;
 772 }
 773
 774 static void svm_get_segment(struct kvm_vcpu *vcpu,
 775                             struct kvm_segment *var, int seg)
 776 {
 777         struct vmcb_seg *s = svm_seg(vcpu, seg);
 778
 779         var->base = s->base;
 780         var->limit = s->limit;
 781         var->selector = s->selector;
 782         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 783         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 784         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 785         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 786         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 787         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 788         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 789         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 790
 791         /*
 792          * SVM always stores 0 for the 'G' bit in the CS selector in
 793          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 794          * Intel's VMENTRY has a check on the 'G' bit.
 795          */
 796         if (seg == VCPU_SREG_CS)
 797                 var->g = s->limit > 0xfffff;
 798
 799         /*
 800          * Work around a bug where the busy flag in the tr selector
 801          * isn't exposed
 802          */
 803         if (seg == VCPU_SREG_TR)
 804                 var->type |= 0x2;
 805
 806         var->unusable = !var->present;
 807 }
 808
 809 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 810 {
 811         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 812
 813         return save->cpl;
 814 }
 815
 816 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 817 {
 818         struct vcpu_svm *svm = to_svm(vcpu);
 819
 820         dt->limit = svm->vmcb->save.idtr.limit;
 821         dt->base = svm->vmcb->save.idtr.base;
 822 }
 823
 824 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 825 {
 826         struct vcpu_svm *svm = to_svm(vcpu);
 827
 828         svm->vmcb->save.idtr.limit = dt->limit;
 829         svm->vmcb->save.idtr.base = dt->base ;
 830 }
 831
 832 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 833 {
 834         struct vcpu_svm *svm = to_svm(vcpu);
 835
 836         dt->limit = svm->vmcb->save.gdtr.limit;
 837         dt->base = svm->vmcb->save.gdtr.base;
 838 }
 839
 840 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 841 {
 842         struct vcpu_svm *svm = to_svm(vcpu);
 843
 844         svm->vmcb->save.gdtr.limit = dt->limit;
 845         svm->vmcb->save.gdtr.base = dt->base ;
 846 }
 847
 848 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 849 {
 850 }
 851
 852 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 853 {
 854         struct vcpu_svm *svm = to_svm(vcpu);
 855
 856 #ifdef CONFIG_X86_64
 857         if (vcpu->arch.shadow_efer & EFER_LME) {
 858                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 859                         vcpu->arch.shadow_efer |= EFER_LMA;
 860                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 861                 }
 862
 863                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 864                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 865                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 866                 }
 867         }
 868 #endif
 869         if (npt_enabled)
 870                 goto set;
 871
 872         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 873                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 874                 vcpu->fpu_active = 1;
 875         }
 876
 877         vcpu->arch.cr0 = cr0;
 878         cr0 |= X86_CR0_PG | X86_CR0_WP;
 879         if (!vcpu->fpu_active) {
 880                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 881                 cr0 |= X86_CR0_TS;
 882         }
 883 set:
 884         /*
 885          * re-enable caching here because the QEMU bios
 886          * does not do it - this results in some delay at
 887          * reboot
 888          */
 889         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 890         svm->vmcb->save.cr0 = cr0;
 891 }
 892
 893 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 894 {
 895         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 896         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 897
 898         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 899                 force_new_asid(vcpu);
 900
 901         vcpu->arch.cr4 = cr4;
 902         if (!npt_enabled)
 903                 cr4 |= X86_CR4_PAE;
 904         cr4 |= host_cr4_mce;
 905         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 906 }
 907
 908 static void svm_set_segment(struct kvm_vcpu *vcpu,
 909                             struct kvm_segment *var, int seg)
 910 {
 911         struct vcpu_svm *svm = to_svm(vcpu);
 912         struct vmcb_seg *s = svm_seg(vcpu, seg);
 913
 914         s->base = var->base;
 915         s->limit = var->limit;
 916         s->selector = var->selector;
 917         if (var->unusable)
 918                 s->attrib = 0;
 919         else {
 920                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 921                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 922                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 923                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 924                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 925                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 926                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 927                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 928         }
 929         if (seg == VCPU_SREG_CS)
 930                 svm->vmcb->save.cpl
 931                         = (svm->vmcb->save.cs.attrib
 932                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 933
 934 }
 935
 936 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 937 {
 938         return -EOPNOTSUPP;
 939 }
 940
 941 static int svm_get_irq(struct kvm_vcpu *vcpu)
 942 {
 943         struct vcpu_svm *svm = to_svm(vcpu);
 944         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 945
 946         if (is_external_interrupt(exit_int_info))
 947                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 948         return -1;
 949 }
 950
 951 static void load_host_msrs(struct kvm_vcpu *vcpu)
 952 {
 953 #ifdef CONFIG_X86_64
 954         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 955 #endif
 956 }
 957
 958 static void save_host_msrs(struct kvm_vcpu *vcpu)
 959 {
 960 #ifdef CONFIG_X86_64
 961         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 962 #endif
 963 }
 964
 965 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 966 {
 967         if (svm_data->next_asid > svm_data->max_asid) {
 968                 ++svm_data->asid_generation;
 969                 svm_data->next_asid = 1;
 970                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 971         }
 972
 973         svm->vcpu.cpu = svm_data->cpu;
 974         svm->asid_generation = svm_data->asid_generation;
 975         svm->vmcb->control.asid = svm_data->next_asid++;
 976 }
 977
 978 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 979 {
 980         unsigned long val = to_svm(vcpu)->db_regs[dr];
 981         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 982         return val;
 983 }
 984
 985 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 986                        int *exception)
 987 {
 988         struct vcpu_svm *svm = to_svm(vcpu);
 989
 990         *exception = 0;
 991
 992         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 993                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 994                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 995                 *exception = DB_VECTOR;
 996                 return;
 997         }
 998
 999         switch (dr) {
1000         case 0 ... 3:
1001                 svm->db_regs[dr] = value;
1002                 return;
1003         case 4 ... 5:
1004                 if (vcpu->arch.cr4 & X86_CR4_DE) {
1005                         *exception = UD_VECTOR;
1006                         return;
1007                 }
1008         case 7: {
1009                 if (value & ~((1ULL << 32) - 1)) {
1010                         *exception = GP_VECTOR;
1011                         return;
1012                 }
1013                 svm->vmcb->save.dr7 = value;
1014                 return;
1015         }
1016         default:
1017                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1018                        __func__, dr);
1019                 *exception = UD_VECTOR;
1020                 return;
1021         }
1022 }
1023
1024 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1025 {
1026         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1027         struct kvm *kvm = svm->vcpu.kvm;
1028         u64 fault_address;
1029         u32 error_code;
1030         bool event_injection = false;
1031
1032         if (!irqchip_in_kernel(kvm) &&
1033             is_external_interrupt(exit_int_info)) {
1034                 event_injection = true;
1035                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1036         }
1037
1038         fault_address  = svm->vmcb->control.exit_info_2;
1039         error_code = svm->vmcb->control.exit_info_1;
1040
1041         if (!npt_enabled)
1042                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1043                             (u32)fault_address, (u32)(fault_address >> 32),
1044                             handler);
1045         else
1046                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1047                             (u32)fault_address, (u32)(fault_address >> 32),
1048                             handler);
1049         /*
1050          * FIXME: Tis shouldn't be necessary here, but there is a flush
1051          * missing in the MMU code. Until we find this bug, flush the
1052          * complete TLB here on an NPF
1053          */
1054         if (npt_enabled)
1055                 svm_flush_tlb(&svm->vcpu);
1056
1057         if (!npt_enabled && event_injection)
1058                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1059         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1060 }
1061
1062 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1063 {
1064         int er;
1065
1066         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1067         if (er != EMULATE_DONE)
1068                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1069         return 1;
1070 }
1071
1072 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1073 {
1074         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1075         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1076                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1077         svm->vcpu.fpu_active = 1;
1078
1079         return 1;
1080 }
1081
1082 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1083 {
1084         /*
1085          * On an #MC intercept the MCE handler is not called automatically in
1086          * the host. So do it by hand here.
1087          */
1088         asm volatile (
1089                 "int $0x12\n");
1090         /* not sure if we ever come back to this point */
1091
1092         return 1;
1093 }
1094
1095 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1096 {
1097         /*
1098          * VMCB is undefined after a SHUTDOWN intercept
1099          * so reinitialize it.
1100          */
1101         clear_page(svm->vmcb);
1102         init_vmcb(svm);
1103
1104         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1105         return 0;
1106 }
1107
1108 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1109 {
1110         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1111         int size, down, in, string, rep;
1112         unsigned port;
1113
1114         ++svm->vcpu.stat.io_exits;
1115
1116         svm->next_rip = svm->vmcb->control.exit_info_2;
1117
1118         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1119
1120         if (string) {
1121                 if (emulate_instruction(&svm->vcpu,
1122                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1123                         return 0;
1124                 return 1;
1125         }
1126
1127         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1128         port = io_info >> 16;
1129         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1130         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1131         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1132
1133         skip_emulated_instruction(&svm->vcpu);
1134         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1135 }
1136
1137 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1138 {
1139         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1140         return 1;
1141 }
1142
1143 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1144 {
1145         ++svm->vcpu.stat.irq_exits;
1146         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1147         return 1;
1148 }
1149
1150 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1151 {
1152         return 1;
1153 }
1154
1155 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1156 {
1157         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1158         skip_emulated_instruction(&svm->vcpu);
1159         return kvm_emulate_halt(&svm->vcpu);
1160 }
1161
1162 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1163 {
1164         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1165         skip_emulated_instruction(&svm->vcpu);
1166         kvm_emulate_hypercall(&svm->vcpu);
1167         return 1;
1168 }
1169
1170 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1171 {
1172         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1173             || !is_paging(&svm->vcpu)) {
1174                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1175                 return 1;
1176         }
1177
1178         if (svm->vmcb->save.cpl) {
1179                 kvm_inject_gp(&svm->vcpu, 0);
1180                 return 1;
1181         }
1182
1183        return 0;
1184 }
1185
1186 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1187 {
1188         struct page *page;
1189
1190         down_read(&current->mm->mmap_sem);
1191         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1192         up_read(&current->mm->mmap_sem);
1193
1194         if (is_error_page(page)) {
1195                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1196                        __func__, gpa);
1197                 kvm_release_page_clean(page);
1198                 kvm_inject_gp(&svm->vcpu, 0);
1199                 return NULL;
1200         }
1201         return page;
1202 }
1203
1204 static int nested_svm_do(struct vcpu_svm *svm,
1205                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1206                          int (*handler)(struct vcpu_svm *svm,
1207                                         void *arg1,
1208                                         void *arg2,
1209                                         void *opaque))
1210 {
1211         struct page *arg1_page;
1212         struct page *arg2_page = NULL;
1213         void *arg1;
1214         void *arg2 = NULL;
1215         int retval;
1216
1217         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1218         if(arg1_page == NULL)
1219                 return 1;
1220
1221         if (arg2_gpa) {
1222                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1223                 if(arg2_page == NULL) {
1224                         kvm_release_page_clean(arg1_page);
1225                         return 1;
1226                 }
1227         }
1228
1229         arg1 = kmap_atomic(arg1_page, KM_USER0);
1230         if (arg2_gpa)
1231                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1232
1233         retval = handler(svm, arg1, arg2, opaque);
1234
1235         kunmap_atomic(arg1, KM_USER0);
1236         if (arg2_gpa)
1237                 kunmap_atomic(arg2, KM_USER1);
1238
1239         kvm_release_page_dirty(arg1_page);
1240         if (arg2_gpa)
1241                 kvm_release_page_dirty(arg2_page);
1242
1243         return retval;
1244 }
1245
1246 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1247 {
1248         to_vmcb->save.fs = from_vmcb->save.fs;
1249         to_vmcb->save.gs = from_vmcb->save.gs;
1250         to_vmcb->save.tr = from_vmcb->save.tr;
1251         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1252         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1253         to_vmcb->save.star = from_vmcb->save.star;
1254         to_vmcb->save.lstar = from_vmcb->save.lstar;
1255         to_vmcb->save.cstar = from_vmcb->save.cstar;
1256         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1257         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1258         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1259         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1260
1261         return 1;
1262 }
1263
1264 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1265                              void *arg2, void *opaque)
1266 {
1267         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1268 }
1269
1270 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1271                              void *arg2, void *opaque)
1272 {
1273         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1274 }
1275
1276 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1277 {
1278         if (nested_svm_check_permissions(svm))
1279                 return 1;
1280
1281         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1282         skip_emulated_instruction(&svm->vcpu);
1283
1284         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1285
1286         return 1;
1287 }
1288
1289 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1290 {
1291         if (nested_svm_check_permissions(svm))
1292                 return 1;
1293
1294         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1295         skip_emulated_instruction(&svm->vcpu);
1296
1297         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1298
1299         return 1;
1300 }
1301
1302 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1303 {
1304         if (nested_svm_check_permissions(svm))
1305                 return 1;
1306
1307         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1308         skip_emulated_instruction(&svm->vcpu);
1309
1310         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1311
1312         return 1;
1313 }
1314
1315 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1316 {
1317         if (nested_svm_check_permissions(svm))
1318                 return 1;
1319
1320         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1321         skip_emulated_instruction(&svm->vcpu);
1322
1323         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1324
1325         /* After a CLGI no interrupts should come */
1326         svm_clear_vintr(svm);
1327         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1328
1329         return 1;
1330 }
1331
1332 static int invalid_op_interception(struct vcpu_svm *svm,
1333                                    struct kvm_run *kvm_run)
1334 {
1335         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1336         return 1;
1337 }
1338
1339 static int task_switch_interception(struct vcpu_svm *svm,
1340                                     struct kvm_run *kvm_run)
1341 {
1342         u16 tss_selector;
1343
1344         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1345         if (svm->vmcb->control.exit_info_2 &
1346             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1347                 return kvm_task_switch(&svm->vcpu, tss_selector,
1348                                        TASK_SWITCH_IRET);
1349         if (svm->vmcb->control.exit_info_2 &
1350             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1351                 return kvm_task_switch(&svm->vcpu, tss_selector,
1352                                        TASK_SWITCH_JMP);
1353         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1354 }
1355
1356 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1357 {
1358         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1359         kvm_emulate_cpuid(&svm->vcpu);
1360         return 1;
1361 }
1362
1363 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1364 {
1365         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1366                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1367         return 1;
1368 }
1369
1370 static int emulate_on_interception(struct vcpu_svm *svm,
1371                                    struct kvm_run *kvm_run)
1372 {
1373         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1374                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1375         return 1;
1376 }
1377
1378 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1379 {
1380         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1381         if (irqchip_in_kernel(svm->vcpu.kvm))
1382                 return 1;
1383         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1384         return 0;
1385 }
1386
1387 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1388 {
1389         struct vcpu_svm *svm = to_svm(vcpu);
1390
1391         switch (ecx) {
1392         case MSR_IA32_TIME_STAMP_COUNTER: {
1393                 u64 tsc;
1394
1395                 rdtscll(tsc);
1396                 *data = svm->vmcb->control.tsc_offset + tsc;
1397                 break;
1398         }
1399         case MSR_K6_STAR:
1400                 *data = svm->vmcb->save.star;
1401                 break;
1402 #ifdef CONFIG_X86_64
1403         case MSR_LSTAR:
1404                 *data = svm->vmcb->save.lstar;
1405                 break;
1406         case MSR_CSTAR:
1407                 *data = svm->vmcb->save.cstar;
1408                 break;
1409         case MSR_KERNEL_GS_BASE:
1410                 *data = svm->vmcb->save.kernel_gs_base;
1411                 break;
1412         case MSR_SYSCALL_MASK:
1413                 *data = svm->vmcb->save.sfmask;
1414                 break;
1415 #endif
1416         case MSR_IA32_SYSENTER_CS:
1417                 *data = svm->vmcb->save.sysenter_cs;
1418                 break;
1419         case MSR_IA32_SYSENTER_EIP:
1420                 *data = svm->vmcb->save.sysenter_eip;
1421                 break;
1422         case MSR_IA32_SYSENTER_ESP:
1423                 *data = svm->vmcb->save.sysenter_esp;
1424                 break;
1425         /* Nobody will change the following 5 values in the VMCB so
1426            we can safely return them on rdmsr. They will always be 0
1427            until LBRV is implemented. */
1428         case MSR_IA32_DEBUGCTLMSR:
1429                 *data = svm->vmcb->save.dbgctl;
1430                 break;
1431         case MSR_IA32_LASTBRANCHFROMIP:
1432                 *data = svm->vmcb->save.br_from;
1433                 break;
1434         case MSR_IA32_LASTBRANCHTOIP:
1435                 *data = svm->vmcb->save.br_to;
1436                 break;
1437         case MSR_IA32_LASTINTFROMIP:
1438                 *data = svm->vmcb->save.last_excp_from;
1439                 break;
1440         case MSR_IA32_LASTINTTOIP:
1441                 *data = svm->vmcb->save.last_excp_to;
1442                 break;
1443         case MSR_VM_HSAVE_PA:
1444                 *data = svm->hsave_msr;
1445                 break;
1446         default:
1447                 return kvm_get_msr_common(vcpu, ecx, data);
1448         }
1449         return 0;
1450 }
1451
1452 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1453 {
1454         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1455         u64 data;
1456
1457         if (svm_get_msr(&svm->vcpu, ecx, &data))
1458                 kvm_inject_gp(&svm->vcpu, 0);
1459         else {
1460                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1461                             (u32)(data >> 32), handler);
1462
1463                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1464                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1465                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1466                 skip_emulated_instruction(&svm->vcpu);
1467         }
1468         return 1;
1469 }
1470
1471 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1472 {
1473         struct vcpu_svm *svm = to_svm(vcpu);
1474
1475         switch (ecx) {
1476         case MSR_IA32_TIME_STAMP_COUNTER: {
1477                 u64 tsc;
1478
1479                 rdtscll(tsc);
1480                 svm->vmcb->control.tsc_offset = data - tsc;
1481                 break;
1482         }
1483         case MSR_K6_STAR:
1484                 svm->vmcb->save.star = data;
1485                 break;
1486 #ifdef CONFIG_X86_64
1487         case MSR_LSTAR:
1488                 svm->vmcb->save.lstar = data;
1489                 break;
1490         case MSR_CSTAR:
1491                 svm->vmcb->save.cstar = data;
1492                 break;
1493         case MSR_KERNEL_GS_BASE:
1494                 svm->vmcb->save.kernel_gs_base = data;
1495                 break;
1496         case MSR_SYSCALL_MASK:
1497                 svm->vmcb->save.sfmask = data;
1498                 break;
1499 #endif
1500         case MSR_IA32_SYSENTER_CS:
1501                 svm->vmcb->save.sysenter_cs = data;
1502                 break;
1503         case MSR_IA32_SYSENTER_EIP:
1504                 svm->vmcb->save.sysenter_eip = data;
1505                 break;
1506         case MSR_IA32_SYSENTER_ESP:
1507                 svm->vmcb->save.sysenter_esp = data;
1508                 break;
1509         case MSR_IA32_DEBUGCTLMSR:
1510                 if (!svm_has(SVM_FEATURE_LBRV)) {
1511                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1512                                         __func__, data);
1513                         break;
1514                 }
1515                 if (data & DEBUGCTL_RESERVED_BITS)
1516                         return 1;
1517
1518                 svm->vmcb->save.dbgctl = data;
1519                 if (data & (1ULL<<0))
1520                         svm_enable_lbrv(svm);
1521                 else
1522                         svm_disable_lbrv(svm);
1523                 break;
1524         case MSR_K7_EVNTSEL0:
1525         case MSR_K7_EVNTSEL1:
1526         case MSR_K7_EVNTSEL2:
1527         case MSR_K7_EVNTSEL3:
1528         case MSR_K7_PERFCTR0:
1529         case MSR_K7_PERFCTR1:
1530         case MSR_K7_PERFCTR2:
1531         case MSR_K7_PERFCTR3:
1532                 /*
1533                  * Just discard all writes to the performance counters; this
1534                  * should keep both older linux and windows 64-bit guests
1535                  * happy
1536                  */
1537                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1538
1539                 break;
1540         case MSR_VM_HSAVE_PA:
1541                 svm->hsave_msr = data;
1542                 break;
1543         default:
1544                 return kvm_set_msr_common(vcpu, ecx, data);
1545         }
1546         return 0;
1547 }
1548
1549 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1550 {
1551         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1552         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1553                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1554
1555         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1556                     handler);
1557
1558         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1559         if (svm_set_msr(&svm->vcpu, ecx, data))
1560                 kvm_inject_gp(&svm->vcpu, 0);
1561         else
1562                 skip_emulated_instruction(&svm->vcpu);
1563         return 1;
1564 }
1565
1566 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1567 {
1568         if (svm->vmcb->control.exit_info_1)
1569                 return wrmsr_interception(svm, kvm_run);
1570         else
1571                 return rdmsr_interception(svm, kvm_run);
1572 }
1573
1574 static int interrupt_window_interception(struct vcpu_svm *svm,
1575                                    struct kvm_run *kvm_run)
1576 {
1577         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1578
1579         svm_clear_vintr(svm);
1580         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1581         /*
1582          * If the user space waits to inject interrupts, exit as soon as
1583          * possible
1584          */
1585         if (kvm_run->request_interrupt_window &&
1586             !svm->vcpu.arch.irq_summary) {
1587                 ++svm->vcpu.stat.irq_window_exits;
1588                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1589                 return 0;
1590         }
1591
1592         return 1;
1593 }
1594
1595 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1596                                       struct kvm_run *kvm_run) = {
1597         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1598         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1599         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1600         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1601         /* for now: */
1602         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1603         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1604         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1605         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1606         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1607         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1608         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1609         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1610         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1611         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1612         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1613         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1614         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1615         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1616         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1617         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1618         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1619         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1620         [SVM_EXIT_INTR]                         = intr_interception,
1621         [SVM_EXIT_NMI]                          = nmi_interception,
1622         [SVM_EXIT_SMI]                          = nop_on_interception,
1623         [SVM_EXIT_INIT]                         = nop_on_interception,
1624         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1625         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1626         [SVM_EXIT_CPUID]                        = cpuid_interception,
1627         [SVM_EXIT_INVD]                         = emulate_on_interception,
1628         [SVM_EXIT_HLT]                          = halt_interception,
1629         [SVM_EXIT_INVLPG]                       = invlpg_interception,
1630         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1631         [SVM_EXIT_IOIO]                         = io_interception,
1632         [SVM_EXIT_MSR]                          = msr_interception,
1633         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1634         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1635         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1636         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1637         [SVM_EXIT_VMLOAD]                       = vmload_interception,
1638         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
1639         [SVM_EXIT_STGI]                         = stgi_interception,
1640         [SVM_EXIT_CLGI]                         = clgi_interception,
1641         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1642         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1643         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1644         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1645         [SVM_EXIT_NPF]                          = pf_interception,
1646 };
1647
1648 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1649 {
1650         struct vcpu_svm *svm = to_svm(vcpu);
1651         u32 exit_code = svm->vmcb->control.exit_code;
1652
1653         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1654                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1655
1656         if (npt_enabled) {
1657                 int mmu_reload = 0;
1658                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1659                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1660                         mmu_reload = 1;
1661                 }
1662                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1663                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1664                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1665                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1666                                 kvm_inject_gp(vcpu, 0);
1667                                 return 1;
1668                         }
1669                 }
1670                 if (mmu_reload) {
1671                         kvm_mmu_reset_context(vcpu);
1672                         kvm_mmu_load(vcpu);
1673                 }
1674         }
1675
1676         kvm_reput_irq(svm);
1677
1678         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1679                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1680                 kvm_run->fail_entry.hardware_entry_failure_reason
1681                         = svm->vmcb->control.exit_code;
1682                 return 0;
1683         }
1684
1685         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1686             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1687             exit_code != SVM_EXIT_NPF)
1688                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1689                        "exit_code 0x%x\n",
1690                        __func__, svm->vmcb->control.exit_int_info,
1691                        exit_code);
1692
1693         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1694             || !svm_exit_handlers[exit_code]) {
1695                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1696                 kvm_run->hw.hardware_exit_reason = exit_code;
1697                 return 0;
1698         }
1699
1700         return svm_exit_handlers[exit_code](svm, kvm_run);
1701 }
1702
1703 static void reload_tss(struct kvm_vcpu *vcpu)
1704 {
1705         int cpu = raw_smp_processor_id();
1706
1707         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1708         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1709         load_TR_desc();
1710 }
1711
1712 static void pre_svm_run(struct vcpu_svm *svm)
1713 {
1714         int cpu = raw_smp_processor_id();
1715
1716         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1717
1718         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1719         if (svm->vcpu.cpu != cpu ||
1720             svm->asid_generation != svm_data->asid_generation)
1721                 new_asid(svm, svm_data);
1722 }
1723
1724
1725 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1726 {
1727         struct vmcb_control_area *control;
1728
1729         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1730
1731         ++svm->vcpu.stat.irq_injections;
1732         control = &svm->vmcb->control;
1733         control->int_vector = irq;
1734         control->int_ctl &= ~V_INTR_PRIO_MASK;
1735         control->int_ctl |= V_IRQ_MASK |
1736                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1737 }
1738
1739 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1740 {
1741         struct vcpu_svm *svm = to_svm(vcpu);
1742
1743         svm_inject_irq(svm, irq);
1744 }
1745
1746 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1747 {
1748         struct vcpu_svm *svm = to_svm(vcpu);
1749         struct vmcb *vmcb = svm->vmcb;
1750         int max_irr, tpr;
1751
1752         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1753                 return;
1754
1755         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1756
1757         max_irr = kvm_lapic_find_highest_irr(vcpu);
1758         if (max_irr == -1)
1759                 return;
1760
1761         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1762
1763         if (tpr >= (max_irr & 0xf0))
1764                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1765 }
1766
1767 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1768 {
1769         struct vcpu_svm *svm = to_svm(vcpu);
1770         struct vmcb *vmcb = svm->vmcb;
1771         int intr_vector = -1;
1772
1773         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1774             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1775                 intr_vector = vmcb->control.exit_int_info &
1776                               SVM_EVTINJ_VEC_MASK;
1777                 vmcb->control.exit_int_info = 0;
1778                 svm_inject_irq(svm, intr_vector);
1779                 goto out;
1780         }
1781
1782         if (vmcb->control.int_ctl & V_IRQ_MASK)
1783                 goto out;
1784
1785         if (!kvm_cpu_has_interrupt(vcpu))
1786                 goto out;
1787
1788         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
1789                 goto out;
1790
1791         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1792             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1793             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1794                 /* unable to deliver irq, set pending irq */
1795                 svm_set_vintr(svm);
1796                 svm_inject_irq(svm, 0x0);
1797                 goto out;
1798         }
1799         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1800         intr_vector = kvm_cpu_get_interrupt(vcpu);
1801         svm_inject_irq(svm, intr_vector);
1802 out:
1803         update_cr8_intercept(vcpu);
1804 }
1805
1806 static void kvm_reput_irq(struct vcpu_svm *svm)
1807 {
1808         struct vmcb_control_area *control = &svm->vmcb->control;
1809
1810         if ((control->int_ctl & V_IRQ_MASK)
1811             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1812                 control->int_ctl &= ~V_IRQ_MASK;
1813                 push_irq(&svm->vcpu, control->int_vector);
1814         }
1815
1816         svm->vcpu.arch.interrupt_window_open =
1817                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1818                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
1819 }
1820
1821 static void svm_do_inject_vector(struct vcpu_svm *svm)
1822 {
1823         struct kvm_vcpu *vcpu = &svm->vcpu;
1824         int word_index = __ffs(vcpu->arch.irq_summary);
1825         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1826         int irq = word_index * BITS_PER_LONG + bit_index;
1827
1828         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1829         if (!vcpu->arch.irq_pending[word_index])
1830                 clear_bit(word_index, &vcpu->arch.irq_summary);
1831         svm_inject_irq(svm, irq);
1832 }
1833
1834 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1835                                        struct kvm_run *kvm_run)
1836 {
1837         struct vcpu_svm *svm = to_svm(vcpu);
1838         struct vmcb_control_area *control = &svm->vmcb->control;
1839
1840         svm->vcpu.arch.interrupt_window_open =
1841                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1842                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
1843                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
1844
1845         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1846                 /*
1847                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1848                  */
1849                 svm_do_inject_vector(svm);
1850
1851         /*
1852          * Interrupts blocked.  Wait for unblock.
1853          */
1854         if (!svm->vcpu.arch.interrupt_window_open &&
1855             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1856                 svm_set_vintr(svm);
1857         else
1858                 svm_clear_vintr(svm);
1859 }
1860
1861 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1862 {
1863         return 0;
1864 }
1865
1866 static void save_db_regs(unsigned long *db_regs)
1867 {
1868         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1869         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1870         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1871         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1872 }
1873
1874 static void load_db_regs(unsigned long *db_regs)
1875 {
1876         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1877         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1878         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1879         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1880 }
1881
1882 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1883 {
1884         force_new_asid(vcpu);
1885 }
1886
1887 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1888 {
1889 }
1890
1891 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1892 {
1893         struct vcpu_svm *svm = to_svm(vcpu);
1894
1895         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1896                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1897                 kvm_lapic_set_tpr(vcpu, cr8);
1898         }
1899 }
1900
1901 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1902 {
1903         struct vcpu_svm *svm = to_svm(vcpu);
1904         u64 cr8;
1905
1906         if (!irqchip_in_kernel(vcpu->kvm))
1907                 return;
1908
1909         cr8 = kvm_get_cr8(vcpu);
1910         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1911         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1912 }
1913
1914 #ifdef CONFIG_X86_64
1915 #define R "r"
1916 #else
1917 #define R "e"
1918 #endif
1919
1920 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1921 {
1922         struct vcpu_svm *svm = to_svm(vcpu);
1923         u16 fs_selector;
1924         u16 gs_selector;
1925         u16 ldt_selector;
1926
1927         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1928         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1929         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1930
1931         pre_svm_run(svm);
1932
1933         sync_lapic_to_cr8(vcpu);
1934
1935         save_host_msrs(vcpu);
1936         fs_selector = kvm_read_fs();
1937         gs_selector = kvm_read_gs();
1938         ldt_selector = kvm_read_ldt();
1939         svm->host_cr2 = kvm_read_cr2();
1940         svm->host_dr6 = read_dr6();
1941         svm->host_dr7 = read_dr7();
1942         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1943         /* required for live migration with NPT */
1944         if (npt_enabled)
1945                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1946
1947         if (svm->vmcb->save.dr7 & 0xff) {
1948                 write_dr7(0);
1949                 save_db_regs(svm->host_db_regs);
1950                 load_db_regs(svm->db_regs);
1951         }
1952
1953         clgi();
1954
1955         local_irq_enable();
1956
1957         asm volatile (
1958                 "push %%"R"bp; \n\t"
1959                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1960                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1961                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1962                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1963                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1964                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1965 #ifdef CONFIG_X86_64
1966                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1967                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1968                 "mov %c[r10](%[svm]), %%r10 \n\t"
1969                 "mov %c[r11](%[svm]), %%r11 \n\t"
1970                 "mov %c[r12](%[svm]), %%r12 \n\t"
1971                 "mov %c[r13](%[svm]), %%r13 \n\t"
1972                 "mov %c[r14](%[svm]), %%r14 \n\t"
1973                 "mov %c[r15](%[svm]), %%r15 \n\t"
1974 #endif
1975
1976                 /* Enter guest mode */
1977                 "push %%"R"ax \n\t"
1978                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1979                 __ex(SVM_VMLOAD) "\n\t"
1980                 __ex(SVM_VMRUN) "\n\t"
1981                 __ex(SVM_VMSAVE) "\n\t"
1982                 "pop %%"R"ax \n\t"
1983
1984                 /* Save guest registers, load host registers */
1985                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1986                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1987                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1988                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1989                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1990                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1991 #ifdef CONFIG_X86_64
1992                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1993                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1994                 "mov %%r10, %c[r10](%[svm]) \n\t"
1995                 "mov %%r11, %c[r11](%[svm]) \n\t"
1996                 "mov %%r12, %c[r12](%[svm]) \n\t"
1997                 "mov %%r13, %c[r13](%[svm]) \n\t"
1998                 "mov %%r14, %c[r14](%[svm]) \n\t"
1999                 "mov %%r15, %c[r15](%[svm]) \n\t"
2000 #endif
2001                 "pop %%"R"bp"
2002                 :
2003                 : [svm]"a"(svm),
2004                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2005                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2006                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2007                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2008                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2009                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2010                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2011 #ifdef CONFIG_X86_64
2012                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2013                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2014                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2015                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2016                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2017                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2018                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2019                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2020 #endif
2021                 : "cc", "memory"
2022                 , R"bx", R"cx", R"dx", R"si", R"di"
2023 #ifdef CONFIG_X86_64
2024                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2025 #endif
2026                 );
2027
2028         if ((svm->vmcb->save.dr7 & 0xff))
2029                 load_db_regs(svm->host_db_regs);
2030
2031         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2032         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2033         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2034         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2035
2036         write_dr6(svm->host_dr6);
2037         write_dr7(svm->host_dr7);
2038         kvm_write_cr2(svm->host_cr2);
2039
2040         kvm_load_fs(fs_selector);
2041         kvm_load_gs(gs_selector);
2042         kvm_load_ldt(ldt_selector);
2043         load_host_msrs(vcpu);
2044
2045         reload_tss(vcpu);
2046
2047         local_irq_disable();
2048
2049         stgi();
2050
2051         sync_cr8_to_lapic(vcpu);
2052
2053         svm->next_rip = 0;
2054 }
2055
2056 #undef R
2057
2058 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2059 {
2060         struct vcpu_svm *svm = to_svm(vcpu);
2061
2062         if (npt_enabled) {
2063                 svm->vmcb->control.nested_cr3 = root;
2064                 force_new_asid(vcpu);
2065                 return;
2066         }
2067
2068         svm->vmcb->save.cr3 = root;
2069         force_new_asid(vcpu);
2070
2071         if (vcpu->fpu_active) {
2072                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2073                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2074                 vcpu->fpu_active = 0;
2075         }
2076 }
2077
2078 static int is_disabled(void)
2079 {
2080         u64 vm_cr;
2081
2082         rdmsrl(MSR_VM_CR, vm_cr);
2083         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2084                 return 1;
2085
2086         return 0;
2087 }
2088
2089 static void
2090 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2091 {
2092         /*
2093          * Patch in the VMMCALL instruction:
2094          */
2095         hypercall[0] = 0x0f;
2096         hypercall[1] = 0x01;
2097         hypercall[2] = 0xd9;
2098 }
2099
2100 static void svm_check_processor_compat(void *rtn)
2101 {
2102         *(int *)rtn = 0;
2103 }
2104
2105 static bool svm_cpu_has_accelerated_tpr(void)
2106 {
2107         return false;
2108 }
2109
2110 static int get_npt_level(void)
2111 {
2112 #ifdef CONFIG_X86_64
2113         return PT64_ROOT_LEVEL;
2114 #else
2115         return PT32E_ROOT_LEVEL;
2116 #endif
2117 }
2118
2119 static int svm_get_mt_mask_shift(void)
2120 {
2121         return 0;
2122 }
2123
2124 static struct kvm_x86_ops svm_x86_ops = {
2125         .cpu_has_kvm_support = has_svm,
2126         .disabled_by_bios = is_disabled,
2127         .hardware_setup = svm_hardware_setup,
2128         .hardware_unsetup = svm_hardware_unsetup,
2129         .check_processor_compatibility = svm_check_processor_compat,
2130         .hardware_enable = svm_hardware_enable,
2131         .hardware_disable = svm_hardware_disable,
2132         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2133
2134         .vcpu_create = svm_create_vcpu,
2135         .vcpu_free = svm_free_vcpu,
2136         .vcpu_reset = svm_vcpu_reset,
2137
2138         .prepare_guest_switch = svm_prepare_guest_switch,
2139         .vcpu_load = svm_vcpu_load,
2140         .vcpu_put = svm_vcpu_put,
2141
2142         .set_guest_debug = svm_guest_debug,
2143         .get_msr = svm_get_msr,
2144         .set_msr = svm_set_msr,
2145         .get_segment_base = svm_get_segment_base,
2146         .get_segment = svm_get_segment,
2147         .set_segment = svm_set_segment,
2148         .get_cpl = svm_get_cpl,
2149         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2150         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2151         .set_cr0 = svm_set_cr0,
2152         .set_cr3 = svm_set_cr3,
2153         .set_cr4 = svm_set_cr4,
2154         .set_efer = svm_set_efer,
2155         .get_idt = svm_get_idt,
2156         .set_idt = svm_set_idt,
2157         .get_gdt = svm_get_gdt,
2158         .set_gdt = svm_set_gdt,
2159         .get_dr = svm_get_dr,
2160         .set_dr = svm_set_dr,
2161         .get_rflags = svm_get_rflags,
2162         .set_rflags = svm_set_rflags,
2163
2164         .tlb_flush = svm_flush_tlb,
2165
2166         .run = svm_vcpu_run,
2167         .handle_exit = handle_exit,
2168         .skip_emulated_instruction = skip_emulated_instruction,
2169         .patch_hypercall = svm_patch_hypercall,
2170         .get_irq = svm_get_irq,
2171         .set_irq = svm_set_irq,
2172         .queue_exception = svm_queue_exception,
2173         .exception_injected = svm_exception_injected,
2174         .inject_pending_irq = svm_intr_assist,
2175         .inject_pending_vectors = do_interrupt_requests,
2176
2177         .set_tss_addr = svm_set_tss_addr,
2178         .get_tdp_level = get_npt_level,
2179         .get_mt_mask_shift = svm_get_mt_mask_shift,
2180 };
2181
2182 static int __init svm_init(void)
2183 {
2184         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2185                               THIS_MODULE);
2186 }
2187
2188 static void __exit svm_exit(void)
2189 {
2190         kvm_exit();
2191 }
2192
2193 module_init(svm_init)
2194 module_exit(svm_exit)