Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[linux-2.6] / arch / powerpc / boot / dts / mpc8540ads.dts
1 /*
2  * MPC8540 ADS Device Tree Source
3  *
4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8540ADS";
16         compatible = "MPC8540ADS", "MPC85xxADS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23                 ethernet2 = &enet2;
24                 serial0 = &serial0;
25                 serial1 = &serial1;
26                 pci0 = &pci0;
27         };
28
29         cpus {
30                 #address-cells = <1>;
31                 #size-cells = <0>;
32
33                 PowerPC,8540@0 {
34                         device_type = "cpu";
35                         reg = <0x0>;
36                         d-cache-line-size = <32>;       // 32 bytes
37                         i-cache-line-size = <32>;       // 32 bytes
38                         d-cache-size = <0x8000>;                // L1, 32K
39                         i-cache-size = <0x8000>;                // L1, 32K
40                         timebase-frequency = <0>;       //  33 MHz, from uboot
41                         bus-frequency = <0>;    // 166 MHz
42                         clock-frequency = <0>;  // 825 MHz, from uboot
43                         next-level-cache = <&L2>;
44                 };
45         };
46
47         memory {
48                 device_type = "memory";
49                 reg = <0x0 0x8000000>;  // 128M at 0x0
50         };
51
52         soc8540@e0000000 {
53                 #address-cells = <1>;
54                 #size-cells = <1>;
55                 device_type = "soc";
56                 ranges = <0x0 0xe0000000 0x100000>;
57                 reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
58                 bus-frequency = <0>;
59
60                 memory-controller@2000 {
61                         compatible = "fsl,8540-memory-controller";
62                         reg = <0x2000 0x1000>;
63                         interrupt-parent = <&mpic>;
64                         interrupts = <18 2>;
65                 };
66
67                 L2: l2-cache-controller@20000 {
68                         compatible = "fsl,8540-l2-cache-controller";
69                         reg = <0x20000 0x1000>;
70                         cache-line-size = <32>; // 32 bytes
71                         cache-size = <0x40000>; // L2, 256K
72                         interrupt-parent = <&mpic>;
73                         interrupts = <16 2>;
74                 };
75
76                 i2c@3000 {
77                         #address-cells = <1>;
78                         #size-cells = <0>;
79                         cell-index = <0>;
80                         compatible = "fsl-i2c";
81                         reg = <0x3000 0x100>;
82                         interrupts = <43 2>;
83                         interrupt-parent = <&mpic>;
84                         dfsrr;
85                 };
86
87                 dma@21300 {
88                         #address-cells = <1>;
89                         #size-cells = <1>;
90                         compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
91                         reg = <0x21300 0x4>;
92                         ranges = <0x0 0x21100 0x200>;
93                         cell-index = <0>;
94                         dma-channel@0 {
95                                 compatible = "fsl,mpc8540-dma-channel",
96                                                 "fsl,eloplus-dma-channel";
97                                 reg = <0x0 0x80>;
98                                 cell-index = <0>;
99                                 interrupt-parent = <&mpic>;
100                                 interrupts = <20 2>;
101                         };
102                         dma-channel@80 {
103                                 compatible = "fsl,mpc8540-dma-channel",
104                                                 "fsl,eloplus-dma-channel";
105                                 reg = <0x80 0x80>;
106                                 cell-index = <1>;
107                                 interrupt-parent = <&mpic>;
108                                 interrupts = <21 2>;
109                         };
110                         dma-channel@100 {
111                                 compatible = "fsl,mpc8540-dma-channel",
112                                                 "fsl,eloplus-dma-channel";
113                                 reg = <0x100 0x80>;
114                                 cell-index = <2>;
115                                 interrupt-parent = <&mpic>;
116                                 interrupts = <22 2>;
117                         };
118                         dma-channel@180 {
119                                 compatible = "fsl,mpc8540-dma-channel",
120                                                 "fsl,eloplus-dma-channel";
121                                 reg = <0x180 0x80>;
122                                 cell-index = <3>;
123                                 interrupt-parent = <&mpic>;
124                                 interrupts = <23 2>;
125                         };
126                 };
127
128                 mdio@24520 {
129                         #address-cells = <1>;
130                         #size-cells = <0>;
131                         compatible = "fsl,gianfar-mdio";
132                         reg = <0x24520 0x20>;
133
134                         phy0: ethernet-phy@0 {
135                                 interrupt-parent = <&mpic>;
136                                 interrupts = <5 1>;
137                                 reg = <0x0>;
138                                 device_type = "ethernet-phy";
139                         };
140                         phy1: ethernet-phy@1 {
141                                 interrupt-parent = <&mpic>;
142                                 interrupts = <5 1>;
143                                 reg = <0x1>;
144                                 device_type = "ethernet-phy";
145                         };
146                         phy3: ethernet-phy@3 {
147                                 interrupt-parent = <&mpic>;
148                                 interrupts = <7 1>;
149                                 reg = <0x3>;
150                                 device_type = "ethernet-phy";
151                         };
152                 };
153
154                 enet0: ethernet@24000 {
155                         cell-index = <0>;
156                         device_type = "network";
157                         model = "TSEC";
158                         compatible = "gianfar";
159                         reg = <0x24000 0x1000>;
160                         local-mac-address = [ 00 00 00 00 00 00 ];
161                         interrupts = <29 2 30 2 34 2>;
162                         interrupt-parent = <&mpic>;
163                         phy-handle = <&phy0>;
164                 };
165
166                 enet1: ethernet@25000 {
167                         cell-index = <1>;
168                         device_type = "network";
169                         model = "TSEC";
170                         compatible = "gianfar";
171                         reg = <0x25000 0x1000>;
172                         local-mac-address = [ 00 00 00 00 00 00 ];
173                         interrupts = <35 2 36 2 40 2>;
174                         interrupt-parent = <&mpic>;
175                         phy-handle = <&phy1>;
176                 };
177
178                 enet2: ethernet@26000 {
179                         cell-index = <2>;
180                         device_type = "network";
181                         model = "FEC";
182                         compatible = "gianfar";
183                         reg = <0x26000 0x1000>;
184                         local-mac-address = [ 00 00 00 00 00 00 ];
185                         interrupts = <41 2>;
186                         interrupt-parent = <&mpic>;
187                         phy-handle = <&phy3>;
188                 };
189
190                 serial0: serial@4500 {
191                         cell-index = <0>;
192                         device_type = "serial";
193                         compatible = "ns16550";
194                         reg = <0x4500 0x100>;   // reg base, size
195                         clock-frequency = <0>;  // should we fill in in uboot?
196                         interrupts = <42 2>;
197                         interrupt-parent = <&mpic>;
198                 };
199
200                 serial1: serial@4600 {
201                         cell-index = <1>;
202                         device_type = "serial";
203                         compatible = "ns16550";
204                         reg = <0x4600 0x100>;   // reg base, size
205                         clock-frequency = <0>;  // should we fill in in uboot?
206                         interrupts = <42 2>;
207                         interrupt-parent = <&mpic>;
208                 };
209                 mpic: pic@40000 {
210                         interrupt-controller;
211                         #address-cells = <0>;
212                         #interrupt-cells = <2>;
213                         reg = <0x40000 0x40000>;
214                         compatible = "chrp,open-pic";
215                         device_type = "open-pic";
216                 };
217         };
218
219         pci0: pci@e0008000 {
220                 cell-index = <0>;
221                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
222                 interrupt-map = <
223
224                         /* IDSEL 0x02 */
225                         0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
226                         0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
227                         0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
228                         0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
229
230                         /* IDSEL 0x03 */
231                         0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
232                         0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
233                         0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
234                         0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
235
236                         /* IDSEL 0x04 */
237                         0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
238                         0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
239                         0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
240                         0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
241
242                         /* IDSEL 0x05 */
243                         0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
244                         0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
245                         0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
246                         0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
247
248                         /* IDSEL 0x0c */
249                         0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
250                         0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
251                         0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
252                         0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
253
254                         /* IDSEL 0x0d */
255                         0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
256                         0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
257                         0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
258                         0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
259
260                         /* IDSEL 0x0e */
261                         0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
262                         0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
263                         0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
264                         0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
265
266                         /* IDSEL 0x0f */
267                         0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
268                         0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
269                         0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
270                         0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
271
272                         /* IDSEL 0x12 */
273                         0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
274                         0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
275                         0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
276                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
277
278                         /* IDSEL 0x13 */
279                         0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
280                         0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
281                         0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
282                         0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
283
284                         /* IDSEL 0x14 */
285                         0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
286                         0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
287                         0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
288                         0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
289
290                         /* IDSEL 0x15 */
291                         0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
292                         0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
293                         0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
294                         0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
295                 interrupt-parent = <&mpic>;
296                 interrupts = <24 2>;
297                 bus-range = <0 0>;
298                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
299                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
300                 clock-frequency = <66666666>;
301                 #interrupt-cells = <1>;
302                 #size-cells = <2>;
303                 #address-cells = <3>;
304                 reg = <0xe0008000 0x1000>;
305                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
306                 device_type = "pci";
307         };
308 };