2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * Based on alpha version.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #ifndef _ASM_POWERPC_OPROFILE_IMPL_H
13 #define _ASM_POWERPC_OPROFILE_IMPL_H
15 #define OP_MAX_COUNTER 8
17 /* Per-counter configuration as set via oprofilefs. */
18 struct op_counter_config {
22 unsigned long enabled;
25 /* Classic doesn't support per-counter user/kernel selection */
28 unsigned long unit_mask;
31 /* System-wide configuration as set via oprofilefs. */
32 struct op_system_config {
38 unsigned long enable_kernel;
39 unsigned long enable_user;
41 unsigned long backtrace_spinlocks;
45 /* Per-arch configuration */
46 struct op_powerpc_model {
47 void (*reg_setup) (struct op_counter_config *,
48 struct op_system_config *,
50 void (*cpu_setup) (void *);
51 void (*start) (struct op_counter_config *);
53 void (*handle_interrupt) (struct pt_regs *,
54 struct op_counter_config *);
58 #ifdef CONFIG_FSL_BOOKE
59 extern struct op_powerpc_model op_model_fsl_booke;
60 #else /* Otherwise, it's classic */
63 extern struct op_powerpc_model op_model_rs64;
64 extern struct op_powerpc_model op_model_power4;
66 #else /* Otherwise, CONFIG_PPC32 */
67 extern struct op_powerpc_model op_model_7450;
70 /* All the classic PPC parts use these */
71 static inline unsigned int ctr_read(unsigned int i)
75 return mfspr(SPRN_PMC1);
77 return mfspr(SPRN_PMC2);
79 return mfspr(SPRN_PMC3);
81 return mfspr(SPRN_PMC4);
83 return mfspr(SPRN_PMC5);
85 return mfspr(SPRN_PMC6);
87 /* No PPC32 chip has more than 6 so far */
90 return mfspr(SPRN_PMC7);
92 return mfspr(SPRN_PMC8);
99 static inline void ctr_write(unsigned int i, unsigned int val)
103 mtspr(SPRN_PMC1, val);
106 mtspr(SPRN_PMC2, val);
109 mtspr(SPRN_PMC3, val);
112 mtspr(SPRN_PMC4, val);
115 mtspr(SPRN_PMC5, val);
118 mtspr(SPRN_PMC6, val);
121 /* No PPC32 chip has more than 6, yet */
124 mtspr(SPRN_PMC7, val);
127 mtspr(SPRN_PMC8, val);
134 #endif /* !CONFIG_FSL_BOOKE */
136 #endif /* _ASM_POWERPC_OPROFILE_IMPL_H */